WO2017171890A1

WO2017171890A1 - Systems, methods, and apparatuses for reducing opc model error via a machine learning algorithm

Info

Publication number: WO2017171890A1
Application number: PCT/US2016/025780
Authority: WO
Inventors: Hyungjin MA; Vasudev LAL; Seongtae Jeong; Erik N. HOGGAN
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2016-04-02
Filing date: 2016-04-02
Publication date: 2017-10-05
Anticipated expiration: 2018-10-02

Abstract

In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for reducing Optical Proximity Correction (OPC) model error via a machine learning algorithm. For instance, in accordance with one embodiment, there are means described for creating a mask via a lithography process; fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; creating a semi-physical model of the mask using physical parameters of the lithography process used to create the mask, the semi-physical model specifying contours of the plurality of features of the mask; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and shifting the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences. Other related embodiments are disclosed.

Description

SYSTEMS, METHODS, AND APPARATUSES FOR REDUCING OPC MODEL ERROR VIA A MACHINE LEARNING ALGORITHM

CLAIM OF PRIORITY [0001] None.

COPYRIGHT NOTICE

[0002] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.

TECHNICAL FIELD [0003] The subject matter described herein relates generally to the field of

semiconductor and electronics manufacturing, and more particularly, to systems, methods, and apparatuses for reducing Optical Proximity Correction (OPC) model error via a machine learning algorithm. BACKGROUND

[0004] The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches, which in and of themselves may also correspond to embodiments of the claimed subject matter.

[0005] Conventional techniques utilizing Optical Proximity Correction (OPC) models are not sufficiently accurate as semiconductor manufacturing techniques necessitate increasingly strict tolerances and smaller physical dimensions.

[0006] For advanced process nodes in semiconductor manufacturing, one of the major challenges are to control defects and yield to a level that is viable for high volume manufacturing (HVM). To maintain the density scaling and reduce cell footprint, process margins are tightening which in turn causes systematic and random process variations resulting in the processes being more prone to defects.

[0007] One such source of process variation is the result of insufficiently accurate model prediction of lithographic processes, which impacts the optical proximity correction (OPC) of mask design.

[0008] The accuracy of these measurements and the accuracy of the model is of utmost importance because any variation of the OPC model translates to a variation of dimensions on the final semiconductors chip produced.

[0009] When the physical dimensions of the manufactured semiconductors were greater, such inaccuracies and uncertainty were manageable due to the greater margins. However, as the physical size of these manufactured semiconductors is reduced farther into the nanometer realm of manufacturing, it becomes necessary to operate using increasingly accurate models if manufacturing yields are to remain economically viable.

[0010] The present state of the art may therefore benefit from the systems, methods, and apparatuses for reducing Optical Proximity Correction (OPC) model error via a machine learning algorithm as described herein.

BRIEF DESCRIPTION OF THE DRAWINGS [0011] Embodiments are illustrated by way of example, and not by way of limitation, and will be more fully understood with reference to the following detailed description when considered in connection with the figures in which:

[0012] Figure 1 depicts an exemplary Artificial Neural Network (ANN) machine learning algorithm in accordance with described embodiments;

[0013] Figure 2 depicts an exemplary modeling flow utilizing the Artificial Neural

Network (ANN) machine learning algorithm in accordance with described embodiments;

[0014] Figure 3 depicts a contour shifting scheme based upon image map distortion in accordance with described embodiments;

[0015] Figure 4 depicts an intensity profile and corresponding resist threshold depicting a step-like function in accordance with described embodiments;

[0016] Figure 5 depicts several SEM image representations showing the model prediction of resist pattern utilizing the described techniques in comparison to conventional models;

[0017] Figure 6 is a flow diagram illustrating a method for reducing Optical Proximity Correction (OPC) model error via a machine learning algorithm in accordance with described embodiments;

[0018] Figure 7 illustrates a computing device in accordance with described embodiments; and

[0019] Figure 8 illustrates an interposer that includes one or more described embodiments.

DETAILED DESCRIPTION

[0020] Described herein are systems, methods, and apparatuses for reducing Optical Proximity Correction (OPC) model error via a machine learning algorithm. For instance, in accordance with one embodiment, there are means described for creating a mask via a lithography process; fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; creating a semi- physical model of the mask using physical parameters of the lithography process used to create the mask, the semi -physical model specifying contours of the plurality of features of the mask; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and shifting the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.

[0021] The methodologies described herein provide improvements to OPC model accuracy which may then be applied to a variety of lithography processes.

[0022] The described techniques result in significant improvements in OPC model prediction based on the described machine learning algorithm and provide for a flexible way to combine the influence of optical image parameters as well as geometric parameters to predict lithographic processes, which are complicated phenomenon originated from optical, chemical and physical effects. This flexibility is realized in a model form which is easy to calibrate from fabrication process data. Moreover, the resulting model is fast enough to deploy in high volume full chip correction by guiding the model generation through non-linear parametric regression and classification.

[0023] Optical Proximity Correction (OPC) models require accurate mask layout dimensions as input parameters. The greater the accuracy, the more useful and accurate the resulting model will be for the semiconductor manufacturing processes. [0024] Resist patterns generated by lithographic processes are the results of complicated optical, chemical and physical phenomenon, which can be modeled based on optical image parameters and geometric parameters. Model predictions, which are represented in the form of contours, are generated based on the distorted image maps, which are numerically stable and efficient enough to be used for high volume manufacturing. To generate an accurate and yet numerically efficient model, machine learning algorithms such as Artificial Neural Network (ANN) algorithms are employed in accordance with certain embodiments.

[0025] Conventional OPC models employed for reticle correction model optical and resist lithography phenomenon utilized various approximations to speed up calculations to enable full-chip correction which resulted in model errors that can no longer be sustained for advanced technology nodes due to the stricter tolerances and reduced dimensions of modem semiconductor manufacturing. Alternate techniques such as rigorous finite difference time domain (FDTD) calculations are accurate but are computationally unfeasible for large scale and high volume manufacturing processes.

[0026] The techniques described herein are demonstrated to produce more accurate lithographic models than conventional OPC models with an acceptable increase in computational cost and are therefore economically viable for manufacturing.

[0027] Rule based model error compensation has also been conventionally utilized for known problematic configurations. However, such a technique is only feasible for a very limited set of geometries, and it is therefore infeasible to generate the requisite rules for all possible configurations in the circuit partem. Moreover, use of rule based model error compensation introduces unnecessary and undesirable complexity into the tapeout flow, which in turn translates to increased costs in terms of the engineering resources necessary to characterize, specify, code, and validate such rules as well as computational resources required to then calculate the models.

[0028] Existing modeling software for OPC modeling provides a predictive model for lithographic processes. Such models are then relied upon for applying corrections to the masks so as to ensure correct partem fidelity and correct dimensions of features on the manufactured silicon wafers.

[0029] The existing modeling software for OPC is deficient in terms of the accuracy when new lithographic systems having tighter margins and dimensions are utilized, resulting in unworkable errors inhibiting the newer technologies from being successfully scaled to high volume manufacturing. Conventional OPC models simply cannot predict with sufficient accuracy and precision to the smaller feature size and feature geometries associated new technologies. [0030] Improvements to the existing OPC models are needed such that the OPC models which drive manufacturing may be successfully utilized to attain sufficiently accurate pattern fidelity on the mask and on the manufactured silicon wafers.

[0031] Use of the conventional models have been demonstrated to result in unacceptable yields from the fabrication process due to the degree of uncertainty of such models, resulting in the features actually printed failing within the layers due to the size of the features as printed which is direct result of the inaccurate models. The position and size of the features of the mask are critical to the functioning of the circuit produced and on the scale of nanometers the margin for error becomes incredibly small, thus necessitating model outputs with a greater degree of precision. Printing deviances of tens of nanometers in the process which are not accounted for in the design will render an entire silicon wafer inoperable. Such a circuit simply will not work and will not function like a processor because such deviations cause joins and shorts which are not part of the circuit design.

[0032] The conventional OPC models need further adjustment and correction or contour shifting so as to move these printed features into the correct position with a greater degree of precision. Such improvements ensure functionally operable silicon and thus improve manufacturing yields and profitability for any given product.

[0033] In the following description, numerous specific details are set forth such as examples of specific systems, languages, components, etc., in order to provide a thorough understanding of the various embodiments. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the embodiments disclosed herein. In other instances, well known materials or methods have not been described in detail in order to avoid unnecessarily obscuring the disclosed embodiments.

[0034] In addition to various hardware components depicted in the figures and described herein, embodiments further include various operations which are described below. The operations described in accordance with such embodiments may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the operations. Alternatively, the operations may be performed by a combination of hardware and software.

[0035] Any of the disclosed embodiments may be used alone or together with one another in any combination. Although various embodiments may have been partially motivated by deficiencies with conventional techniques and approaches, some of which are described or alluded to within the specification, the embodiments need not necessarily address or solve any of these deficiencies, but rather, may address only some of the deficiencies, address none of the deficiencies, or be directed toward different deficiencies and problems which are not directly discussed.

[0036] Figure 1 depicts an exemplary Artificial Neural Network (ANN) 100 machine learning algorithm in which the input variables predict the deterministic model error or process driven changes in critical dimension.

[0037] More particularly, there is depicted on the left an initial OPC contour 120 represented by the bold line and outermost ellipse and then a second contour is further depicted via the inner ellipse showing the Scanning Electron Microscope (SEM) contour 125 representing fabrication data as taken from an SEM image.

[0038] On the right is a neural network 105 having as input several input image parameters 110 which are calculated using an OPC model and the resulting output from the neural network is a contour shift prediction 115. In accordance with one embodiment the image input parameters 110 used to train the neural network 105 are simulated optical parameters representing the entirety of the feature set for use as the input image parameters 110.

[0039] Any specific layout will have a deterministic OPC model error. Neural networks, such as Artificial Neural Network (ANN) 100, are able to approximate any arbitrary formula. Therefore, in accordance with described embodiments, the neural network 105 is trained to describe the relationship between the layout and the respective OPC model error, using the image input parameters 110 to enable the neural network 105 to learn about the layout. A sufficient quantity of image input parameters 110 are provided so as to enable such learning.

[0040] A simulated optical image from conventional OPC models is obtained from the convolution of the layout and an optical transfer function. According to described embodiments, image parameters are defined via optical images that capture information about the layout which is then used to train the neural network 105 to describe the deterministic relationship between the layout and conventional OPC model error.

[0041] According to certain embodiments, geometric information from the layout is additionally utilized to directly train the neural network to predict the amount of model error associated with the geometry. Once trained, the neural network 105 provides a more accurate model which can then be implemented by shifting the initial OPC contour 120 by an amount predicted by neural network 105.

[0042] The OPC model provides a forward function which connects what is on the mask to what is on the wafer. Software algorithms provide a basic physics solution to this problem, but the solution requires many approximations which thus operates as a source of inaccuracies. Described embodiments therefore reformulate the problem in such a way that a list of features are provided to the neural network for the purposes of training. Through training based on such input features, such as those derived from the depicted input image parameters, the neural network learns what adaptations are necessary to conform the base OPC models to known physical models. These adaptations are output as the contour shift predictions 115 and result in a semi-physical model which permits formulas and corrections by which the trained neural network 105 describes the differences between the incoming base OPC model and the observed physical realities.

[0043] Because the model, the structures, the features, and the mask is so complex it simply is not practical to manually determine what function or adaptations to the incoming base OPC model are necessary to conform that model to the reality as observed in the SEM imagery taken from fabricated silicon wafers utilizing the base OPC model. Use of the neural network

105 to apply machine learning therefore provides a significant advantage as the neural network is leveraged to determine the complexity and learn the necessary adaptations.

[0044] In accordance with certain embodiments, the neural network 105 predicts the deterministic model error or process driven changes in critical dimensions for the size and position of features. According to a particular embodiment, the neural network provides contour fitting to the SEM contour 125 image representing the actually observed physical outputs from a fabrication process utilizing the base OPC model which provides the initial OPC contour 120.

[0045] In accordance with certain embodiments, the initial OPC contour 120 is a result of the software algorithms which provides a prediction of the physical space via a semi-physical model. According to such an embodiment, SEM image data is then collected for the patterns to generate or determine the SEM contour 125 representing the fab data for actual physical samples of fabricated physical silicon wafers generated using the initial OPC base model.

[0046] According to such an embodiment, the delta between the initial OPC contour 120 and the SEM contour 125 is the determined model error of the base OPC model. The neural network 105 is trained to be able to predict the determined model error of the base OPC model so as to output an improved model using the contour shift prediction 115 provided by the trained neural network 105.

[0047] Figure 2 depicts an exemplary modeling flow 200 utilizing the Artificial Neural Network (ANN) machine learning algorithm in accordance with described embodiments. As depicted here, the modeling flow 200 portion within the dashed line indicates newly introduced elements to a modeling flow to utilize the provided contour shift as predicted by the trained neural network.

[0048] More particularly, there is described at block 205 means for sampling data collection for model building when then proceeds to block 210 where a base OPC model (e.g., an initial contour such as the initial OPC contour depicted by element 120 at Figure 1) is provided. According to certain embodiments, the processing advances to block 215 where a correction engine for mask design applies the contour as rendered by the base OPC model.

[0049] However, described embodiments provide further correction and improvement over the base OPC model via the contour shift as predicted by the trained neural network. In particular, returning to block 210 where the base OPC model or the initial contour is provided, the processing instead advances into the newly introduced elements of the modeling flow 200 depicted by the dashed line in which processing from block 210 advances to next to block 220 where a model error and lithographic process characterization is applied. Next, contour shifting 225 is applied utilizing the contour shift as predicted by the trained neural network. After contour shifting 225, processing then advances to block 230 where the final model or the final contour is provided as a result of the contour shifting 225 applied using the contour shift as predicted by the neural network.

[0050] After the final model is provided, processing then returns to block 215 where a correction engine for the mask design applies the appropriate correction as benefitted from the contour shifting 225 operation.

[0051] In accordance with one embodiment, the trained neural network output providing the contour shift prediction results in a third contour, one between the initial OPC contour 120 and the SEM contour 125, which is a predicted contour as output by applying the contour shift prediction 115 of the trained neural network as a correction for the base OPC model, thus yielding an improved contour fit between the improved prediction and reality.

[0052] As depicted, the contour shifting 225 operation produces from the input base OPC model's initial contour at block 210 the final model's final contour at block 230, and it is this final contour which is then utilized by the correction engine for the mask design at block 215.

[0053] Ideally, the combination of the semi-physical model and the output of the trained neural network would exactly equal the physical data which equates the observed measurements from the SEM imagery data. In practice, significant improvement is attained as described below, but the predicted final contour 230 is not exactly identical, but it is sufficiently accurate for the smaller feature size dimensions and positions utilized by the newer technologies, and thus, appropriate for scaling up silicon wafer production in high volume manufacturing.

[0054] Although not exact, the predicted final contour rendered by the final model at block 230 is much closer to the actually observed SEM data and the contour shifting 225 as provided by the contour shift prediction 115 from Figure 1 is thus usable to better predict a wide array of structures and how they will behave, which may then compared to new SEM imagery for such features. Moreover, iterative training of the neural network further improves the predictive capability and thus improves the eventual final model and final contour 230 for any mask structures and features.

[0055] As depicted, the final model 230 is then re-applied via OPC correction to modify the mask such that features and structures are positioned in the correct location such that when a next silicon wafer is fabricated through the manufacturing process, all the structures and features will be in the correct location and the resulting silicon die will be functional and operate correctly according to design specifications.

[0056] Figure 3 depicts a contour shifting scheme 300 based upon image map distortion in accordance with described embodiments. Implementation of the contour shift scheme utilizes a predicted model from the trained neural network. The amount of contour shift is given as a function of input variables including, for example, optical image parameters, geometrical parameters, density, pseudo-critical dimensions (pseudo-CDs), and so forth.

[0057] More particularly, there is depicted both the final contour 320 via the bold outer ellipse and also an initial contour 315 depicted via the dashed line of the inner ellipse. In the blow out to the right, it can be seen that location X' 325 is found via iterative processing, where as the shift according to element 330 represents an "initial guess."

[0058] Below the plot over distance on the horizontal axis depicts both the shifted intensity map 305 and also the initial intensity map 310.

[0059] According to certain embodiments, for the sake of numerical efficiency, contour crossing at a given location X is calculated locally. Since the location X' is unknown, training input at location X' is calculated iteratively, which is described by the equation

X_n+1' = X - F(G(X_n' )). For such a series, sufficient condition for the convergence is according to I dF / dX I < 1 .

[0060] In accordance with described embodiments, the OPC base model generates a contour with specified optical intensities resulting from light originating at the beginning of the imager or the imaging tool. The intensities vary and are generally nonlinear. By systematically processing these intensities it is possible to develop many points on the contour location to establish the shape of the pattern.

[0061] In accordance with a particular embodiment, a correction is made to the initial contour 315 using an initial guess 330 and then iteratively the correction made to the initial contour 315, with the correction being represented at Figure 3 by location "X" 325, is shifted over and over to improve the resulting prediction, ultimately resulting in a point on the final contour 320 corresponding to the known SEM contour.

[0062] In such a way, by utilizing the optical intensity mask an equation is applied to cause a shift to the depth mask such that the final contour 320 is closer to the actual measured contour based on the SEM contour (element 125 from Figure 1) of an SEM image from wafer fabrication. The equations may continually be manipulated and adjusted by the neural network until the adaptation to the initial contour 315 is sufficiently close or equal to the final contour 320 sought.

[0063] Because the basic physics are known from the base OPC model, it is possible for the neural network to continuously attempt to draw contours to approximate the final contour 320 utilizing the base OPC model until the desired shift is attained for every point on the contour sought. It is the shift in the intensity map as represented by the initial intensity map 310 and the shifted intensity map 305 which is algorithmically manipulated through the iterations of the neural network to ultimately render a new model (e.g., a neural network model) contour which matches the final contour 320 provided by the SEM image.

[0064] During the lithographic process light is shone through the photomask to image the pattern onto the wafer, creating these intensities at each point. Some points are bright and some points are dark, resulting in the initial intensity map 310 depicted.

[0065] Therefore, according to one embodiment, the neural network determines how the shifted intensity map 305 will be translated into a physical feature within a polymer photoresist as part of predicting the final contour 320.

[0066] According to a particular embodiment, the initial intensity map 310 is created from the initial OPC model, which is a semi-physical modeling tool, and the shifts are then applied through the initial OPC model to the initial intensity map 310 to render the shifted intensity map 305.

[0067] Figure 4 depicts an intensity profile and corresponding resist threshold depicting a step-like function in accordance with described embodiments. In particular, a step-like function 401 is depicted on the left and on the right there are depicted various input variables for a non- linear resist threshold classification including iMax at element 405, threshold 415, iMin 410, and neighboring intensity with an exemplary 6nm step up to +/- 12nm at element 420.

[0068] As an alternative to application of the contour shifting scheme, the final contour may instead be described by modulating the resist threshold, which is the intensity at the boundaries after the development of the model. By modulating the resist threshold,

regularization is accomplished by classifying shifted locations from the boundaries as inside or outside of the contours, forming a step-like function 401 threshold form, which can be fit by the neural network's predicted model. In such an embodiment, the model contour is generated where the threshold crosses the intensity which is pinpointed on the exemplary graph at element 415. In such a way, it is possible to bypass or eliminate the iterative operation for finding the initial contour location which may therefore yield a regularized model in faster time due to less computationally intensive processing.

[0069] According to certain embodiments, both image parameters as well as geometric density of dot negative Sub-Resolution Assisting Features (SRAFs) are utilized as inputs for training the neural network to generate the improved model. With such inputs, the trained neural network smoothly combines the provided geometric parameters with the image parameters to compensate for the focus shift effect induced by dot negative SRAFs inputs. According to described embodiments, the demonstrated range of error for various geometries is reduced from 12nm utilizing conventional methodologies down to 5nm utilizing the techniques as described herein.

[0070] According to particular embodiments, such criteria are checked at the full chip level to ensure a stable contour generation. In order to improve the convergence, a damping term may additionally be added to the iteration.

[0071] Moreover, problems with over-fit and contour stability are preventable at the neural network training level via the introduction of a regularization technique.

[0072] Therefore, in accordance with certain embodiments, regularization is applied during the training of the neural network to ensure stable models are achieved. Two reasons for application of such a regularization technique are for the sake of spatial stability and also to prevent over-fitting.

[0073] In particular, spatially, the neural network is trained to predict the contour shift at the contour locations. However, the entire two dimensional image map is distorted to achieve the contour shift in the new model. Consequently, it is important for the contour shift prediction to exhibit stability via characteristics such as slowly varying and varying within bounds, at spatial locations away from the contours. Otherwise, the contour shift prediction could result in a seemingly chaotic result which may be mathematically accurate but pragmatically unrealistic for the application of the prediction to the corrected OPC base model.

[0074] Secondly, neural networks, especially those of high complexity, are prone to over-fitting. It is therefore in accordance with certain embodiments that a safeguard is provided against over-fitting by the trained neural network by imposing a physical condition mandating within the model that any contour shift prediction must be a slowly varying function of space.

[0075] Such regularization is achieved by having spatial sites in the target function, in which the values of the contour shift at the spatial sites are obtained by a distance-weighted sum of the desired contour shift at other nearby contour locations. Through application of such a regularization technique, it has been demonstrated that both predictive capability is increased and also model stability is increased for the models obtained utilizing the methodologies described herein. [0076] According to described embodiments, any target variable to the contour location is a determination of best fit for vector length from an OPC base model predicted contour to the SEM contour representing the actual fabrication result. The delta between these two points represents the shift from the predicted result to the determined reality corresponding to the physical measurements from SEM images. Determining the length of the vector for every one of a series of points making up the contour thus establishes the shift to the contour to attain the final result.

[0077] Due to the manner by which the contour is shifted, the entire mask is locally distorted. Both the contour and the shifted contour represent a 2D quantity and the regularization process applies a smoothing function to the shifted contour to avoid problems such as over fitting. Otherwise, the shifting of the contour may provide a result which is not useful.

[0078] While the input parameters are provided for only target locations, in accordance with certain embodiments, additional points are additionally extrapolated to nearby pseudo target points, distinct from the actual target locations provided. By determining the delta between the base OPC model's initial contour and the SEM contour and additionally introducing the pseudo target locations for the nearby points extrapolated from the target locations, the resulting shift is smoothed. Stated differently, the contour shifting for the model error is determined on the basis of the delta from the initial contour to not just the actually measured points of the SEM image input into the neural network, but additionally based on the delta to the pseudo target locations extrapolated as nearby points to the actually measured points of the SEM image.

[0079] According to one embodiment, the predicted contour represents an intermediate result and a final contour is generated through the smoothing function by fitting the contour to both the SEM contour points and also the extrapolated pseudo nearby points.

[0080] According to a particular embodiment, the neural network generates the intermediate contour using preferential locations for each of the points on the contour which are best possible matches without regard to over-fitting problems or model stability and the final contour is regularized to enhance model stability and remove or smooth out over-fitting of the contour to the measured SEM contour points.

[0081] Figure 5 depicts several SEM image representations 501, 502, and 503 showing the model prediction of resist pattern utilizing the described techniques in comparison to conventional models.

[0082] As depicted at SEM image representation 501, the outer bold line at elements 510 and 515 represent the improved model prediction results for a resist partem using the exemplary fit of a conventional model depicted by the non-bolded interior lines at the elements 510 and 515. As depicted by the SEM image representation 501 the overall fit of the model calibration dataset has been improved for a particular manufacturing process known to suffer from thick resist effects.

[0083] SEM image representation 502 represents a different manufacturing process, again in which during testing there was a demonstrated reduction in error observed for a manufacturing process having one of the strictest process margins. As shown, the outer bold line at each of elements 520 and 525 depict the improved model prediction results versus those of the conventional model depicted by the non-bolded interior lines at the elements 520 and 525.

[0084] SEM image representation 503 represents a corner-to-corner configuration. Use of the trained neural network results in superior predictability of the models especially in regard to tight comer-to-comer configurations as depicted by element 530, which is a critical feature in the manufacturability of certain semiconductor products in accordance with reliability and yield targets. Improvements in the model's predictive capability thus translates directly into significant improvements of lithographic processes which in turn enables the capability of optimizing manufacturing yield, which directly determines the profitability silicon products produced.

[0085] Figure 6 is a flow diagram illustrating a method 600 for reducing Optical

Proximity Correction (OPC) model error via a machine learning algorithm in accordance with described embodiments. Some of the blocks and/or operations listed below are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from method 600 may be utilized in a variety of combinations.

[0086] At block 605 the method for reducing Optical Proximity Correction (OPC) model error via a machine learning algorithm begins with creating a mask via a lithography process.

[0087] At block 610 the method includes fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask.

[0088] At block 615 the method includes creating a semi-physical model of the mask using physical parameters of the lithography process used to create the mask, the semi-physical model specifying contours of the plurality of features of the mask.

[0089] At block 620 the method includes capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer.

[0090] At block 625 the method includes quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images.

[0091] At block 630 the method includes shifting the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.

[0092] In accordance with another embodiment, method 600 further includes:

performing a regularization operation to smooth the shifting of the contours of the plurality of features of the mask.

[0093] In accordance with another embodiment of method 600, shifting the contours of the plurality of features of the mask distorts a two dimensional (2D) quantity representing the semi-physical model of the mask; and in which the regularization operation smoothes the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the mask within the semi-physical model.

[0094] In accordance with another embodiment, method 600 further includes: training a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer and the contours of the plurality of features of the mask as specified by the semi-physical model.

[0095] In accordance with another embodiment of method 600, training the neural network includes: inputting SEM image data of the physical silicon wafer fabricated using the mask into the neural network; and inputting the shifted contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.

[0096] In accordance with another embodiment of method 600, training the neural network includes: inputting SEM images of the physical silicon wafer fabricated using the mask into the neural network; and generating smoothed shifted contours of the plurality of features of the mask via a regularization process; and inputting the smoothed shifted contours of the plurality of features into the neural network.

[0097] In accordance with another embodiment of method 600, training the neural network includes: inputting image input parameters based on the SEM images collected, in which the image input parameters are simulated optical parameters describing the physical parameters of the lithography process used to create the mask.

[0098] In accordance with another embodiment of method 600, training the neural network includes: inputting a simulated optical image from an Optical Proximity Correction (OPC) base model, the simulated optical image obtained from a layout of the contours of the plurality of features of the mask as specified by the semi-physical model and an optical transfer function; and in which the trained neural network generates a deterministic relationship between the layout of the contours of the plurality of features of the mask as specified by the semi- physical model and the quantified differences.

[0099] In accordance with another embodiment of method 600, training the neural network includes: inputting geometric information from a layout of the contours of the plurality of features of the mask as specified by the semi-physical model to directly train the neural network to predict an amount of model error observed in the semi-physical model associated with the input geometric information based on the quantified differences.

[00100] In accordance with another embodiment of method 600, the trained neural network performs contour fitting of the contours of the plurality of features of the mask as specified by the semi-physical model to the plurality of features embodied within the physical silicon wafer represented within the captured SEM images.

[00101] In accordance with another embodiment of method 600, the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features of the mask as specified by the semi -physical model based on the quantified differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and in which the neural network generates a new model of the mask specifying the contours of the plurality of features of the mask shifted by the delta at each of a plurality of points of the shifted contour according to the equation function generated by the neural network.

[00102] In accordance with another embodiment of method 600, the neural network performs a regularization process to smooth the shifted contour, in which the neural network is trained against over-fitting of the shifted contour by imposing a physical condition mandate upon the trained neural network within the new model of the mask requiring that any contour shift prediction be a slowly varying function of space.

[00103] In accordance with another embodiment, method 600 further includes: using the new model generated by the trained neural network to predict new mask features based on a predicted contour shift generated by the trained neural network to contours of the new mask features as determined by the semi-physical model.

[00104] In accordance with another embodiment of method 600, the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features of the mask as specified by the semi-physical model to each of a plurality of targets corresponding to points on the features embodied within the physical silicon wafer represented by the SEM images; and in which the neural network smoothes the shift of the contours of the plurality of features of the mask through a regularization process by obtaining values of the contour shift to each of the plurality of targets by a distance- weighted sum of a determined contour shift at other nearby targets within a threshold distance of each target.

[00105] In accordance with another embodiment of method 600, any target variable to the contour target location is a determination of best fit for vector length from a predicted contour of an Optical Proximity Correction (OPC) base model to a measured contour from the SEM images representing fabrication results for the plurality of features embodied within the physical silicon wafer.

[00106] In accordance with another embodiment of method 600, quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images includes: collecting multiple measurements of critical dimensions of the features embodied by the physical silicon wafer as captured by the SEM images and comparing the multiple measurements of the critical dimensions of the features to the contours of the plurality of features of the mask as specified by the semi-physical model to determine the differences.

[00107] In accordance with another embodiment of method 600, quantifying differences includes: measuring critical dimensions of the features embodied by the physical silicon wafer from thousands of the SEM images captured, in which the measuring of the critical dimensions includes measuring at each of a plurality of target points along the contours of the plurality of features of the mask as specified by the semi-physical model and comparing to the plurality of features embodied by the physical silicon wafer to generate millions of data points quantifying the differences between the SEM images and the semi-physical model.

[00108] In accordance with another embodiment, method 600 further includes:

generating a contour via the semi-physical model with specified optical intensities resulting from light originating at an imager which illuminates the mask, in which the intensities vary and are nonlinear; and systematically processing the optical intensities to develop a plurality of points on the contour to establish a shape for each of the plurality of features of the mask as specified by the semi-physical model.

[00109] In accordance with another embodiment, method 600 further includes: applying correction to the contour generated via the semi-physical model with specified optical intensities, in which the correction includes an initial guess; and iteratively shifting the correction made to the contour via the initial guess to improve the correction until the iterative shifting of the correction made to the contour results in a point on a targeted contour of one of the plurality of features embodied within the physical silicon wafer corresponding to the SEM images.

[00110] In accordance with a particular embodiment there is a non-transitory computer readable storage medium having instructions stored thereupon that, when executed by a processor, the instructions cause the processor to perform operations for reducing Optical Proximity Correction (OPC) model error, in which operations include: creating a mask via a lithography process; fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; creating a semi- physical model of the mask using physical parameters of the lithography process used to create the mask, the semi-physical model specifying contours of the plurality of features of the mask; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and shifting the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.

[00111] In accordance with a related embodiment there is a system having means by which to reduce Optical Proximity Correction (OPC) model error, in which such an exemplary system includes: a mask created via a lithography process; a physical silicon wafer having been fabricated using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; a semi-physical model of the mask created using physical parameters of the lithography process used to create the mask, the semi-physical model to specify contours of the plurality of features of the mask; storage to capture Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; an analysis unit to quantify differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and the analysis unit to shift the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.

[00112] Described embodiments may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials.

Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the described embodiments.

[00113] A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various described embodiments, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the described embodiments may also be carried out using nonplanar transistors.

[00114] Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (SiC ) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[00115] The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.

[00116] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[00117] In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further described embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[00118] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[00119] As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or

phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

[00120] One or more interlay er dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or

polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

[00121] Figure 7 illustrates a computing device 700 in accordance with described embodiments. The computing device 700 houses a board 702. The board 702 may include a number of components, including but not limited to a processor 704 and at least one

communication chip 706. The processor 704 is physically and electrically coupled to the board 702. In some implementations the at least one communication chip 706 is also physically and electrically coupled to the board 702. In further implementations, the communication chip 706 is part of the processor 704.

[00122] Depending on its applications, computing device 700 may include other components that may or may not be physically and electrically coupled to the board 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

[00123] The communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 700 may include a plurality of communication chips 706. For instance, a first communication chip 706 may be dedicated to shorter range wireless

communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[00124] The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. In some described embodiments, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors built in accordance with described embodiments. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[00125] The communication chip 706 also includes an integrated circuit die packaged within the communication chip 706. In accordance with other described embodiments, the integrated circuit die of the communication chip includes one or more devices, such as MOS- FET transistors built in accordance with described embodiments.

[00126] In further implementations, another component housed within the computing device 700 may contain an integrated circuit die that includes one or more devices, such as MOS-FET transistors built in accordance with described embodiments.

[00127] In various implementations, the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 700 may be any other electronic device that processes data.

[00128] Figure 8 illustrates an interposer 800 that includes one or more described embodiments. The interposer 800 is an intervening substrate used to bridge a first substrate 802 to a second substrate 804. The first substrate 802 may be, for instance, an integrated circuit die. The second substrate 804 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 800 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 800 may couple an integrated circuit die to a ball grid array (BGA) 806 that can subsequently be coupled to the second substrate 804. In some embodiments, the first and second substrates 802/804 are attached to opposing sides of the interposer 800. In other embodiments, the first and second substrates 802/804 are attached to the same side of the interposer 800. And in further embodiments, three or more substrates are interconnected by way of the interposer 800.

[00129] The interposer 800 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further

implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

[00130] The interposer may include metal interconnects 808 and vias 810, including but not limited to through-silicon vias (TSVs) 812. The interposer 800 may further include embedded devices 814, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 800. In accordance with described embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer 800.

[00131] While the subject matter disclosed herein has been described by way of example and in terms of the specific embodiments, it is to be understood that the claimed embodiments are not limited to the explicitly enumerated embodiments disclosed. To the contrary, the disclosure is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the disclosed subject matter is therefore to be determined in reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

[00132] It is therefore in accordance with the described embodiments that:

[00133] According to one embodiment, there is a method for reducing Optical Proximity Correction (OPC) model error, wherein the method comprises: creating a mask via a lithography process; fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; creating a semi-physical model of the mask using physical parameters of the lithography process used to create the mask, the semi- physical model specifying contours of the plurality of features of the mask; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and shifting the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.

[00134] According to one embodiment the method further includes: performing a regularization operation to smooth the shifting of the contours of the plurality of features of the mask.

[00135] According to one embodiment, shifting the contours of the plurality of features of the mask distorts a two dimensional (2D) quantity representing the semi-physical model of the mask; and wherein the regularization operation smoothes the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the mask within the semi-physical model.

[00136] According to one embodiment the method further includes: training a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer and the contours of the plurality of features of the mask as specified by the semi-physical model.

[00137] According to one embodiment, training the neural network comprises: inputting SEM image data of the physical silicon wafer fabricated using the mask into the neural network; and inputting the shifted contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.

[00138] According to one embodiment, training the neural network comprises: inputting SEM images of the physical silicon wafer fabricated using the mask into the neural network; and generating smoothed shifted contours of the plurality of features of the mask via a regularization process; and inputting the smoothed shifted contours of the plurality of features into the neural network.

[00139] According to one embodiment, training the neural network comprises: inputting image input parameters based on the SEM images collected, wherein the image input parameters are simulated optical parameters describing the physical parameters of the lithography process used to create the mask.

[00140] According to one embodiment, training the neural network comprises: inputting a simulated optical image from an Optical Proximity Correction (OPC) base model, the simulated optical image obtained from a layout of the contours of the plurality of features of the mask as specified by the semi-physical model and an optical transfer function; and wherein the trained neural network generates a deterministic relationship between the layout of the contours of the plurality of features of the mask as specified by the semi-physical model and the quantified differences.

[00141] According to one embodiment, training the neural network comprises: inputting geometric information from a layout of the contours of the plurality of features of the mask as specified by the semi-physical model to directly train the neural network to predict an amount of model error observed in the semi-physical model associated with the input geometric information based on the quantified differences.

[00142] According to one embodiment, the trained neural network performs contour fitting of the contours of the plurality of features of the mask as specified by the semi-physical model to the plurality of features embodied within the physical silicon wafer represented within the captured SEM images.

[00143] According to one embodiment, the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and wherein the neural network generates a new model of the mask specifying the contours of the plurality of features of the mask shifted by the delta at each of a plurality of points of the shifted contour according to the equation function generated by the neural network.

[00144] According to one embodiment, the neural network performs a regularization process to smooth the shifted contour, wherein the neural network is trained against over-fitting of the shifted contour by imposing a physical condition mandate upon the trained neural network within the new model of the mask requiring that any contour shift prediction be a slowly varying function of space.

[00145] According to one embodiment the method further includes: using the new model generated by the trained neural network to predict new mask features based on a predicted contour shift generated by the trained neural network to contours of the new mask features as determined by the semi-physical model.

[00146] According to one embodiment, the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features of the mask as specified by the semi-physical model to each of a plurality of targets corresponding to points on the features embodied within the physical silicon wafer represented by the SEM images; and wherein the neural network smoothes the shift of the contours of the plurality of features of the mask through a regularization process by obtaining values of the contour shift to each of the plurality of targets by a distance-weighted sum of a determined contour shift at other nearby targets within a threshold distance of each target.

[00147] According to one embodiment, any target variable to the contour target location is a determination of best fit for vector length from a predicted contour of an Optical Proximity Correction (OPC) base model to a measured contour from the SEM images representing fabrication results for the plurality of features embodied within the physical silicon wafer.

[00148] According to one embodiment, quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images comprises: collecting multiple measurements of critical dimensions of the features embodied by the physical silicon wafer as captured by the SEM images and comparing the multiple measurements of the critical dimensions of the features to the contours of the plurality of features of the mask as specified by the semi-physical model to determine the differences.

[00149] According to one embodiment, quantifying differences comprises: measuring critical dimensions of the features embodied by the physical silicon wafer from thousands of the SEM images captured, wherein the measuring of the critical dimensions comprises measuring at each of a plurality of target points along the contours of the plurality of features of the mask as specified by the semi-physical model and comparing to the plurality of features embodied by the physical silicon wafer to generate millions of data points quantifying the differences between the SEM images and the semi-physical model.

[00150] According to one embodiment the method further includes: generating a contour via the semi -physical model with specified optical intensities resulting from light originating at an imager which illuminates the mask, wherein the intensities vary and are nonlinear; and systematically processing the optical intensities to develop a plurality of points on the contour to establish a shape for each of the plurality of features of the mask as specified by the semi- physical model.

[00151] According to one embodiment the method further includes: applying correction to the contour generated via the semi-physical model with specified optical intensities, wherein the correction comprises an initial guess; and iteratively shifting the correction made to the contour via the initial guess to improve the correction until the iterative shifting of the correction made to the contour results in a point on a targeted contour of one of the plurality of features embodied within the physical silicon wafer corresponding to the SEM images.

[00152] According to one embodiment there is a system to reduce Optical Proximity Correction (OPC) model error, wherein the system comprises: a mask created via a lithography process; a physical silicon wafer having been fabricated using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; a semi-physical model of the mask created using physical parameters of the lithography process used to create the mask, the semi-physical model to specify contours of the plurality of features of the mask; storage to capture Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; an analysis unit to quantify differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and the analysis unit to shift the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.

[00153] According to one embodiment, the analysis unit is to further perform a regularization operation to smooth the shifting of the contours of the plurality of features of the mask; wherein shifting the contours of the plurality of features of the mask distorts a two dimensional (2D) quantity representing the semi-physical model of the mask; and wherein the regularization operation is to smooth the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the mask within the semi-physical model.

[00154] According to one embodiment, the analysis unit is to further train a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer and the contours of the plurality of features of the mask as specified by the semi-physical model; wherein training the neural network comprises: inputting SEM image data of the physical silicon wafer fabricated using the mask into the neural network and inputting the shifted contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.

[00155] According to one embodiment there is non-transitory computer readable storage media having instructions stored thereupon that, when executed by a processor, the instructions cause the processor to perform operations for reducing Optical Proximity Correction (OPC) model error, wherein operations comprise: creating a mask via a lithography process; fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask; creating a semi-physical model of the mask using physical parameters of the lithography process used to create the mask, the semi-physical model specifying contours of the plurality of features of the mask; capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer; quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and shifting the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.

[00156] According to one embodiment, the instructions cause the processor to perform operations further comprising: performing a regularization operation to smooth the shifting of the contours of the plurality of features of the mask; wherein shifting the contours of the plurality of features of the mask distorts a two dimensional (2D) quantity representing the semi-physical model of the mask; and wherein the regularization operation smoothes the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the mask within the semi-physical model.

[00157] According to one embodiment, the instructions cause the processor to perform operations further comprising: training a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer and the contours of the plurality of features of the mask as specified by the semi-physical model; inputting SEM image data of the physical silicon wafer fabricated using the mask into the neural network; and inputting the shifted contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.

Claims

CLAIMS What is claimed is:

1. A method for reducing Optical Proximity Correction (OPC) model error, wherein the method comprises:

creating a mask via a lithography process;

fabricating a physical silicon wafer using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask;

creating a semi-physical model of the mask using physical parameters of the lithography process used to create the mask, the semi-physical model specifying contours of the plurality of features of the mask;

capturing Scanning Electron Microscope (SEM) images of the plurality of features embodied within the physical silicon wafer;

quantifying differences between (a) the contours of the plurality of features of the mask as

specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and

shifting the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.

2. The method of claim 1 , further comprising:

3. The method of claim 2:

wherein shifting the contours of the plurality of features of the mask distorts a two dimensional

(2D) quantity representing the semi-physical model of the mask; and

wherein the regularization operation smoothes the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the mask within the semi-physical model.

4. The method of claim 1 , further comprising:

training a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer and the contours of the plurality of features of the mask as specified by the semi-physical model.

5. The method of claim 4, wherein training the neural network comprises:

inputting SEM image data of the physical silicon wafer fabricated using the mask into the neural network; and

inputting the shifted contours of the plurality of features of the mask as specified by the semi- physical model based on the quantified differences.

6. The method of claim 4, wherein training the neural network comprises:

inputting SEM images of the physical silicon wafer fabricated using the mask into the neural network; and

generating smoothed shifted contours of the plurality of features of the mask via a regularization process; and

inputting the smoothed shifted contours of the plurality of features into the neural network.

7. The method of claim 4, wherein training the neural network comprises:

inputting image input parameters based on the SEM images collected, wherein the image input parameters are simulated optical parameters describing the physical parameters of the lithography process used to create the mask.

8. The method of claim 4, wherein training the neural network comprises:

inputting a simulated optical image from an Optical Proximity Correction (OPC) base model, the simulated optical image obtained from a layout of the contours of the plurality of features of the mask as specified by the semi-physical model and an optical transfer function; and wherein the trained neural network generates a deterministic relationship between the layout of the contours of the plurality of features of the mask as specified by the semi-physical model and the quantified differences.

9. The method of claim 4, wherein training the neural network comprises:

inputting geometric information from a layout of the contours of the plurality of features of the mask as specified by the semi-physical model to directly train the neural network to predict an amount of model error observed in the semi-physical model associated with the input geometric information based on the quantified differences.

10. The method of claim 4, wherein the trained neural network performs contour fitting of the contours of the plurality of features of the mask as specified by the semi-physical model to the plurality of features embodied within the physical silicon wafer represented within the captured SEM images.

1 1. The method of claim 4:

wherein the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and wherein the neural network generates a new model of the mask specifying the contours of the plurality of features of the mask shifted by the delta at each of a plurality of points of the shifted contour according to the equation function generated by the neural network.

12. The method of claim 11 , wherein the neural network performs a regularization process to smooth the shifted contour, wherein the neural network is trained against over-fitting of the shifted contour by imposing a physical condition mandate upon the trained neural network within the new model of the mask requiring that any contour shift prediction be a slowly varying function of space.

13. The method of claim 1 1, further comprising:

using the new model generated by the trained neural network to predict new mask features based on a predicted contour shift generated by the trained neural network to contours of the new mask features as determined by the semi-physical model.

14. The method of claim 4:

wherein the neural network generates an equation function to represent a delta by which to shift the contours of the plurality of features of the mask as specified by the semi-physical model to each of a plurality of targets corresponding to points on the features embodied within the physical silicon wafer represented by the SEM images; and

wherein the neural network smoothes the shift of the contours of the plurality of features of the mask through a regularization process by obtaining values of the contour shift to each of the plurality of targets by a distance-weighted sum of a determined contour shift at other nearby targets within a threshold distance of each target.

15. The method of claim 14, wherein any target variable to the contour target location is a

determination of best fit for vector length from a predicted contour of an Optical Proximity Correction (OPC) base model to a measured contour from the SEM images representing fabrication results for the plurality of features embodied within the physical silicon wafer.

16. The method of claim 1, wherein quantifying differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images comprises:

collecting multiple measurements of critical dimensions of the features embodied by the physical silicon wafer as captured by the SEM images and comparing the multiple measurements of the critical dimensions of the features to the contours of the plurality of features of the mask as specified by the semi-physical model to determine the differences.

17. The method of claim 1, wherein quantifying differences comprises:

measuring critical dimensions of the features embodied by the physical silicon wafer from

thousands of the SEM images captured, wherein the measuring of the critical dimensions comprises measuring at each of a plurality of target points along the contours of the plurality of features of the mask as specified by the semi-physical model and comparing to the plurality of features embodied by the physical silicon wafer to generate millions of data points quantifying the differences between the SEM images and the semi-physical model.

18. The method of claim 1, further comprising:

generating a contour via the semi-physical model with specified optical intensities resulting from light originating at an imager which illuminates the mask, wherein the intensities vary and are nonlinear; and

systematically processing the optical intensities to develop a plurality of points on the contour to establish a shape for each of the plurality of features of the mask as specified by the semi- physical model.

19. The method of claim 18, further comprising:

applying correction to the contour generated via the semi-physical model with specified optical intensities, wherein the correction comprises an initial guess; and

iteratively shifting the correction made to the contour via the initial guess to improve the

correction until the iterative shifting of the correction made to the contour results in a point on a targeted contour of one of the plurality of features embodied within the physical silicon wafer corresponding to the SEM images.

20. A system to reduce Optical Proximity Correction (OPC) model error, wherein the system comprises:

a mask created via a lithography process;

a physical silicon wafer having been fabricated using the mask, the physical silicon wafer having a plurality of features embodied therein as defined by the mask;

a semi-physical model of the mask created using physical parameters of the lithography process used to create the mask, the semi-physical model to specify contours of the plurality of features of the mask;

storage to capture Scanning Electron Microscope (SEM) images of the plurality of features

embodied within the physical silicon wafer;

an analysis unit to quantify differences between (a) the contours of the plurality of features of the mask as specified by the semi-physical model and (b) the plurality of features embodied within the physical silicon wafer as captured by the SEM images; and

the analysis unit to shift the contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.

21. The system of claim 20: wherein the analysis unit is to further perform a regularization operation to smooth the shifting of the contours of the plurality of features of the mask;

(2D) quantity representing the semi-physical model of the mask; and

wherein the regularization operation is to smooth the shifting of the contours to improve spatial stability and prevent over-fitting of the shifted contours of the plurality of features of the mask within the semi-physical model.

22. The system of claim 20:

wherein the analysis unit is to further train a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer and the contours of the plurality of features of the mask as specified by the semi- physical model;

wherein training the neural network comprises: inputting SEM image data of the physical silicon wafer fabricated using the mask into the neural network and inputting the shifted contours of the plurality of features of the mask as specified by the semi-physical model based on the quantified differences.

23. Non-transitory computer readable storage media having instructions stored thereupon that, when executed by a processor, the instructions cause the processor to perform operations for reducing Optical Proximity Correction (OPC) model error, wherein operations comprise:

creating a mask via a lithography process;

24. The non-transitory computer readable media of claim 23, wherein the instructions cause the processor to perform operations further comprising: performing a regularization operation to smooth the shifting of the contours of the plurality of features of the mask;

(2D) quantity representing the semi-physical model of the mask; and

25. The non-transitory computer readable media of claim 23, wherein the instructions cause the processor to perform operations further comprising:

training a neural network to describe a relationship between the captured SEM images of the plurality of features embodied within the physical silicon wafer and the contours of the plurality of features of the mask as specified by the semi-physical model;