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WO2017161626A1 - Manufacturing method for tft substrate and manufactured tft substrate - Google Patents

Manufacturing method for tft substrate and manufactured tft substrate Download PDF

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Publication number
WO2017161626A1
WO2017161626A1 PCT/CN2016/080190 CN2016080190W WO2017161626A1 WO 2017161626 A1 WO2017161626 A1 WO 2017161626A1 CN 2016080190 W CN2016080190 W CN 2016080190W WO 2017161626 A1 WO2017161626 A1 WO 2017161626A1
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Prior art keywords
region
gate
lightly doped
drain
source
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French (fr)
Chinese (zh)
Inventor
迟世鹏
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/106,812 priority Critical patent/US20180083142A1/en
Publication of WO2017161626A1 publication Critical patent/WO2017161626A1/en
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
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    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6719—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions having significant overlap between the lightly-doped drains and the gate electrodes, e.g. gate-overlapped LDD [GOLDD] TFTs
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
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    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
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    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate and a TFT substrate produced.
  • OLED is a promising flat panel display technology, which has excellent display performance, especially self-illumination, simple structure, ultra-thin, fast response, wide viewing angle, low power consumption and flexible display.
  • OLED has been on the eve of mass production. With the further development of research and the emergence of new technologies, OLED display devices will have a breakthrough development.
  • OLED can be divided into two types: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED), namely direct addressing and thin film transistor matrix addressing.
  • PMOLED passive matrix OLED
  • AMOLED active matrix OLED
  • the AMOLED has pixels arranged in an array, belongs to an active display type, has high luminous efficiency, and is generally used as a high-definition large-sized display device.
  • AMOLED is gradually maturing. In AMOLED, it is required to drive with current.
  • Low temperature Poly-Silicon (LTPS) has a large mobility, and a thin film transistor (Thin Film Transistor) is used as an active layer.
  • TFT can meet the current drive mode of AMOLED.
  • Low-temperature polysilicon thin film transistors (LTPS TFTs) have higher mobility and can obtain higher on-state currents.
  • LTPS TFTs will have a high off state when they are off. Current.
  • a Lightly Doped Offset structure can be employed.
  • Lightly doped compensation structures have been studied more, but the lightly doped compensation structure forms a high-resistance region, which reduces the on-state current of the LTPS TFT. In order to obtain a higher on-state current, the light-doped compensation structure can be improved. .
  • the light doping compensation region has no carrier accumulation and has high resistance.
  • the off-state current can be effectively reduced, but the TFT is in the on state.
  • the presence of a lightly doped compensation region also reduces the on-state current and affects the switching characteristics of the LTPS TFT.
  • An object of the present invention is to provide a method for fabricating a TFT substrate by setting first and second lightly doped compensation regions in the TFT to reduce the off-state current of the TFT while using the first gate and the second gate to form a double
  • the gate structure reduces the influence of the first and second lightly doped compensation regions on the on-state current of the TFT, the process is simple, the production cost is low, and the obtained TFT substrate has good electrical properties.
  • the object of the present invention is to provide a TFT substrate with a light doping compensation structure to reduce the off-state current of the TFT, and a double-gate structure to reduce the influence of the light doping compensation structure on the on-state current of the TFT, and the structure is simple, and Excellent electrical performance.
  • the present invention provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, forming an active layer on the substrate, performing ion implantation on the active layer, and defining a channel region on the active layer;
  • Step 2 depositing an insulating layer and a first metal layer on the active layer and the substrate, and patterning the first metal layer and the insulating layer by using a photomask to obtain a trench with the active layer a first gate and a gate insulating layer having equal widths and aligned ends in the width direction;
  • the first active gate and the gate insulating layer are used as a barrier layer, and the active layer is ion-implanted to obtain a first ion heavily doped region and a second ion heavily doped region respectively located on both sides of the channel region. ;
  • Step 3 depositing a second metal layer on the first gate, the active layer, and the substrate, and patterning the first metal layer by using a photomask to obtain two sides on the active layer And a source and a drain respectively contacting the first ion heavily doped region of the active layer and the second ion heavily doped region;
  • a portion of the doped region between the first gate and the drain is etched to remove a portion having a higher concentration of the upper layer, and a portion having a lower concentration of the lower layer is retained, thereby obtaining a source contact region and a channel region.
  • Step 4 depositing a passivation protective layer on the source, the drain, the active layer, and the first gate, and patterning the passivation protective layer by using a photomask corresponding to the source Forming a first through hole, a second through hole, and a third through hole respectively above the drain and the first gate;
  • Step 5 depositing a conductive layer on the passivation protective layer, using a photomask to the conductive layer Performing a patterning process to obtain a first contact electrode, a second contact electrode, and a second gate, wherein the first and second contact electrodes are respectively connected to the source and the drain via the first and second via holes, The second gate is connected to the first gate via the third via hole;
  • the width of the second gate is greater than the width of the first gate, and the two sides of the second gate respectively cover the first lightly doped compensation region and the second portion on both sides of the first gate Lightly doped compensation zone.
  • the active layer is formed on the substrate: an amorphous silicon film is deposited on the substrate, and the amorphous silicon film is converted into a low-temperature polysilicon film by a solid phase crystallization method. A reticle is patterned on the low temperature polysilicon film to obtain an active layer.
  • the channel region is an N-type ion lightly doped region, the source contact region and the drain contact region are P-type ion heavily doped regions, the first lightly doped compensation region, and the second lightly doped compensation
  • the region is a P-type ion lightly doped region; or the channel region is a P-type ion lightly doped region, and the source contact region and the drain contact region are N-type ion heavily doped regions, the first The lightly doped compensation region and the second lightly doped compensation region are N-type ion lightly doped regions.
  • a first overlap region is formed between a left side of the second gate and a right side of the source, and a second overlap region is formed between a right side of the second gate and a left side of the drain.
  • the materials of the first and second contact electrodes and the second gate are all transparent conductive metal oxides.
  • the present invention also provides a TFT substrate including a substrate, an active layer disposed on the substrate, a source and a drain disposed on the active layer and the substrate, and a gate disposed on the active layer a first insulating layer disposed on the gate insulating layer, a passivation protective layer disposed on the source, the drain, the active layer, and the first gate, and a passivation protective layer disposed on the gate insulating layer Passivating the first contact electrode, the second contact electrode, and the second gate on the protective layer;
  • the active layer includes a channel region in the middle, a source contact region and a drain contact region at both ends, a first lightly doped compensation region between the source contact region and the channel region, and a second lightly doped compensation region between the channel region and the drain contact region;
  • the first gate electrode and the gate insulating layer are equal in width to the channel region of the active layer and are aligned at both ends in the width direction;
  • the passivation protective layer is provided with a first through hole, a second through hole, and a third through hole respectively corresponding to the source, the drain, and the first gate; the first and second The contact electrodes are respectively connected to the source and the drain via the first and second via holes, and the second gate is connected to the first gate via the third via hole;
  • the width of the second gate is greater than the width of the first gate, and the two of the second gate The sides respectively cover the first lightly doped compensation region and the second lightly doped compensation region on both sides of the first gate.
  • the upper surfaces of the first lightly doped compensation region and the second lightly doped compensation region are lower than the upper surfaces of the channel region, the source contact region, and the drain contact region.
  • the channel region is an N-type ion lightly doped region, the source contact region and the drain contact region are P-type ion heavily doped regions, the first lightly doped compensation region, and the second lightly doped compensation
  • the region is a P-type ion lightly doped region; or the channel region is a P-type ion lightly doped region, and the source contact region and the drain contact region are N-type ion heavily doped regions, the first The lightly doped compensation region and the second lightly doped compensation region are N-type ion lightly doped regions.
  • a first overlap region is formed between a left side of the second gate and a right side of the source, and a second overlap region is formed between a right side of the second gate and a left side of the drain.
  • the materials of the first and second contact electrodes and the second gate are all transparent conductive metal oxides.
  • the present invention also provides a TFT substrate including a substrate, an active layer disposed on the substrate, a source and a drain disposed on the active layer and the substrate, and a gate disposed on the active layer a first insulating layer disposed on the gate insulating layer, a passivation protective layer disposed on the source, the drain, the active layer, and the first gate, and a passivation protective layer disposed on the gate insulating layer Passivating the first contact electrode, the second contact electrode, and the second gate on the protective layer;
  • the active layer includes a channel region in the middle, a source contact region and a drain contact region at both ends, a first lightly doped compensation region between the source contact region and the channel region, and a second lightly doped compensation region between the channel region and the drain contact region;
  • the first gate electrode and the gate insulating layer are equal in width to the channel region of the active layer and are aligned at both ends in the width direction;
  • the passivation protective layer is provided with a first through hole, a second through hole, and a third through hole respectively corresponding to the source, the drain, and the first gate; the first and second The contact electrodes are respectively connected to the source and the drain via the first and second via holes, and the second gate is connected to the first gate via the third via hole;
  • the width of the second gate is greater than the width of the first gate, and the two sides of the second gate respectively cover the first lightly doped compensation region and the second portion on both sides of the first gate Lightly doped compensation zone;
  • the upper surface of the first lightly doped compensation region and the second lightly doped compensation region is lower than the upper surfaces of the channel region, the source contact region, and the drain contact region;
  • the channel region is an N-type ion lightly doped region
  • the source contact region and the drain contact region are P-type ion heavily doped regions
  • the first lightly doped compensation region and the second lightly doped region
  • Miscellaneous compensation zone is P a type of lightly doped region
  • the channel region is a P-type ion lightly doped region
  • the source contact region and the drain contact region are N-type ion heavily doped regions
  • the compensation region and the second lightly doped compensation region are N-type ion lightly doped regions.
  • a method for fabricating a TFT substrate can reduce the off-state current of the TFT by providing first and second lightly doped compensation regions in the TFT;
  • the two gates form a double gate structure, which reduces the influence of the first and second lightly doped compensation regions on the on-state current of the TFT, wherein the first gate is connected to the second gate and controlled by the same gate voltage. No additional voltage signal is required; the process is simple, the production cost is low, and the obtained TFT substrate has good electrical properties.
  • the TFT substrate prepared by the invention adopts a light doping compensation structure to reduce the off-state current of the TFT, and adopts a double-gate structure to reduce the influence of the light doping compensation structure on the on-state current of the TFT, and has a simple structure and excellent electrical performance.
  • FIG. 1 is a flow chart showing a method of fabricating a TFT substrate of the present invention
  • step 1 is a schematic view of step 1 of a method of fabricating a TFT substrate of the present invention
  • 3-5 is a schematic diagram of the second step of the method for fabricating the TFT substrate of the present invention.
  • 6-7 is a schematic view showing a step 3 of a method for fabricating a TFT substrate of the present invention.
  • FIG. 8 is a schematic view showing a step 4 of a method of fabricating a TFT substrate of the present invention.
  • 9-10 are schematic views showing the fifth step of the method of fabricating the TFT substrate of the present invention.
  • the present invention provides a method for fabricating a TFT substrate, including the following steps:
  • Step 1 as shown in FIG. 2, a substrate 10 is provided, an active layer 20 is formed on the substrate 10, ion implantation is performed on the active layer 20, and a channel is defined on the active layer 20. District 21.
  • the substrate 10 is a glass substrate.
  • the specific implementation of forming the active layer 20 on the substrate 10 The method is as follows: depositing an amorphous silicon (a-Si) film on the substrate 10, and converting the amorphous silicon film into low temperature polycrystalline silicon by a solid phase crystallization (SPC, Solid-Phase-Crystallization) method (Low Temperature Poly) After the silicon film is formed, the low temperature polysilicon film is patterned by using a photomask to obtain the active layer 20.
  • a-Si amorphous silicon
  • SPC Solid-Phase-Crystallization
  • the threshold voltage of the channel region 21 can be adjusted to improve the electrical performance of the TFT.
  • Step 2 As shown in FIG. 3-5, an insulating layer 32 and a first metal layer 31 are sequentially deposited on the active layer 20 and the substrate 10, and the first metal layer 31 and the insulating layer are covered by a photomask. 32 performing a patterning process to obtain a first gate 40 and a gate insulating layer 30 which are equal in width to the channel region 21 of the active layer 20 and which are both ends aligned in the width direction;
  • the first gate 40 and the gate insulating layer 30 are used as a barrier layer, and the active layer 20 is ion-implanted to obtain first ion heavily doped regions 22 and second respectively located on both sides of the channel region 21 Ion heavily doped region 23.
  • the gate insulating layer 30 may be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the material of the first gate 40 may be a stack combination of one or more of aluminum (Al), molybdenum (Mo), copper (Cu), and silver (Ag).
  • Step 3 depositing a second metal layer 41 on the first gate 40, the active layer 20, and the substrate 10, and patterning the first metal layer 41 by using a photomask a source 51 and a drain which are located on both sides of the active layer 20 and are respectively in contact with the first ion heavily doped region 22 and the second ion heavily doped region 23 of the active layer 20 52;
  • a portion of the first ion heavily doped region 22 that is in contact with the source 51 is defined as a source contact region 24; a portion of the second ion heavily doped region 23 that is in contact with the drain 52 is defined as Drain contact region 25.
  • the material of the source 51 and the drain 52 may be a stack combination of one or more of aluminum (Al), molybdenum (Mo), copper (Cu), and silver (Ag).
  • the channel region 21 is an N-type ion lightly doped region
  • the source contact region 24, The drain contact region 25 is a P-type ion heavily doped region
  • the first lightly doped compensation region 26 and the second lightly doped compensation region 27 are P-type ion lightly doped regions; or, the channel region 21
  • the P-type ion lightly doped region, the source contact region 24 and the drain contact region 25 are N-type ion heavily doped regions, and the first lightly doped compensation region 26 and the second lightly doped compensation region 27 It is a lightly doped region of N-type ions.
  • the N-type ions are phosphorus ions or arsenic ions
  • the P-type ions are boron ions or gallium ions.
  • Step 4 depositing a passivation protective layer 60 on the source 51, the drain 52, the active layer 20, and the first gate 40, and using a mask to the passivation protective layer
  • the patterning process is performed to form a first via hole 61, a second via hole 62, and a third via hole 63 respectively corresponding to the source 51, the drain 52, and the first gate 40.
  • the passivation protective layer 60 may be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • Step 5 depositing a conductive layer 90 on the passivation protective layer 60, and patterning the conductive layer 90 by using a photomask to obtain a first contact electrode 71 and a second contact.
  • the electrode 72 and the second gate 80 are connected to the source 51 and the drain 52 via the first and second vias 61 and 62, respectively.
  • 80 is connected to the first gate 40 via the third via 63;
  • the width of the second gate 80 is greater than the width of the first gate 40, and the two sides of the second gate 80 respectively cover the first light doping compensation on both sides of the first gate 40.
  • the first and second lightly doped compensation regions 26, 27 are used as high resistance regions to reduce the off current of the TFT; the second gate 80 covers the first and second lightly doped compensation regions 26, 27, When the TFT is in an on state, the second gate 80 can cause the first and second lightly doped compensation regions 26, 27 to generate carrier accumulation to form a channel, and reduce the resistance of the first and second lightly doped compensation regions 26, 27.
  • the on-state current of the TFT is increased; when the TFT is off, the second gate 80 has no effect on the first and second lightly doped compensation regions 26, 27, and the first and second lightly doped compensation regions 26, 27 remain The high-impedance state can reduce the off-state current of the TFT.
  • a first overlap 810 is formed between the left side of the second gate 80 and the right side of the source 51, and the right side of the second gate 80 and the left side of the drain 52
  • a second overlap region 820 is formed therebetween.
  • the materials of the first and second contact electrodes 71, 72 and the second gate 80 are all transparent conductive metal oxides, preferably ITO (indium tin oxide).
  • one of the applications of the first and second contact electrodes 71 and 72 is to connect the source 51 and the drain 52 to the data line as a lead, and the second application is to serve as a test site. Description The voltage signal at the source 51 and the drain 52.
  • the off-state current of the TFT can be reduced; and the first gate 40 and the second gate 80 are used to form a double gate.
  • the pole structure reduces the influence of the first and second lightly doped compensation regions 26, 27 on the on-state current of the TFT, and the first gate 40 is connected to the second gate 80 and controlled by the same gate voltage, An additional voltage signal is required; the process is simple, the production cost is low, and the obtained TFT substrate has good electrical properties.
  • the present invention further provides a TFT substrate, comprising a substrate 10, an active layer 20 disposed on the substrate 10, and a source 51 and a drain disposed on the active layer 20 and the substrate 10.
  • a gate insulating layer 30 disposed on the active layer 20, a first gate 40 disposed on the gate insulating layer 30, and the source 51, the drain 52, and the active layer 20, and a passivation protective layer 60 on the first gate 40, and a first contact electrode 71, a second contact electrode 72, and a second gate 80 provided on the passivation protective layer 60;
  • the active layer 20 includes a channel region 21 in the middle, a source contact region 24 and a drain contact region 25 at both ends, and a first lightly doped region between the source contact region 24 and the channel region 21. a compensation region 26, and a second lightly doped compensation region 27 between the channel region 21 and the drain contact region 25;
  • the first gate electrode 40 and the gate insulating layer 30 are equal in width to the channel region 21 of the active layer 20 and are aligned at both ends in the width direction;
  • the passivation protective layer 60 is provided with a first through hole 61, a second through hole 62, and a third through hole 63 respectively corresponding to the source 51, the drain 52, and the first gate 40;
  • the first and second contact electrodes 71 and 72 are respectively connected to the source 51 and the drain 52 via the first and second vias 61 and 62, and the second gate 80 is connected to the first via the third via 63.
  • the gates 40 are connected;
  • the width of the second gate 80 is greater than the width of the first gate 40, and the two sides of the second gate 80 respectively cover the first light doping compensation on both sides of the first gate 40.
  • the upper surfaces of the first lightly doped compensation region 26 and the second lightly doped compensation region 27 are lower than the upper surfaces of the channel region 21, the source contact region 24, and the drain contact region 25.
  • the channel region 21 is an N-type ion lightly doped region, and the source contact region 24 and the drain contact region 25 are P-type ion heavily doped regions, and the first lightly doped compensation region 26
  • the second lightly doped compensation region 27 is a P-type ion lightly doped region; or the channel region 21 is a P-type ion lightly doped region, and the source contact region 24 and the drain contact region 25 are N.
  • the type Ion heavily doped region, the first lightly doped compensation region 26, and the second lightly doped compensation region 27 are N-type ion lightly doped regions.
  • the N-type ions are phosphorus ions or arsenic ions; and the P-type ions are boron ions or gallium ions.
  • a first overlap region 810 is formed between the left side of the second gate 80 and the right side of the source 51, and the right side of the second gate 80 and the left side of the drain 52 form a first Two overlapping regions 820.
  • the first overlap region 810 and the second overlap region 820 it is advantageous to increase the on-state current of the TFT.
  • the materials of the first and second contact electrodes 71, 72 and the second gate 80 are all transparent conductive metal oxides, preferably ITO (indium tin oxide).
  • one of the applications of the first and second contact electrodes 71 and 72 is to connect the source 51 and the drain 52 to the data line as a lead, and the second application is to serve as a test site.
  • the voltage signal at the source 51 and the drain 52 is described.
  • the substrate 10 is a glass substrate.
  • the material of the active layer 20 is low temperature polysilicon.
  • the material of the first gate 40, the source 51, and the drain 52 may be one or more of aluminum (Al), molybdenum (Mo), copper (Cu), and silver (Ag). Stack combination.
  • the gate insulating layer 30 and the passivation protective layer 60 may be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer. .
  • the TFT substrate is configured to form a double gate structure by using the first gate 40 and the second gate 80.
  • the first gate 40 and the second gate 80 are interconnected and controlled by the same gate voltage, and no additional is needed.
  • the voltage signal, the first and second lightly doped compensation regions 26, 27 between the first gate 40 and the source 51 and the drain 52 serve as a high resistance region, which can reduce the off current of the TFT;
  • the second gate 80 Covering the first and second lightly doped compensation regions 26, 27, the second gate 80 can cause the first and second lightly doped compensation regions 26, 27 to generate carrier accumulation to form a channel when the TFT is in an on state.
  • the resistances of the first and second lightly doped compensation regions 26, 27 are lowered to increase the on-state current of the TFT; when the TFT is off, the second gate 80 is free of the first and second lightly doped compensation regions 26, 27 As a result, the first and second lightly doped compensation regions 26, 27 maintain a high resistance state, which can reduce the off current of the TFT.
  • the method for fabricating a TFT substrate can reduce the off-state current of the TFT by providing the first and second lightly doped compensation regions in the TFT; and adopting the first gate and the second
  • the gate constitutes a double gate structure, which reduces the influence of the first and second lightly doped compensation regions on the on-state current of the TFT, wherein the first gate is connected to the second gate and controlled by the same gate voltage, An additional voltage signal is required; the process is simple, the production cost is low, and the obtained TFT substrate has good electrical properties.
  • the TFT substrate prepared by the invention adopts a light doping compensation structure to reduce the off-state current of the TFT, and adopts a double-gate structure to reduce the influence of the light doping compensation structure on the on-state current of the TFT, and has a simple structure and excellent electrical performance.

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Abstract

Provided is a manufacturing method for a TFT (thin film transistor) substrate, and a manufactured TFT substrate. The manufacturing method for the TFT substrate comprises arranging a first and a second lightly doped compensation area on a TFT to reduce the off-state current of the TFT; simultaneously using a first gate electrode and a second gate electrode to collectively form a double gate electrode structure, reducing the impact of the first and the second lightly doped compensation areas on the on-state current of the TFT; the first gate electrode and the second gate electrode are connected, are controlled by the same gate electrode voltage, and do not require an additional voltage signal; manufacturing is simple, production costs are low, and the manufactured TFT substrate has good electrical performance. The manufactured TFT substrate uses the lightly doped compensation structure to reduce the off-state current of the TFT, and uses the double gate electrode structure to reduce the impact of the lightly doped compensation areas on the on-state of the TFT; the structure is simple and electrical performance is excellent.

Description

TFT基板的制作方法及制得的TFT基板TFT substrate manufacturing method and TFT substrate obtained 技术领域Technical field

本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法及制得的TFT基板。The present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate and a TFT substrate produced.

背景技术Background technique

OLED是一种极具发展前景的平板显示技术，它具有十分优异的显示性能，特别是自发光、结构简单、超轻薄、响应速度快、宽视角、低功耗及可实现柔性显示等特性，被誉为“梦幻显示器”，再加上其生产设备投资远小于TFT-LCD，得到了各大显示器厂家的青睐，已成为显示技术领域中第三代显示器件的主力军。目前OLED已处于大规模量产的前夜，随着研究的进一步深入，新技术的不断涌现，OLED显示器件必将有一个突破性的发展。OLED is a promising flat panel display technology, which has excellent display performance, especially self-illumination, simple structure, ultra-thin, fast response, wide viewing angle, low power consumption and flexible display. Known as "Dream Display", coupled with its investment in production equipment is much smaller than TFT-LCD, it has been favored by major display manufacturers, and has become the main force of the third-generation display devices in the display technology field. At present, OLED has been on the eve of mass production. With the further development of research and the emergence of new technologies, OLED display devices will have a breakthrough development.

OLED按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED，PMOLED)和有源矩阵型OLED(Active Matrix OLED，AMOLED)两大类，即直接寻址和薄膜晶体管矩阵寻址两类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。According to the driving method, OLED can be divided into two types: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED), namely direct addressing and thin film transistor matrix addressing. Among them, the AMOLED has pixels arranged in an array, belongs to an active display type, has high luminous efficiency, and is generally used as a high-definition large-sized display device.

目前，AMOLED正在逐步走向成熟，在AMOLED中，需要以电流作为驱动，低温多晶硅(Low Temperature Poly-Silicon，LTPS)具有较大的迁移率，以其为有源层制作的薄膜晶体管(Thin Film Transistor，TFT)可以满足AMOLED的电流驱动模式。低温多晶硅薄膜晶体管(LTPS TFT)具有较高的迁移率，可以得到比较高的开态电流，但是由于LTPS中晶粒存在造成的缺陷，会导致LTPS TFT在关态时会出现较高的关态电流。为了减小LTPS TFT的关态电流，可以采用轻掺杂补偿(Lightly Doped Offset)结构。轻掺杂补偿结构目前已被研究的较多，但是轻掺杂补偿结构形成高阻区会降低LTPS TFT的开态电流，为了获得较高的开态电流，可以对轻掺杂补偿结构进行改进。At present, AMOLED is gradually maturing. In AMOLED, it is required to drive with current. Low temperature Poly-Silicon (LTPS) has a large mobility, and a thin film transistor (Thin Film Transistor) is used as an active layer. , TFT) can meet the current drive mode of AMOLED. Low-temperature polysilicon thin film transistors (LTPS TFTs) have higher mobility and can obtain higher on-state currents. However, due to defects in the presence of grains in LTPS, LTPS TFTs will have a high off state when they are off. Current. In order to reduce the off-state current of the LTPS TFT, a Lightly Doped Offset structure can be employed. Lightly doped compensation structures have been studied more, but the lightly doped compensation structure forms a high-resistance region, which reduces the on-state current of the LTPS TFT. In order to obtain a higher on-state current, the light-doped compensation structure can be improved. .

在具有轻掺杂补偿结构的LTPS TFT中，轻掺杂补偿区不存在载流子积累，具有较高的电阻，当TFT处于关态时，可以有效的降低关态电流，但在TFT开态时，轻掺杂补偿区的存在同样会降低开态电流，影响LTPS TFT的开关特性。 In the LTPS TFT with light doping compensation structure, the light doping compensation region has no carrier accumulation and has high resistance. When the TFT is in the off state, the off-state current can be effectively reduced, but the TFT is in the on state. The presence of a lightly doped compensation region also reduces the on-state current and affects the switching characteristics of the LTPS TFT.

发明内容Summary of the invention

本发明的目的在于提供一种TFT基板的制作方法，通过在TFT中设置第一、第二轻掺杂补偿区，降低TFT的关态电流，同时采用第一栅极与第二栅极组成双栅极结构，减小第一、第二轻掺杂补偿区对TFT开态电流的影响，制程简单，生产成本低，制得的TFT基板具有较好的电学性能。An object of the present invention is to provide a method for fabricating a TFT substrate by setting first and second lightly doped compensation regions in the TFT to reduce the off-state current of the TFT while using the first gate and the second gate to form a double The gate structure reduces the influence of the first and second lightly doped compensation regions on the on-state current of the TFT, the process is simple, the production cost is low, and the obtained TFT substrate has good electrical properties.

本发明的目的还在于提供一种TFT基板，采用轻掺杂补偿结构来降低TFT的关态电流，采用双栅极结构来降低轻掺杂补偿结构对TFT开态电流的影响，结构简单，且电学性能优异。The object of the present invention is to provide a TFT substrate with a light doping compensation structure to reduce the off-state current of the TFT, and a double-gate structure to reduce the influence of the light doping compensation structure on the on-state current of the TFT, and the structure is simple, and Excellent electrical performance.

为实现上述目的，本发明提供一种TFT基板的制作方法，包括如下步骤：To achieve the above object, the present invention provides a method for fabricating a TFT substrate, comprising the following steps:

步骤1、提供一基板，在所述基板上形成有源层，对所述有源层进行离子注入，并在所述有源层上定义出沟道区；Step 1, providing a substrate, forming an active layer on the substrate, performing ion implantation on the active layer, and defining a channel region on the active layer;

步骤2、在所述有源层、及基板上沉积绝缘层与第一金属层，采用一道光罩对所述第一金属层和绝缘层进行图形化处理，得到与所述有源层的沟道区的宽度相等并且在宽度方向上两端对齐的第一栅极与栅极绝缘层；Step 2, depositing an insulating layer and a first metal layer on the active layer and the substrate, and patterning the first metal layer and the insulating layer by using a photomask to obtain a trench with the active layer a first gate and a gate insulating layer having equal widths and aligned ends in the width direction;

以所述第一栅极和栅极绝缘层为阻挡层，对所述有源层进行离子注入，得到分别位于沟道区两侧的第一离子重掺杂区与第二离子重掺杂区；The first active gate and the gate insulating layer are used as a barrier layer, and the active layer is ion-implanted to obtain a first ion heavily doped region and a second ion heavily doped region respectively located on both sides of the channel region. ;

步骤3、在所述第一栅极、有源层、及基板上沉积第二金属层，采用一道光罩对所述第一金属层进行图形化处理，得到位于所述有源层的两侧且分别与所述有源层的第一离子重掺杂区与第二离子重掺杂区相接触的源极与漏极；Step 3, depositing a second metal layer on the first gate, the active layer, and the substrate, and patterning the first metal layer by using a photomask to obtain two sides on the active layer And a source and a drain respectively contacting the first ion heavily doped region of the active layer and the second ion heavily doped region;

将所述第一离子重掺杂区上与源极相接触的部分定义为源极接触区；将所述第二离子重掺杂区上与漏极相接触的部分定义为漏极接触区；Defining a portion of the first ion heavily doped region in contact with the source as a source contact region; defining a portion of the second ion heavily doped region in contact with the drain as a drain contact region;

以所述源极、漏极、及第一栅极为阻挡层，对所述第一离子重掺杂区上位于所述源极与第一栅极之间的部分、以及所述第二离子重掺杂区上位于第一栅极与漏极之间的部分进行蚀刻，去除上层离子浓度较高的部分，保留下层离子浓度较低的部分，从而得到位于所述源极接触区与沟道区之间的第一轻掺杂补偿区、以及位于所述沟道区与漏极接触区之间的第二轻掺杂补偿区；a portion of the first ion heavily doped region between the source and the first gate, and the second ion heavy with the source, the drain, and the first gate as a barrier layer A portion of the doped region between the first gate and the drain is etched to remove a portion having a higher concentration of the upper layer, and a portion having a lower concentration of the lower layer is retained, thereby obtaining a source contact region and a channel region. a first lightly doped compensation region therebetween, and a second lightly doped compensation region between the channel region and the drain contact region;

步骤4、在所述源极、漏极、有源层、及第一栅极上沉积钝化保护层，采用一道光罩对所述钝化保护层进行图形化处理，对应于所述源极、漏极、及第一栅极的上方分别形成第一通孔、第二通孔、及第三通孔；Step 4, depositing a passivation protective layer on the source, the drain, the active layer, and the first gate, and patterning the passivation protective layer by using a photomask corresponding to the source Forming a first through hole, a second through hole, and a third through hole respectively above the drain and the first gate;

步骤5、在所述钝化保护层上沉积导电层，采用一道光罩对所述导电层 进行图形化处理，得到第一接触电极、第二接触电极、及第二栅极，所述第一、第二接触电极分别经由第一、第二通孔与源极、漏极相连，所述第二栅极经由第三通孔与第一栅极相连；Step 5, depositing a conductive layer on the passivation protective layer, using a photomask to the conductive layer Performing a patterning process to obtain a first contact electrode, a second contact electrode, and a second gate, wherein the first and second contact electrodes are respectively connected to the source and the drain via the first and second via holes, The second gate is connected to the first gate via the third via hole;

所述第二栅极的宽度大于所述第一栅极的宽度，且所述第二栅极的两侧分别覆盖位于所述第一栅极两侧的第一轻掺杂补偿区与第二轻掺杂补偿区。The width of the second gate is greater than the width of the first gate, and the two sides of the second gate respectively cover the first lightly doped compensation region and the second portion on both sides of the first gate Lightly doped compensation zone.

所述步骤1中，在所述基板上形成有源层的具体实施方式为：在基板上沉积非晶硅薄膜，采用固相结晶方法将所述非晶硅薄膜转化为低温多晶硅薄膜后，采用一道光罩对所述低温多晶硅薄膜进行图形化处理，得到有源层。In the step 1, the active layer is formed on the substrate: an amorphous silicon film is deposited on the substrate, and the amorphous silicon film is converted into a low-temperature polysilicon film by a solid phase crystallization method. A reticle is patterned on the low temperature polysilicon film to obtain an active layer.

所述沟道区为N型离子轻掺杂区，所述源极接触区、漏极接触区为P型离子重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区为P型离子轻掺杂区；或者，所述沟道区为P型离子轻掺杂区，所述源极接触区、漏极接触区为N型离子重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区为N型离子轻掺杂区。The channel region is an N-type ion lightly doped region, the source contact region and the drain contact region are P-type ion heavily doped regions, the first lightly doped compensation region, and the second lightly doped compensation The region is a P-type ion lightly doped region; or the channel region is a P-type ion lightly doped region, and the source contact region and the drain contact region are N-type ion heavily doped regions, the first The lightly doped compensation region and the second lightly doped compensation region are N-type ion lightly doped regions.

所述第二栅极的左侧与源极的右侧之间形成第一重叠区，所述第二栅极的右侧与漏极的左侧之间形成第二重叠区。A first overlap region is formed between a left side of the second gate and a right side of the source, and a second overlap region is formed between a right side of the second gate and a left side of the drain.

所述第一、第二接触电极、及第二栅极的材料均为透明导电金属氧化物。The materials of the first and second contact electrodes and the second gate are all transparent conductive metal oxides.

本发明还提供一种TFT基板，包括基板、设于所述基板上的有源层、设于所述有源层及基板上的源极与漏极、设于所述有源层上的栅极绝缘层、设于所述栅极绝缘层上的第一栅极、设于所述源极、漏极、有源层、及第一栅极上的钝化保护层、以及设于所述钝化保护层上的第一接触电极、第二接触电极、及第二栅极；The present invention also provides a TFT substrate including a substrate, an active layer disposed on the substrate, a source and a drain disposed on the active layer and the substrate, and a gate disposed on the active layer a first insulating layer disposed on the gate insulating layer, a passivation protective layer disposed on the source, the drain, the active layer, and the first gate, and a passivation protective layer disposed on the gate insulating layer Passivating the first contact electrode, the second contact electrode, and the second gate on the protective layer;

所述有源层包括位于中间的沟道区、位于两端的源极接触区与漏极接触区、位于所述源极接触区与沟道区之间的第一轻掺杂补偿区、以及位于所述沟道区与漏极接触区之间的第二轻掺杂补偿区；The active layer includes a channel region in the middle, a source contact region and a drain contact region at both ends, a first lightly doped compensation region between the source contact region and the channel region, and a second lightly doped compensation region between the channel region and the drain contact region;

所述第一栅极、及栅极绝缘层与所述有源层的沟道区的宽度相等并且在宽度方向上两端对齐；The first gate electrode and the gate insulating layer are equal in width to the channel region of the active layer and are aligned at both ends in the width direction;

所述钝化保护层上设有分别对应于所述源极、漏极、及第一栅极上方的第一通孔、第二通孔、及第三通孔；所述第一、第二接触电极分别经由第一、第二通孔与源极、漏极相连，所述第二栅极经由第三通孔与第一栅极相连；The passivation protective layer is provided with a first through hole, a second through hole, and a third through hole respectively corresponding to the source, the drain, and the first gate; the first and second The contact electrodes are respectively connected to the source and the drain via the first and second via holes, and the second gate is connected to the first gate via the third via hole;

所述第二栅极的宽度大于所述第一栅极的宽度，且所述第二栅极的两 侧分别覆盖位于所述第一栅极两侧的第一轻掺杂补偿区与第二轻掺杂补偿区。The width of the second gate is greater than the width of the first gate, and the two of the second gate The sides respectively cover the first lightly doped compensation region and the second lightly doped compensation region on both sides of the first gate.

所述第一轻掺杂补偿区与第二轻掺杂补偿区的上表面低于所述沟道区、源极接触区、及漏极接触区的上表面。The upper surfaces of the first lightly doped compensation region and the second lightly doped compensation region are lower than the upper surfaces of the channel region, the source contact region, and the drain contact region.

所述沟道区为N型离子轻掺杂区，所述源极接触区、漏极接触区为P型离子重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区为P型离子轻掺杂区；或者，所述沟道区为P型离子轻掺杂区，所述源极接触区、漏极接触区为N型离子重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区为N型离子轻掺杂区。The channel region is an N-type ion lightly doped region, the source contact region and the drain contact region are P-type ion heavily doped regions, the first lightly doped compensation region, and the second lightly doped compensation The region is a P-type ion lightly doped region; or the channel region is a P-type ion lightly doped region, and the source contact region and the drain contact region are N-type ion heavily doped regions, the first The lightly doped compensation region and the second lightly doped compensation region are N-type ion lightly doped regions.

所述第二栅极的左侧与源极的右侧之间形成第一重叠区，所述第二栅极的右侧与漏极的左侧之间形成第二重叠区。A first overlap region is formed between a left side of the second gate and a right side of the source, and a second overlap region is formed between a right side of the second gate and a left side of the drain.

所述第一、第二接触电极、及第二栅极的材料均为透明导电金属氧化物。The materials of the first and second contact electrodes and the second gate are all transparent conductive metal oxides.

本发明还提供一种TFT基板，包括基板、设于所述基板上的有源层、设于所述有源层及基板上的源极与漏极、设于所述有源层上的栅极绝缘层、设于所述栅极绝缘层上的第一栅极、设于所述源极、漏极、有源层、及第一栅极上的钝化保护层、以及设于所述钝化保护层上的第一接触电极、第二接触电极、及第二栅极；The present invention also provides a TFT substrate including a substrate, an active layer disposed on the substrate, a source and a drain disposed on the active layer and the substrate, and a gate disposed on the active layer a first insulating layer disposed on the gate insulating layer, a passivation protective layer disposed on the source, the drain, the active layer, and the first gate, and a passivation protective layer disposed on the gate insulating layer Passivating the first contact electrode, the second contact electrode, and the second gate on the protective layer;

所述有源层包括位于中间的沟道区、位于两端的源极接触区与漏极接触区、位于所述源极接触区与沟道区之间的第一轻掺杂补偿区、以及位于所述沟道区与漏极接触区之间的第二轻掺杂补偿区；The active layer includes a channel region in the middle, a source contact region and a drain contact region at both ends, a first lightly doped compensation region between the source contact region and the channel region, and a second lightly doped compensation region between the channel region and the drain contact region;

所述第一栅极、及栅极绝缘层与所述有源层的沟道区的宽度相等并且在宽度方向上两端对齐；The first gate electrode and the gate insulating layer are equal in width to the channel region of the active layer and are aligned at both ends in the width direction;

所述钝化保护层上设有分别对应于所述源极、漏极、及第一栅极上方的第一通孔、第二通孔、及第三通孔；所述第一、第二接触电极分别经由第一、第二通孔与源极、漏极相连，所述第二栅极经由第三通孔与第一栅极相连；The passivation protective layer is provided with a first through hole, a second through hole, and a third through hole respectively corresponding to the source, the drain, and the first gate; the first and second The contact electrodes are respectively connected to the source and the drain via the first and second via holes, and the second gate is connected to the first gate via the third via hole;

所述第二栅极的宽度大于所述第一栅极的宽度，且所述第二栅极的两侧分别覆盖位于所述第一栅极两侧的第一轻掺杂补偿区与第二轻掺杂补偿区；The width of the second gate is greater than the width of the first gate, and the two sides of the second gate respectively cover the first lightly doped compensation region and the second portion on both sides of the first gate Lightly doped compensation zone;

其中，所述第一轻掺杂补偿区与第二轻掺杂补偿区的上表面低于所述沟道区、源极接触区、及漏极接触区的上表面；The upper surface of the first lightly doped compensation region and the second lightly doped compensation region is lower than the upper surfaces of the channel region, the source contact region, and the drain contact region;

其中，所述沟道区为N型离子轻掺杂区，所述源极接触区、漏极接触区为P型离子重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区为P 型离子轻掺杂区；或者，所述沟道区为P型离子轻掺杂区，所述源极接触区、漏极接触区为N型离子重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区为N型离子轻掺杂区。Wherein, the channel region is an N-type ion lightly doped region, the source contact region and the drain contact region are P-type ion heavily doped regions, the first lightly doped compensation region, and the second lightly doped region Miscellaneous compensation zone is P a type of lightly doped region; or the channel region is a P-type ion lightly doped region, the source contact region and the drain contact region are N-type ion heavily doped regions, the first lightly doped region The compensation region and the second lightly doped compensation region are N-type ion lightly doped regions.

本发明的有益效果：本发明提供的一种TFT基板的制作方法，通过在TFT中设置第一、第二轻掺杂补偿区，可降低TFT的关态电流；同时采用第一栅极与第二栅极组成双栅极结构，减小第一、第二轻掺杂补偿区对TFT开态电流的影响，所述第一栅极与第二栅极相连，由同一个栅极电压控制，不需要额外的电压信号；制程简单，生产成本低，制得的TFT基板具有较好的电学性能。本发明制得的TFT基板，采用轻掺杂补偿结构来降低TFT的关态电流，采用双栅极结构来降低轻掺杂补偿结构对TFT开态电流的影响，结构简单，且电学性能优异。Advantageous Effects of Invention According to the present invention, a method for fabricating a TFT substrate can reduce the off-state current of the TFT by providing first and second lightly doped compensation regions in the TFT; The two gates form a double gate structure, which reduces the influence of the first and second lightly doped compensation regions on the on-state current of the TFT, wherein the first gate is connected to the second gate and controlled by the same gate voltage. No additional voltage signal is required; the process is simple, the production cost is low, and the obtained TFT substrate has good electrical properties. The TFT substrate prepared by the invention adopts a light doping compensation structure to reduce the off-state current of the TFT, and adopts a double-gate structure to reduce the influence of the light doping compensation structure on the on-state current of the TFT, and has a simple structure and excellent electrical performance.

为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。The detailed description of the present invention and the accompanying drawings are to be understood,

附图说明DRAWINGS

下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。The technical solutions and other advantageous effects of the present invention will be apparent from the following detailed description of embodiments of the invention.

附图中，In the drawings,

图1为本发明的TFT基板的制作方法的流程图；1 is a flow chart showing a method of fabricating a TFT substrate of the present invention;

图2为本发明的TFT基板的制作方法的步骤1的示意图；2 is a schematic view of step 1 of a method of fabricating a TFT substrate of the present invention;

图3-5为本发明的TFT基板的制作方法的步骤2的示意图；3-5 is a schematic diagram of the second step of the method for fabricating the TFT substrate of the present invention;

图6-7为本发明的TFT基板的制作方法的步骤3的示意图；6-7 is a schematic view showing a step 3 of a method for fabricating a TFT substrate of the present invention;

图8为本发明的TFT基板的制作方法的步骤4的示意图；8 is a schematic view showing a step 4 of a method of fabricating a TFT substrate of the present invention;

图9-10为本发明的TFT基板的制作方法的步骤5的示意图。9-10 are schematic views showing the fifth step of the method of fabricating the TFT substrate of the present invention.

具体实施方式detailed description

为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。In order to further clarify the technical means and effects of the present invention, the following detailed description will be made in conjunction with the preferred embodiments of the invention and the accompanying drawings.

请参阅图1，本发明提供一种TFT基板的制作方法，包括如下步骤：Referring to FIG. 1 , the present invention provides a method for fabricating a TFT substrate, including the following steps:

步骤1、如图2所示，提供一基板10，在所述基板10上形成有源层20，对所述有源层20进行离子注入，并在所述有源层20上定义出沟道区21。Step 1, as shown in FIG. 2, a substrate 10 is provided, an active layer 20 is formed on the substrate 10, ion implantation is performed on the active layer 20, and a channel is defined on the active layer 20. District 21.

具体的，所述基板10为玻璃基板。Specifically, the substrate 10 is a glass substrate.

具体的，所述步骤1中，在所述基板10上形成有源层20的具体实施 方式为：在基板10上沉积非晶硅(Amorphous Silion，a-Si)薄膜，采用固相结晶(SPC，Solid-Phase-Crystallization)方法将所述非晶硅薄膜转化为低温多晶硅(Low Temperature Poly Silicon)薄膜后，采用一道光罩对所述低温多晶硅薄膜进行图形化处理，得到有源层20。Specifically, in the step 1, the specific implementation of forming the active layer 20 on the substrate 10 The method is as follows: depositing an amorphous silicon (a-Si) film on the substrate 10, and converting the amorphous silicon film into low temperature polycrystalline silicon by a solid phase crystallization (SPC, Solid-Phase-Crystallization) method (Low Temperature Poly) After the silicon film is formed, the low temperature polysilicon film is patterned by using a photomask to obtain the active layer 20.

具体的，所述步骤1中，通过对所述有源层20进行N型(或P型)离子注入，可以调节沟道区21的阈值电压，提升TFT的电学性能。Specifically, in the step 1, by performing N-type (or P-type) ion implantation on the active layer 20, the threshold voltage of the channel region 21 can be adjusted to improve the electrical performance of the TFT.

步骤2、如图3-5所示，在所述有源层20、及基板10上依次沉积绝缘层32与第一金属层31，采用一道光罩对所述第一金属层31和绝缘层32进行图形化处理，得到与所述有源层20的沟道区21的宽度相等并且在宽度方向上两端对齐的第一栅极40与栅极绝缘层30；Step 2: As shown in FIG. 3-5, an insulating layer 32 and a first metal layer 31 are sequentially deposited on the active layer 20 and the substrate 10, and the first metal layer 31 and the insulating layer are covered by a photomask. 32 performing a patterning process to obtain a first gate 40 and a gate insulating layer 30 which are equal in width to the channel region 21 of the active layer 20 and which are both ends aligned in the width direction;

以所述第一栅极40和栅极绝缘层30为阻挡层，对所述有源层20进行离子注入，得到分别位于沟道区21两侧的第一离子重掺杂区22与第二离子重掺杂区23。The first gate 40 and the gate insulating layer 30 are used as a barrier layer, and the active layer 20 is ion-implanted to obtain first ion heavily doped regions 22 and second respectively located on both sides of the channel region 21 Ion heavily doped region 23.

具体的，所述栅极绝缘层30可以为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。Specifically, the gate insulating layer 30 may be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.

具体的，所述第一栅极40的材料可以是铝(Al)、钼(Mo)、铜(Cu)、银(Ag)中的一种或多种的堆栈组合。Specifically, the material of the first gate 40 may be a stack combination of one or more of aluminum (Al), molybdenum (Mo), copper (Cu), and silver (Ag).

步骤3、如图6-7所示，在所述第一栅极40、有源层20、及基板10上沉积第二金属层41，采用一道光罩对所述第一金属层41进行图形化处理，得到位于所述有源层20的两侧且分别与所述有源层20的第一离子重掺杂区22与第二离子重掺杂区23相接触的源极51与漏极52；Step 3, as shown in FIG. 6-7, depositing a second metal layer 41 on the first gate 40, the active layer 20, and the substrate 10, and patterning the first metal layer 41 by using a photomask a source 51 and a drain which are located on both sides of the active layer 20 and are respectively in contact with the first ion heavily doped region 22 and the second ion heavily doped region 23 of the active layer 20 52;

将所述第一离子重掺杂区22上与源极51相接触的部分定义为源极接触区24；将所述第二离子重掺杂区23上与漏极52相接触的部分定义为漏极接触区25。A portion of the first ion heavily doped region 22 that is in contact with the source 51 is defined as a source contact region 24; a portion of the second ion heavily doped region 23 that is in contact with the drain 52 is defined as Drain contact region 25.

以所述源极51、漏极52、及第一栅极40为阻挡层，对所述第一离子重掺杂区22上位于所述源极51与第一栅极40之间的部分、以及所述第二离子重掺杂区23上位于第一栅极40与漏极52之间的部分进行蚀刻，去除上层离子浓度较高的部分，保留下层离子浓度较低的部分，从而得到位于所述源极接触区24与沟道区21之间的第一轻掺杂补偿区(Lightly Doped Offset)26、以及位于所述沟道区21与漏极接触区25之间的第二轻掺杂补偿区27。a portion of the first ion heavily doped region 22 between the source 51 and the first gate 40, with the source 51, the drain 52, and the first gate 40 as a barrier layer, And a portion of the second ion heavily doped region 23 located between the first gate 40 and the drain 52 is etched to remove a portion having a higher concentration of the upper layer ions, and a portion having a lower ion concentration is retained, thereby obtaining a location a first lightly doped offset set 26 between the source contact region 24 and the channel region 21, and a second lightly doped region between the channel region 21 and the drain contact region 25 Miscellaneous compensation zone 27.

具体的，所述源极51与漏极52的材料可以是铝(Al)、钼(Mo)、铜(Cu)、银(Ag)中的一种或多种的堆栈组合。Specifically, the material of the source 51 and the drain 52 may be a stack combination of one or more of aluminum (Al), molybdenum (Mo), copper (Cu), and silver (Ag).

具体的，所述沟道区21为N型离子轻掺杂区，所述源极接触区24、 漏极接触区25为P型离子重掺杂区，所述第一轻掺杂补偿区26、第二轻掺杂补偿区27为P型离子轻掺杂区；或者，所述沟道区21为P型离子轻掺杂区，所述源极接触区24、漏极接触区25为N型离子重掺杂区，所述第一轻掺杂补偿区26、第二轻掺杂补偿区27为N型离子轻掺杂区。优选的，所述N型离子为磷离子或砷离子；所述P型离子为硼离子或镓离子。Specifically, the channel region 21 is an N-type ion lightly doped region, and the source contact region 24, The drain contact region 25 is a P-type ion heavily doped region, and the first lightly doped compensation region 26 and the second lightly doped compensation region 27 are P-type ion lightly doped regions; or, the channel region 21 The P-type ion lightly doped region, the source contact region 24 and the drain contact region 25 are N-type ion heavily doped regions, and the first lightly doped compensation region 26 and the second lightly doped compensation region 27 It is a lightly doped region of N-type ions. Preferably, the N-type ions are phosphorus ions or arsenic ions; and the P-type ions are boron ions or gallium ions.

步骤4、如图8所示，在所述源极51、漏极52、有源层20、及第一栅极40上沉积钝化保护层60，采用一道光罩对所述钝化保护层60进行图形化处理，对应于所述源极51、漏极52、及第一栅极40的上方分别形成第一通孔61、第二通孔62、及第三通孔63。Step 4, as shown in FIG. 8, depositing a passivation protective layer 60 on the source 51, the drain 52, the active layer 20, and the first gate 40, and using a mask to the passivation protective layer The patterning process is performed to form a first via hole 61, a second via hole 62, and a third via hole 63 respectively corresponding to the source 51, the drain 52, and the first gate 40.

具体的，所述钝化保护层60可以为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。Specifically, the passivation protective layer 60 may be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.

步骤5、如图9-10所示，在所述钝化保护层60上沉积导电层90，采用一道光罩对所述导电层90进行图形化处理，得到第一接触电极71、第二接触电极72、及第二栅极80，所述第一、第二接触电极71、72分别经由第一、第二通孔61、62与源极51、漏极52相连，所述第二栅极80经由第三通孔63与第一栅极40相连；Step 5, as shown in FIG. 9-10, depositing a conductive layer 90 on the passivation protective layer 60, and patterning the conductive layer 90 by using a photomask to obtain a first contact electrode 71 and a second contact. The electrode 72 and the second gate 80 are connected to the source 51 and the drain 52 via the first and second vias 61 and 62, respectively. 80 is connected to the first gate 40 via the third via 63;

所述第二栅极80的宽度大于所述第一栅极40的宽度，且所述第二栅极80的两侧分别覆盖位于所述第一栅极40两侧的第一轻掺杂补偿区26与第二轻掺杂补偿区27。The width of the second gate 80 is greater than the width of the first gate 40, and the two sides of the second gate 80 respectively cover the first light doping compensation on both sides of the first gate 40. Zone 26 and second lightly doped compensation zone 27.

本发明采用第一、第二轻掺杂补偿区26、27作为高阻区，可降低TFT的关态电流；第二栅极80覆盖第一、第二轻掺杂补偿区26、27，在TFT开态时，第二栅极80可以使第一、第二轻掺杂补偿区26、27产生载流子积累形成沟道，降低第一、第二轻掺杂补偿区26、27的电阻，提高TFT的开态电流；在TFT关态时，第二栅极80对第一、第二轻掺杂补偿区26、27无影响，第一、第二轻掺杂补偿区26、27保持高阻状态，能够降低TFT的关态电流。The first and second lightly doped compensation regions 26, 27 are used as high resistance regions to reduce the off current of the TFT; the second gate 80 covers the first and second lightly doped compensation regions 26, 27, When the TFT is in an on state, the second gate 80 can cause the first and second lightly doped compensation regions 26, 27 to generate carrier accumulation to form a channel, and reduce the resistance of the first and second lightly doped compensation regions 26, 27. The on-state current of the TFT is increased; when the TFT is off, the second gate 80 has no effect on the first and second lightly doped compensation regions 26, 27, and the first and second lightly doped compensation regions 26, 27 remain The high-impedance state can reduce the off-state current of the TFT.

优选的，所述第二栅极80的左侧与源极51的右侧之间形成第一重叠区(overlap)810，所述第二栅极80的右侧与漏极52的左侧之间形成第二重叠区820。通过设置该第一重叠区810与第二重叠区820，可进一步提高TFT的开态电流。Preferably, a first overlap 810 is formed between the left side of the second gate 80 and the right side of the source 51, and the right side of the second gate 80 and the left side of the drain 52 A second overlap region 820 is formed therebetween. By providing the first overlap region 810 and the second overlap region 820, the on-state current of the TFT can be further increased.

具体的，所述第一、第二接触电极71、72、及第二栅极80的材料均为透明导电金属氧化物，优选为ITO(氧化铟锡)。Specifically, the materials of the first and second contact electrodes 71, 72 and the second gate 80 are all transparent conductive metal oxides, preferably ITO (indium tin oxide).

具体的，所述第一、第二接触电极71、72的用途之一为作为引线将所述源极51、及漏极52接至数据线，用途之二为作为测试位点，来测试所述 源极51、及漏极52处的电压信号。Specifically, one of the applications of the first and second contact electrodes 71 and 72 is to connect the source 51 and the drain 52 to the data line as a lead, and the second application is to serve as a test site. Description The voltage signal at the source 51 and the drain 52.

上述TFT基板的制作方法，通过在TFT中设置第一、第二轻掺杂补偿区26、27，可降低TFT的关态电流；同时采用第一栅极40与第二栅极80组成双栅极结构，减小第一、第二轻掺杂补偿区26、27对TFT开态电流的影响，所述第一栅极40与第二栅极80相连，由同一个栅极电压控制，不需要额外的电压信号；制程简单，生产成本低，制得的TFT基板具有较好的电学性能。In the above method for fabricating a TFT substrate, by providing first and second lightly doped compensation regions 26 and 27 in the TFT, the off-state current of the TFT can be reduced; and the first gate 40 and the second gate 80 are used to form a double gate. The pole structure reduces the influence of the first and second lightly doped compensation regions 26, 27 on the on-state current of the TFT, and the first gate 40 is connected to the second gate 80 and controlled by the same gate voltage, An additional voltage signal is required; the process is simple, the production cost is low, and the obtained TFT substrate has good electrical properties.

请参阅图10，本发明还提供一种TFT基板，包括基板10、设于所述基板10上的有源层20、设于所述有源层20及基板10上的源极51与漏极52、设于所述有源层20上的栅极绝缘层30、设于所述栅极绝缘层30上的第一栅极40、设于所述源极51、漏极52、有源层20、及第一栅极40上的钝化保护层60、以及设于所述钝化保护层60上的第一接触电极71、第二接触电极72、及第二栅极80；Referring to FIG. 10, the present invention further provides a TFT substrate, comprising a substrate 10, an active layer 20 disposed on the substrate 10, and a source 51 and a drain disposed on the active layer 20 and the substrate 10. a gate insulating layer 30 disposed on the active layer 20, a first gate 40 disposed on the gate insulating layer 30, and the source 51, the drain 52, and the active layer 20, and a passivation protective layer 60 on the first gate 40, and a first contact electrode 71, a second contact electrode 72, and a second gate 80 provided on the passivation protective layer 60;

所述有源层20包括位于中间的沟道区21、位于两端的源极接触区24与漏极接触区25、位于所述源极接触区24与沟道区21之间的第一轻掺杂补偿区26、以及位于所述沟道区21与漏极接触区25之间的第二轻掺杂补偿区27；The active layer 20 includes a channel region 21 in the middle, a source contact region 24 and a drain contact region 25 at both ends, and a first lightly doped region between the source contact region 24 and the channel region 21. a compensation region 26, and a second lightly doped compensation region 27 between the channel region 21 and the drain contact region 25;

所述第一栅极40、及栅极绝缘层30与所述有源层20的沟道区21的宽度相等并且在宽度方向上两端对齐；The first gate electrode 40 and the gate insulating layer 30 are equal in width to the channel region 21 of the active layer 20 and are aligned at both ends in the width direction;

所述钝化保护层60上设有分别对应于所述源极51、漏极52、及第一栅极40上方的第一通孔61、第二通孔62、及第三通孔63；所述第一、第二接触电极71、72分别经由第一、第二通孔61、62与源极51、漏极52相连，所述第二栅极80经由第三通孔63与第一栅极40相连；The passivation protective layer 60 is provided with a first through hole 61, a second through hole 62, and a third through hole 63 respectively corresponding to the source 51, the drain 52, and the first gate 40; The first and second contact electrodes 71 and 72 are respectively connected to the source 51 and the drain 52 via the first and second vias 61 and 62, and the second gate 80 is connected to the first via the third via 63. The gates 40 are connected;

所述第二栅极80的宽度大于所述第一栅极40的宽度，且所述第二栅极80的两侧分别覆盖位于所述第一栅极40两侧的第一轻掺杂补偿区26与第二轻掺杂补偿区27。The width of the second gate 80 is greater than the width of the first gate 40, and the two sides of the second gate 80 respectively cover the first light doping compensation on both sides of the first gate 40. Zone 26 and second lightly doped compensation zone 27.

具体的，所述第一轻掺杂补偿区26与第二轻掺杂补偿区27的上表面低于所述沟道区21、源极接触区24、及漏极接触区25的上表面。Specifically, the upper surfaces of the first lightly doped compensation region 26 and the second lightly doped compensation region 27 are lower than the upper surfaces of the channel region 21, the source contact region 24, and the drain contact region 25.

具体的，所述沟道区21为N型离子轻掺杂区，所述源极接触区24、漏极接触区25为P型离子重掺杂区，所述第一轻掺杂补偿区26、第二轻掺杂补偿区27为P型离子轻掺杂区；或者，所述沟道区21为P型离子轻掺杂区，所述源极接触区24、漏极接触区25为N型离子重掺杂区，所述第一轻掺杂补偿区26、第二轻掺杂补偿区27为N型离子轻掺杂区。优选的，所述N型离子为磷离子或砷离子；所述P型离子为硼离子或镓离子。 Specifically, the channel region 21 is an N-type ion lightly doped region, and the source contact region 24 and the drain contact region 25 are P-type ion heavily doped regions, and the first lightly doped compensation region 26 The second lightly doped compensation region 27 is a P-type ion lightly doped region; or the channel region 21 is a P-type ion lightly doped region, and the source contact region 24 and the drain contact region 25 are N. The type Ion heavily doped region, the first lightly doped compensation region 26, and the second lightly doped compensation region 27 are N-type ion lightly doped regions. Preferably, the N-type ions are phosphorus ions or arsenic ions; and the P-type ions are boron ions or gallium ions.

优选的，所述第二栅极80的左侧与源极51的右侧之间形成第一重叠区810，所述第二栅极80的右侧与漏极52的左侧之间形成第二重叠区820。通过设置该第一重叠区810与第二重叠区820，有利于提高TFT的开态电流。Preferably, a first overlap region 810 is formed between the left side of the second gate 80 and the right side of the source 51, and the right side of the second gate 80 and the left side of the drain 52 form a first Two overlapping regions 820. By providing the first overlap region 810 and the second overlap region 820, it is advantageous to increase the on-state current of the TFT.

具体的，所述第一、第二接触电极71、72、及第二栅极80的材料均为透明导电金属氧化物，优选为ITO(氧化铟锡)。Specifically, the materials of the first and second contact electrodes 71, 72 and the second gate 80 are all transparent conductive metal oxides, preferably ITO (indium tin oxide).

具体的，所述第一、第二接触电极71、72的用途之一为作为引线将所述源极51、及漏极52接至数据线，用途之二为作为测试位点，来测试所述源极51、及漏极52处的电压信号。Specifically, one of the applications of the first and second contact electrodes 71 and 72 is to connect the source 51 and the drain 52 to the data line as a lead, and the second application is to serve as a test site. The voltage signal at the source 51 and the drain 52 is described.

具体的，所述基板10为玻璃基板。Specifically, the substrate 10 is a glass substrate.

具体的，所述有源层20的材料为低温多晶硅。Specifically, the material of the active layer 20 is low temperature polysilicon.

具体的，所述第一栅极40、源极51、及漏极52的材料可以是铝(Al)、钼(Mo)、铜(Cu)、银(Ag)中的一种或多种的堆栈组合。Specifically, the material of the first gate 40, the source 51, and the drain 52 may be one or more of aluminum (Al), molybdenum (Mo), copper (Cu), and silver (Ag). Stack combination.

具体的，所述栅极绝缘层30与钝化保护层60可以为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。Specifically, the gate insulating layer 30 and the passivation protective layer 60 may be a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer. .

上述TFT基板，采用第一栅极40与第二栅极80组成双栅极结构，所述第一栅极40与第二栅极80互连，由同一个栅极电压控制，不需要额外的电压信号，第一栅极40与源极51和漏极52之间的第一、第二轻掺杂补偿区26、27作为高阻区，可降低TFT的关态电流；第二栅极80覆盖第一、第二轻掺杂补偿区26、27，在TFT开态时，第二栅极80可以使第一、第二轻掺杂补偿区26、27产生载流子积累形成沟道，降低第一、第二轻掺杂补偿区26、27的电阻，提高TFT的开态电流；在TFT关态时，第二栅极80对第一、第二轻掺杂补偿区26、27无影响，第一、第二轻掺杂补偿区26、27保持高阻状态，能够降低TFT的关态电流。The TFT substrate is configured to form a double gate structure by using the first gate 40 and the second gate 80. The first gate 40 and the second gate 80 are interconnected and controlled by the same gate voltage, and no additional is needed. The voltage signal, the first and second lightly doped compensation regions 26, 27 between the first gate 40 and the source 51 and the drain 52 serve as a high resistance region, which can reduce the off current of the TFT; the second gate 80 Covering the first and second lightly doped compensation regions 26, 27, the second gate 80 can cause the first and second lightly doped compensation regions 26, 27 to generate carrier accumulation to form a channel when the TFT is in an on state. The resistances of the first and second lightly doped compensation regions 26, 27 are lowered to increase the on-state current of the TFT; when the TFT is off, the second gate 80 is free of the first and second lightly doped compensation regions 26, 27 As a result, the first and second lightly doped compensation regions 26, 27 maintain a high resistance state, which can reduce the off current of the TFT.

综上所述，本发明提供的一种TFT基板的制作方法，通过在TFT中设置第一、第二轻掺杂补偿区，可降低TFT的关态电流；同时采用第一栅极与第二栅极组成双栅极结构，减小第一、第二轻掺杂补偿区对TFT开态电流的影响，所述第一栅极与第二栅极相连，由同一个栅极电压控制，不需要额外的电压信号；制程简单，生产成本低，制得的TFT基板具有较好的电学性能。本发明制得的TFT基板，采用轻掺杂补偿结构来降低TFT的关态电流，采用双栅极结构来降低轻掺杂补偿结构对TFT开态电流的影响，结构简单，且电学性能优异。In summary, the method for fabricating a TFT substrate provided by the present invention can reduce the off-state current of the TFT by providing the first and second lightly doped compensation regions in the TFT; and adopting the first gate and the second The gate constitutes a double gate structure, which reduces the influence of the first and second lightly doped compensation regions on the on-state current of the TFT, wherein the first gate is connected to the second gate and controlled by the same gate voltage, An additional voltage signal is required; the process is simple, the production cost is low, and the obtained TFT substrate has good electrical properties. The TFT substrate prepared by the invention adopts a light doping compensation structure to reduce the off-state current of the TFT, and adopts a double-gate structure to reduce the influence of the light doping compensation structure on the on-state current of the TFT, and has a simple structure and excellent electrical performance.

以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形 都应属于本发明权利要求的保护范围。 In the above, various other changes and modifications can be made in accordance with the technical solutions and technical concept of the present invention, and all such changes and modifications can be made by those skilled in the art. All should fall within the scope of protection of the claims of the present invention.

Claims (13)

一种TFT基板的制作方法，包括如下步骤：A method for fabricating a TFT substrate, comprising the following steps: 步骤1、提供一基板，在所述基板上形成有源层，对所述有源层进行离子注入，并在所述有源层上定义出沟道区；Step 1, providing a substrate, forming an active layer on the substrate, performing ion implantation on the active layer, and defining a channel region on the active layer; 步骤2、在所述有源层、及基板上依次沉积绝缘层与第一金属层，采用一道光罩对所述第一金属层和绝缘层进行图形化处理，得到与所述有源层的沟道区的宽度相等并且在宽度方向上两端对齐的第一栅极与栅极绝缘层；Step 2, sequentially depositing an insulating layer and a first metal layer on the active layer and the substrate, and patterning the first metal layer and the insulating layer by using a photomask to obtain an active layer a first gate and a gate insulating layer having the same width of the channel region and being aligned at both ends in the width direction; 以所述第一栅极和栅极绝缘层为阻挡层，对所述有源层进行离子注入，得到分别位于沟道区两侧的第一离子重掺杂区与第二离子重掺杂区；The first active gate and the gate insulating layer are used as a barrier layer, and the active layer is ion-implanted to obtain a first ion heavily doped region and a second ion heavily doped region respectively located on both sides of the channel region. ; 步骤3、在所述第一栅极、有源层、及基板上沉积第二金属层，采用一道光罩对所述第一金属层进行图形化处理，得到位于所述有源层的两侧且分别与所述有源层的第一离子重掺杂区与第二离子重掺杂区相接触的源极与漏极；Step 3, depositing a second metal layer on the first gate, the active layer, and the substrate, and patterning the first metal layer by using a photomask to obtain two sides on the active layer And a source and a drain respectively contacting the first ion heavily doped region of the active layer and the second ion heavily doped region; 将所述第一离子重掺杂区上与源极相接触的部分定义为源极接触区；将所述第二离子重掺杂区上与漏极相接触的部分定义为漏极接触区；Defining a portion of the first ion heavily doped region in contact with the source as a source contact region; defining a portion of the second ion heavily doped region in contact with the drain as a drain contact region; 以所述源极、漏极、及第一栅极为阻挡层，对所述第一离子重掺杂区上位于所述源极与第一栅极之间的部分、以及所述第二离子重掺杂区上位于第一栅极与漏极之间的部分进行蚀刻，去除上层离子浓度较高的部分，保留下层离子浓度较低的部分，从而得到位于所述源极接触区与沟道区之间的第一轻掺杂补偿区、以及位于所述沟道区与漏极接触区之间的第二轻掺杂补偿区；a portion of the first ion heavily doped region between the source and the first gate, and the second ion heavy with the source, the drain, and the first gate as a barrier layer A portion of the doped region between the first gate and the drain is etched to remove a portion having a higher concentration of the upper layer, and a portion having a lower concentration of the lower layer is retained, thereby obtaining a source contact region and a channel region. a first lightly doped compensation region therebetween, and a second lightly doped compensation region between the channel region and the drain contact region; 步骤4、在所述源极、漏极、有源层、及第一栅极上沉积钝化保护层，采用一道光罩对所述钝化保护层进行图形化处理，对应于所述源极、漏极、及第一栅极的上方分别形成第一通孔、第二通孔、及第三通孔；Step 4, depositing a passivation protective layer on the source, the drain, the active layer, and the first gate, and patterning the passivation protective layer by using a photomask corresponding to the source Forming a first through hole, a second through hole, and a third through hole respectively above the drain and the first gate; 步骤5、在所述钝化保护层上沉积导电层，采用一道光罩对所述导电层进行图形化处理，得到第一接触电极、第二接触电极、及第二栅极，所述第一、第二接触电极分别经由第一、第二通孔与源极、漏极相连，所述第二栅极经由第三通孔与第一栅极相连；Step 5, depositing a conductive layer on the passivation protective layer, and patterning the conductive layer by using a photomask to obtain a first contact electrode, a second contact electrode, and a second gate, the first The second contact electrode is connected to the source and the drain via the first and second via holes, and the second gate is connected to the first gate via the third via hole; 所述第二栅极的宽度大于所述第一栅极的宽度，且所述第二栅极的两侧分别覆盖位于所述第一栅极两侧的第一轻掺杂补偿区与第二轻掺杂补偿区。 The width of the second gate is greater than the width of the first gate, and the two sides of the second gate respectively cover the first lightly doped compensation region and the second portion on both sides of the first gate Lightly doped compensation zone. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤1中，在所述基板上形成有源层的具体实施方式为：在基板上沉积非晶硅薄膜，采用固相结晶方法将所述非晶硅薄膜转化为低温多晶硅薄膜后，采用一道光罩对所述低温多晶硅薄膜进行图形化处理，得到有源层。The method of fabricating a TFT substrate according to claim 1, wherein in the step 1, a method of forming an active layer on the substrate is: depositing an amorphous silicon film on the substrate, using a solid phase crystallization method After converting the amorphous silicon film into a low-temperature polysilicon film, the low-temperature polysilicon film is patterned by using a photomask to obtain an active layer. 如权利要求1所述的TFT基板的制作方法，其中，所述沟道区为N型离子轻掺杂区，所述源极接触区、漏极接触区为P型离子重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区为P型离子轻掺杂区；或者，所述沟道区为P型离子轻掺杂区，所述源极接触区、漏极接触区为N型离子重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区为N型离子轻掺杂区。The method of fabricating a TFT substrate according to claim 1, wherein the channel region is an N-type ion lightly doped region, and the source contact region and the drain contact region are P-type ion heavily doped regions. The first lightly doped compensation region and the second lightly doped compensation region are P-type ion lightly doped regions; or the channel region is a P-type ion lightly doped region, the source contact region and the drain The contact region is an N-type ion heavily doped region, and the first lightly doped compensation region and the second lightly doped compensation region are N-type ion lightly doped regions. 如权利要求1所述的TFT基板的制作方法，其中，所述第二栅极的左侧与源极的右侧之间形成第一重叠区，所述第二栅极的右侧与漏极的左侧之间形成第二重叠区。The method of fabricating a TFT substrate according to claim 1, wherein a first overlap region is formed between a left side of the second gate and a right side of the source, and a right side and a drain of the second gate A second overlap region is formed between the left sides. 如权利要求1所述的TFT基板的制作方法，其中，所述第一、第二接触电极、及第二栅极的材料均为透明导电金属氧化物。The method of fabricating a TFT substrate according to claim 1, wherein the materials of the first and second contact electrodes and the second gate are all transparent conductive metal oxides. 一种TFT基板，包括基板、设于所述基板上的有源层、设于所述有源层及基板上的源极与漏极、设于所述有源层上的栅极绝缘层、设于所述栅极绝缘层上的第一栅极、设于所述源极、漏极、有源层、及第一栅极上的钝化保护层、以及设于所述钝化保护层上的第一接触电极、第二接触电极、及第二栅极；A TFT substrate includes a substrate, an active layer disposed on the substrate, a source and a drain disposed on the active layer and the substrate, a gate insulating layer disposed on the active layer, a first gate disposed on the gate insulating layer, a passivation protective layer disposed on the source, the drain, the active layer, and the first gate, and a passivation protective layer disposed on the gate insulating layer a first contact electrode, a second contact electrode, and a second gate; 所述有源层包括位于中间的沟道区、位于两端的源极接触区与漏极接触区、位于所述源极接触区与沟道区之间的第一轻掺杂补偿区、以及位于所述沟道区与漏极接触区之间的第二轻掺杂补偿区；The active layer includes a channel region in the middle, a source contact region and a drain contact region at both ends, a first lightly doped compensation region between the source contact region and the channel region, and a second lightly doped compensation region between the channel region and the drain contact region; 所述第一栅极、及栅极绝缘层与所述有源层的沟道区的宽度相等并且在宽度方向上两端对齐；The first gate electrode and the gate insulating layer are equal in width to the channel region of the active layer and are aligned at both ends in the width direction; 所述钝化保护层上设有分别对应于所述源极、漏极、及第一栅极上方的第一通孔、第二通孔、及第三通孔；所述第一、第二接触电极分别经由第一、第二通孔与源极、漏极相连，所述第二栅极经由第三通孔与第一栅极相连；The passivation protective layer is provided with a first through hole, a second through hole, and a third through hole respectively corresponding to the source, the drain, and the first gate; the first and second The contact electrodes are respectively connected to the source and the drain via the first and second via holes, and the second gate is connected to the first gate via the third via hole; 所述第二栅极的宽度大于所述第一栅极的宽度，且所述第二栅极的两侧分别覆盖位于所述第一栅极两侧的第一轻掺杂补偿区与第二轻掺杂补偿区。The width of the second gate is greater than the width of the first gate, and the two sides of the second gate respectively cover the first lightly doped compensation region and the second portion on both sides of the first gate Lightly doped compensation zone. 如权利要求6所述的TFT基板，其中，所述第一轻掺杂补偿区与第二轻掺杂补偿区的上表面低于所述沟道区、源极接触区、及漏极接触区的 上表面。The TFT substrate of claim 6, wherein upper surfaces of the first lightly doped compensation region and the second lightly doped compensation region are lower than the channel region, the source contact region, and the drain contact region of Upper surface. 如权利要求6所述的TFT基板，其中，所述沟道区为N型离子轻掺杂区，所述源极接触区、漏极接触区为P型离子重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区为P型离子轻掺杂区；或者，所述沟道区为P型离子轻掺杂区，所述源极接触区、漏极接触区为N型离子重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区为N型离子轻掺杂区。The TFT substrate according to claim 6, wherein the channel region is an N-type ion lightly doped region, and the source contact region and the drain contact region are P-type ion heavily doped regions, the first The lightly doped compensation region and the second lightly doped compensation region are P-type ion lightly doped regions; or the channel region is a P-type ion lightly doped region, and the source contact region and the drain contact region are The N-type ion heavily doped region, the first lightly doped compensation region and the second lightly doped compensation region are N-type ion lightly doped regions. 如权利要求6所述的TFT基板，其中，所述第二栅极的左侧与源极的右侧之间形成第一重叠区，所述第二栅极的右侧与漏极的左侧之间形成第二重叠区。The TFT substrate according to claim 6, wherein a first overlap region is formed between a left side of the second gate and a right side of the source, and a right side of the second gate and a left side of the drain A second overlap region is formed between them. 如权利要求6所述的TFT基板，其中，所述第一、第二接触电极、及第二栅极的材料均为透明导电金属氧化物。The TFT substrate according to claim 6, wherein the materials of the first and second contact electrodes and the second gate are all transparent conductive metal oxides. 一种TFT基板，包括基板、设于所述基板上的有源层、设于所述有源层及基板上的源极与漏极、设于所述有源层上的栅极绝缘层、设于所述栅极绝缘层上的第一栅极、设于所述源极、漏极、有源层、及第一栅极上的钝化保护层、以及设于所述钝化保护层上的第一接触电极、第二接触电极、及第二栅极；A TFT substrate includes a substrate, an active layer disposed on the substrate, a source and a drain disposed on the active layer and the substrate, a gate insulating layer disposed on the active layer, a first gate disposed on the gate insulating layer, a passivation protective layer disposed on the source, the drain, the active layer, and the first gate, and a passivation protective layer disposed on the gate insulating layer a first contact electrode, a second contact electrode, and a second gate; 所述有源层包括位于中间的沟道区、位于两端的源极接触区与漏极接触区、位于所述源极接触区与沟道区之间的第一轻掺杂补偿区、以及位于所述沟道区与漏极接触区之间的第二轻掺杂补偿区；The active layer includes a channel region in the middle, a source contact region and a drain contact region at both ends, a first lightly doped compensation region between the source contact region and the channel region, and a second lightly doped compensation region between the channel region and the drain contact region; 所述第一栅极、及栅极绝缘层与所述有源层的沟道区的宽度相等并且在宽度方向上两端对齐；The first gate electrode and the gate insulating layer are equal in width to the channel region of the active layer and are aligned at both ends in the width direction; 所述钝化保护层上设有分别对应于所述源极、漏极、及第一栅极上方的第一通孔、第二通孔、及第三通孔；所述第一、第二接触电极分别经由第一、第二通孔与源极、漏极相连，所述第二栅极经由第三通孔与第一栅极相连；The passivation protective layer is provided with a first through hole, a second through hole, and a third through hole respectively corresponding to the source, the drain, and the first gate; the first and second The contact electrodes are respectively connected to the source and the drain via the first and second via holes, and the second gate is connected to the first gate via the third via hole; 所述第二栅极的宽度大于所述第一栅极的宽度，且所述第二栅极的两侧分别覆盖位于所述第一栅极两侧的第一轻掺杂补偿区与第二轻掺杂补偿区；The width of the second gate is greater than the width of the first gate, and the two sides of the second gate respectively cover the first lightly doped compensation region and the second portion on both sides of the first gate Lightly doped compensation zone; 其中，所述第一轻掺杂补偿区与第二轻掺杂补偿区的上表面低于所述沟道区、源极接触区、及漏极接触区的上表面；The upper surface of the first lightly doped compensation region and the second lightly doped compensation region is lower than the upper surfaces of the channel region, the source contact region, and the drain contact region; 其中，所述沟道区为N型离子轻掺杂区，所述源极接触区、漏极接触区为P型离子重掺杂区，所述第一轻掺杂补偿区、第二轻掺杂补偿区为P型离子轻掺杂区；或者，所述沟道区为P型离子轻掺杂区，所述源极接触区、漏极接触区为N型离子重掺杂区，所述第一轻掺杂补偿区、第二轻掺 杂补偿区为N型离子轻掺杂区。Wherein, the channel region is an N-type ion lightly doped region, the source contact region and the drain contact region are P-type ion heavily doped regions, the first lightly doped compensation region, and the second lightly doped region The impurity compensation region is a P-type ion lightly doped region; or the channel region is a P-type ion lightly doped region, and the source contact region and the drain contact region are N-type ion heavily doped regions, First lightly doped compensation zone, second lightly doped The impurity compensation region is an N-type ion lightly doped region. 如权利要求11所述的TFT基板，其中，所述第二栅极的左侧与源极的右侧之间形成第一重叠区，所述第二栅极的右侧与漏极的左侧之间形成第二重叠区。The TFT substrate according to claim 11, wherein a first overlap region is formed between a left side of the second gate and a right side of the source, and a right side of the second gate and a left side of the drain A second overlap region is formed between them. 如权利要求11所述的TFT基板，其中，所述第一、第二接触电极、及第二栅极的材料均为透明导电金属氧化物。 The TFT substrate according to claim 11, wherein the materials of the first and second contact electrodes and the second gate are all transparent conductive metal oxides.
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