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WO2017031773A1 - 一种goa电路及液晶显示器 - Google Patents

一种goa电路及液晶显示器 Download PDF

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Publication number
WO2017031773A1
WO2017031773A1 PCT/CN2015/088378 CN2015088378W WO2017031773A1 WO 2017031773 A1 WO2017031773 A1 WO 2017031773A1 CN 2015088378 W CN2015088378 W CN 2015088378W WO 2017031773 A1 WO2017031773 A1 WO 2017031773A1
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WO
WIPO (PCT)
Prior art keywords
transistor
clock
control
signal
goa
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/088378
Other languages
English (en)
French (fr)
Inventor
赵莽
肖军城
田勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd, Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/781,293 priority Critical patent/US9799286B2/en
Publication of WO2017031773A1 publication Critical patent/WO2017031773A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystals, and in particular to a GOA circuit and a liquid crystal display.
  • All Gate The On function refers to setting all the gate driving signals in the GOA circuit to an active level to simultaneously charge all horizontal scanning lines, thereby clearing the residual charge of each pixel in the liquid crystal display to solve the residual image when the machine is turned on and off. problem.
  • the technical problem to be solved by the present invention is to provide a GOA circuit and a liquid crystal display, which can avoid generating redundant pulse signals on the horizontal scanning line before the output of the first gate driving signal, thereby ensuring normal operation of the GOA circuit.
  • a technical solution adopted by the present invention is to provide a GOA circuit for a liquid crystal display, the GOA circuit including a plurality of cascaded GOA units, each GOA unit for transmitting a clock at the first stage And driving the corresponding horizontal scanning line in the display area under the driving of the second-level clock, the first control clock, and the second control clock, and the first-level clock and the second-level clock are used to control the level transmission of the GOA unit.
  • the input of the signal and the generation of the gate drive signal, the first control clock and the second control clock are used to control the gate drive signal to be at a predetermined level, wherein the level transfer signal is a start pulse signal or a gate of an adjacent GOA unit
  • the driving signal; the GOA circuit further includes a control module, configured to: after the GOA circuit simultaneously charges all the horizontal scanning lines, shielding the first-level clock and the second-level clock to make the first control clock and the second control clock Controlling the gate drive signal on the horizontal scan line to discharge to a predetermined level, thereby avoiding redundancy on the horizontal scan line before the output of the first gate drive signal
  • the control module includes a first control transistor and a second control transistor.
  • the first ends of the first control transistor and the second control transistor are connected to each other to receive an enable signal, and the second terminal of the first control transistor and the second control crystal Corresponding to connecting the first-stage clock and the second-stage clock, the third end of the first control transistor and the second control transistor are connected to the GOA unit, wherein after the GOA circuit simultaneously charges all the horizontal scanning lines, the enabling signal is controlled.
  • the GOA circuit receives the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, wherein the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal operate in the GOA circuit
  • the cycle is time-divisionally effective;
  • the GOA circuit includes a first GOA sub-circuit formed by cascading odd-numbered GOA units, and the first GOA sub-circuit is in the The odd-level horizontal scanning lines are charged by the level-clocked clock, the second-stage clock, the first control clock, and the second control clock; wherein, in the first GOA sub-circuit, the first-stage clock and the second The stepping clock corresponds to the first clock signal and the third clock signal, and the first control clock and the second control clock correspond to the second clock signal and the fourth clock signal; the GOA
  • the first control transistor and the second control transistor are PMOS transistors, and the first end, the second end, and the third end of the first control transistor and the second control transistor correspond to a gate, a drain, and a source of the PMOS transistor; When the enable signal is a high level signal, the first control transistor and the second control transistor are turned off.
  • another technical solution adopted by the present invention is to provide a GOA circuit for a liquid crystal display, the GOA circuit including a plurality of cascaded GOA units, each GOA unit being used for transmitting in the first stage
  • the corresponding horizontal scanning line in the display area is charged by the clock, the second-level clock, the first control clock, and the second control clock, and the first-level clock and the second-stage clock are used to control the level of the GOA unit.
  • the input of the signal and the generation of the gate driving signal, the first control clock and the second control clock are used to control the gate driving signal to be at a predetermined level, wherein the level signal is a start pulse signal or a gate of an adjacent GOA unit
  • the GOA circuit further includes a control module, configured to: after the GOA circuit simultaneously charges all the horizontal scanning lines, shielding the first-level clock and the second-level clock to make the first control clock and the second control
  • the gate drive signal on the clocked horizontal scan line is discharged to a predetermined level, thereby avoiding redundancy on the horizontal scan line before the output of the first gate drive signal Pulse signal.
  • the control module includes a first control transistor and a second control transistor.
  • the first ends of the first control transistor and the second control transistor are connected to each other to receive an enable signal, and the second end of the first control transistor and the second control crystal correspond to Connecting the first stage clock and the second stage clock, the third end of the first control transistor and the second control transistor are connected to the GOA unit, wherein after the GOA circuit simultaneously charges all the horizontal scan lines, the enable signal controls the first
  • the control transistor and the second control transistor are turned off to shield the first stage clock and the second stage clock, so that the first control clock and the second control clock control the gate driving signals on all horizontal scanning lines to discharge to a predetermined level.
  • the first control transistor and the second control transistor are PMOS transistors, and the first end, the second end, and the third end of the first control transistor and the second control transistor correspond to a gate, a drain, and a source of the PMOS transistor; When the enable signal is a high level signal, the first control transistor and the second control transistor are turned off.
  • the first control transistor and the second control transistor are NMOS transistors, and the first end, the second end, and the third end of the first control transistor and the second control transistor correspond to a gate, a drain, and a source of the NMOS transistor; When the control signal is a low level signal, the first control transistor and the second control transistor are turned off.
  • the GOA circuit receives the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, wherein the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are in the GOA circuit
  • the duty cycle is time-divisionally effective;
  • the GOA circuit includes a first GOA sub-circuit formed by cascading odd-numbered GOA units, the first GOA sub-circuit transmitting clock at the first stage, the second-level clock, the first control clock, and the second Controlling the driving of the clock to charge the odd-numbered horizontal scanning lines; wherein, in the first GOA sub-circuit, the first-level clock and the second-level clock correspond to the first clock signal and the third clock signal, and the first control The clock and the second control clock correspond to the second clock signal and the fourth clock signal;
  • the GOA circuit further includes a control module corresponding to the first GOA sub-circuit, which is recorded as a first control module, and the first control module is used in the first GOA sub- In the
  • the GOA circuit further includes a second GOA sub-circuit formed by cascading even-numbered GOA units, and the second GOA sub-circuit is driven by the first-stage clock, the second-stage clock, the first control clock, and the second control clock. And charging the horizontal scanning lines of the even-numbered stages; wherein, in the second GOA sub-circuit, the first-level clock, the second-level clock correspond to the second clock signal, the fourth clock signal, the first control clock, and the second The control clock corresponds to the first clock signal and the third clock signal; the GOA circuit further includes a control module corresponding to the second GOA sub-circuit, which is recorded as a second control module, and the second control module is configured to block in the second GOA sub-circuit The second clock signal and the fourth clock signal are configured to cause the first clock signal and the third clock signal to control the gate driving signal on the horizontal scanning line of the even-numbered stage to be discharged to a predetermined level.
  • the GOA unit includes a forward and reverse scanning unit, an input control unit, a pull-up maintaining unit, an output control unit, a GAS signal acting unit, and a bootstrap capacitor unit.
  • the forward and reverse scanning unit includes a first transistor, a second transistor, and a third a transistor and a fourth transistor, the gate of the first transistor receives the first scan control signal, the source of the first transistor receives the gate drive signal output by the next stage GOA unit, and the gate of the second transistor receives the second scan control signal
  • the source of the second transistor receives the gate drive signal outputted by the GOA unit of the previous stage, the drains of the first transistor and the second transistor are connected to each other and then connected to the input control unit, and the gate of the third transistor receives the first scan control a signal, a source of the third transistor receives a third control clock, a gate of the fourth transistor receives a second scan control signal, a source of the fourth transistor receives a fourth control clock, and drains of the third transistor and the fourth transistor are
  • the gate of the seventh transistor is connected to the drain of the fifth transistor, the source of the seventh transistor is connected to the common signal point, the drain of the seventh transistor is connected to the first constant voltage source, and the gate of the ninth transistor is connected to the third The drain of the transistor and the fourth transistor are connected, the source of the ninth transistor is connected to the second constant voltage source, the drain of the ninth transistor is connected to the common signal point, and the gate of the tenth transistor is connected to the common signal point, the tenth The source of the transistor is connected to the gate driving signal, the drain of the tenth transistor is connected to the first constant voltage source, and one end of the first capacitor is connected to the first constant voltage source, and the other end of the first capacitor and the common signal
  • the output control unit includes an eleventh transistor and a second capacitor.
  • the gate of the eleventh transistor is connected to the gate signal point, and the drain of the eleventh transistor is connected to the gate driving signal, and the source of the eleventh transistor Receiving a fourth-stage clock, one end of the second capacitor is connected to the gate signal point, and the other end of the second capacitor is connected to the gate driving signal;
  • the GAS signal acting unit includes a thirteenth transistor and a fourteenth transistor, the thirteenth The gate of the transistor, the gate and the drain of the fourteenth transistor receive the GAS signal, the drain of the thirteenth transistor is connected to the first constant voltage source, the source of the thirteenth transistor is connected to the common signal point, and the thirteenth transistor is connected The source is connected to the gate driving signal;
  • the bootstrap capacitor unit includes a bootstrap capacitor, one end of the bootstrap capacitor is connected to the gate driving signal, and the other end of the bootstrap capacitor is connected to the ground signal;
  • the third-level transmission clock and the fourth-level transmission clock correspond to the first-level transmission clock, the second-level transmission clock, or the second-level transmission clock, and the first-level transmission clock
  • the third control clock and the fourth control clock correspond to the first Control clock, second control clock or second control clock, first control clock.
  • the GOA unit further includes a voltage stabilizing unit, the voltage stabilizing unit includes an eighth transistor, the gate of the eighth transistor is connected to the second constant voltage source, the drain of the eighth transistor is connected to the drain of the fifth transistor, and the eighth transistor The source is connected to the gate signal point.
  • the GOA unit further includes a pull-up auxiliary unit, the pull-up auxiliary unit includes a twelfth transistor, the gate of the twelfth transistor is connected to the drains of the first transistor and the second transistor, and the source and the common of the twelfth transistor The signal points are connected, and the drains of the twelve transistors are connected to the first constant voltage source.
  • a liquid crystal display including a GOA circuit including a plurality of cascaded GOA units, each GOA unit for transmitting a clock at the first stage And driving the corresponding horizontal scanning line in the display area under the driving of the second-level clock, the first control clock, and the second control clock, and the first-level clock and the second-level clock are used to control the level transmission of the GOA unit.
  • the input of the signal and the generation of the gate drive signal, the first control clock and the second control clock are used to control the gate drive signal to be at a predetermined level, wherein the level transfer signal is a start pulse signal or a gate of an adjacent GOA unit
  • the driving signal; the GOA circuit further includes a control module, configured to: after the GOA circuit simultaneously charges all the horizontal scanning lines, shielding the first-level clock and the second-level clock to make the first control clock and the second control clock Controlling the gate drive signal on the horizontal scan line to discharge to a predetermined level, thereby avoiding redundancy on the horizontal scan line before the output of the first gate drive signal Pulse signal.
  • the control module includes a first control transistor and a second control transistor.
  • the first ends of the first control transistor and the second control transistor are connected to each other to receive an enable signal, and the second end of the first control transistor and the second control crystal correspond to Connecting the first stage clock and the second stage clock, the third end of the first control transistor and the second control transistor are connected to the GOA unit, wherein after the GOA circuit simultaneously charges all the horizontal scan lines, the enable signal controls the first
  • the control transistor and the second control transistor are turned off to shield the first stage clock and the second stage clock, so that the first control clock and the second control clock control the gate driving signals on all horizontal scanning lines to discharge to a predetermined level.
  • the first control transistor and the second control transistor are PMOS transistors, and the first end, the second end, and the third end of the first control transistor and the second control transistor correspond to a gate, a drain, and a source of the PMOS transistor; When the enable signal is a high level signal, the first control transistor and the second control transistor are turned off.
  • the first control transistor and the second control transistor are NMOS transistors, and the first end, the second end, and the third end of the first control transistor and the second control transistor correspond to a gate, a drain, and a source of the NMOS transistor; When the control signal is a low level signal, the first control transistor and the second control transistor are turned off.
  • the GOA circuit receives the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, wherein the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are in the GOA circuit
  • the duty cycle is time-divisionally effective;
  • the GOA circuit includes a first GOA sub-circuit formed by cascading odd-numbered GOA units, the first GOA sub-circuit transmitting clock at the first stage, the second-level clock, the first control clock, and the second Controlling the driving of the clock to charge the odd-numbered horizontal scanning lines; wherein, in the first GOA sub-circuit, the first-level clock and the second-level clock correspond to the first clock signal and the third clock signal, and the first control The clock and the second control clock correspond to the second clock signal and the fourth clock signal;
  • the GOA circuit further includes a control module corresponding to the first GOA sub-circuit, which is recorded as a first control module, and the first control module is used in the first GOA sub- In the
  • the GOA circuit further includes a second GOA sub-circuit formed by cascading even-numbered GOA units, and the second GOA sub-circuit is driven by the first-stage clock, the second-stage clock, the first control clock, and the second control clock. And charging the horizontal scanning lines of the even-numbered stages; wherein, in the second GOA sub-circuit, the first-level clock, the second-level clock correspond to the second clock signal, the fourth clock signal, the first control clock, and the second The control clock corresponds to the first clock signal and the third clock signal; the GOA circuit further includes a control module corresponding to the second GOA sub-circuit, which is recorded as a second control module, and the second control module is configured to block in the second GOA sub-circuit The second clock signal and the fourth clock signal are configured to cause the first clock signal and the third clock signal to control the gate driving signal on the horizontal scanning line of the even-numbered stage to be discharged to a predetermined level.
  • the GOA unit includes a forward and reverse scanning unit, an input control unit, a pull-up maintaining unit, an output control unit, a GAS signal acting unit, and a bootstrap capacitor unit.
  • the forward and reverse scanning unit includes a first transistor, a second transistor, and a third a transistor and a fourth transistor, the gate of the first transistor receives the first scan control signal, the source of the first transistor receives the gate drive signal output by the next stage GOA unit, and the gate of the second transistor receives the second scan control signal
  • the source of the second transistor receives the gate drive signal outputted by the GOA unit of the previous stage, the drains of the first transistor and the second transistor are connected to each other and then connected to the input control unit, and the gate of the third transistor receives the first scan control a signal, a source of the third transistor receives a third control clock, a gate of the fourth transistor receives a second scan control signal, a source of the fourth transistor receives a fourth control clock, and drains of the third transistor and the fourth transistor are
  • the gate of the seventh transistor is connected to the drain of the fifth transistor, the source of the seventh transistor is connected to the common signal point, the drain of the seventh transistor is connected to the first constant voltage source, and the gate of the ninth transistor is connected to the third The drain of the transistor and the fourth transistor are connected, the source of the ninth transistor is connected to the second constant voltage source, the drain of the ninth transistor is connected to the common signal point, and the gate of the tenth transistor is connected to the common signal point, the tenth The source of the transistor is connected to the gate driving signal, the drain of the tenth transistor is connected to the first constant voltage source, and one end of the first capacitor is connected to the first constant voltage source, and the other end of the first capacitor and the common signal
  • the output control unit includes an eleventh transistor and a second capacitor.
  • the gate of the eleventh transistor is connected to the gate signal point, and the drain of the eleventh transistor is connected to the gate driving signal, and the source of the eleventh transistor Receiving a fourth-stage clock, one end of the second capacitor is connected to the gate signal point, and the other end of the second capacitor is connected to the gate driving signal;
  • the GAS signal acting unit includes a thirteenth transistor and a fourteenth transistor, the thirteenth The gate of the transistor, the gate and the drain of the fourteenth transistor receive the GAS signal, the drain of the thirteenth transistor is connected to the first constant voltage source, the source of the thirteenth transistor is connected to the common signal point, and the thirteenth transistor is connected The source is connected to the gate driving signal;
  • the bootstrap capacitor unit includes a bootstrap capacitor, one end of the bootstrap capacitor is connected to the gate driving signal, and the other end of the bootstrap capacitor is connected to the ground signal;
  • the third-level transmission clock and the fourth-level transmission clock correspond to the first-level transmission clock, the second-level transmission clock, or the second-level transmission clock, and the first-level transmission clock
  • the third control clock and the fourth control clock correspond to the first Control clock, second control clock or second control clock, first control clock.
  • the GOA unit further includes a voltage stabilizing unit, the voltage stabilizing unit includes an eighth transistor, the gate of the eighth transistor is connected to the second constant voltage source, the drain of the eighth transistor is connected to the drain of the fifth transistor, and the eighth transistor The source is connected to the gate signal point.
  • the GOA unit further includes a pull-up auxiliary unit, the pull-up auxiliary unit includes a twelfth transistor, the gate of the twelfth transistor is connected to the drains of the first transistor and the second transistor, and the source and the common of the twelfth transistor The signal points are connected, and the drains of the twelve transistors are connected to the first constant voltage source.
  • the GOA circuit and the liquid crystal display of the present invention simultaneously charge all horizontal scanning lines through the GOA circuit, and shield the first-level clock and the second-level clock to make the first control clock and the second control
  • the gate drive signal of the clock control horizontal scan line is discharged to a predetermined level, thereby avoiding generation of redundant pulse signals on the horizontal scan line before the output of the first gate drive signal, thereby ensuring normal operation of the GOA circuit.
  • FIG. 1 is a schematic structural view of a GOA circuit according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a GOA circuit according to a second embodiment of the present invention.
  • FIG. 3 is a circuit schematic diagram of a GOA unit in a GOA circuit according to a second embodiment of the present invention.
  • FIG. 4 is a timing chart showing the operation of the first GOA sub-circuit in the GOA circuit of the second embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a GOA circuit according to a first embodiment of the present invention.
  • the GOA circuit 10 includes a plurality of cascaded GOA units 11 and a control module 12.
  • Each GOA unit 11 is configured to charge a corresponding horizontal scan line in the display area under the driving of the first stage transfer clock CK_A1, the second stage transfer clock CK_A2, the first control clock CK_B1, and the second control clock CK_B2.
  • the first stage clock CK_A1 and the second level clock CK_A2 are used to control the input of the level signal CON_1 of the GOA unit 11 and the generation of the gate drive signal GATE(N) (N is a natural number), and the first control clock CK_B1
  • the second control clock CK_B2 is used to control the gate driving signal GATE(N) to be at a predetermined level, that is, an inactive level, wherein the level signal CON_1 is a start pulse signal or a gate driving signal of the adjacent GOA unit 11.
  • the control module 12 is respectively connected to the first-level transfer clock CK_A1, the second-level transfer clock CK_A2, and the respective GOA units 11 for simultaneously charging the horizontal scan lines in the GOA circuit 10, that is, completing All.
  • the first stage transfer clock CK_A1 and the second stage transfer clock CK_A2 are shielded so that the first control clock CK_B1 and the second control clock CK_B2 control the gate drive signal GATE(N) on the horizontal scan line to discharge to a predetermined level. That is, the level is inactive, thereby avoiding the generation of redundant pulse signals on the horizontal scan line before the output of the first gate drive signal GATE(1).
  • the GOA circuit 20 includes a first GOA sub-circuit 201 formed by cascading odd-level GOA units 21, and a second GOA sub-circuit 202 formed by cascading even-numbered GOA units 21, corresponding to the first GOA sub-circuit 201.
  • the first control module 22A and the second control module 22B corresponding to the second GOA sub-circuit 202.
  • the first GOA sub-circuit 201 is formed by cascading the odd-numbered GOA units 21, which means that the first GOA sub-circuit 201 is composed of the first, third, fifth, ... 2N+1 (N is a natural number) level GOA.
  • Unit 21 is formed in cascade.
  • the second GOA sub-circuit 202 is formed by cascading even-numbered GOA units 21, meaning that the second GOA sub-circuit 201 is composed of the second, fourth, sixth, ..., 2N+2 (N is a natural number) level GOA unit 21 Cascade formation.
  • the GOA circuit 20 receives the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4, wherein the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth The clock signal CK4 is sequentially time-divided in one duty cycle of the GOA circuit 20.
  • the first GOA sub-circuit 201 and the second GOA sub-circuit 202 are located on both sides of the display area of the liquid crystal display.
  • the first GOA sub-circuit 201 charges the odd-numbered horizontal scanning lines under the driving of the first-stage transfer clock CK_LA1, the second-stage transfer clock CK_LA2, the first control clock CK_LB1, and the second control clock CK_LB2.
  • the second GOA sub-circuit 202 charges the even-numbered horizontal scanning lines under the driving of the first-stage transfer clock CK_RA1, the second-stage transfer clock CK_RA2, the first control clock CK_RB1, and the second control clock CK_RB2.
  • the first-level clock CK_LA1 and the second-level clock CK_LA2 correspond to the first clock signal CK1 and the third clock signal CK3, and the first control clock CK_LB1 and the second control clock CK_LB2 correspond to the second clock.
  • the first clock signal CK1 and the third clock signal CK3 are used to control the input of the level transfer signal of the GOA unit 21 and the generation of the gate drive signal G(2N+1) (N is a natural number), and the second clock signal
  • the CK2 and the fourth clock signal CK4 are used to control the gate drive signal G(2N+1) to be at a predetermined level, that is, an inactive level.
  • the level-transmitting signal of the first-stage GOA unit 21 is the start pulse signal STV
  • the level-transmitting signal of the third-stage GOA unit 21 is the first
  • the level-transmitted signal of the fifth-stage GOA unit 21 is the gate drive signal G(3) of the third-stage GOA unit 21, and so on.
  • the level-transmitting signal of the first-stage GOA unit 21 is the gate driving signal G(3) of the third-stage GOA unit 21, and the third-stage GOA
  • the level-transmitting signal of the unit 21 is the gate driving signal G(5) of the fifth-stage GOA unit 21, and so on, wherein the level-transmitting signal of the last-stage GOA unit 21 is the start-up pulse signal STV.
  • the first-level clock CK_RA1 and the second-stage clock CK_RA2 correspond to the second clock signal CK2 and the fourth clock signal CK4.
  • the first control clock CK_RB1 and the second control clock CK_RB2 correspond to the first clock signal CK1 and the third clock signal CK3.
  • the second clock signal CK2 and the fourth clock signal CK4 are used to control the input of the level transmission signal of the GOA unit 21 and the generation of the gate drive signal G(2N+2) (N is a natural number), the first clock signal.
  • the CK1 and the third clock signal CK3 are used to control the gate drive signal G(2N+2) to be at a predetermined level, that is, an inactive level.
  • the level-transmitting signal of the second-stage GOA unit 21 is the start pulse signal STV
  • the level-transmitting signal of the fourth-stage GOA unit 21 is the first
  • the level-transmitted signal of the sixth-stage GOA unit 21 is the gate drive signal G(4) of the fourth-stage GOA unit 21, and so on.
  • the level-transmitted signal of the second-stage GOA unit 21 is the gate driving signal G(4) of the fourth-stage GOA unit 21, and the fourth-stage GOA
  • the level-transmitting signal of the unit 21 is the gate driving signal G(6) of the sixth-stage GOA unit 21, and so on, wherein the level-transmitting signal of the last-stage GOA unit 21 is the start-up pulse signal STV.
  • the first control module 22A is respectively connected to the first clock signal CK1, the third clock signal CK3 and the first GOA sub-circuit 201 for shielding the first clock signal CK1 after the GOA circuit 20 simultaneously charges all the horizontal scanning lines.
  • the three clock signal CK3 causes the second clock signal CK2 and the fourth clock signal CK4 to control the gate drive signal G(2N+1) on the odd-numbered horizontal scan lines to be discharged to a predetermined level, thereby avoiding the first gate A pulse signal is generated on the horizontal scan line before the output of the pole drive signal GATE(1).
  • the first control module 22A includes a first control transistor T1 and a second control transistor T2.
  • the first terminals of the first control transistor T1 and the second control transistor T2 are connected to each other to receive an enable signal EN.
  • the second ends of the first control transistor T1 and the second control transistor T2 are connected to the first clock signal CK1 and the third clock signal CK3.
  • the third terminal of the first control transistor T1 and the second control transistor T2 is connected to the GOA unit 21 for outputting the first-stage transfer clock CK_LA1 and the second-stage transfer clock CK_LA2.
  • the enable signal EN controls the first control transistor T1 and the second control transistor T2 to be turned off to shield the first clock signal CK1 and the third clock signal CK3, thereby making the second clock
  • the signal CK2 and the fourth clock signal CK4 control the gate drive signal G(2N+1) on the odd-numbered horizontal scanning lines to be discharged to a predetermined level.
  • the second control module 22B is respectively connected to the second clock signal CK2, the fourth clock signal CK4 and the second GOA sub-circuit 202 for shielding the second clock signal CK2 after the GOA circuit 20 simultaneously charges all the horizontal scanning lines.
  • the four clock signal CK4 causes the first clock signal CK1 and the third clock signal CK3 to control the gate drive signal G(2N+2) on the horizontal scanning line of the even-numbered stage to be discharged to a predetermined level, thereby avoiding the first gate A pulse signal is generated on the horizontal scan line before the output of the pole drive signal GATE(1).
  • the second control module 22B includes a third control transistor T3 and a fourth control transistor T4.
  • the first ends of the third control transistor T3 and the fourth control transistor T4 are connected to each other to receive the enable signal EN.
  • the second ends of the third control transistor T3 and the fourth control transistor T4 are connected to the second clock signal CK2 and the fourth clock signal CK4.
  • the third end of the third control transistor T3 and the fourth control transistor T4 are connected to the GOA unit 21 for outputting the first-stage transfer clock CK_RA1 and the second-stage transfer clock CK_RA2.
  • the enable signal EN controls the third control transistor T3 and the fourth control transistor T4 to be turned off to shield the two clock signals CK2 and the fourth clock signal CK4, thereby making the first clock
  • the signal CK1 and the third clock signal CK3 control the gate drive signal G(2N+2) on the horizontal scanning line of the even-numbered stage to be discharged to a predetermined level.
  • the first control transistor T1, the second control transistor T2, the third control transistor T3, and the fourth control transistor T4 are PMOS transistors, and the first control transistor T1, the second control transistor T2, and the third control transistor T3.
  • the first end, the second end, and the third end of the fourth control transistor T4 correspond to a gate, a drain, and a source of the PMOS transistor.
  • the enable signal EN is a high level signal, the first control transistor T1 and the second control transistor T2 are turned off.
  • the first control transistor T1, the second control transistor T2, the third control transistor T3, and the fourth control transistor T4 may also be an NMOS transistor, a first control transistor T1, a second control transistor T2, and a third control.
  • the first end, the second end, and the third end of the transistor T3 and the fourth control transistor T4 correspond to a gate, a drain, and a source of the NMOS transistor.
  • the enable signal EN is a low level signal
  • the first control transistor T1, the second control transistor T2, the third control transistor T3, and the fourth control transistor T4 are turned off.
  • the GOA unit 21 includes a forward/reverse scan unit 100, an input control unit 200, a pull-up maintaining unit 300, an output control unit 400, a GAS signal action unit 500, and a bootstrap capacitor unit 600.
  • the first forward/reverse scan unit 100 is configured to control forward driving or reverse driving of the GOA circuit 20, and control the common signal point P(2N+1) to be maintained under the control of the third control clock CK_D1 or the fourth control clock CK_D2. Low level.
  • the third control clock CK_D1 and the fourth control clock CK_D2 correspond to the first control clock CK_LB1, the second control clock CK_LB2, or the second control clock CK_LB2, and the first control clock CK_LB1.
  • the input control unit 200 is configured to control the input of the level transmission signal according to the third stage transmission clock CK_C1 to complete charging of the gate signal point Q(2N+1) (N is a natural number).
  • the third-level transmission clock CK_C1 corresponds to the first-level transmission clock CK_LA1 or corresponds to the second-level transmission clock CK_LA2.
  • the pull-up maintaining unit 300 is configured to control the gate signal point Q(2N+1) to maintain a predetermined level, that is, an inactive level, during the inactive period according to the common signal point P(2N+1).
  • the output control unit 400 is configured to control the output of the gate drive signal G(2N+1) corresponding to the gate signal point Q(2N+1) according to the fourth-stage transfer clock CK_C2.
  • the fourth-level transmission clock CK_C2 corresponds to the first-level transmission clock CK_LA1 or corresponds to the second-level transmission clock CK_LA2.
  • the GAS signal action unit 500 is for controlling the gate drive signal G(2N+1) to be at an active level to implement charging of the horizontal scan line corresponding to the GOA unit 21.
  • the bootstrap capacitor unit 600 is used to raise the voltage of the gate signal point Q(2N+1) again.
  • the front and back scanning unit 100 includes a first transistor PT0, a second transistor PT1, a third transistor PT2, and a fourth transistor PT3, and the gate of the first transistor PT0 receives the first a scan control signal, that is, a reverse scan control signal D2U, the source of the first transistor PT0 receives the gate drive signal G(2N+3) output by the next stage GOA unit 21, and the gate of the second transistor PT1 receives the second
  • the scan control signal is also the forward scan control signal U2D, the source of the second transistor PT1 receives the gate drive signal G(2N-1) output by the upper stage GOA unit, and the drains of the first transistor PT0 and the second transistor PT1.
  • the gate of the third transistor PT2 receives the first scan control signal, that is, the reverse scan control signal D2U, the source of the third transistor PT2 receives the third control clock CK_D1, and the fourth transistor PT3
  • the gate receives the second scan control signal, that is, the forward scan control signal U2D
  • the source of the fourth transistor PT3 receives the fourth control clock CK_D2
  • the drains of the third transistor PT2 and the fourth transistor PT3 are connected to each other.
  • the pull-maintenance unit 300 is connected.
  • the source of the second transistor PT1 receives the start pulse signal STV.
  • the source of the first transistor PT0 receives the start pulse signal STV.
  • the input control unit 200 includes a fifth transistor PT4, the gate of the fifth transistor PT4 receives the third-stage transfer clock CK_C1, and the source of the fifth transistor PT4 is connected to the drains of the first transistor PT0 and the second transistor PT1, and the fifth transistor The drain of PT4 is connected to the gate signal point Q(2N+1).
  • the pull-up maintaining unit 300 includes a sixth transistor PT5, a seventh transistor PT6, a ninth transistor PT8, a tenth transistor PT9, and a first capacitor C1, and a gate of the sixth transistor PT5 is connected to a common signal point P(2N+1),
  • the source of the sixth transistor PT5 is connected to the drain of the fifth transistor PT4, and the drain of the sixth transistor PT5 is connected to the first constant voltage source, that is, the positive voltage constant voltage source VGH, and the gate and the fifth of the seventh transistor PT6.
  • the drain of the transistor PT4 is connected, the source of the seventh transistor PT6 is connected to the common signal point P(2N+1), and the drain of the seventh transistor PT6 is connected to the first constant voltage source, that is, the positive voltage constant voltage source VGH.
  • the gate of the nine-transistor PT8 is connected to the drains of the third transistor PT2 and the fourth transistor PT3, and the source of the ninth transistor PT8 is connected to the second constant voltage source, that is, the negative voltage constant voltage source VGL, and the drain of the ninth transistor PT8
  • the pole is connected to the common signal point P(2N+1)
  • the gate of the tenth transistor PT9 is connected to the common signal point P(2N+1)
  • the source and gate drive signal G(2N+1) of the tenth transistor PT9 Connected, the drain of the tenth transistor PT9 is connected to the first constant voltage source, that is, the positive voltage constant voltage source VGH, and the first capacitor C
  • One end of 1 is connected to a first constant voltage source, that is, a positive voltage constant voltage source VGH, and the other end of the first capacitor C1 is connected to a common signal point (2N+1).
  • the output control unit 400 includes an eleventh transistor PT10 and a second capacitor C2.
  • the gate of the eleventh transistor PT10 is connected to the gate signal point Q(2N+1), and the drain and gate driving signals of the eleventh transistor PT10 are connected.
  • Q (2N+1) is connected, the source of the eleventh transistor PT10 receives the fourth-level clock CK_C2, one end of the second capacitor C2 is connected to the gate signal point Q(2N+1), and the other end of the second capacitor C2 Connected to the gate drive signal G(2N+1);
  • the GAS signal action unit 500 includes a thirteenth transistor PT12 and a fourteenth transistor PT13.
  • the gate of the thirteenth transistor PT12, the gate and the drain of the fourteenth transistor PT13 receive the GAS signal GAS, and the drain of the thirteenth transistor PT12
  • the first constant voltage source is connected to the first constant voltage source, that is, the positive voltage constant voltage source VGH
  • the source of the thirteenth transistor PT12 is connected to the common signal point P(2N+1)
  • the source of the thirteenth transistor PT12 is connected to the gate driving signal G ( 2N+1).
  • the bootstrap capacitor unit 600 includes a bootstrap capacitor Cload, one end of the bootstrap capacitor Cload and a gate drive signal G (2N+1) connection, the other end of the bootstrap capacitor Cload is connected to the ground signal GND.
  • the GOA unit 21 further includes a voltage stabilizing unit 700 for implementing voltage regulation of the gate signal point Q(2N+1) and leakage prevention of the gate signal point Q(2N+1).
  • the voltage stabilizing unit 700 includes an eighth transistor PT7 serially connected between the source of the fifth transistor PT4 and the gate signal point Q(2N+1), and the gate of the eighth transistor PT7
  • the second constant voltage source is also connected to the negative voltage constant voltage source VGL
  • the drain of the eighth transistor PT7 is connected to the drain of the fifth transistor PT4, and the source and gate signal point Q (2N+1) of the eighth transistor PT7 connection.
  • the GOA unit 21 further includes a pull-up assisting unit 800 for preventing leakage of the fifth transistor PT4 and the sixth transistor PT5 during charging of the gate signal point Q(2N+1)
  • the pull-up auxiliary unit 800 includes a twelfth transistor PT11, the gate of the twelfth transistor PT11 is connected to the drains of the first transistor PT0 and the second transistor PT1, and the source and the common signal of the twelfth transistor PT11.
  • the point P (2N+1) is connected, and the drain of the twelfth transistor PT11 is connected to the first constant voltage source, that is, the positive voltage constant voltage source VGH.
  • the third-level transfer clock CK_C1 is the first-level transfer clock CK_LA1, that is, the first The clock signal CK1
  • the fourth-level clock CK_C2 is the second-level clock CK_LA2, that is, the third clock signal CK3
  • the third control clock CK_D1 is the first control clock CK_LB1, that is, the second clock signal CK2, and the fourth control clock CK_D2
  • the second control clock CK_LB2 is also the fourth clock signal CK4.
  • the third level transmission clock CK_C1 is the second level transmission clock CK_LA2, that is, the third clock signal CK3, the fourth level transmission
  • the clock CK_C2 is the first-level clock CK_LA1, that is, the first clock signal CK1
  • the third control clock CK_D1 is the second control clock CK_LB2, that is, the fourth clock signal CK4
  • the fourth control clock CK_D2 is the first control clock CK_LB2.
  • the GOA unit is an NMOS circuit
  • all the transistors are NMOS transistors
  • the first scan control signal corresponds to the forward scan control signal U2D
  • the second scan control signal corresponds to the inverted scan control signal D2U
  • a constant voltage source corresponds to a negative pressure constant voltage source VGL
  • a second constant voltage source corresponds to a positive pressure constant voltage source VGH.
  • the GOA unit in the first GOA sub-circuit is a PMOS circuit
  • the corresponding first control module 22A, the first control transistor T1 and the second control transistor T2 are PMOS transistors.
  • the GOA unit in the first GOA sub-circuit is an NMOS circuit, and the corresponding first control module 22A, the first control transistor T1 and the second control transistor T2, are NMOS transistors.
  • the second N+2 stage GOA unit 21 located in the second GOA sub-circuit 202 is similar to the 2N+1th stage GOA unit 21 located in the first GOA sub-circuit 202, and will not be described in detail herein for the sake of simplicity.
  • the first-level clock CK_RA1, the second-stage clock CK_RA2, the first control clock CK_RB1, and the second control clock CK_RB2 in the second N+2-level GOA unit 21 correspond to the second in the 2N+1-th GOA unit 21.
  • FIG. 4 is a timing chart showing the operation of the first GOA sub-circuit in the GOA circuit of the second embodiment of the present invention.
  • the GOA circuit 20 implements All.
  • the Gate On function outputs a low level signal to the gate drive signal G(2N+1) corresponding to each odd-level horizontal scanning line.
  • the gate drive signal G(2N+1) corresponding to each odd-level horizontal scan line does not immediately become a high level, but will remain Cload. Holding a low level signal.
  • the GOA circuit 20 as the forward driving as an example, if the gate driving signal corresponding to the odd-numbered horizontal scanning line cannot be discharged to the high level before the third clock signal CK3 is valid, the odd-numbers other than the first-level horizontal scanning line A redundant pulse signal is generated on the horizontal scanning line.
  • the first-level horizontal scan line is driven by the first-stage GOA unit. Since the level-transmitted signal of the first-stage GOA unit is the start-up pulse signal STV, the first-stage GOA unit is normally driven, and no redundant pulse signal is generated. .
  • the third-level horizontal scan line is driven by the third-stage GOA unit, and the level-transmitted signal of the third-stage GOA unit is the gate drive signal G(1) of the first-stage GOA unit, when the first clock signal CK1 is low. Since the gate drive signal G(1) holds Cload Holding a low level signal, the low level signal of the gate drive signal G(1) is transmitted to the gate signal point Q(3) of the third stage GOA unit, so that the third stage GOA unit 21 precedes the first The stage GOA unit 21 operates, and causes the gate drive signal G(3) outputted by the third stage GOA unit 21 to generate a redundant pulse, which will continue to affect the gate drive signal of the next stage GOA unit 21. . For the same reason, when the first clock signal CK1 is active, the gate drive signals of the seventh stage, the tenth stage, ... the 4th N+3 stage GOA unit generate redundant pulses.
  • the enable signal EN is set to a high level and maintained for one duty cycle.
  • the first control transistor T1 and the second control The transistor T2 is turned off, and the first clock signal CK1 and the third clock signal CK3 cannot be sent to the first-level transfer clock CK_LA1 and the second-level transfer clock CK_LA2.
  • the GOA unit in the first GOA sub-circuit is at the first control clock CK_LB1.
  • the second control clock CK_LB2 (that is, the second clock signal CK2 and the fourth clock signal CK4) controls the common signal point P(2N+1) to be at a low level signal, thereby causing the gate drive signal G (2N+). 1) A high level signal is asserted before the third clock signal CK3 is asserted, thereby avoiding the generation of redundant pulse signals. Subsequently, the driving sequence of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 that are normally maintained is driven to the first GOA sub-circuit 201, thereby achieving normal charging of the horizontal scanning line. .
  • the one working cycle refers to a time period in which the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are sequentially valid.
  • the operation timing of the second GOA sub-circuit 202 is similar to the operation timing of the first GOA sub-circuit 201. For the sake of brevity, details are not described herein again.
  • the present invention further provides a liquid crystal display comprising the above GOA circuit.
  • the GOA circuit and the liquid crystal display of the present invention simultaneously charge all horizontal scanning lines through the GOA circuit, and shield the first-level clock and the second-level clock to make the first control clock and the second control
  • the gate drive signal of the clock control horizontal scan line is discharged to a predetermined level, thereby avoiding generation of redundant pulse signals on the horizontal scan line before the output of the first gate drive signal, thereby ensuring normal operation of the GOA circuit.

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Abstract

公开了一种GOA电路及液晶显示器。该GOA电路（10）包括多个级联的GOA单元（11）和控制模块（12），每一GOA单元（11）用于在第一级传时钟（CK-A1）、第二级传时钟（CK-A2）、第一控制时钟（CK-B1）、第二控制时钟（CK-B2）的驱动下对显示区域中对应的水平扫描线进行充电，控制模块（12）用于在GOA电路（10）对所有水平扫描线同时充电后，屏蔽第一级传时钟（CK-A1）、第二级传时钟（CK-A2），以使第一控制时钟（CK-B1）、第二控制时钟（CK-B2）控制水平扫描线上的栅极驱动信号（GATE（1），GATE（M），GATE（N））放电至预定电平。通过上述方式实现在GOA电路对所有扫描线同时充电后，避免在第一个栅极驱动信号（GATE（1））输出之前在水平扫描线上产生冗余的脉冲信号，从而保证GOA电路（10）正常工作。

Description

一种GOA电路及液晶显示器
【技术领域】
本发明涉及液晶领域，特别是涉及一种GOA电路及液晶显示器。
【背景技术】
现有的GOA（Gate driver on array）电路在搭配All Gate On功能时，由于自举电容的存在，GOA电路中的栅极驱动信号在All Gate On功能完成后，不会马上变为无效电平，从而存在产生冗余的栅极驱动信号、进而导致电路出现失效的可能。
其中，All Gate On功能是指将GOA电路中的所有栅极驱动信号设置为有效电平以同时对所有水平扫描线进行充电，从而清除液晶显示器中每个像素点残存的电荷以解决开关机时出现残影的问题。
【发明内容】
本发明主要解决的技术问题是提供一种GOA电路及液晶显示器，能够避免在第一个栅极驱动信号输出之前在水平扫描线上产生冗余的脉冲信号，从而保证GOA电路的正常工作。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种GOA电路，用于液晶显示器，该GOA电路包括级联的多个GOA单元，每一GOA单元用于在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对显示区域中对应的水平扫描线进行充电，第一级传时钟、第二级传时钟用于控制GOA单元的级传信号的输入以及栅极驱动信号的产生，第一控制时钟、第二控制时钟用于控制栅极驱动信号处于预定电平，其中，级传信号为启动脉冲信号或相邻的GOA单元的栅极驱动信号；GOA电路进一步包括控制模块，控制模块用于在GOA电路对所有水平扫描线同时充电后，屏蔽第一级传时钟、第二级传时钟，以使第一控制时钟、第二控制时钟控制水平扫描线上的栅极驱动信号放电至预定电平，从而避免在第一个栅极驱动信号输出之前在水平扫描线上产生冗余的脉冲信号；控制模块包括第一控制晶体管和第二控制晶体管，第一控制晶体管、第二控制晶体管的第一端相互连接后接收使能信号，第一控制晶体管、第二控制晶体的第二端对应连接第一级传时钟、第二级传时钟，第一控制晶体管、第二控制晶体管的第三端连接GOA单元，其中，在GOA电路对所有水平扫描线同时充电后，使能信号控制第一控制晶体管、第二控制晶体管截止以屏蔽第一级传时钟、第二级传时钟，从而使得第一控制时钟、第二控制时钟控制所有水平扫描线上的栅极驱动信号放电至预定电平；GOA电路接收第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，其中，第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号在GOA电路的工作周期依次分时有效；GOA电路包括奇数级的GOA单元级联形成的第一GOA子电路，第一GOA子电路在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对奇数级的水平扫描线进行充电；其中，在第一GOA子电路中，第一级传时钟、第二级传时钟对应第一时钟信号、第三时钟信号，第一控制时钟、第二控制时钟对应第二时钟信号、第四时钟信号；GOA电路进一步包括与第一GOA子电路对应的控制模块，记为第一控制模块，第一控制模块用于在第一GOA子电路中，屏蔽第一时钟信号、第三时钟信号，以使第二时钟信号、第四时钟信号控制奇数级的水平扫描线上的栅极驱动信号放电至预定电平；GOA电路进一步包括偶数级的GOA单元级联形成的第二GOA子电路，第二GOA子电路在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对偶数级的水平扫描线进行充电；其中，在第二GOA子电路中，第一级传时钟、第二级传时钟对应第二时钟信号、第四时钟信号，第一控制时钟、第二控制时钟对应第一时钟信号、第三时钟信号；GOA电路进一步包括与第二GOA子电路对应的控制模块，记为第二控制模块，第二控制模块用于在第二GOA子电路中，屏蔽第二时钟信号、第四时钟信号，以使第一时钟信号、第三时钟信号控制偶数级的水平扫描线上的栅极驱动信号放电至预定电平。
其中，第一控制晶体管、第二控制晶体管为PMOS管，第一控制晶体管、第二控制晶体管的第一端、第二端、第三端对应PMOS管的栅极、漏极和源极；其中，当使能信号为高电平信号时，第一控制晶体管、第二控制晶体管截止。为解决上述技术问题，本发明采用的另一个技术方案是：提供一种GOA电路，用于液晶显示器，该GOA电路包括级联的多个GOA单元，每一GOA单元用于在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对显示区域中对应的水平扫描线进行充电，第一级传时钟、第二级传时钟用于控制GOA单元的级传信号的输入以及栅极驱动信号的产生，第一控制时钟、第二控制时钟用于控制栅极驱动信号处于预定电平，其中，级传信号为启动脉冲信号或相邻的GOA单元的栅极驱动信号；GOA电路进一步包括控制模块，控制模块用于在GOA电路对所有水平扫描线同时充电后，屏蔽第一级传时钟、第二级传时钟，以使第一控制时钟、第二控制时钟控制水平扫描线上的栅极驱动信号放电至预定电平，从而避免在第一个栅极驱动信号输出之前在水平扫描线上产生冗余的脉冲信号。
其中，控制模块包括第一控制晶体管和第二控制晶体管，第一控制晶体管、第二控制晶体管的第一端相互连接后接收使能信号，第一控制晶体管、第二控制晶体的第二端对应连接第一级传时钟、第二级传时钟，第一控制晶体管、第二控制晶体管的第三端连接GOA单元，其中，在GOA电路对所有水平扫描线同时充电后，使能信号控制第一控制晶体管、第二控制晶体管截止以屏蔽第一级传时钟、第二级传时钟，从而使得第一控制时钟、第二控制时钟控制所有水平扫描线上的栅极驱动信号放电至预定电平。
其中，第一控制晶体管、第二控制晶体管为PMOS管，第一控制晶体管、第二控制晶体管的第一端、第二端、第三端对应PMOS管的栅极、漏极和源极；其中，当使能信号为高电平信号时，第一控制晶体管、第二控制晶体管截止。
其中，第一控制晶体管、第二控制晶体管为NMOS管，第一控制晶体管、第二控制晶体管的第一端、第二端、第三端对应NMOS管的栅极、漏极和源极；其中，当控制信号为低电平信号时，第一控制晶体管、第二控制晶体管截止。
其中，GOA电路接收第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，其中，第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号在GOA电路的工作周期依次分时有效；GOA电路包括奇数级的GOA单元级联形成的第一GOA子电路，第一GOA子电路在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对奇数级的水平扫描线进行充电；其中，在第一GOA子电路中，第一级传时钟、第二级传时钟对应第一时钟信号、第三时钟信号，第一控制时钟、第二控制时钟对应第二时钟信号、第四时钟信号；GOA电路进一步包括与第一GOA子电路对应的控制模块，记为第一控制模块，第一控制模块用于在第一GOA子电路中，屏蔽第一时钟信号、第三时钟信号，以使第二时钟信号、第四时钟信号控制奇数级的水平扫描线上的栅极驱动信号放电至预定电平。
其中，GOA电路进一步包括偶数级的GOA单元级联形成的第二GOA子电路，第二GOA子电路在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对偶数级的水平扫描线进行充电；其中，在第二GOA子电路中，第一级传时钟、第二级传时钟对应第二时钟信号、第四时钟信号，第一控制时钟、第二控制时钟对应第一时钟信号、第三时钟信号；GOA电路进一步包括与第二GOA子电路对应的控制模块，记为第二控制模块，第二控制模块用于在第二GOA子电路中，屏蔽第二时钟信号、第四时钟信号，以使第一时钟信号、第三时钟信号控制偶数级的水平扫描线上的栅极驱动信号放电至预定电平。
其中，GOA单元包括正反扫描单元、输入控制单元、上拉维持单元、输出控制单元、GAS信号作用单元和自举电容单元；其中，正反扫描单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，第一晶体管的栅极接收第一扫描控制信号，第一晶体管的源极接收下一级GOA单元输出的栅极驱动信号，第二晶体管的栅极接收第二扫描控制信号，第二晶体管的源极接收上一级GOA单元输出的栅极驱动信号，第一晶体管和第二晶体管的漏极相互连接后与输入控制单元连接，第三晶体管的栅极接收第一扫描控制信号，第三晶体管的源极接收第三控制时钟，第四晶体管的栅极接收第二扫描控制信号，第四晶体管的源极接收第四控制时钟，第三晶体管和第四晶体管的漏极相互连接后与上拉维持单元连接；输入控制单元包括第五晶体管，第五晶体管的栅极接收第三级传时钟，第五晶体管的源极与第一晶体管、第二晶体管的漏极连接，第五晶体管的漏极与栅极信号点连接；上拉维持单元包括第六晶体管、第七晶体管、第九晶体管、第十晶体管和第一电容，第六晶体管的栅极与公共信号点连接，第六晶体管的源极与第五晶体管的漏极连接，第六晶体管的漏极与第一恒压源连接，第七晶体管的栅极与第五晶体管的漏极连接，第七晶体管的源极与公共信号点连接，第七晶体管的漏极与第一恒压源连接，第九晶体管的栅极与第三晶体管、第四晶体管的漏极连接，第九晶体管的源极与第二恒压源连接，第九晶体管的漏极与公共信号点连接，第十晶体管的栅极与公共信号点连接，第十晶体管的源极与栅极驱动信号连接，第十晶体管的漏极与第一恒压源连接，第一电容的一端与第一恒压源连接，第一电容的另一端与公共信号点连接；输出控制单元包括第十一晶体管和第二电容，第十一晶体管的栅极与栅极信号点连接，第十一晶体管的漏极与栅极驱动信号连接，第十一晶体管的源极接收第四级传时钟，第二电容的一端与栅极信号点连接，第二电容的另一端与栅极驱动信号连接；GAS信号作用单元包括第十三晶体管和第十四晶体管，第十三晶体管的栅极、第十四晶体管的栅极和漏极接收GAS信号，第十三晶体管的漏极连接第一恒压源，第十三晶体管的源极连接公共信号点，第十三晶体管的源极连接栅极驱动信号；自举电容单元包括自举电容，自举电容的一端与栅极驱动信号连接，自举电容的另一端与地信号连接；
其中，第三级传时钟、第四级传时钟对应第一级传时钟、第二级传时钟或第二级传时钟、第一级传时钟，第三控制时钟、第四控制时钟对应第一控制时钟、第二控制时钟或第二控制时钟、第一控制时钟。
其中，GOA单元进一步包括稳压单元，稳压单元包括第八晶体管，第八晶体管的栅极与第二恒压源连接，第八晶体管的漏极与第五晶体管的漏极连接，第八晶体管的源极与栅极信号点连接。
其中，GOA单元进一步包括上拉辅助单元，上拉辅助单元包括第十二晶体管，第十二晶体管的栅极与第一晶体管、第二晶体管的漏极连接，第十二晶体管的源极与公共信号点连接，十二晶体管的漏极与第一恒压源连接。
为解决上述技术问题，本发明采用的再一个技术方案是：提供一种液晶显示器，包括GOA电路，该GOA电路包括级联的多个GOA单元，每一GOA单元用于在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对显示区域中对应的水平扫描线进行充电，第一级传时钟、第二级传时钟用于控制GOA单元的级传信号的输入以及栅极驱动信号的产生，第一控制时钟、第二控制时钟用于控制栅极驱动信号处于预定电平，其中，级传信号为启动脉冲信号或相邻的GOA单元的栅极驱动信号；GOA电路进一步包括控制模块，控制模块用于在GOA电路对所有水平扫描线同时充电后，屏蔽第一级传时钟、第二级传时钟，以使第一控制时钟、第二控制时钟控制水平扫描线上的栅极驱动信号放电至预定电平，从而避免在第一个栅极驱动信号输出之前在水平扫描线上产生冗余的脉冲信号。
其中，控制模块包括第一控制晶体管和第二控制晶体管，第一控制晶体管、第二控制晶体管的第一端相互连接后接收使能信号，第一控制晶体管、第二控制晶体的第二端对应连接第一级传时钟、第二级传时钟，第一控制晶体管、第二控制晶体管的第三端连接GOA单元，其中，在GOA电路对所有水平扫描线同时充电后，使能信号控制第一控制晶体管、第二控制晶体管截止以屏蔽第一级传时钟、第二级传时钟，从而使得第一控制时钟、第二控制时钟控制所有水平扫描线上的栅极驱动信号放电至预定电平。
其中，第一控制晶体管、第二控制晶体管为PMOS管，第一控制晶体管、第二控制晶体管的第一端、第二端、第三端对应PMOS管的栅极、漏极和源极；其中，当使能信号为高电平信号时，第一控制晶体管、第二控制晶体管截止。
其中，第一控制晶体管、第二控制晶体管为NMOS管，第一控制晶体管、第二控制晶体管的第一端、第二端、第三端对应NMOS管的栅极、漏极和源极；其中，当控制信号为低电平信号时，第一控制晶体管、第二控制晶体管截止。
其中，GOA电路接收第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，其中，第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号在GOA电路的工作周期依次分时有效；GOA电路包括奇数级的GOA单元级联形成的第一GOA子电路，第一GOA子电路在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对奇数级的水平扫描线进行充电；其中，在第一GOA子电路中，第一级传时钟、第二级传时钟对应第一时钟信号、第三时钟信号，第一控制时钟、第二控制时钟对应第二时钟信号、第四时钟信号；GOA电路进一步包括与第一GOA子电路对应的控制模块，记为第一控制模块，第一控制模块用于在第一GOA子电路中，屏蔽第一时钟信号、第三时钟信号，以使第二时钟信号、第四时钟信号控制奇数级的水平扫描线上的栅极驱动信号放电至预定电平。
其中，GOA电路进一步包括偶数级的GOA单元级联形成的第二GOA子电路，第二GOA子电路在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对偶数级的水平扫描线进行充电；其中，在第二GOA子电路中，第一级传时钟、第二级传时钟对应第二时钟信号、第四时钟信号，第一控制时钟、第二控制时钟对应第一时钟信号、第三时钟信号；GOA电路进一步包括与第二GOA子电路对应的控制模块，记为第二控制模块，第二控制模块用于在第二GOA子电路中，屏蔽第二时钟信号、第四时钟信号，以使第一时钟信号、第三时钟信号控制偶数级的水平扫描线上的栅极驱动信号放电至预定电平。
其中，GOA单元包括正反扫描单元、输入控制单元、上拉维持单元、输出控制单元、GAS信号作用单元和自举电容单元；其中，正反扫描单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，第一晶体管的栅极接收第一扫描控制信号，第一晶体管的源极接收下一级GOA单元输出的栅极驱动信号，第二晶体管的栅极接收第二扫描控制信号，第二晶体管的源极接收上一级GOA单元输出的栅极驱动信号，第一晶体管和第二晶体管的漏极相互连接后与输入控制单元连接，第三晶体管的栅极接收第一扫描控制信号，第三晶体管的源极接收第三控制时钟，第四晶体管的栅极接收第二扫描控制信号，第四晶体管的源极接收第四控制时钟，第三晶体管和第四晶体管的漏极相互连接后与上拉维持单元连接；输入控制单元包括第五晶体管，第五晶体管的栅极接收第三级传时钟，第五晶体管的源极与第一晶体管、第二晶体管的漏极连接，第五晶体管的漏极与栅极信号点连接；上拉维持单元包括第六晶体管、第七晶体管、第九晶体管、第十晶体管和第一电容，第六晶体管的栅极与公共信号点连接，第六晶体管的源极与第五晶体管的漏极连接，第六晶体管的漏极与第一恒压源连接，第七晶体管的栅极与第五晶体管的漏极连接，第七晶体管的源极与公共信号点连接，第七晶体管的漏极与第一恒压源连接，第九晶体管的栅极与第三晶体管、第四晶体管的漏极连接，第九晶体管的源极与第二恒压源连接，第九晶体管的漏极与公共信号点连接，第十晶体管的栅极与公共信号点连接，第十晶体管的源极与栅极驱动信号连接，第十晶体管的漏极与第一恒压源连接，第一电容的一端与第一恒压源连接，第一电容的另一端与公共信号点连接；输出控制单元包括第十一晶体管和第二电容，第十一晶体管的栅极与栅极信号点连接，第十一晶体管的漏极与栅极驱动信号连接，第十一晶体管的源极接收第四级传时钟，第二电容的一端与栅极信号点连接，第二电容的另一端与栅极驱动信号连接；GAS信号作用单元包括第十三晶体管和第十四晶体管，第十三晶体管的栅极、第十四晶体管的栅极和漏极接收GAS信号，第十三晶体管的漏极连接第一恒压源，第十三晶体管的源极连接公共信号点，第十三晶体管的源极连接栅极驱动信号；自举电容单元包括自举电容，自举电容的一端与栅极驱动信号连接，自举电容的另一端与地信号连接；
其中，第三级传时钟、第四级传时钟对应第一级传时钟、第二级传时钟或第二级传时钟、第一级传时钟，第三控制时钟、第四控制时钟对应第一控制时钟、第二控制时钟或第二控制时钟、第一控制时钟。
其中，GOA单元进一步包括稳压单元，稳压单元包括第八晶体管，第八晶体管的栅极与第二恒压源连接，第八晶体管的漏极与第五晶体管的漏极连接，第八晶体管的源极与栅极信号点连接。
其中，GOA单元进一步包括上拉辅助单元，上拉辅助单元包括第十二晶体管，第十二晶体管的栅极与第一晶体管、第二晶体管的漏极连接，第十二晶体管的源极与公共信号点连接，十二晶体管的漏极与第一恒压源连接。
本发明的有益效果是：本发明的GOA电路及液晶显示器通过GOA电路对所有水平扫描线同时充电后，屏蔽第一级传时钟、第二级传时钟，以使第一控制时钟、第二控制时钟控制水平扫描线上的栅极驱动信号放电至预定电平，从而能够避免在第一个栅极驱动信号输出之前在水平扫描线上产生冗余的脉冲信号，进而保证了GOA电路的正常工作。
【附图说明】
图1是本发明第一实施例的GOA电路的结构示意图；
图2是本发明第二实施例的GOA电路的结构示意图；
图3是本发明第二实施例的GOA电路中GOA单元的电路原理图；
图4是本发明第二实施例的GOA电路中第一GOA子电路的工作时序图。
【具体实施方式】
在说明书及权利要求书当中使用了某些词汇来指称特定的组件，所属领域中的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。下面结合附图和实施例对本发明进行详细说明。
图1是本发明第一实施例的GOA电路的结构示意图。如图1所示，GOA电路10包括级联的多个GOA单元11和控制模块12。
每一GOA单元11用于在第一级传时钟CK_A1、第二级传时钟CK_A2、第一控制时钟CK_B1、第二控制时钟CK_B2的驱动下对显示区域中对应的水平扫描线进行充电。其中，第一级传时钟CK_A1、第二级传时钟CK_A2用于控制GOA单元11的级传信号CON_1的输入以及栅极驱动信号GATE（N）（N为自然数）的产生，第一控制时钟CK_B1、第二控制时钟CK_B2用于控制栅极驱动信号GATE（N）处于预定电平也即无效电平，其中，级传信号CON_1为启动脉冲信号或相邻的GOA单元11的栅极驱动信号。
控制模块12分别与第一级传时钟CK_A1、第二级传时钟CK_A2和各个GOA单元11连接，用于在GOA电路10对水平扫描线同时充电也即完成All Gate on 功能后，屏蔽第一级传时钟CK_A1、第二级传时钟CK_A2，以使第一控制时钟CK_B1、第二控制时钟CK_B2控制水平扫描线上的栅极驱动信号GATE（N）放电至预定电平也即无效电平，从而避免在第一个栅极驱动信号GATE（1）输出之前在水平扫描线上产生冗余的脉冲信号。
图2是本发明第二实施例的GOA电路的结构示意图。如图2所示，GOA电路20包括奇数级GOA单元21级联形成的第一GOA子电路201、偶数级GOA单元21级联形成的第二GOA子电路202、与第一GOA子电路201对应的第一控制模块22A以及与第二GOA子电路202对应的第二控制模块22B。
其中，第一GOA子电路201由奇数级GOA单元21级联形成是指第一GOA子电路201由第一级、第三级、第五级、…第2N+1（N为自然数）级GOA单元21级联形成。第二GOA子电路202由偶数级GOA单元21级联形成是指第二GOA子电路201由第二级、第四级、第六级、…第2N+2（N为自然数）级GOA单元21级联形成。
GOA电路20接收第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3和第四时钟信号CK4，其中，第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3和第四时钟信号CK4在GOA电路20的一个工作周期依次分时有效。
第一GOA子电路201和第二GOA子电路202位于液晶显示器的显示区域的两侧。第一GOA子电路201在第一级传时钟CK_LA1、第二级传时钟CK_LA2、第一控制时钟CK_LB1、第二控制时钟CK_LB2的驱动下对奇数级的水平扫描线进行充电。第二GOA子电路202在第一级传时钟CK_RA1、第二级传时钟CK_RA2、第一控制时钟CK_RB1、第二控制时钟CK_RB2的驱动下对偶数级的水平扫描线进行充电。
在第一GOA子电路201中，第一级传时钟CK_LA1、第二级传时钟CK_LA2对应第一时钟信号CK1、第三时钟信号CK3，第一控制时钟CK_LB1、第二控制时钟CK_LB2对应第二时钟信号CK2、第四时钟信号CK4。
也就是说，第一时钟信号CK1、第三时钟信号CK3用于控制GOA单元21的级传信号的输入以及栅极驱动信号G（2N+1）（N为自然数）的产生，第二时钟信号CK2、第四时钟信号CK4用于控制栅极驱动信号G（2N+1）处于预定电平也即无效电平。其中，当GOA电路20为正向驱动电路时（如图中实线所示），第一级GOA单元21的级传信号为启动脉冲信号STV，第三级GOA单元21的级传信号为第一级GOA单元21的栅极驱动信号G（1），第五级GOA单元21的级传信号为第三级GOA单元21的栅极驱动信号G（3），依次类推。当GOA电路20为反向驱动电路时（如图中虚线所示），第一级GOA单元21的级传信号为第三级GOA单元21的栅极驱动信号G（3），第三级GOA单元21的级传信号为第五级GOA单元21的栅极驱动信号G（5），依次类推，其中，最后一级GOA单元21的级传信号为启动脉冲信号STV。
在第二GOA子电路202中，第一级传时钟CK_RA1、第二级传时钟CK_RA2对应第二时钟信号CK2、第四时钟信号CK4。第一控制时钟CK_RB1、第二控制时钟CK_RB2对应第一时钟信号CK1、第三时钟信号CK3。
也就是说，第二时钟信号CK2、第四时钟信号CK4用于控制GOA单元21的级传信号的输入以及栅极驱动信号G（2N+2）（N为自然数）的产生，第一时钟信号CK1、第三时钟信号CK3用于控制栅极驱动信号G（2N+2）处于预定电平也即无效电平。其中，当GOA电路20为正向驱动电路时（如图中实线所示），第二级GOA单元21的级传信号为启动脉冲信号STV，第四级GOA单元21的级传信号为第二级GOA单元21的栅极驱动信号G（2），第六级GOA单元21的级传信号为第四级GOA单元21的栅极驱动信号G（4），依次类推。当GOA电路20为反向驱动电路时（如图中虚线所示），第二级GOA单元21的级传信号为第四级GOA单元21的栅极驱动信号G（4），第四级GOA单元21的级传信号为第六级GOA单元21的栅极驱动信号G（6），依次类推，其中，最后一级GOA单元21的级传信号为启动脉冲信号STV。
第一控制模块22A分别与第一时钟信号CK1、第三时钟信号CK3和第一GOA子电路201连接，用于在GOA电路20对所有水平扫描线同时充电后，屏蔽第一时钟信号CK1、第三时钟信号CK3，以使第二时钟信号CK2、第四时钟信号CK4控制奇数级的水平扫描线上的栅极驱动信号G（2N+1）放电至预定电平，从而避免在第一个栅极驱动信号GATE（1）输出之前在水平扫描线上产生冗余的脉冲信号。
具体来说，第一控制模块22A包括第一控制晶体管T1和第二控制晶体管T2，第一控制晶体管T1、第二控制晶体管T2的第一端相互连接后接收使能信号EN。第一控制晶体管T1、第二控制晶体管T2的第二端对应连接第一时钟信号CK1、第三时钟信号CK3。第一控制晶体管T1、第二控制晶体管T2的第三端连接GOA单元21，用于输出第一级传时钟CK_LA1、第二级传时钟CK_LA2。其中，在GOA电路20对所有扫描线同时充电后，使能信号EN控制第一控制晶体管T1、第二控制晶体管T2截止以屏蔽第一时钟信号CK1、第三时钟信号CK3，从而使得第二时钟信号CK2、第四时钟信号CK4控制奇数级的水平扫描线上的栅极驱动信号G（2N+1）放电至预定电平。
第二控制模块22B分别与第二时钟信号CK2、第四时钟信号CK4和第二GOA子电路202连接，用于在GOA电路20对所有水平扫描线同时充电后，屏蔽第二时钟信号CK2、第四时钟信号CK4，以使第一时钟信号CK1、第三时钟信号CK3控制偶数级的水平扫描线上的栅极驱动信号G（2N+2）放电至预定电平，从而避免在第一个栅极驱动信号GATE（1）输出之前在水平扫描线上产生冗余的脉冲信号。
具体来说，第二控制模块22B包括第三控制晶体管T3和第四控制晶体管T4，第三控制晶体管T3、第四控制晶体管T4的第一端相互连接后接收使能信号EN。第三控制晶体管T3、第四控制晶体管T4的第二端对应连接第二时钟信号CK2、第四时钟信号CK4。第三控制晶体管T3、第四控制晶体管T4的第三端连接GOA单元21，用于输出第一级传时钟CK_RA1、第二级传时钟CK_RA2。其中，在GOA电路20对所有水平扫描线同时充电后，使能信号EN控制第三控制晶体管T3、第四控制晶体管T4截止以屏蔽二时钟信号CK2、第四时钟信号CK4，从而使得第一时钟信号CK1、第三时钟信号CK3控制偶数级的水平扫描线上的栅极驱动信号G（2N+2）放电至预定电平。
在本实施例中，第一控制晶体管T1、第二控制晶体管T2、第三控制晶体管T3、第四控制晶体管T4为PMOS管，第一控制晶体管T1、第二控制晶体管T2、第三控制晶体管T3、第四控制晶体管T4的第一端、第二端、第三端对应PMOS管的栅极、漏极和源极。其中，当使能信号EN为高电平信号时，第一控制晶体管T1、第二控制晶体管T2截止。
在其它实施例中，第一控制晶体管T1、第二控制晶体管T2、第三控制晶体管T3、第四控制晶体管T4也可以为NMOS管，第一控制晶体管T1、第二控制晶体管T2、第三控制晶体管T3、第四控制晶体管T4的第一端、第二端、第三端对应NMOS管的栅极、漏极和源极。其中，当使能信号EN为低电平信号时，第一控制晶体管T1、第二控制晶体管T2、第三控制晶体管T3、第四控制晶体管T4截止。
图3是本发明第二实施例的GOA电路中GOA单元的电路原理图。如图3所示，GOA单元21包括正反扫描单元100、输入控制单元200、上拉维持单元300、输出控制单元400、GAS信号作用单元500和自举电容单元600。
以位于第一GOA子电路201的第2N+1级GOA单元21为例，以第2N+1级GOA单元21为PMOS电路为例来说：
第一正反扫描单元100用于控制GOA电路20的正向驱动或反向驱动，并在第三控制时钟CK_D1或第四控制时钟CK_D2的控制下，控制公共信号点P（2N+1）保持低电平。其中，第三控制时钟CK_D1、第四控制时钟CK_D2对应为第一控制时钟CK_LB1、第二控制时钟CK_LB2或者对应为第二控制时钟CK_LB2、第一控制时钟CK_LB1。
输入控制单元200用于根据第三级传时钟CK_C1控制级传信号的输入以完成对栅极信号点Q（2N+1）（N为自然数）的充电。其中，第三级传时钟CK_C1对应为第一级传时钟CK_LA1或对应为第二级传时钟CK_LA2。
上拉维持单元300用于根据公共信号点P（2N+1）控制栅极信号点Q（2N+1）在非作用期间保持预定电平也即无效电平。
输出控制单元400用于根据第四级传时钟CK_C2控制与栅极信号点Q（2N+1）对应的栅极驱动信号G（2N+1）的输出。其中，第四级传时钟CK_C2对应为第一级传时钟CK_LA1或对应为第二级传时钟CK_LA2。
GAS信号作用单元500用于控制栅极驱动信号G（2N+1）处于有效电平，以实现GOA单元21对应的水平扫描线的充电。
自举电容单元600用于对栅极信号点Q（2N+1）的电压进行再次抬升。
具体来说，以GOA单元为PMOS电路为例来说，正反扫描单元100包括第一晶体管PT0、第二晶体管PT1、第三晶体管PT2和第四晶体管PT3，第一晶体管PT0的栅极接收第一扫描控制信号也即反向扫描控制信号D2U，第一晶体管PT0的源极接收下一级GOA单元21输出的栅极驱动信号G（2N+3），第二晶体管PT1的栅极接收第二扫描控制信号也即正向扫描控制信号U2D，第二晶体管PT1的源极接收上一级GOA单元输出的栅极驱动信号G（2N-1），第一晶体管PT0和第二晶体管PT1的漏极相互连接后与输入控制单元200连接，第三晶体管PT2的栅极接收第一扫描控制信号也即反向扫描控制信号D2U，第三晶体管PT2的源极接收第三控制时钟CK_D1，第四晶体管PT3的栅极接收第二扫描控制信号也即正向扫描控制信号U2D，第四晶体管PT3的源极接收第四控制时钟CK_D2，第三晶体管PT2和第四晶体管PT3的漏极相互连接后与上拉维持单元300连接。
其中，在第一级GOA单元中，第二晶体管PT1的源极接收启动脉冲信号STV。在最后一级GOA单元中，第一晶体管PT0的源极接收启动脉冲信号STV。
输入控制单元200包括第五晶体管PT4，第五晶体管PT4的栅极接收第三级传时钟CK_C1，第五晶体管PT4的源极与第一晶体管PT0、第二晶体管PT1的漏极连接，第五晶体管PT4的漏极与栅极信号点Q（2N+1）连接。
上拉维持单元300包括第六晶体管PT5、第七晶体管PT6、第九晶体管PT8、第十晶体管PT9和第一电容C1，第六晶体管PT5的栅极与公共信号点P（2N+1）连接，第六晶体管PT5的源极与第五晶体管PT4的漏极连接，第六晶体管PT5的漏极与第一恒压源也即正压恒压源VGH连接，第七晶体管PT6的栅极与第五晶体管PT4的漏极连接，第七晶体管PT6的源极与公共信号点P（2N+1）连接，第七晶体管PT6的漏极与第一恒压源也即正压恒压源VGH连接，第九晶体管PT8的栅极与第三晶体管PT2、第四晶体管PT3的漏极连接，第九晶体管PT8的源极与第二恒压源也即负压恒压源VGL连接，第九晶体管PT8的漏极与公共信号点P（2N+1）连接，第十晶体管PT9的栅极与公共信号点P（2N+1）连接，第十晶体管PT9的源极与栅极驱动信号G（2N+1）连接，第十晶体管PT9的漏极与第一恒压源也即正压恒压源VGH连接，第一电容C1的一端与第一恒压源也即正压恒压源VGH连接，第一电容C1的另一端与公共信号点（2N+1）连接。
输出控制单元400包括第十一晶体管PT10和第二电容C2，第十一晶体管PT10的栅极与栅极信号点Q（2N+1）连接，第十一晶体管PT10的漏极与栅极驱动信号Q（2N+1）连接，第十一晶体管PT10的源极接收第四级传时钟CK_C2，第二电容C2的一端与栅极信号点Q（2N+1）连接，第二电容C2的另一端与栅极驱动信号G（2N+1）连接；
GAS信号作用单元500包括第十三晶体管PT12和第十四晶体管PT13，第十三晶体管PT12的栅极、第十四晶体管PT13的栅极和漏极接收GAS信号GAS，第十三晶体管PT12的漏极连接第一恒压源也即正压恒压源VGH，第十三晶体管PT12的源极连接公共信号点P（2N+1），第十三晶体管PT12的源极连接栅极驱动信号G（2N+1）。
自举电容单元600包括自举电容Cload，自举电容Cload的一端与栅极驱动信号G (2N+1)连接，自举电容Cload的另一端与地信号GND连接。
优选地，GOA单元21进一步包括稳压单元700，稳压单元700用于实现栅极信号点Q（2N+1）的稳压以及栅极信号点Q（2N+1）的漏电防治。具体来说，稳压单元700包括第八晶体管PT7，第八晶体管PT7串接于第五晶体管PT4的源极与栅极信号点Q(2N+1)之间，第八晶体管PT7的栅极与第二恒压源也即负压恒压源VGL连接，第八晶体管PT7的漏极与第五晶体管PT4的漏极连接，第八晶体管PT7的源极与栅极信号点Q（2N+1）连接。
优选地，GOA单元21进一步包括上拉辅助单元800，上拉辅助单元800用于防止第五晶体管PT4和第六晶体管PT5在对栅极信号点Q（2N+1）进行充电的过程中出现漏电的问题。具体来说，上拉辅助单元800包括第十二晶体管PT11，第十二晶体管PT11的栅极与第一晶体管PT0、第二晶体管PT1的漏极连接，第十二晶体管PT11的源极与公共信号点P（2N+1）连接，第十二晶体管PT11的漏极与第一恒压源也即正压恒压源VGH连接。
在第一GOA子电路201中，在第一级、第五级、…第4N+1（N为自然数）级GOA单元21中，第三级传时钟CK_C1为第一级传时钟CK_LA1也即第一时钟信号CK1，第四级传时钟CK_C2为第二级传时钟CK_LA2也即第三时钟信号CK3，第三控制时钟CK_D1为第一控制时钟CK_LB1也即第二时钟信号CK2，第四控制时钟CK_D2为第二控制时钟CK_LB2也即为第四时钟信号CK4。在第三级、第七级、…第4N+3（N为自然数）级GOA单元21中，第三级传时钟CK_C1为第二级传时钟CK_LA2也即第三时钟信号CK3，第四级传时钟CK_C2为第一级传时钟CK_LA1也即第一时钟信号CK1，第三控制时钟CK_D1为第二控制时钟CK_LB2也即第四时钟信号CK4，第四控制时钟CK_D2为第一控制时钟CK_LB2也即第二时钟信号CK2。
本领域的技术人员可以理解，当GOA单元为NMOS电路时，上述所有晶体管为NMOS晶体管，第一扫描控制信号对应正向扫描控制信号U2D，第二扫描控制信号对应反相扫描控制信号D2U，第一恒压源对应负压恒压源VGL，第二恒压源对应正压恒压源VGH。
本领域的技术人员可以理解，当第一GOA子电路中的GOA单元为PMOS电路，对应的第一控制模块22A第一控制晶体管T1和第二控制晶体管T2为PMOS管。第一GOA子电路中的GOA单元为NMOS电路，对应的第一控制模块22A第一控制晶体管T1和第二控制晶体管T2为NMOS管。
位于第二GOA子电路202的第2N+2级GOA单元21与位于第一GOA子电路202的第2N+1级GOA单元21类似，为简单起见，在此不再详述。其中，第2N+2级GOA单元21中的第一级传时钟CK_RA1、第二级传时钟CK_RA2、第一控制时钟CK_RB1、第二控制时钟CK_RB2对应于第2N+1级GOA单元21中的第一级传时钟CK_LA1、第二级传时钟CK_LA2、第一控制时钟CK_LB1、第二控制时钟CK_LB2。
图4是本发明第二实施例的GOA电路中第一GOA子电路的工作时序图。如图4所示，以第一GOA子电路为PMOS电路为例来说，当GAS信号GAS有效也即为低电平信号时，GOA电路20实现All Gate On功能，与各奇数级水平扫描线对应的栅极驱动信号G（2N+1）输出低电平信号。当GOA电路20完成All Gate On功能后，由于自举电容Cload的存在，与各奇数级水平扫描线对应的栅极驱动信号G（2N+1）不会马上变为高电平，而会保持Cload holding的低电平信号。
以GOA电路20为正向驱动为例，如果与奇数级水平扫描线对应的栅极驱动信号在第三时钟信号CK3有效之前不能放电至高电平，则除第一级水平扫描线以外，其它奇数级水平扫描线上会产生冗余的脉冲信号。具体来说，第一级水平扫描线由第一级GOA单元驱动，由于第一级GOA单元的级传信号为启动脉冲信号STV，第一级GOA单元正常驱动，不会产生冗余的脉冲信号。第三级水平扫描线由第三级GOA单元驱动，而第三级GOA单元的级传信号为第一级GOA单元的栅极驱动信号G（1），当第一时钟信号CK1为低电平时，由于栅极驱动信号G（1）保持Cload holding的低电平信号，则栅极驱动信号G（1）的低电平信号会传递至第三级GOA单元的栅极信号点Q（3），使得第三级GOA单元21先于第一级GOA单元21工作，并使得第三级GOA单元21输出的栅极驱动信号G（3）产生一个冗余的脉冲，这个冗余的脉冲会继续影响下一级GOA单元21的栅极驱动信号。基于相同的理由，在第一时钟信号CK1有效时，第七级、第十一级、…第4N+3级GOA单元的栅极驱动信号均会产生冗余的脉冲。
为了避免上述问题的产生，如图4所示，在第一时钟信号CK1开始有效时，设置使能信号EN为高电平且保持一个工作周期，此时，第一控制晶体管T1、第二控制晶体管T2截止，第一时钟信号CK1和第三时钟信号CK3无法输送至第一级传时钟CK_LA1、第二级传时钟CK_LA2，此时，第一GOA子电路中的GOA单元在第一控制时钟CK_LB1、第二控制时钟CK_LB2（也即第二时钟信号CK2、第四时钟信号CK4）的控制下使公共信号点P（2N+1）处于低电平信号，进而使得栅极驱动信号G（2N+1）在第三时钟信号CK3有效之前处于高电平信号，从而避免产生冗余的脉冲信号。随后，保持正常的第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4的驱动顺序对第一GOA子电路201进行驱动，从而实现对水平扫描线的正常充电。其中，一个工作周期是指第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4依次有效所持续的时间周期。
在第二实施例中，第二GOA子电路202的工作时序与第一GOA子电路201的工作时序类似，为简约起见，在此不再赘述。
本发明进一步提供一种液晶显示器，包括了上述GOA电路。
本发明的有益效果是：本发明的GOA电路及液晶显示器通过GOA电路对所有水平扫描线同时充电后，屏蔽第一级传时钟、第二级传时钟，以使第一控制时钟、第二控制时钟控制水平扫描线上的栅极驱动信号放电至预定电平，从而能够避免在第一个栅极驱动信号输出之前在水平扫描线上产生冗余的脉冲信号，进而保证了GOA电路的正常工作。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种GOA电路，用于液晶显示器，其中，所述GOA电路包括级联的多个GOA单元，每一所述GOA单元用于在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对显示区域中对应的水平扫描线进行充电，所述第一级传时钟、第二级传时钟用于控制所述GOA单元的级传信号的输入以及栅极驱动信号的产生，所述第一控制时钟、第二控制时钟用于控制所述栅极驱动信号处于预定电平，其中，所述级传信号为启动脉冲信号或相邻的所述GOA单元的所述栅极驱动信号；
    所述GOA电路进一步包括控制模块，所述控制模块用于在所述GOA电路对所有所述水平扫描线同时充电后，屏蔽所述第一级传时钟、第二级传时钟，以使所述第一控制时钟、第二控制时钟控制所述水平扫描线上的所述栅极驱动信号放电至预定电平，从而避免在第一个所述栅极驱动信号输出之前在所述水平扫描线上产生冗余的脉冲信号；
    所述控制模块包括第一控制晶体管和第二控制晶体管，所述第一控制晶体管、第二控制晶体管的第一端相互连接后接收使能信号，所述第一控制晶体管、第二控制晶体的第二端对应连接所述第一级传时钟、第二级传时钟，所述第一控制晶体管、第二控制晶体管的第三端连接所述GOA单元，其中，在所述GOA电路对所有所述水平扫描线同时充电后，所述使能信号控制所述第一控制晶体管、第二控制晶体管截止以屏蔽所述第一级传时钟、第二级传时钟，从而使得所述第一控制时钟、第二控制时钟控制所有所述水平扫描线上的栅极驱动信号放电至所述预定电平；
    所述GOA电路接收第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，其中，所述第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号在所述GOA电路的工作周期依次分时有效；
    所述GOA电路包括奇数级的所述GOA单元级联形成的第一GOA子电路，所述第一GOA子电路在所述第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对奇数级的所述水平扫描线进行充电；
    其中，在所述第一GOA子电路中，所述第一级传时钟、第二级传时钟对应所述第一时钟信号、第三时钟信号，所述第一控制时钟、第二控制时钟对应所述第二时钟信号、第四时钟信号；
    所述GOA电路进一步包括与所述第一GOA子电路对应的控制模块，记为第一控制模块，所述第一控制模块用于在所述第一GOA子电路中，屏蔽所述第一时钟信号、第三时钟信号，以使所述第二时钟信号、第四时钟信号控制奇数级的所述水平扫描线上的栅极驱动信号放电至所述预定电平；
    所述GOA电路进一步包括偶数级的所述GOA单元级联形成的第二GOA子电路，所述第二GOA子电路在所述第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对偶数级的所述水平扫描线进行充电；
    其中，在所述第二GOA子电路中，所述第一级传时钟、第二级传时钟对应所述第二时钟信号、第四时钟信号，所述第一控制时钟、第二控制时钟对应所述第一时钟信号、第三时钟信号；
    所述GOA电路进一步包括与所述第二GOA子电路对应的控制模块，记为第二控制模块，所述第二控制模块用于在所述第二GOA子电路中，屏蔽所述第二时钟信号、第四时钟信号，以使所述第一时钟信号、第三时钟信号控制偶数级的所述水平扫描线上的栅极驱动信号放电至所述预定电平。
  2. 根据权利要求1所述的GOA电路，其中，所述第一控制晶体管、第二控制晶体管为PMOS管，所述第一控制晶体管、第二控制晶体管的所述第一端、第二端、第三端对应所述PMOS管的栅极、漏极和源极；其中，当所述使能信号为高电平信号时，所述第一控制晶体管、第二控制晶体管截止。
  3. 一种GOA电路，用于液晶显示器，其中，所述GOA电路包括级联的多个GOA单元，每一所述GOA单元用于在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对显示区域中对应的水平扫描线进行充电，所述第一级传时钟、第二级传时钟用于控制所述GOA单元的级传信号的输入以及栅极驱动信号的产生，所述第一控制时钟、第二控制时钟用于控制所述栅极驱动信号处于预定电平，其中，所述级传信号为启动脉冲信号或相邻的所述GOA单元的所述栅极驱动信号；
    所述GOA电路进一步包括控制模块，所述控制模块用于在所述GOA电路对所有所述水平扫描线同时充电后，屏蔽所述第一级传时钟、第二级传时钟，以使所述第一控制时钟、第二控制时钟控制所述水平扫描线上的所述栅极驱动信号放电至预定电平，从而避免在第一个所述栅极驱动信号输出之前在所述水平扫描线上产生冗余的脉冲信号。
  4. 根据权利要求3所述的GOA电路，其中，所述控制模块包括第一控制晶体管和第二控制晶体管，所述第一控制晶体管、第二控制晶体管的第一端相互连接后接收使能信号，所述第一控制晶体管、第二控制晶体的第二端对应连接所述第一级传时钟、第二级传时钟，所述第一控制晶体管、第二控制晶体管的第三端连接所述GOA单元，其中，在所述GOA电路对所有所述水平扫描线同时充电后，所述使能信号控制所述第一控制晶体管、第二控制晶体管截止以屏蔽所述第一级传时钟、第二级传时钟，从而使得所述第一控制时钟、第二控制时钟控制所有所述水平扫描线上的栅极驱动信号放电至所述预定电平。
  5. 根据权利要求4所述的GOA电路，其中，所述第一控制晶体管、第二控制晶体管为PMOS管，所述第一控制晶体管、第二控制晶体管的所述第一端、第二端、第三端对应所述PMOS管的栅极、漏极和源极；其中，当所述使能信号为高电平信号时，所述第一控制晶体管、第二控制晶体管截止。
  6. 根据权利要求4所述的GOA电路，所述第一控制晶体管、第二控制晶体管为NMOS管，所述第一控制晶体管、第二控制晶体管的所述第一端、第二端、第三端对应所述NMOS管的栅极、漏极和源极；其中，当所述控制信号为低电平信号时，所述第一控制晶体管、第二控制晶体管截止。
  7. 根据权利要求3所述的GOA电路，其中，所述GOA电路接收第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，其中，所述第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号在所述GOA电路的工作周期依次分时有效；
    所述GOA电路包括奇数级的所述GOA单元级联形成的第一GOA子电路，所述第一GOA子电路在所述第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对奇数级的所述水平扫描线进行充电；
    其中，在所述第一GOA子电路中，所述第一级传时钟、第二级传时钟对应所述第一时钟信号、第三时钟信号，所述第一控制时钟、第二控制时钟对应所述第二时钟信号、第四时钟信号；
    所述GOA电路进一步包括与所述第一GOA子电路对应的控制模块，记为第一控制模块，所述第一控制模块用于在所述第一GOA子电路中，屏蔽所述第一时钟信号、第三时钟信号，以使所述第二时钟信号、第四时钟信号控制奇数级的所述水平扫描线上的栅极驱动信号放电至所述预定电平。
  8. 根据权利要求7所述的GOA电路，其中，
    所述GOA电路进一步包括偶数级的所述GOA单元级联形成的第二GOA子电路，所述第二GOA子电路在所述第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对偶数级的所述水平扫描线进行充电；
    其中，在所述第二GOA子电路中，所述第一级传时钟、第二级传时钟对应所述第二时钟信号、第四时钟信号，所述第一控制时钟、第二控制时钟对应所述第一时钟信号、第三时钟信号；
    所述GOA电路进一步包括与所述第二GOA子电路对应的控制模块，记为第二控制模块，所述第二控制模块用于在所述第二GOA子电路中，屏蔽所述第二时钟信号、第四时钟信号，以使所述第一时钟信号、第三时钟信号控制偶数级的所述水平扫描线上的栅极驱动信号放电至所述预定电平。
  9. 根据权利要求8所述的GOA电路，其中，所述GOA单元包括正反扫描单元、输入控制单元、上拉维持单元、输出控制单元、GAS信号作用单元和自举电容单元；
    其中，所述正反扫描单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，所述第一晶体管的栅极接收第一扫描控制信号，所述第一晶体管的源极接收下一级所述GOA单元输出的所述栅极驱动信号，所述第二晶体管的栅极接收第二扫描控制信号，所述第二晶体管的源极接收上一级所述GOA单元输出的所述栅极驱动信号，所述第一晶体管和所述第二晶体管的漏极相互连接后与所述输入控制单元连接，所述第三晶体管的栅极接收所述第一扫描控制信号，所述第三晶体管的源极接收第三控制时钟，所述第四晶体管的栅极接收所述第二扫描控制信号，所述第四晶体管的源极接收第四控制时钟，所述第三晶体管和所述第四晶体管的漏极相互连接后与所述上拉维持单元连接；
    所述输入控制单元包括第五晶体管，所述第五晶体管的栅极接收第三级传时钟，所述第五晶体管的源极与所述第一晶体管、第二晶体管的漏极连接，所述第五晶体管的漏极与栅极信号点连接；
    所述上拉维持单元包括第六晶体管、第七晶体管、第九晶体管、第十晶体管和第一电容，所述第六晶体管的栅极与公共信号点连接，所述第六晶体管的源极与所述第五晶体管的漏极连接，所述第六晶体管的漏极与第一恒压源连接，所述第七晶体管的栅极与所述第五晶体管的漏极连接，所述第七晶体管的源极与所述公共信号点连接，所述第七晶体管的漏极与所述第一恒压源连接，所述第九晶体管的栅极与所述第三晶体管、第四晶体管的漏极连接，所述第九晶体管的源极与第二恒压源连接，所述第九晶体管的漏极与所述公共信号点连接，所述第十晶体管的栅极与所述公共信号点连接，所述第十晶体管的源极与所述栅极驱动信号连接，所述第十晶体管的漏极与所述第一恒压源连接，所述第一电容的一端与所述第一恒压源连接，所述第一电容的另一端与所述公共信号点连接；
    所述输出控制单元包括第十一晶体管和第二电容，所述第十一晶体管的栅极与所述栅极信号点连接，所述第十一晶体管的漏极与所述栅极驱动信号连接，所述第十一晶体管的源极接收第四级传时钟，所述第二电容的一端与所述栅极信号点连接，所述第二电容的另一端与所述栅极驱动信号连接；
    所述GAS信号作用单元包括第十三晶体管和第十四晶体管，所述第十三晶体管的栅极、第十四晶体管的栅极和漏极接收GAS信号，所述第十三晶体管的漏极连接所述第一恒压源，所述第十三晶体管的源极连接所述公共信号点，所述第十三晶体管的源极连接所述栅极驱动信号；
    所述自举电容单元包括自举电容，所述自举电容的一端与所述栅极驱动信号连接，所述自举电容的另一端与地信号连接；
    其中，所述第三级传时钟、第四级传时钟对应所述第一级传时钟、第二级传时钟或所述第二级传时钟、第一级传时钟，所述第三控制时钟、第四控制时钟对应所述第一控制时钟、第二控制时钟或所述第二控制时钟、第一控制时钟。
  10. 根据权利要求9所述的GOA电路，所述GOA单元进一步包括稳压单元，所述稳压单元包括第八晶体管，所述第八晶体管串接于所述第五晶体管的源极与所述栅极信号点之间，所述第八晶体管的栅极与所述第二恒压源连接，所述第八晶体管的漏极与所述第五晶体管的漏极连接，所述第八晶体管的源极与所述栅极信号点连接。
  11. 根据权利要求10所述的GOA电路，所述GOA单元进一步包括上拉辅助单元，所述上拉辅助单元包括第十二晶体管，所述第十二晶体管的栅极与所述第一晶体管、第二晶体管的漏极连接，所述第十二晶体管的源极与所述公共信号点连接，所述十二晶体管的漏极与所述第一恒压源连接。
  12. 一种液晶显示器，其中，包括GOA电路，所述GOA电路包括级联的多个GOA单元，每一所述GOA单元用于在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对显示区域中对应的水平扫描线进行充电，所述第一级传时钟、第二级传时钟用于控制所述GOA单元的级传信号的输入以及栅极驱动信号的产生，所述第一控制时钟、第二控制时钟用于控制所述栅极驱动信号处于预定电平，其中，所述级传信号为启动脉冲信号或相邻的所述GOA单元的所述栅极驱动信号；
    所述GOA电路进一步包括控制模块，所述控制模块用于在所述GOA电路对所有所述水平扫描线同时充电后，屏蔽所述第一级传时钟、第二级传时钟，以使所述第一控制时钟、第二控制时钟控制所述水平扫描线上的所述栅极驱动信号放电至预定电平，从而避免在第一个所述栅极驱动信号输出之前在所述水平扫描线上产生冗余的脉冲信号。
  13. 根据权利要求12所述的液晶显示器，其中，所述控制模块包括第一控制晶体管和第二控制晶体管，所述第一控制晶体管、第二控制晶体管的第一端相互连接后接收使能信号，所述第一控制晶体管、第二控制晶体的第二端对应连接所述第一级传时钟、第二级传时钟，所述第一控制晶体管、第二控制晶体管的第三端连接所述GOA单元，其中，在所述GOA电路对所有所述水平扫描线同时充电后，所述使能信号控制所述第一控制晶体管、第二控制晶体管截止以屏蔽所述第一级传时钟、第二级传时钟，从而使得所述第一控制时钟、第二控制时钟控制所有所述水平扫描线上的栅极驱动信号放电至所述预定电平。
  14. 根据权利要求13所述的液晶显示器，其中，所述第一控制晶体管、第二控制晶体管为PMOS管，所述第一控制晶体管、第二控制晶体管的所述第一端、第二端、第三端对应所述PMOS管的栅极、漏极和源极；其中，当所述使能信号为高电平信号时，所述第一控制晶体管、第二控制晶体管截止。
  15. 根据权利要求13所述的液晶显示器，所述第一控制晶体管、第二控制晶体管为NMOS管，所述第一控制晶体管、第二控制晶体管的所述第一端、第二端、第三端对应所述NMOS管的栅极、漏极和源极；其中，当所述控制信号为低电平信号时，所述第一控制晶体管、第二控制晶体管截止。
  16. 根据权利要求12所述的液晶显示器，其中，所述GOA电路接收第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，其中，所述第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号在所述GOA电路的工作周期依次分时有效；
    所述GOA电路包括奇数级的所述GOA单元级联形成的第一GOA子电路，所述第一GOA子电路在所述第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对奇数级的所述水平扫描线进行充电；
    其中，在所述第一GOA子电路中，所述第一级传时钟、第二级传时钟对应所述第一时钟信号、第三时钟信号，所述第一控制时钟、第二控制时钟对应所述第二时钟信号、第四时钟信号；
    所述GOA电路进一步包括与所述第一GOA子电路对应的控制模块，记为第一控制模块，所述第一控制模块用于在所述第一GOA子电路中，屏蔽所述第一时钟信号、第三时钟信号，以使所述第二时钟信号、第四时钟信号控制奇数级的所述水平扫描线上的栅极驱动信号放电至所述预定电平。
  17. 根据权利要求16所述的液晶显示器，其中，
    所述GOA电路进一步包括偶数级的所述GOA单元级联形成的第二GOA子电路，所述第二GOA子电路在所述第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对偶数级的所述水平扫描线进行充电；
    其中，在所述第二GOA子电路中，所述第一级传时钟、第二级传时钟对应所述第二时钟信号、第四时钟信号，所述第一控制时钟、第二控制时钟对应所述第一时钟信号、第三时钟信号；
    所述GOA电路进一步包括与所述第二GOA子电路对应的控制模块，记为第二控制模块，所述第二控制模块用于在所述第二GOA子电路中，屏蔽所述第二时钟信号、第四时钟信号，以使所述第一时钟信号、第三时钟信号控制偶数级的所述水平扫描线上的栅极驱动信号放电至所述预定电平。
  18. 根据权利要求17所述的液晶显示器，其中，所述GOA单元包括正反扫描单元、输入控制单元、上拉维持单元、输出控制单元、GAS信号作用单元和自举电容单元；
    其中，所述正反扫描单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，所述第一晶体管的栅极接收第一扫描控制信号，所述第一晶体管的源极接收下一级所述GOA单元输出的所述栅极驱动信号，所述第二晶体管的栅极接收第二扫描控制信号，所述第二晶体管的源极接收上一级所述GOA单元输出的所述栅极驱动信号，所述第一晶体管和所述第二晶体管的漏极相互连接后与所述输入控制单元连接，所述第三晶体管的栅极接收所述第一扫描控制信号，所述第三晶体管的源极接收第三控制时钟，所述第四晶体管的栅极接收所述第二扫描控制信号，所述第四晶体管的源极接收第四控制时钟，所述第三晶体管和所述第四晶体管的漏极相互连接后与所述上拉维持单元连接；
    所述输入控制单元包括第五晶体管，所述第五晶体管的栅极接收第三级传时钟，所述第五晶体管的源极与所述第一晶体管、第二晶体管的漏极连接，所述第五晶体管的漏极与栅极信号点连接；
    所述上拉维持单元包括第六晶体管、第七晶体管、第九晶体管、第十晶体管和第一电容，所述第六晶体管的栅极与公共信号点连接，所述第六晶体管的源极与所述第五晶体管的漏极连接，所述第六晶体管的漏极与第一恒压源连接，所述第七晶体管的栅极与所述第五晶体管的漏极连接，所述第七晶体管的源极与所述公共信号点连接，所述第七晶体管的漏极与所述第一恒压源连接，所述第九晶体管的栅极与所述第三晶体管、第四晶体管的漏极连接，所述第九晶体管的源极与第二恒压源连接，所述第九晶体管的漏极与所述公共信号点连接，所述第十晶体管的栅极与所述公共信号点连接，所述第十晶体管的源极与所述栅极驱动信号连接，所述第十晶体管的漏极与所述第一恒压源连接，所述第一电容的一端与所述第一恒压源连接，所述第一电容的另一端与所述公共信号点连接；
    所述输出控制单元包括第十一晶体管和第二电容，所述第十一晶体管的栅极与所述栅极信号点连接，所述第十一晶体管的漏极与所述栅极驱动信号连接，所述第十一晶体管的源极接收第四级传时钟，所述第二电容的一端与所述栅极信号点连接，所述第二电容的另一端与所述栅极驱动信号连接；
    所述GAS信号作用单元包括第十三晶体管和第十四晶体管，所述第十三晶体管的栅极、第十四晶体管的栅极和漏极接收GAS信号，所述第十三晶体管的漏极连接所述第一恒压源，所述第十三晶体管的源极连接所述公共信号点，所述第十三晶体管的源极连接所述栅极驱动信号；
    所述自举电容单元包括自举电容，所述自举电容的一端与所述栅极驱动信号连接，所述自举电容的另一端与地信号连接；
    其中，所述第三级传时钟、第四级传时钟对应所述第一级传时钟、第二级传时钟或所述第二级传时钟、第一级传时钟，所述第三控制时钟、第四控制时钟对应所述第一控制时钟、第二控制时钟或所述第二控制时钟、第一控制时钟。
  19. 根据权利要求18所述的液晶显示器，所述GOA单元进一步包括稳压单元，所述稳压单元包括第八晶体管，所述第八晶体管串接于所述第五晶体管的源极与所述栅极信号点之间，所述第八晶体管的栅极与所述第二恒压源连接，所述第八晶体管的漏极与所述第五晶体管的漏极连接，所述第八晶体管的源极与所述栅极信号点连接。
  20. 根据权利要求19所述的液晶显示器，所述GOA单元进一步包括上拉辅助单元，所述上拉辅助单元包括第十二晶体管，所述第十二晶体管的栅极与所述第一晶体管、第二晶体管的漏极连接，所述第十二晶体管的源极与所述公共信号点连接，所述十二晶体管的漏极与所述第一恒压源连接。
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