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WO2017028909A1 - Registres physiques partagés et table de mappage pour registres architecturaux de fils multiples - Google Patents

Registres physiques partagés et table de mappage pour registres architecturaux de fils multiples Download PDF

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Publication number
WO2017028909A1
WO2017028909A1 PCT/EP2015/068977 EP2015068977W WO2017028909A1 WO 2017028909 A1 WO2017028909 A1 WO 2017028909A1 EP 2015068977 W EP2015068977 W EP 2015068977W WO 2017028909 A1 WO2017028909 A1 WO 2017028909A1
Authority
WO
WIPO (PCT)
Prior art keywords
registers
register
threads
architectural
recent usage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2015/068977
Other languages
English (en)
Inventor
Simcha Gochman
Zuguang WU
Weiguang CAI
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to PCT/EP2015/068977 priority Critical patent/WO2017028909A1/fr
Priority to CN201580082261.5A priority patent/CN107851006B/zh
Publication of WO2017028909A1 publication Critical patent/WO2017028909A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30138—Extension of register space, e.g. register cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Definitions

  • the present invention in some embodiments thereof, relates to
  • CPU cores especially those that are targeted to server market segments, increasingly support multi-threading (MT).
  • MT multi-threading
  • the demand for multi-threaded cores has been increasing at a high rate in all server market segments, especially in the context of Scale-out applications (e.g. Big Data).
  • Fine Grain MT (FGMT) - Threads are interleaved on a clock by clock basis;
  • Coarse Grain MT (CGMT, also denoted Switch on Event MT and SoE MT) - A thread runs until it is blocked by an event (that typically results in a long latency stall). Then it is replaced by the next thread that waits in the raw.
  • Each Architectural Register File Set typically includes:
  • Integer Register File (e.g. ARMv8 employs 31 Registers, each 64-bits wide);
  • Floating Point / SIMD Register File e.g. ARMv8 employs 32 Registers, each 128-bits wide;
  • Status Register e.g. ARMv8 employs roughly 6 Registers, each 64- bits wide).
  • Duplicating the ARF for each thread This is used for FGMT and SMT and in some cases also for CGMT (to avoid long switch times). Duplicating ARFs is very wasteful in terms of silicon area and energy consumption.
  • An object of the current invention is to improve multi-threading.
  • Embodiments presented herein perform map recently and/or frequently used registers of running threads (i.e. active threads) to physical registers. Registers of all the threads are saved in architectural registers, optionally in a SRAM. When a requested register is not mapped to a physical register, the content of the architectural register is stored in an allocated physical register, possibly replacing previously stored content (e.g. from a suspended thread). In this way, silicon area and energy
  • the system includes an interface which receives register accessing requests and a processing unit.
  • the processing unit dynamically maps a group of registers from multiple architectural registers to at least one of a multiplicity of physical registers based on at least one of recent usage and access frequency of each one of the architectural registers by multiple multithreading (MT) threads, and looks up a match for each one of the register accessing requests in the architectural registers when the match is not found in the physical registers.
  • MT multithreading
  • the MT threads submit the register accessing requests and are of a multithreading processor.
  • the register accessing requests are received via at least one pipeline engine.
  • the architectural registers are stored in a static random access memory (SRAM).
  • SRAM static random access memory
  • the system further includes a memory for storing an access frequency dataset.
  • the processing unit updates the access frequency dataset with a frequency of access to respective registers and performs the mapping according to the access frequency dataset.
  • the system further includes a memory for storing a recent usage dataset.
  • the processing unit updates the recent usage dataset with the recent usage and performs the mapping according to the recent usage dataset.
  • the recent usage dataset includes multiple records.
  • Each of the records documents a recent usage of each one of the MT threads to the architectural registers.
  • the recent usage dataset includes respective allocation states of architectural registers.
  • the architectural registers maps to an allocation of suspended and running threads of the multiple MT threads and the physical registers maps to an allocation of running threads of the multiple MT threads.
  • the processing unit updates the recent usage dataset when switching an allocation of any of the physical registers from one of the MT threads to another of the MT threads.
  • the processing unit maps the architectural registers to the MT threads.
  • the processing unit switches mapping of any of the architectural registers from one of the MT threads to another of the architectural registers.
  • the processing unit sets a respective state of physical registers mapped to an active thread to available when the active thread is inactivated by a switch to a different thread.
  • a method for handling a register accessing request includes:
  • mapping dynamically a group of registers from multiple architectural registers to at least one of a multiplicity of physical registers based on at least one of recent usage and access frequency of each one of the architectural registers by multiple multithreading (MT) threads;
  • the method further includes monitoring the at least one of recent usage and access frequency by recording the plurality of register accessing requests which are received via at least one pipeline engine.
  • Fig. 1 is a simplified block diagram of system for handling a register accessing request, according to embodiments of the invention
  • Fig. 2 is a simplified illustration of a register mapping scheme, according to embodiments of the invention.
  • Fig. 3 is a simplified block diagram of a method for handling register accessing requests according to embodiments of the invention.
  • Fig. 4 is a simplified block diagram of a method for thread context switching according to embodiments of the invention.
  • Fig. 5 is a simplified flowchart of a method for handling a register accessing request according to embodiments of the invention.
  • the present invention in some embodiments thereof, relates to multithreading and, more specifically, but not exclusively, to architectural register management in multi-threading cores.
  • Embodiments of the invention utilize a register mapping scheme that dynamically maps the most recently and/or frequently used architectural registers to a smaller physical register file set, and fetches the registers' content on demand.
  • the register mapping (also denoted herein the mapping table) is checked to see if the requested architectural register is mapped to a physical registers.
  • the physical register is utilized for the register access.
  • mapping table is maintained dynamically and updated as needed during assignment and reassignment of physical registers to architectural registers.
  • the present invention may be a system, a method, and/or a computer program product.
  • the computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.
  • the computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device.
  • the computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.
  • Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network.
  • a network for example, the Internet, a local area network, a wide area network and/or a wireless network.
  • the computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.
  • the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
  • LAN local area network
  • WAN wide area network
  • Internet Service Provider for example, AT&T, MCI, Sprint, EarthLink, MSN, GTE, etc.
  • electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
  • FPGA field-programmable gate arrays
  • PLA programmable logic arrays
  • each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s).
  • the functions noted in the block may occur out of the order noted in the figures.
  • two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
  • a memory e.g. an SRAM that stores architectural states of multiple
  • architectural register file and "ARF” mean the dataset which includes the entire architectural state for all threads. The terms are not limited to a particular type of file, organization of data or memory element used for storing the ARF.
  • the memory storing the ARF has denser data storage than the physical registers but its access time is longer than the access time of the physical registers.
  • a reasonably sized PRF enables quick access to some architectural register content without requiring a drastic increase in silicon area.
  • physical register file and “PRF” mean the dataset stored in the physical registers. The terms are not limited to a particular type of file or organization of data.
  • the memory stores all the architectural states for all threads. This embodiment uses simple logic for fixed indexing but is more costly in area. In other embodiments, the memory only stores architectural states not stored in the PRF, resulting in a reduction in area with increased indexing complexity.
  • each active thread has predefined number of physical registers cannot use physical registers allocated to other threads.
  • physical registers are dynamically allocated to all active threads.
  • the mapping table shows that the requested register is present in the PRF
  • the physical register is utilized for the register access.
  • a replacement cycle occurs.
  • one or more physical registers for example the least recently used registers
  • These physical registers are then available for storage of other architectural register values.
  • all the selected architectural registers e.g. recently used
  • the mapping table is maintained dynamically and updated as needed during or after the replacement cycle.
  • register request and "register access request” include requests for read and write operations to the register.
  • Fig. 1 is a simplified block diagram of system for handling a register accessing request, according to embodiments of the invention.
  • System 100 includes interface 110 and processing unit 120.
  • Interface 110 receives register accessing requests.
  • the register accessing requests are submitted by multiple MT threads.
  • the register accessing requests are received via at least one pipeline engine.
  • Processing unit 120 dynamically maps a group of registers from architectural registers 150 to physical registers 140. Optionally the mapping is based on:
  • processing unit 120 determines from the mapping table whether the register value is stored in physical registers 140. When a match is not found in the physical registers 140, processing unit 120 looks up a match for the requested register in architectural registers 150.
  • the architectural registers are stored in a static random access memory (SRAM).
  • SRAM static random access memory
  • system 100 includes a memory which stores a recent usage dataset.
  • Processing unit 120 updates the recent usage dataset with recent usage of each register, and performs the mapping, at least in part, according to the recent usage dataset.
  • the memory stores an access frequency dataset.
  • Processing unit 120 updates the recent usage dataset with access frequency of each register, and performs the mapping, at least in part, according to the access frequency dataset.
  • the recent usage dataset comprises multiple records.
  • Each record documents the recent usage of architectural registers by a respective thread.
  • the recent usage dataset includes an allocation state of each architectural register.
  • the allocation state indicates when the architectural register is allocated to a physical register, in which case the architectural register value may be read from or written to the physical register, and optionally indicates the physical register to which the architectural register is allocated.
  • architectural registers 150 are allocated to both suspended (i.e. inactive) and running (i.e. active) threads of the multiple MT threads, and physical registers 140 are allocated to running threads.
  • processing unit 120 updates the recent usage dataset when the allocation of an architectural register is switched from one MT thread to another thread. This may occur when a thread is terminated or added.
  • processing unit 120 updates the recent usage dataset when the allocation of a physical register is switched from one MT thread to another thread. This may occur when a thread is inactive and the physical register is reallocated to an architectural register of a different thread.
  • processing unit 120 maps the architectural registers to respective MT threads.
  • processing unit 120 switches the mapping of an architectural register for a given MT thread to different architectural register.
  • FIG. 2 is a simplified illustration of a register mapping scheme, according to embodiments of the invention.
  • Fig. 2 is a simplified illustration of a register mapping scheme, according to embodiments of the invention.
  • N denotes a number of active threads
  • M denotes a total number of threads (active and inactive);
  • K denotes a number of all registers per thread
  • J denotes a number of registers per thread which are stored in
  • the total number of registers in the ARF is M*K, whereas the number of registers in the PRF is the smaller number N*J.
  • the registers stored in the PRF are selected on the basis of access frequency ("frequently-used").
  • the registers stored in the PRF are selected by a different criterion (e.g. recently-used) and register mapping, access and handling is performed in a substantially similar manner.
  • mapping table 210 specifies whether the requested register is allocated in PRF 220 and also maintains other information used for finding candidates for replacement (e.g. the least frequently used register). In the embodiment of Fig. 2, mapping table 210 holds the following fields for each register of the active thread:
  • iii) Dirty - indicates whether the value stored in the architectural register is corresponds to the value of the mapped physical register; iv) Access frequency - May be used to select a physical register for overwrite when a requested architectural register is not in the PRF.
  • pipeline engine 200 is running N active threads. Active threads issue register access requests for architectural registers.
  • mapping table 210 is used to determine whether the register value may be accessed from the PRF 220 relatively quickly or must be obtained from ARF 230.
  • ARF 230 stores the architecture register files of all the active and inactive threads. Data may be transferred between ARF 230 and PRF 220 to keep the architectural and physical register values up to date as required for operation. The mapping table is updated accordingly.
  • a "victim" physical register is reallocated for the requested architectural register and the content is of the reallocated register is replaced.
  • inactive threads are the preferred providers of victim physical registers.
  • the victim physical register is selected at least in part on data stored in the mapping table (e.g. access frequency and/or recent access).
  • remapping of source and destination registers is done in the pipeline engine.
  • FIG. 3 is a simplified flowchart of a method for handling a register accessing request according to embodiments of the invention.
  • register accessing requests are received.
  • the register mapping is checked in 320 to determine when the requested register is mapped to a physical register.
  • a match is looked up in the architectural registers (i.e. ARF) for each requested register which is not mapped to a physical register.
  • the architectural registers i.e. ARF
  • the requested register is accessed from the PRF.
  • Register mapping from architectural registers to physical registers is performed dynamically in 360.
  • the mapping may be based on a recent usage of each architectural register by the MT threads and/or on recent usage of each architectural register by the MT threads.
  • the mapping is performed based on an alternate or additional mapping criterion.
  • recent usage of register usage is monitored by recording register accessing requests which are received via at least one pipeline engine.
  • FIG. 4 is a simplified block diagram of a method for handling register accessing requests according to embodiments of the invention.
  • a register accessing request is issued by a pipeline engine.
  • the mapping table is checked to determine whether the requested register is stored in the PRF (e.g. by checking the "valid" bit of the requested register).
  • register read or write access is performed in 420.
  • the write data is stored in the physical register mapped to the requested architectural register.
  • the value stored in the physical register mapped to the requested architectural register is returned.
  • the PRF is searched in
  • FIG. 5 is a simplified block diagram of a method for thread context switching according to embodiments of the invention.
  • the thread switch is hardware or software.
  • the engine pipeline switches the active thread to a different thread, temporarily blocking the previously active thread.
  • the valid bits for the now active thread are set to zero.
  • only registers marked as dirty in the mapping table are updated in the ARF.
  • the thread switch is a software switch
  • the software switches the active thread to another thread, inactivating the previously active thread.
  • all physical registers mapped to architectural registers for the currently active thread are read and written to memory (i.e. updated in the ARF).
  • all valid bits in the mapping table are set to zero for the currently active thread.
  • the previously active thread is deleted from the thread control register which specifies active threads.
  • ARFs are not duplicated per thread and recovery of architectural registers is done on demand.
  • Retrieval of registers for a new thread may be performed during the thread switch time (i.e. while the machine front- end is fetching instructions from the new thread). Suspended threads naturally provide physical register victim candidates. Avoiding full ARF duplication results in significant reduction in area (die size) and in energy consumption.
  • the thread switch time is significantly shortened relative to full ARFs save and restore and may be performed primarily in the background of execution.
  • composition or method may include additional ingredients and/or steps, but only if the additional ingredients and/or steps do not materially alter the basic and novel characteristics of the claimed composition or method.
  • the singular form “a”, “an” and “the” include plural references unless the context clearly dictates otherwise.
  • the term “a compound” or “at least one compound” may include a plurality of compounds, including mixtures thereof.
  • range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
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Abstract

L'invention concerne un système permettant de gérer une demande d'accès aux registres, ledit système comprenant une interface permettant de recevoir des demandes d'accès aux registres et une unité de traitement connectée à l'interface. L'unité de traitement mappe dynamiquement des registres architecturaux avec des registres physiques d'après un critère tel qu'une utilisation récente et/ou une fréquence d'accès aux registres architecturaux par des fils de traitement multifil (MT). L'unité de traitement recherche également un registre architectural respectif pour des demandes d'accès aux registres pour lesquelles une correspondance n'a pas été trouvée dans les registres physiques.
PCT/EP2015/068977 2015-08-18 2015-08-18 Registres physiques partagés et table de mappage pour registres architecturaux de fils multiples Ceased WO2017028909A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/EP2015/068977 WO2017028909A1 (fr) 2015-08-18 2015-08-18 Registres physiques partagés et table de mappage pour registres architecturaux de fils multiples
CN201580082261.5A CN107851006B (zh) 2015-08-18 2015-08-18 多线程寄存器映射

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2015/068977 WO2017028909A1 (fr) 2015-08-18 2015-08-18 Registres physiques partagés et table de mappage pour registres architecturaux de fils multiples

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US20210132985A1 (en) * 2019-10-30 2021-05-06 Advanced Micro Devices, Inc. Shadow latches in a shadow-latch configured register file for thread storage
CN112445616B (zh) * 2020-11-25 2023-03-21 海光信息技术股份有限公司 资源分配方法以及装置
CN113626205B (zh) * 2021-09-03 2023-05-12 海光信息技术股份有限公司 处理器、物理寄存器管理方法及电子装置

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