WO2017010708A1 - Method and device for transmitting high-capacity feedback in carrier aggregation-based wireless communication cellular system - Google Patents

Abstract

Provided is a method for transmitting feedback information through an uplink control channel by a transmitter. The transmitter modulates the feedback information into a plurality of symbols. The transmitter spreads the plurality of symbols, using a spreading orthogonal sequence having a length shorter than 5. The transmitter maps the plurality of spread symbols to a plurality of resource elements (REs).

Description

Method and apparatus for transmitting high capacity feedback in carrier aggregation based wireless communication cellular system

The present invention relates to a method and apparatus for transmitting high capacity feedback in a carrier aggregation based wireless communication cellular system.

A physical layer of a long term evolution (LTE) cellular network using carrier aggregation technology aggregates up to five carriers (ie, 100 MHz) based on a 20 MHz bandwidth to perform a response after signal transmission and signal processing. .

However, the total bandwidth of the five carriers is relatively narrow compared to the specification of the 160 MHz band using current IEEE 802.11ac. In particular, when LTE is operated in an unlicensed band such as licensed assisted access (LAA), even though there is abundant available bandwidth of the 5 GHz band, there is a limit of increasing transmission capacity due to the limitation of 5 carriers. Thus, efforts to support more than five carrier aggregation technologies are underway in standardization work. Standardization work is being carried out on procedures and techniques for aggregating and transmitting up to 32 carriers and reporting feedback to the base station.

However, if the number of carrier aggregations increases to 32, much of the existing LTE specification is affected. Conventional carrier aggregation technology divides functions by frequency bandwidth using the concept of PCell (primary cell) and SCell (secondary cell). For example, when an LTE base station using a total bandwidth of 60MHz transmits a signal to a terminal, there is a bandwidth region corresponding to the PCell and a bandwidth region corresponding to the SCell for each frequency band period. Here, the PCell (ie, primary carrier) occupies 20 MHz, and the remaining 40 MHz is divided into two 20 MHz SCells (ie, secondary carriers). Thus, if 100 MHz is supported, the primary carrier occupies 20 MHz of bandwidth in the PCell and each of the remaining four secondary carriers occupies 20 MHz of bandwidth in the SCell.

When the carrier aggregation technology is applied, the PCell transmits and receives important control information of all aggregated SCell carriers. For example, when the base station transmits signals to the terminal using five carriers, the terminal transmits (uplink transmission) responses corresponding to all five carriers only through the PCell (uplink transmission). . For example, the terminal may transmit ACK / NACK, channel state information (CSI), scheduling request, and the like.

Therefore, when five or more carriers are aggregated (eg, when up to 32 carriers are aggregated), the information transfer burden on the PCell is inevitably increased. In particular, when the UE periodically sends feedback to the base station, the maximum number of information bits for uplink transmission through physical uplink control channel (PUCCH) format 3 may be performed if spatial multiplexing is not applied. , 11 per subframe. When up to 32 carriers are aggregated, approximately six times as many bits are needed as when five carriers are aggregated. However, in the current LTE standard, there is no modulation method and resource allocation method for the terminal to handle approximately six times the capacity of the PCell carrier.

The problem to be solved by the present invention is to provide a method and apparatus for increasing the information transmission capacity.

According to an embodiment of the present invention, a method is provided by a transmitter for transmitting feedback information through an uplink control channel. The transmitting method of the transmitter may include modulating the feedback information into a plurality of symbols; Spreading the plurality of symbols using a spreading orthogonal sequence of length less than 5; And mapping the spread symbols to a plurality of resource elements.

The modulating may include adding first cyclic redundancy check (CRC) information to the feedback information to generate first information; Generating second information by applying tail biting convolutional channel coding (TBCC) and rate matching to the first information; And modulating the second information through at least one of quadrature phase shift keying (QPSK), phase shift keying (8-PSK), quadrature amplitude modulation (4-QAM), and 16-QAM to generate the plurality of symbols. It may include the step.

The spread symbols may include a plurality of first symbols and a plurality of second symbols.

The mapping of the plurality of REs may include sequentially mapping the plurality of first symbols to remaining time domain symbols except for time domain symbols for a reference signal among a plurality of time domain symbols for a first slot; And sequentially mapping the plurality of second symbols to time domain symbols next to the time domain symbol to which the plurality of first symbols are mapped among the remaining time domain symbols.

The modulating may include grouping the plurality of symbols into a plurality of first symbol groups mapped to a plurality of PRBs for a first slot and a plurality of second symbol groups mapped to a plurality of PRBs for a second slot. It may include.

The mapping to the plurality of REs may include: allocating a plurality of first reference signals for the feedback information to some of the plurality of time domain symbols for a first slot; And assigning a plurality of second reference signals for the feedback information to some of the plurality of time domain symbols for the second slot.

A first spreading orthogonal sequence having a length of 4 among the spreading orthogonal sequences is [1 1 1 1], [1 -1 1 -1], [1 1 -1 -1], and [1 -1 -1] 1] may be at least one.

The mapping to the plurality of REs may include sequentially mapping the plurality of first symbols to a plurality of subcarriers for a first slot; And sequentially mapping the plurality of second symbols to subcarriers subsequent to the subcarrier to which the plurality of first symbols are mapped among the plurality of subcarriers for the first slot.

The first spreading orthogonal sequence having a length of 2 among the spreading orthogonal sequences may be at least one of [1 1] and [1 -1].

According to another embodiment of the present invention, a method is provided by a transmitter for transmitting feedback information through an uplink control channel. The transmitting method of the transmitter includes: modulating the feedback information into a plurality of first symbols through one of quadrature phase shift keying (QPSK) and quadrature amplitude modulation (4-QAM); Doubling the plurality of first symbols based on a spreading orthogonal sequence of length 2 to generate a plurality of second symbols; And mapping the plurality of second symbols to a plurality of resource elements (REs) based on a mapping order in which the frequency axis comes first and the time axis comes later.

The plurality of REs may include a plurality of REs for a first slot and a plurality of REs for a second slot after the first slot.

The mapping to the plurality of REs may include: mapping a portion of the plurality of second symbols to a plurality of REs for a first time domain symbol among the plurality of REs for the first slot; And mapping another part of the plurality of second symbols to a plurality of REs for a second time domain symbol next to the first time domain symbol among a plurality of REs for the first slot.

The plurality of REs may include a plurality of first REs corresponding to a PRB for a first slot and a plurality of second REs corresponding to a PRB for a second slot next to the first slot.

The mapping of the plurality of REs may include: mapping at least one reference signal for the feedback information to a portion of the plurality of first REs; And mapping a part of the plurality of second symbols to the rest of the plurality of first REs based on the mapping order.

The modulating may include adding first cyclic redundancy check (CRC) information to the feedback information to generate first information; Generating second information by applying tail biting convolutional channel coding (TBCC) and rate matching to the first information; Modulating the second information through QPSK to generate the plurality of first symbols; And grouping the plurality of first symbols into a first symbol group mapped to a first slot and a second symbol group mapped to a second slot.

In addition, according to another embodiment of the present invention, a method is provided by a transmitter for transmitting feedback information through an uplink control channel. The transmitting method of the transmitter may include generating first information by applying a cyclic redundancy check (CRC) and tail biting convolutional channel coding (TBCC) to first feedback information larger than 22 bits of the feedback information; Generating a plurality of symbols by modulating the first information; And mapping the plurality of symbols to a plurality of resource elements.

The plurality of symbols may include a plurality of first symbols mapped to a first slot and a plurality of second symbols mapped to a second slot next to the first slot.

The mapping to the plurality of REs may include: applying a phase rotation to the plurality of first symbols; Applying a cyclic shift to the phase rotated symbols; And applying discrete Fourier transform (DFT) precoding to the cyclically shifted symbols.

According to the embodiment of the present invention, it is possible to realize an increase in the capacity of the PUCCH signal. Through this, the terminal may deviate from the response for the carrier aggregation transmission having a limited number of carriers (eg, five) and may report a response for up to 32 carriers to the base station.

In addition, according to the embodiment of the present invention, while using the same amount of resources as those used in the existing carrier aggregation transmission (with a limit of the number of carriers (for example, five)), it corresponds to approximately six times the existing information It is possible to transmit the information through the PUCCH which is an uplink control channel.

1 is a diagram illustrating an LTE frame structure type in the FDD form.

2 is a diagram illustrating a basic structure of an uplink physical resource block (PRB).

FIG. 3 is a diagram illustrating a useful resource region of a normal CP and a useful resource region of an extended CP in the FDD scheme.

4 is a diagram illustrating an 8-bit CRC generator.

FIG. 5 is a diagram illustrating an input / output relationship between a tail biting convolutional channel coding (TBCC) unit.

6 is a diagram illustrating a rate matching unit.

7A and 7B illustrate encoding and modulation of a 64-bit PUCCH transmission method based on an FDD scheme, a normal CP, and one DM-RS SC-FDMA symbol according to an embodiment of the present invention.

8A and 8B illustrate encoding and modulation of a 64-bit PUCCH transmission method using two DM-RSs in a normal CP mode according to an embodiment of the present invention.

9 is a diagram illustrating an embodiment in which Equation 10 is applied according to an embodiment of the present invention.

10A and 10B illustrate encoding and modulation of a 64-bit PUCCH transmission method for an extended CP based on FDD scheme according to an embodiment of the present invention.

11A, 11B, and 11C are diagrams illustrating a 64-bit PUCCH transmission method for two PRBs and one DM-RS per slot, QPSK, and normal CP, according to an embodiment of the present invention. to be.

12A, 12B, and 12C illustrate a 64-bit PUCCH transmission method for a case where two PRBs and two DM-RSs are used per slot, QPSK is used, and a normal CP is used, according to an embodiment of the present invention. to be.

13A, 13B, and 13C illustrate a 64-bit PUCCH transmission method for a case in which two PRBs per slot are used, QPSK is used, and an extended CP is used according to an embodiment of the present invention.

14A, 14B, and 14C illustrate 64-bit PUCCH transmission for the case where two PRBs and one DM-RS are used per slot, QPSK is used, and normal CP and OCC = 4 are used according to an embodiment of the present invention. It is a figure which shows a method.

15 is a diagram illustrating an embodiment in which Equation 11 is applied according to an embodiment of the present invention.

16A, 16B, and 16C illustrate 64-bit PUCCH transmission for the case where two PRBs and two DM-RSs are used per slot, QPSK is used, and normal CP and OCC = 4 are used according to an embodiment of the present invention. It is a figure which shows a method.

17A, 17B, and 17C illustrate 64-bit PUCCH transmission for a case where two PRBs and one DM-RS are used per slot, QPSK is used, and an extended CP and OCC = 4 are used according to an embodiment of the present invention. It is a figure which shows a method.

18A and 18B illustrate a 64-bit PUCCH transmission method for a case where one PRB and one DM-RS are used per slot, QPSK modulation is used, and OCC = 2 is used in a normal CP mode according to an embodiment of the present invention. A diagram illustrating encoding and modulation.

19A and 19B illustrate a 64-bit PUCCH transmission method for a case where one PRB and two DM-RSs are used per slot, QPSK modulation is used, and OCC = 2 is used in a normal CP mode according to an embodiment of the present invention. A diagram illustrating encoding and modulation.

20A, 20B, and 20C illustrate 64-bit PUCCH transmission for a case where one PRB and one DM-RS are used per slot, QPSK is used, and normal CP and OCC = 2 are used according to an embodiment of the present invention. It is a figure which shows a method.

21A and 21B illustrate a 58-bit PUCCH transmission method for a case in which one PRB and two DM-RSs are used per slot, QPSK is used, and normal CP and OCC = 2 are used according to an embodiment of the present invention. to be.

22A and 22B illustrate a 52-bit PUCCH transmission method for a case where one PRB and one DM-RS are used per slot, QPSK is used, and extended CP and OCC = 2 are used according to an embodiment of the present invention. to be.

23A and 23B illustrate a 128-bit PUCCH transmission method for a case in which one PRB and one DM-RS are used per slot, QPSK is used, and normal CP and OCC = 1 are used according to an embodiment of the present invention. to be.

24A and 24B illustrate a 128-bit PUCCH transmission method for a case in which one PRB and two DM-RSs are used per slot, QPSK is used, and normal CP and OCC = 1 are used according to an embodiment of the present invention. to be.

25 is a diagram illustrating input and output relationships between a DFT unit and an IFFT unit included in a terminal according to an embodiment of the present invention.

FIG. 26 is a diagram illustrating a method of mapping a PUCCH to a frequency domain according to the number of PRBs used per slot according to an embodiment of the present invention.

27 is a diagram illustrating a DAI mapping method for each CC for an FDD type according to an embodiment of the present invention.

FIG. 28 is a diagram illustrating a total and counter DAI mapping method for a TDD type according to an embodiment of the present invention. FIG.

29 is a diagram illustrating a transmitter according to an embodiment of the present invention.

30 is a diagram illustrating a receiver according to an embodiment of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification and claims, when a portion is said to include a certain component, it means that it can further include other components, except to exclude other components unless specifically stated otherwise.

Throughout the specification, a terminal may be a mobile terminal, a mobile station, an advanced mobile station, a high reliability mobile station, a subscriber station, a portable device. It may also refer to a portable subscriber station, an access terminal, a user equipment (UE), or the like, and may include a terminal, a mobile terminal, a mobile station, an advanced mobile station, a high reliability mobile station, a subscriber station, and a mobile subscription. It may also include all or part of the functionality of a home station, access terminal, user equipment, and the like.

In addition, a base station (BS) may include an advanced base station, a high reliability base station, a node B, an evolved node B, an eNodeB, an eNB, An access point, a radio access station, a base transceiver station, a mobile multihop relay (BSR) -BS, a relay station serving as a base station, and a base station It may also refer to a high reliability relay station, a repeater, a macro base station, a small base station, and the like, and may include a base station, an advanced base station, HR-BS, a Node B, an eNodeB, an access point, a wireless access station, a transceiver base station, and an MMR- It may include all or part of the functionality of a BS, repeater, high reliability repeater, repeater, macro base station, small base station, and the like.

Meanwhile, in the present specification, 'A or B' may include 'A', 'B', or 'both A and B'.

Method and apparatus according to an embodiment of the present invention, may belong to the physical layer of the LTE wireless mobile communication system, and specifically may be related to the configuration of the transmission signal of the terminal.

When a large number of downlink signals are transmitted by the base station in the form of carrier aggregation and the terminal receives the signal, the terminal transmits a response (eg acknowledgment) to the base station for the data aggregated for each carrier. Configure the link feedback signal. Hereinafter, the structure of such an uplink feedback signal will be described. In addition, hereinafter, a method of increasing information transmission capacity while occupying the same amount of PRB as the physical resource block (PRB) required by the PUCCH format 3, which is an existing LTE uplink control channel, will be described.

1 is a diagram illustrating an LTE frame structure type in the FDD form.

LTE includes frequency division duplexing (FDD) and time division duplexing (TDD), which are duplexing schemes. In the case of FDD, as illustrated in FIG. 1, one radio frame occupies 10 ms (ie, T _f = 10 ms) and includes 10 subframes, and one subframe occupies 1 ms and two slots. And one slot occupies 0.5 ms (ie, T _slot = 0.5 ms). In FIG. 1, T _s is 1 / (30.72e6) = 0.326us based on a 20 MHz bandwidth.

2 is a diagram illustrating a basic structure of an uplink physical resource block (PRB).

값은 12로 고정되어 있으며, k는 주파수의 부반송파(subcarrier)의 인덱스를 나타내고,

는 상향링크의 대역폭을 나타낸다. 즉, 상향링크 PRB는 주파수 축으로 12개의 부반송파를 가지고, 시간 축으로 7개 또는 6개의 시간 도메인 심볼(예, SC(single carrier)-FDMA(frequency division multiple access) 심볼)을 가진다. 여기서, SC-FDMA 심볼은 OFDM(orthogonal frequency division multiplexing) 심볼과 동일한 전송 시간을 가진다. 도 2에서,

은 슬롯 당 SC-FDMA 심볼 개수(예, 7개)를 나타내고, l은 SC-FDMA 심볼의 인덱스를 나타낸다.The uplink PRB of LTE may be defined as illustrated in FIG. 2. In Figure 2,

The value is fixed to 12, k denotes the index of the subcarrier of the frequency,

Denotes the bandwidth of the uplink. That is, the uplink PRB has 12 subcarriers on the frequency axis and has 7 or 6 time domain symbols (eg, single carrier (SC) -frequency division multiple access (FDMA) symbols) on the time axis. Here, the SC-FDMA symbol has the same transmission time as an orthogonal frequency division multiplexing (OFDM) symbol. In Figure 2,

Denotes the number of SC-FDMA symbols (eg, 7) per slot, and denotes the index of the SC-FDMA symbol.

Therefore, if two slots constitute one subframe, when the normal cyclic prefix (CP) of the SC-FDMA symbol is used, 14 SC-FDMA symbols may be allocated to one subframe and may be extended. When the extended CP is used, 12 SC-FDMA symbols may be allocated to one subframe.

In FDD of LTE, periodic feedback information through uplink of a UE is mainly transmitted through a physical uplink control channel (PUCCH). Types of formats for PUCCH transmission is six main (PUCCH format 1a, 1b, 2, 2a, 2b, 3), as shown in Table 1 (Supported PUCCH formats) below, the number of transmittable bits (M _bit) Therefore, transmission formats are mainly divided.

PUCCH format Modulation scheme Number of bits per subframe, M _bit One N / A N / A 1a Binary phase shift keying (BPSK) One 1b Quadrature phase shift keying (QPSK) 2 2 QPSK 20 2a QPSK + BPSK 21 2b QPSK + QPSK 22 3 QPSK 48

One of six types (PUCCH formats 1a, 1b, 2, 2a, 2b, and 3) is usually transmitted by the terminal through two PRBs (ie, one subframe).

The terminal receiving the downlink signal of the multi-band through the carrier aggregation transmits the feedback to the base station using the PUCCH format 3. The transmission time point of the PUCCH format 3 is a fixed time rather than an adaptively scheduled time according to a situation, and the uplink transmission of the PUCCH format 3 is performed at a fixed time and a fixed frequency band. Although 48 bits are modulated after channel coding is applied through PUCCH format 3, only 22 bits are actually useful information bits.

As shown in Table 1, bit information is modulated into symbols and then mapped over two PRBs illustrated in FIG. Modulated symbols containing information are not mapped to all 168 resource elements (refer to a normal CP and one subframe). That is, when REs including a DM-RS or a demodulation reference signal (DMRS) are considered, 120 REs are provided in the case of a normal CP, and 120 REs are similarly provided in the case of an extended CP. The relationship between the actual useful RE will be described with reference to FIG. 3.

FIG. 3 is a diagram illustrating a useful resource region of a normal CP and a useful resource region of an extended CP in the FDD scheme.

Specifically, in FIG. 3, (a1) represents a useful resource region of a normal CP, and (a2) represents a useful resource region of an extended CP.

In (a1), each of slot 1 and slot 2 following slot 1 includes seven SC-FDMA symbols, and RS (reference signal) is transmitted in the second and sixth SC-FDMA symbols among the seven SC-FDMA symbols. The case is illustrated.

In (a2), each of slot 1 and slot 2 includes six SC-FDMA symbols, and RS is transmitted in the fourth SC-FDMA symbol among the six SC-FDMA symbols.

Hereinafter, a method of greatly increasing the number of useful information bits (payload bits) and transmitting high-capacity feedback information (eg, more than 22 bits) while using the same number of REs as in the conventional scheme will be described. .

In the channel coding method for new PUCCH transmission, tail-biting convolutional coding (TBCC) is applied.

4 is a diagram illustrating an 8-bit CRC generator.

If payload bit is a _i (i = 0,1, ..., 63), CRC bit generated after adding cyclic redundancy check (CRC bit) p _i (i = 0,1, ..., 63) 7) is added to the payload bit a _i , and the CRC bit p _i is generated by a polynomial generator such as Equation 1 below.

In Equation 1, gCRC8 (D) represents a polynomial generating a CRC, and each of D, D ₃ , D ₄ , D ₇ , and D ₈ represents a point at which an XOR operation for binary operation is applied. For example, D ₄ is the payload bit input bit a _i value (0 or 1), the output value (0 or 1) of the fourth shift register (square box) of FIG. 4, and 8 of FIG. 4. The point where the output values of the first shift register are all XORed. Here, all of the shift registers of FIG. 4 may be initialized to binary bit 1.

Meanwhile, scrambling is applied to a portion corresponding to the CRC (ie, p _i (i = 0, 1, ..., 7)) in various ways, and thus scheduling information is added. There are two classification methods (inverting all CRC bits, modulo 2 addition with C-RNTI).

The 'inverting all CRC bit' method inverts all CRC output bits to indicate scheduling request information. The 'inverting all CRC bit' method may be expressed as in the following equation.

는 'inverting all CRC bit' 방법에 의한 scrambled CRC비트를 나타낸다. 만약 단말이 첫번째 전송 블록(transport block)에 관한 스케줄링 요청을 가지고 있다면, SR₁=1 이 되고 그렇지 않으면 SR₁=0이 된다. 마찬가지로 단말이 두번째 전송 블록에 관한 스케줄링 요청을 가지고 있다면, SR₂=1 이 되고 그렇지 않으면 SR₂=0이 된다.In the above equation,

Denotes a scrambled CRC bit by the 'inverting all CRC bit' method. If the UE has a scheduling request for the first transport block, SR ₁ = 1, otherwise SR ₁ = 0. Similarly, if the UE has a scheduling request for the second transport block, SR ₂ = 1, otherwise SR ₂ = 0.

The 'modulo 2 addition with C-RNTI' method is a method of using a 16-bit radio network temporary identifier (RNTI) and a modulo 2 addition that a base station assigns to a terminal to display scheduling request information. n _RNTI (i) (i = 0, 1, ..., 3) is the most significant bit (MSB) 4 bits or the least significant bit (LSB) 4 bits of the 16-bit RNTI that the base station gives to the terminal.

If the UE has a scheduling request, the UE maps the CRC bits to RNTI MSB 4 bits or RNTI LSB 4 bits, as shown in the following equation.

는 'modulo 2 addition with C-RNTI' 방법에 의한 최종CRC 비트를 나타낸다. In the above equation,

Denotes the final CRC bit by the 'modulo 2 addition with C-RNTI' method.

If the terminal does not have a scheduling request, the terminal does not apply scrambling to the CRC bit as shown in the following equation.

Therefore, the information to be transmitted by the device (eg, the terminal) is generalized in the form of the following CRC is added to the TBCC unit.

은 상술한 방법에 의해 구해진 CRC 비트를 나타낸다.In the above equation, M represents the amount of information to be transmitted (that is, payload size), b _k represents the input bits of the TBCC unit, a _k represents information to be transmitted by the device (eg, the terminal),

Denotes a CRC bit obtained by the method described above.

For example, when a device (eg, a terminal) wants to transmit 64 bits, M = 64, and when CRC 8 bits are added thereto, 72 bits are finally determined as input bits of the TBCC unit.

FIG. 5 is a diagram illustrating an input / output relationship between a tail biting convolutional channel coding (TBCC) unit.

를 출력한다. 즉, 입력된 비트 수의 3배의 비트가 최종 출력된다. 도 5에서, G₀, G₁, 및 G₂ 각각은 특정 지점의 다수개의 시프트 레지스터의 binary 값에 modulo 2 addition 연산이 적용된 경우의 결과 값을 나타낸다. 예를 들어, G₀는 입력 bit b_k, 시프트 레지스터(SH1b)에 저장된 bit, 시프트 레지스터(SH1c)에 저장된 bit, 시프트 레지스터(SH1e)에 저장된 bit, 그리고 시프트 레지스터(SH1f)에 저장된 bit 간에 modulo 2 addition 연산이 적용된 경우의 결과 값을 나타낸다. G₁ 및 G₂은 G₀와 유사한 형태로 생성된다.As illustrated in FIG. 5, the TBCC unit 20 receives a binary number b _k ,

Outputs That is, the bits of three times the number of input bits are finally output. In FIG. 5, each of G ₀ , G ₁ , and G ₂ represents a result value when a modulo 2 addition operation is applied to binary values of a plurality of shift registers at a specific point. For example, G ₀ modulo between input bit b _k , the bit stored in shift register SH1b, the bit stored in shift register SH1c, the bit stored in shift register SH1e, and the bit stored in shift register SH1f. 2 Shows the result value when the addition operation is applied. G ₁ and G ₂ are produced in a form similar to G ₀ .

Where it before the TBCC section 20 inputs a b _k, the initial value of the six shift registers (shift register, SH1a, SH1b, SH1c, SH1d, SH1e, SH1f) is given in the last 6 bits b _k. Therefore, when _k in b _k is 0 to 71, the initial value input order s ₀ , s ₁ , s ₂ , ..., s ₅ of the shift registers SH1a to SH1f is s _i = b _{(71-i )} it may be a formulation.

The output of the TBCC unit 20 is subjected to a rate matching unit, and receives an adjustment of a code rate.

6 is a diagram illustrating a rate matching unit.

In detail, the rate matching unit 30 includes a subblock interleaver 31a, 31b, and 31c and a virtual circular buffer 32. Here, the virtual circular buffer 32 includes a bit collection unit 32a and a bit selection and pruning unit 32b.

은, 서브블록 인터리버(31a~31c)와 비트 수집부(32a)를 통해 단일 비트 스트림 w_k 로 변환된다. Three bit streams output from the TBCC unit 20

Is converted into a single bit stream w _k through the subblock interleavers 31a to 31c and the bit collector 32a.

w _k is finally converted into a bit stream e _k of the required length through bit selection and pruning of the bit selection & pruning unit 32b.

각각의 비트 스트림의 길이가 D라고 하면, 서브블록 인터리버(31a~31c)의 입력은

로 표현될 수 있다. 이때, 인터리빙을 위한 매트릭스(matrix)의 행(row) 크기

는

을 만족하는 최소 정수(integer)이다. 여기서, 인터리빙을 위한 매트릭스(matrix)의 열(column) 크기

=32 이다.

If the length of each bit stream is D, the inputs of the subblock interleavers 31a to 31c are

It can be expressed as. At this time, the row size of the matrix for interleaving

Is

Minimum integer that satisfies Where the column size of the matrix for interleaving

= 32.

이라면,

만큼의 더미 비트 y_k = <NULL> (k=0, 1, ..., N_D-1)가 패딩(padding)된다. if

If

As many dummy bits y _k = <NULL> (k = 0, 1, ..., N _D -1) are padded.

가 된다. 즉,

앞에

만큼의 더미 비트가 추가된다. 더미 비트가 추가된 매트릭스는, 다음의 매트릭스와 같은 형태를 가진다.Therefore, the final bit stream input to each subblock interleaver 31a to 31c,

Becomes In other words,

Before

As many dummy bits are added. The matrix to which the dummy bit is added has the same form as the following matrix.

Permutation between columns is applied to the matrix to which the dummy bit is added, thereby creating a matrix having the following form.

는 열 간 순열 패턴을 나타낸다. In the matrix,

Denotes a thermal permutation pattern.

In more detail, the permutation patterns between columns may be defined as shown in Table 2 (Inter-column permutation pattern for sub-block interleaver).

Number of columns C ^ CC_subblock Inter-column permutation pattern <P (0), P (1), ..., P (C ^ CC_subblock-1)> 32 <1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31, 0, 16 , 8, 24, 4, 20, 12, 28, 2 , 18, 10, 26, 6, 22, 14, 30>

이다.In Table 2, C ^ CC_subblock is

to be.

로 표현되며, 여기서 매트릭스의 총 원소(element) 개수를 나타내는 값인

는

이다. The outputs of the subblock interleavers 31a to 31c

Where is the value representing the total number of elements in the matrix

Is

to be.

이다. 스트림 w_k 는 아래의 수학식과 같이 구성될 수 있다.The length of the final stream w _k input to the bit select & pruning section 32b is K _w ,

to be. The stream w _k may be configured as in the following equation.

In FIG. 6, the bit stream w _k is finally input to the bit select & pruning unit 32b that satisfies the code rate and filters NULL bits. The output of the bit select & pruning section 32b, e _k , satisfies the code rate.

The output bit stream is filtered and selected through the following process.

The end E of the bitstream Portrait matching unit _{(30) e k (k =} 0,1, ..., E-1) Assuming that the length of the final bit stream e _k will be generated as shown in Equation 2 below Can be.

In Equation 2, e (k) corresponds to the final bit stream e _k .

The length E of the rate matching may be defined as 144, 192, or N in the case of a normal CP, and 120, 160, or N in the case of an extended CP. N may be one of 120, 144, 160, and 192.

The output bit stream e _k and the scrambling sequence c (i) are binary addition, which can be expressed as Equation 3 below.

는 스크램블링 시퀀스 c(i)와의 이진 가산이 적용된 비트 스트림을 나타내고, e(i)는 비트 스트림 e_k에 대응한다.In Equation 3, i is an element index,

Denotes a bit stream to which a binary addition with the scrambling sequence c (i) is applied, and e (i) corresponds to the bit stream e _k .

The scrambling sequence c (i) may be generated through Equation 4 below.

에 의해 정해진다. 여기서 c_init는

에 의해 정의된다.

는 물리 셀 ID(physical cell identity)를 나타내고, n_RNTI는 기지국이 단말에게 부여하는 RNTI를 나타내며, n_s는 슬롯 번호를 나타낸다.In Equation 4, N _c = 1600 and is defined as x ₁ (0) = 1, x ₁ (n) = 0 (n = 1,2, ..., 30). Also x ₂ (i) is

Determined by Where c _init is

Is defined by

Denotes a physical cell identity, n _RNTI denotes an RNTI assigned to a terminal by a base station, and n _s denotes a slot number.

The output of the scrambled bit stream through the scrambling sequence c (i) is subjected to interleaving of Equation 5 below.

Bits that have undergone the scrambling process and the interleaving process are mapped to resources through a modulation process and a spreading process. Depending on the bit length of the payload that the device (eg, terminal) intends to transmit, the modulation process, spreading process, and resource mapping process vary.

First, the case where the number of payload bits is 64 will be described.

7A and 7B illustrate encoding and modulation of a 64-bit PUCCH transmission method based on an FDD scheme, a normal CP, and one DM-RS SC-FDMA symbol according to an embodiment of the present invention.

Specifically, FIG. 7A and FIG. 7B illustrate a high capacity PUCCH transmission method for transmitting 64 bits.

The CRC process (S100), TBCC and rate matching process (S101), and the scrambling process (S102) illustrated in FIG. 7A are performed in the same or similar manner as described above with respect to CRC, TBCC, rate matching, scrambling, and interleaving. Can be.

As illustrated in FIGS. 7A and 7B, when the CP is a normal CP, since there are one SC-FDMA symbol for the DM-RS, 144 REs (that is, one subframe) for a time corresponding to one subframe 144 subcarriers) may be used.

The output of the scrambled bit stream is subject to interleaving of equation (5). Here, the value of N in Equation 5 is 144 in the case of 8-PSK (phase shift keying) when the normal CP is applied and 192 in the case of 16-QAM (quadrature amplitude modulation). If extended CP is applied, the value of N is 120 for 8-PSK and 160 for 16-QAM.

The output of the scrambled bit stream is modulated via 8-PSK or 16-QAM (S103). Modulation mapping methods are shown in Table 3 (8-PSK modulation mapping) and Table 4 (16-QAM modulation mapping) below.

~ e (i), ~ e (i + 1), ~ e (i + 2) I Q 000 -1 / √2 -1 / √2 001 -One 0 010 0 One 011 -1 / √2 1 / √2 100 0 -One 101 1 / √2 -1 / √2 110 1 / √2 1 / √2 111 One 0

이고, √2은

이다.In Table 3, ~ e (i), ~ e (i + 1), and ~ e (i + 2) are

√2 is

to be.

~ e (i), ~ e (i + 1), ~ e (i + 2), ~ e (i + 3) I Q 0000 1 / √10 1 / √10 0001 1 / √10 3 / √10 0010 3 / √10 1 / √10 0011 3 / √10 3 / √10 0100 1 / √10 -1 / √10 0101 1 / √10 -3 / √10 0110 3 / √10 -1 / √10 0111 3 / √10 -3 / √10 1000 -1 / √10 1 / √10 1001 -1 / √10 3 / √10 1010 -3 / √10 1 / √10 1011 -3 / √10 3 / √10 1100 -1 / √10 -1 / √10 1101 -1 / √10 -3 / √10 1110 -3 / √10 -1 / √10 1111 -3 / √10 -3 / √10

이고, √10은

이다.In Table 4, ~ e (i), ~ e (i + 1), ~ e (i + 2), and ~ e (i + 3) are

√10 is

to be.

A total of 48 symbols are modulated via 8-PSK or 16-QAM. 48 8-PSK symbols or 48 16-QAM symbols are divided into 4 symbol groups, as illustrated in FIG. 7B. Each symbol group includes 12 symbols. Two of the four symbol groups correspond to slot 1 (containing seven SC-FDMA symbols) and the rest correspond to slot 2 (containing seven SC-FDMA symbols).

에 의해 3배로 스프레딩(spreading)된다(S105). For each symbol group corresponding to one PRB bandwidth, a common phase rotation of a cell-specific length is applied in the time domain (S104). After phase rotation is commonly applied to all 12 symbols in a symbol group, each symbol is a spreading factor for PUCCH.

Is spread by three times (S105).

Equation 6 below shows the process up until the application of discrete Fourier transform (DFT) pre-coding to a signal modulated through 8-PSK or 16-QAM. RE mapping is based on equation (6).

는 DFT 프리코딩 직전의 신호를 나타내며, 인덱스 i(단, i=0,1,...,

-1)는 주파수 축의 매핑을 위한 인덱스에 해당하고, n은 인덱스이며,

는 안테나 포트를 나타낸다.In Equation 6,

Denotes the signal immediately before DFT precoding, where index i (i = 0,1, ...,

-1) corresponds to the index for mapping the frequency axis, n is the index,

Represents an antenna port.

는 1개의 PRB 대역폭을 나타내며 LTE 시스템에서는 12로 정의된다. 수학식 6에서,

는 셀 특정(cell-specific)한 공통 위상 로테이션의 값을 나타내며, 값의 범위(range)는 0~11이다. 수학식 6에서, n_s는 슬롯의 번호를 나타내며, l는 SC-FDMA 심볼 번호(인덱스)를 나타낸다. 수학식 6에서,

=3이다.In Equation 6, s (i) represents a symbol modulated via 8-PSK or 16-QAM based on Table 3 or Table 4. In Equation 6,

Represents one PRB bandwidth and is defined as 12 in the LTE system. In Equation 6,

Denotes a cell-specific common phase rotation value, and a range of values is 0-11. In Equation 6, n _s represents a slot number, and l represents an SC-FDMA symbol number (index). In Equation 6,

= 3.

는

에 대응한다.In Equation 6,

Is

Corresponds to.

는, 아래의 표 5(The orthogonal sequence

)와 같이 정의될 수 있다.Orthogonal cover code (OCC) sequences for spreading

Table 5 (The orthogonal sequence)

Can be defined as

Sequence index n _oc Orthogonal sequence [w_noc (0) ... w_noc (N ^ PUCCH_SF -1)] N ^ PUCCH_SF = 3 0  [1 1 1] One  [1 e ^ j2π / 3 e ^ j4π / 3] 2 [1 e ^ j4π / 3 e ^ j2π / 3]

이고, N^PUCCH_SF는

이고, e^j2π/3는

이고, e^j4π/3는

이다.In Table 5, w_noc () is

N ^ PUCCH_SF is

And e ^ j2π / 3 is

And e ^ j4π / 3 is

to be.

That is, the spreading orthogonal sequence applied to Equation 6 is a sequence index n _oc defined in Table 5 Selected by one of the selected spreading orthogonal sequences is used for spreading.

은, 시간 도메인에서 순환 시프트(cyclic shift) 값으로써 사용될 수도 있다. 1개의 PRB 대역폭에 해당하는 변조 심볼 그룹 각각에는, 각 SC-FDMA 심볼 레벨 단위에서 순환 시프트가 적용된다(S106). 순환 시프트의 적용 방법은 아래의 수학식 7과 같다.Common phase rotation applied on the frequency axis

May be used as a cyclic shift value in the time domain. A cyclic shift is applied in each SC-FDMA symbol level unit to each modulation symbol group corresponding to one PRB bandwidth (S106). The application method of the cyclic shift is shown in Equation 7 below.

는 순환 시프트가 적용된 심볼을 나타낸다.In Equation 7,

Denotes a symbol to which a cyclic shift is applied.

A cyclic shift allows up to 12 different uplink signals to be multiplexed and the multiplexed signals can be received by the base station. Cyclic shift also has the function of causing the uplink signal to generate minimal interference.

As illustrated in FIG. 7B, DFT precoding is applied to each modulation symbol group that has undergone the spreading process and the cyclic shift process as shown in Equation 8 below (S107).

, k=0,1,2,...,11, n=0,1,2,...,11에 대하여, 후술할 도 25 및 도 26에 예시된 바와 같이, 특정(specific) 대역(band)이 지정되고, 지정된 OFDM 심볼(또는 SC-FDMA 심볼) 위치가 매핑되고, 최종적으로 IFFT(inverse fast Fourier transform)가 적용된다(S108). 그리고 IFFT 과정을 거친 신호는 해당 대역폭에서 전송된다(S109).In Equation 8, P represents the number of antennas for PUCCH transmission. 12 DFT pre-coded symbols with precoding

, k = 0,1,2, ..., 11, for n = 0,1,2, ..., 11, as illustrated in FIGS. 25 and 26 to be described later, specific band ( band), a designated OFDM symbol (or SC-FDMA symbol) location is mapped, and finally an inverse fast Fourier transform (IFFT) is applied (S108). The signal that has undergone the IFFT process is transmitted in the corresponding bandwidth (S109).

)에 의해 생성될 수 있다.Meanwhile, a reference signal (DM-RS) for demodulating the PUCCH signal is also transmitted. The reference signal is represented by Equation 9 and Table 6 below.

Can be generated by

u φ (0), φ (1), ..., φ (11) 0 -One One 3 -3 3 3 One One 3 One -3 3 One One One 3 3 3 -One One -3 -3 One -3 3 2 One One -3 -3 -3 -One -3 -3 One -3 One -One 3 -One One One One One -One -3 -3 One -3 3 -One 4 -One 3 One -One One -One -3 -One One -One One 3 5 One -3 3 -One -One One One -One -One 3 -3 One 6 -One 3 -3 -3 -3 3 One -One 3 3 -3 One 7 -3 -One -One -One One -3 3 -One One -3 3 One 8 One -3 3 One -One -One -One One One 3 -One One 9 One -3 -One 3 3 -One -3 One One One One One 10 -One 3 -One One One -3 -3 -One -3 -3 3 -One 11 3 One -One -One 3 3 -3 One 3 One 3 3 12 One -3 One One -3 One One One -3 -3 -3 One 13 3 3 -3 3 -3 One One 3 -One -3 3 3 14 -3 One -One -3 -One 3 One 3 3 3 -One One 15 3 -One One -3 -One -One One One 3 One -One -3 16 One 3 One -One One 3 3 3 -One -One 3 -One 17 -3 One One 3 -3 3 -3 -3 3 One 3 -One 18 -3 3 One One -3 One -3 -3 -One -One One -3 19 -One 3 One 3 One -One -One 3 -3 -One -3 -One 20 -One -3 One One One One 3 One -One One -3 -One 21 -One 3 -One One -3 -3 -3 -3 -3 One -One -3 22 One One -3 -3 -3 -3 -One 3 -3 One -3 3 23 One One -One -3 -One -3 One -One One 3 -One One 24 One One 3 One 3 3 -One One -One -3 -3 One 25 One -3 3 3 One 3 3 One -3 -One -One 3 26 One 3 -3 -3 3 -3 One -One -One 3 -One -3 27 -3 -One -3 -One -3 3 One -One One 3 -3 -3 28 -One 3 -3 3 -One 3 3 -3 3 3 -One -One 29 3 -3 -3 -One -One -3 -One 3 -3 3 One -One

(단, n=0,1,...,11)이다.In Table 6, φ (0), φ (1), ..., φ (11) are

(N = 0,1, ..., 11).

When a normal CP is used, four DM-RS (SC-FDMA type) signals exist in one subframe, and when an extended CP is used, two DM-RS (SC- in one subframe) are used. FDMA type) signal is present.

In Table 6, u is a UE-specific value, and the base station informs the terminal of the selected value as a value for having low interference between the terminals.

는 도 3과 같이 RS(DM-RS로 표현 가능)에 해당하고, IFFT 과정을 거쳐 1개의 PRB에 해당하는 대역폭에서 전송된다(S109). 도 7b에는, 레퍼런스 신호

가 슬롯1의 7개의 SC-FDMA 심볼 중 4번째 심볼을 통해 전송되고, 슬롯2의 7개의 SC-FDMA 심볼 중 4번째 심볼을 통해 전송되는 경우가 예시되어 있다.Reference signal

3 corresponds to RS (can be represented by DM-RS) and is transmitted in a bandwidth corresponding to one PRB through an IFFT process (S109). 7B shows a reference signal

Is transmitted through a fourth symbol of seven SC-FDMA symbols in slot 1 and is transmitted through a fourth symbol among seven SC-FDMA symbols in slot 2.

8A and 8B illustrate encoding and modulation of a 64-bit PUCCH transmission method using two DM-RSs in a normal CP mode according to an embodiment of the present invention.

When a device (eg, a terminal) in a normal CP mode uses two reference signals (RSs) per slot, PUCCH transmission may be configured as illustrated in FIGS. 8A and 8B.

When a device (eg, a terminal) transmits a PUCCH using two RSs, the PUCCH is transmitted through a process similar to that of the embodiment of FIGS. 7A and 7B.

However, in an embodiment in which two RSs are transmitted (e.g., FIGS. 8A and 8B), since the RE is insufficient in comparison with the embodiment in which one RS is transmitted (e.g., FIGS. 7A and 7B), not 48 symbols Only 40 modulated symbols are transmitted.

The CRC process (S120), the TBCC and rate matching process (S121), and the scrambling and interleaving process (S122) illustrated in FIG. 8A are the same as or similar to those described above.

As illustrated in FIG. 8A, the output of the TBCC is converted to 120 bits (for 8-PSK) or 160 bits (for 16-QAM) via rate matching.

The output of the scrambled bit stream is subject to interleaving of equation (5). Here, the value of N in Equation 5 is 120 in case of 8-PSK and 160 in case of 16-QAM when a normal CP or extended CP is set.

When the scrambled bit is modulated through 8-PSK or 16-QAM, 40 modulation symbols are generated (S123). 40 modulation symbols are divided into four symbol groups. Each symbol group includes 10 modulation symbols. Two of the four symbol groups correspond to slot 1 (containing seven SC-FDMA symbols) and the rest correspond to slot 2 (containing seven SC-FDMA symbols).

For each symbol group, common phase rotation is applied in the time domain (S124).

Triple spreading is applied to each symbol group (S125).

)으로 곱해진 각 심볼 그룹은 부분적으로(partially) 나뉘어, 후술할 도 9에 예시된 바와 같이, 3개의 SC-FDMA 심볼 단위로 묶인다(S126). S126 과정은 도 9에 예시된 바와 같이, 3개의 심볼이 각 슬롯을 위한 60개의 RE(=6 columns * 5 rows)에 매핑되는 과정을 나타낸다.Each phase value defined in Table 5 (e.g.,

Each symbol group multiplied by) is partially divided and grouped into three SC-FDMA symbol units as illustrated in FIG. 9 to be described later (S126). As illustrated in FIG. 9, the process S126 represents a process in which three symbols are mapped to 60 REs (= 6 columns * 5 rows) for each slot.

On the other hand, the frequency axis is not limited to one subcarrier, but symbols may be allocated over two subcarriers.

When the preparation for DFT precoding is completed, as illustrated in FIG. 8B, a cyclic shift based on Equation 7 and DFT precoding based on Equation 8 are applied to the result of the step S126 (S127, S128). IFFT is finally applied (S129). The signal that has undergone the IFFT process is transmitted in the corresponding bandwidth (S130).

Meanwhile, the base station requires RS (eg, a DeModulation Reference Signal (DM-RS)) to perform channel estimation. The DM-RS represents a frequency domain symbol generated using Equation 9. In FIG. 8B, the reference signal is transmitted through the 2nd and 6th symbols of the 7 SC-FDMA symbols of slot 1 and is transmitted through the 2nd and 6th symbols of the 7 SC-FDMA symbols of slot 2 (S130). ).

Meanwhile, the following Equation 10 may be applied to the embodiment of FIGS. 8A and 8B.

Equation 10 represents a process up until immediately before DFT precoding is applied to a signal modulated by 8-PSK or 16-QAM modulation. RE mapping is based on equation (10).

A method of mapping symbols to REs based on Equation 10 will be described with reference to FIG. 9.

9 is a diagram illustrating an embodiment in which Equation 10 is applied according to an embodiment of the present invention. In Figure 9, the vertical axis is the frequency axis and the horizontal axis is the time axis.

In the embodiment of Equation 10 illustrated in FIG. 9, the spreading of the transmission signal in the time domain is performed before the transmission signal is spread in the frequency domain. That is, the transmission signal is spread in the order of the time axis and the frequency axis. In FIG. 9, the frequency increases downward with respect to the frequency axis.

In the embodiment of FIG. 9, it is assumed that RS is transmitted through SC-FDMA symbols 1, 5, 8, and 12.

In FIG. 9, a set of three symbols (eg, {w (0) s (0), w (1) s (0), w (2) s (0)), {w (0) s (1), w (1) s (1), w (2) s (1)}, etc.) represent three symbols to which spreading is applied by the process S125 in FIG. 8B. For example, {w (0) s (0), w (1) s (0), w (2) s (0)} are the SC-FDMA symbols 0, 2, and 3 of the first subcarrier. Sequentially mapped to the three REs corresponding to {w (0) s (1), w (1) s (1), w (2) s (1)} are SC-FDMA symbols 4 of the first subcarrier. It is sequentially mapped to two REs corresponding to Nos. And 6 and one RE corresponding to SC-FDMA symbol 0 of the second subcarrier. And {w (0) s (2), w (1) s (2), w (2) s (2)} correspond to SC-FDMA symbols # 2, # 3, and # 4 of the second subcarrier. Mapped sequentially to three REs. As illustrated in FIG. 9, when symbols are mapped to slot 1 three by S126, a predetermined number (eg, 24 (= 72/3)) is filled in all resources. Similarly, in slot 2, symbols are sequentially filled with resources three by three through the S126 process.

에 대응한다.For example, symbols w (0) s (0), symbols w (1) s (0), and symbols w (2) s (0) each represent SC-FDMA symbols 0, 2, and 3, respectively. And symbols w (0) s (2), symbols w (1) s (2), and symbols w (2) s (2), respectively, are SC-FDMA symbols 2, 3, and 4 And symbol w (0) s (20), symbol w (1) s (20), and symbol w (2) s (20) may each be mapped to SC-FDMA symbols # 7, # 9, And number 10, respectively. Where w () is

Corresponds to.

10A and 10B illustrate encoding and modulation of a 64-bit PUCCH transmission method for an extended CP based on FDD scheme according to an embodiment of the present invention.

When extended CP is applied, a process similar to the process illustrated in FIGS. 8A and 8B may be performed. That is, as illustrated in FIGS. 10A and 10B, the coding process, the rate matching process, the modulation process, and the DFT precoding process are performed similarly to the embodiment of FIGS. 8A and 8B.

The CRC process (S140), TBCC and rate matching process (S141), the scrambling and interleaving process (S142), and the modulation process (S143) illustrated in FIG. 10A are each S120, S121, S122, and S123 of FIG. 8A. Similar to each of the processes.

10B, the phase rotation process S144, the spreading process S145, the resource mapping process S146, the cyclic shift process S147, the DFT process S148, the IFFT process S149, and the SC-FDMA After the symbol generation, each of the signal transmission processes S150 is similar to each of S124, S125, S126, S127, S128, S129, and S130 illustrated in FIG. 8B.

10A and 10B differ from the embodiment of FIGS. 8A and 8B in that only one reference signal is transmitted per slot.

In FIG. 10B, a case where an RS is transmitted through a fourth symbol of six SC-FDMA symbols in slot 1 and is transmitted through a fourth symbol among six SC-FDMA symbols in slot 2 is illustrated.

11A, 11B, and 11C are diagrams illustrating a 64-bit PUCCH transmission method for two PRBs and one DM-RS per slot, QPSK, and normal CP, according to an embodiment of the present invention. to be.

Two PRBs per slot are used instead of one PRB per slot, signals are transmitted in normal CP mode, one RS per slot is used, and instead of higher order modulation, the following table 7 (QPSK modulation mapping) In the case where the QPSK (or 4-QAM) modulation scheme defined in FIG. 6 is used, PUCCH transmission may be configured as illustrated in FIGS. 11A, 11B, and 11C.

~ e (i), ~ e (i + 1) I Q 00 1 / √2 1 / √2 01 1 / √2 -1 / √2 10 -1 / √2 1 / √2 11 -1 / √2 -1 / √2

이고, √2는

이다.In Table 7, ~ e (i) and ~ e (i + 1) are

√2 is

to be.

In addition, the interleaving process is performed after the TBCC process, the rate matching process, and the scrambling process. Here, the interleaving process may be expressed as follows.

The output of the scrambled bit stream is subject to interleaving of equation (5). The value of N in Equation 5 is 192 in the case of normal CP and 160 in the case of extended CP.

The CRC process (S160), TBCC and rate matching process (S161), the scrambling and interleaving process (S162), and the modulation process (S163) illustrated in FIG. 11A are each S100 process, S101 process, S102 process, and S103 of FIG. 7A. Similar to each of the processes. However, in step S163, instead of higher order modulation, a QPSK (or 4-QAM) modulation scheme defined in Table 7 may be used.

11B and 11C, the signal after the phase rotation process (S164), spreading process (S165), cyclic shift process (S166), DFT process (S167), IFFT process (S168), and SC-FDMA symbol generation Each of the transmission process S169 is similar to each of the S104 process, the S105 process, the S106 process, the S107 process, the S108 process, and the S109 process illustrated in FIG. 7B.

The 96 symbols modulated by the S163 process are divided into eight symbol groups. Each symbol group includes 12 symbols. Four of the eight symbol groups correspond to slot 1 (containing seven SC-FDMA symbols) and the rest correspond to slot 2 (containing seven SC-FDMA symbols). Specifically, two of the four symbol groups corresponding to slot 1 correspond to (mapped) one of the two PRBs for slot 1 (FIG. 11B), and the remaining two symbol groups are two PRBs for slot 1 Corresponds to the other one of (mapped) (FIG. 11C). Similarly, two of the four symbol groups corresponding to slot 2 correspond to (mapped) one of the two PRBs for slot 2 (FIG. 11B), and the remaining two symbol groups are of the two PRBs for slot 2 Corresponds to the other one (mapped) (FIG. 11C).

11B and 11C illustrate an example in which an RS is transmitted through a fourth symbol of seven SC-FDMA symbols in slot 1 and is transmitted through a fourth symbol among seven SC-FDMA symbols in slot 2.

12A, 12B, and 12C illustrate a 64-bit PUCCH transmission method for a case where two PRBs and two DM-RSs are used per slot, QPSK is used, and a normal CP is used, according to an embodiment of the present invention. to be.

As illustrated in FIGS. 12A, 12B, and 12C, when two DM-RSs are allocated (mapped to resources) and transmitted, the PUCCH is the same as that of the embodiment of FIGS. 11A, 11B, and 11C. It is sent through a similar process.

However, in an embodiment in which two RSs are transmitted per slot (e.g., FIGS. 12A to 12C), the RE is insufficient in comparison with an embodiment in which one RS is transmitted per slot (e.g., FIGS. 11A to 11C). Only 80 modulated QPSK symbols are transmitted, not 96 QPSK symbols.

The 160 bits output through the rate matching are interleaved. Specifically, the output of the scrambled bit scrim is subjected to the interleaving of Equation 5. The value of N in Equation 5 is 160 in the case of a normal CP or an extended CP.

The CRC process (S180), the TBCC and rate matching process (S181), the scrambling and interleaving process (S182), and the modulation process (S183) illustrated in FIG. 12A are each S160, S161, S162, and Similar to each of the S163 process.

12B and 12C, the signal after the phase rotation process (S164), the spreading process (S165), the cyclic shift process (S187), the DFT process (S188), the IFFT process (S189), and the SC-FDMA symbol generation Each of the transmission process S190 is similar to each of the S164 process, the S165 process, the S166 process, the S167 process, the S168 process, and the S169 process illustrated in FIGS. 11B and 11C.

The resource mapping process S186, illustrated in FIGS. 12B and 12C, is similar to the process S126 illustrated in FIG. 8B. Instead of the method of applying the OCC to only three limited SC-FDMA symbols (eg, the method illustrated in Equation 6 and FIG. 7B), another method may be considered. Specifically, a method of spreading symbols by spreading the REs of various combinations of SC-FDMA symbols and utilizing OCC groups in all possible cases, and mapping unit bundles of OCC number of spreaded symbols to the REs (eg , The method illustrated in FIG. 9) may be applied to a process S186.

The 80 symbols modulated by the S183 process are divided into 8 symbol groups. Each symbol group includes ten symbols. Four of the eight symbol groups correspond to slot 1 (containing seven SC-FDMA symbols) and the rest correspond to slot 2 (containing seven SC-FDMA symbols). Specifically, two of the four symbol groups corresponding to slot 1 correspond to one of two PRBs for slot 1 (FIG. 12B), and the remaining two symbol groups are assigned to the other of the two PRBs for slot 1. Corresponding (FIG. 12C). Similarly, two of the four symbol groups corresponding to slot 2 correspond to one of the two PRBs for slot 2 (FIG. 12B), and the remaining two symbol groups correspond to the other of the two PRBs for slot 2 (FIG. 12C).

12B and 12C, RS is transmitted on the second and sixth symbols of the seven SC-FDMA symbols of slot 1 and transmitted on the second and sixth symbols of the seven SC-FDMA symbols of slot 2. The case is illustrated.

13A, 13B, and 13C illustrate a 64-bit PUCCH transmission method for a case in which two PRBs per slot are used, QPSK is used, and an extended CP is used according to an embodiment of the present invention.

When the extended CP is set, a process similar to the process illustrated in FIGS. 12A to 12C may be performed. That is, as illustrated in FIGS. 13A to 13C, a coding process, a rate matching process, a modulation process, and a DFT precoding process may be performed similarly to the embodiment of FIGS. 12A to 12C.

In the embodiments of FIGS. 13A to 13C, the number of SC-FDMA symbols transmitted per slot is limited to 5 and only one DM-RS is transmitted per slot, which is different from the embodiments of FIGS. 12A to 12C.

The CRC process (S200), the TBCC and rate matching process (S201), the scrambling and interleaving process (S202), and the modulation process (S203) illustrated in FIG. 13A are each S180, S181, S182, and Similar to each of the S183 process.

13B and 13C, the phase rotation process (S204), the spreading process (S205), the resource mapping process (S206), the cyclic shift process (S207), the DFT process (S208), the IFFT process (S209), and After the SC-FDMA symbol generation, the signal transmission process S210 is similar to each of the processes S184, S185, S186, S187, S188, S189, and S190 illustrated in FIGS. 12B and 12C.

The 80 symbols modulated by the S203 process are divided into 8 symbol groups. Each symbol group includes ten symbols. Four of the eight symbol groups correspond to slot 1 (containing six SC-FDMA symbols) and the rest correspond to slot 2 (containing six SC-FDMA symbols). Specifically, two of the four symbol groups corresponding to slot 1 correspond to one of two PRBs for slot 1 (FIG. 13B), and the remaining two symbol groups are assigned to the other of the two PRBs for slot 1. (Fig. 13C). Similarly, two of the four symbol groups corresponding to slot 2 correspond to one of the two PRBs for slot 2 (FIG. 13B), and the remaining two symbol groups correspond to the other of the two PRBs for slot 2 (FIG. 13C).

13B and 13C illustrate an example in which an RS is transmitted through a fourth symbol of six SC-FDMA symbols in slot 1 and is transmitted through a fourth symbol among six SC-FDMA symbols in slot 2.

14A, 14B, and 14C illustrate 64-bit PUCCH transmission for the case where two PRBs and one DM-RS are used per slot, QPSK is used, and normal CP and OCC = 4 are used according to an embodiment of the present invention. It is a figure which shows a method.

=4 인 경우도 고려될 수 있다.

=4는 OCC=4에 대응한다. 이때, 스프레딩의 적용을 위한 OCC 시퀀스

는 아래의 표 8(The orthogonal sequence

)과 같이 정의될 수 있다. On the other hand, in the embodiment of the present invention,

The case of = 4 may also be considered.

= 4 corresponds to OCC = 4. At this time, OCC sequence for application of spreading

Table 8 below shows the orthogonal sequence.

Can be defined as

Sequence index n _oc Orthogonal sequence [w_noc (0) ... w_noc (N ^ PUCCH_SF -1)] N ^ PUCCH_SF = 4 0  [1 1 1 1] One [1 -1 1 -1] 2 [1 1 -1 -1] 3 [1 -1 -1 1]

이고, N^PUCCH_SF는

이다.In Table 8, w_noc () is

N ^ PUCCH_SF is

to be.

=4인 스프레딩을 적용 받는 심볼들은, SC-FDMA DFT 프리코딩이 적용 될 수 있도록 준비 과정을 거친다. DFT 프리코딩을 위한 준비가 완료되면, 도 14a~도 14c에 예시된 바와 같이, S226 과정의 결과에 대하여, 수학식 5와 수학식 11에 기초한 과정들이 적용되고(S227, S228), IFFT가 최종적으로 적용된다(S229).

Symbols subjected to spreading of = 4 are prepared to be applied to SC-FDMA DFT precoding. When the preparation for DFT precoding is completed, as illustrated in FIGS. 14A to 14C, the processes based on Equations 5 and 11 are applied to the result of the S226 process (S227 and S228), and the IFFT is finally obtained. It is applied to (S229).

As illustrated in FIG. 14A, 144 bits output through rate matching are subjected to interleaving. Specifically, the output of the scrambled bit stream is subjected to the interleaving of Equation 5. The value of N in Equation 5 is 144 in the case of normal CP.

Equation 11 below may be applied to the embodiment of FIGS. 14A to 14C.

The spreading orthogonal sequence applied to Equation 11 is selected by one of the sequence indices n _oc defined in Table 8, and the selected spreading orthogonal sequence is used for spreading. Equation 11 shows the process up until the DFT precoding is applied to the QPSK modulated signal. RE mapping is based on equation (11).

A method of mapping symbols to REs based on Equation 11 will be described with reference to FIG. 15 to be described later.

The CRC process (S220), the TBCC and rate matching process (S221), the scrambling and interleaving process (S222), and the modulation process (S223) illustrated in FIG. 14A are respectively S180, S181, S182, and Similar to each of the S183 process. However, 144 bits are output by step S221 and 72 symbols are output by step S223.

14B and 14C, the phase rotation process S224, the spreading process S225, the resource mapping process S226, the cyclic shift process S227, the DFT process S228, the IFFT process S229, and After the SC-FDMA symbol generation, the signal transmission process S230 is similar to each of the processes S184, S185, S186, S187, S188, S189, and S190 illustrated in FIGS. 12B and 12C.

The 72 symbols modulated by the S223 process are divided into 8 symbol groups. Each symbol group includes nine symbols. Four of the eight symbol groups correspond to slot 1 (containing seven SC-FDMA symbols) and the rest correspond to slot 2 (containing seven SC-FDMA symbols). Specifically, two of the four symbol groups corresponding to slot 1 correspond to one of two PRBs for slot 1 (FIG. 14B), and the remaining two symbol groups are assigned to the other of the two PRBs for slot 1. (Fig. 14C). Similarly, two of the four symbol groups corresponding to slot 2 correspond to one of the two PRBs for slot 2 (FIG. 14B), and the remaining two symbol groups correspond to the other of the two PRBs for slot 2 (FIG. 14C).

RS may be generated using Equation (9).

14B and 14C illustrate an example in which an RS is transmitted through a fourth symbol of seven SC-FDMA symbols in slot 1 and is transmitted through a fourth symbol among seven SC-FDMA symbols in slot 2.

15 is a diagram illustrating an embodiment in which Equation 11 is applied according to an embodiment of the present invention. Specifically, FIG. 15 illustrates an embodiment in which symbols to which modulation and spreading are applied are mapped to an RE when OCC = 4.

The embodiment of Equation 11 illustrated in FIG. 15 is similar to the embodiment of FIG. 9.

Specifically, spreading the transmission signal in the time domain is performed before spreading the transmission signal in the frequency domain. That is, the transmission signal is spread in the order of the time axis and the frequency axis. In FIG. 15, the frequency increases downward with respect to the frequency axis.

For example, symbol w (0) s (0), symbol w (1) s (0), symbol w (2) s (0), and symbol w (3) s (0) are each SC-FDMA symbols. Can be mapped to 0, 1, 2, and 4, respectively, symbols w (0) s (2), symbols w (1) s (2), symbols w (2) s (2), and Each of the symbols w (3) s (2) may be mapped to SC-FDMA symbols 2, 4, 5, and 6, respectively, and symbols w (0) s (18) and symbol w (1) s Each of (18), symbols w (2) s (18), and w (3) s (18) may be mapped to SC-FDMA symbols 7, 8, 9, and 11, respectively.

In the embodiment of FIG. 15, it is assumed that RS is transmitted through SC-FDMA symbols 3 and 10.

16A, 16B, and 16C illustrate 64-bit PUCCH transmission for the case where two PRBs and two DM-RSs are used per slot, QPSK is used, and normal CP and OCC = 4 are used according to an embodiment of the present invention. It is a figure which shows a method.

When two DM-RSs are applied per slot, the PUCCH may be transmitted as in the embodiment of FIGS. 16A to 16C. In the embodiments of Figs. 16A to 16C, the following Equation 12 is applied instead of Equation 11.

The output of the scrambled bit stream is subjected to interleaving of Equation 5. The value of N in Equation 5 is 120 in the case of a normal CP or an extended CP.

Equation 12 shows a process until the DFT precoding is applied to a signal to which interleaving, QPSK modulation, and spreading are applied. RE mapping is based on equation (12).

The CRC process (S240), the TBCC and rate matching process (S241), the scrambling and interleaving process (S242), and the modulation process (S243) illustrated in FIG. 16A are respectively S180, S181, S182, and Similar to each of the S183 process. However, 120 bits are output by the S241 process, and 60 symbols are output by the S243 process.

The phase rotation process (S244), the spreading process (S245), the resource mapping process (S246), the cyclic shift process (S247), the DFT process (S248), the IFFT process (S249), and the process illustrated in FIGS. 14B and 14C. After the SC-FDMA symbol generation, each signal transmission process S250 is similar to each of processes S184, S185, S186, S187, S188, S189, and S190 illustrated in FIGS. 12B and 12C.

The 60 symbols modulated by the S243 process are divided into 4 symbol groups. Each symbol group contains 15 symbols. Two of the four symbol groups correspond to slot 1 (containing seven SC-FDMA symbols) and the rest correspond to slot 2 (containing seven SC-FDMA symbols). Specifically, one of the two symbol groups corresponding to slot 1 corresponds to one of the two PRBs for slot 1 (FIG. 16B), and the other one symbol group corresponds to the other of the two PRBs for slot 1 (FIG. 16C). Similarly, one of the two symbol groups corresponding to slot 2 corresponds to one of the two PRBs for slot 2 (FIG. 16B) and the other one symbol group corresponds to the other of the two PRBs for slot 2 (FIG. 16C).

16B and 16C, RS is transmitted on the second and sixth symbols of the seven SC-FDMA symbols of slot 1, and RS is transmitted on the second and sixth symbols of the seven SC-FDMA symbols of slot 2. The case is illustrated.

17A, 17B, and 17C illustrate 64-bit PUCCH transmission for a case where two PRBs and one DM-RS are used per slot, QPSK is used, and an extended CP and OCC = 4 are used according to an embodiment of the present invention. It is a figure which shows a method.

When extended CP is applied to an OFDM symbol (or SC-FDMA symbol), a signal processing procedure as illustrated in FIGS. 17A to 17C is performed.

17A to 17C, the number of DM-RSs transmitted per slot is different from the number of DM-RSs transmitted per slot in the embodiments of FIGS. 16A to 16C.

17A to 17C, the same interleaving process and resource mapping process as the embodiment of FIGS. 16A to 16C are performed.

The signal that has undergone the resource mapping process is mapped to the SC-FDMA symbol n which finally transmits data and transmitted.

The CRC process (S260), TBCC and rate matching process (S261), the scrambling and interleaving process (S262), and the modulation process (S263) illustrated in FIG. 17A are each of steps S240, S241, S242, and S242 of FIG. Similar to each S243 process.

17B and 17C, the phase rotation process (S264), the spreading process (S265), the resource mapping process (S266), the cyclic shift process (S267), the DFT process (S268), the IFFT process (S269), and After the SC-FDMA symbol generation, the signal transmission process S270 is similar to each of the processes S244, S245, S246, S247, S248, S249, and S250 illustrated in FIGS. 16B and 16C.

The 60 symbols modulated by the S263 process are divided into 4 symbol groups. Each symbol group contains 15 symbols. Two of the four symbol groups correspond to slot 1 (containing six SC-FDMA symbols) and the rest correspond to slot 2 (containing six SC-FDMA symbols). Specifically, one of the two symbol groups corresponding to slot 1 corresponds to one of the two PRBs for slot 1 (FIG. 17B), and the other one symbol group corresponds to the other of the two PRBs for slot 1 (FIG. 17C). Similarly, one of the two symbol groups corresponding to slot 2 corresponds to one of the two PRBs for slot 2 (FIG. 17B) and the other one symbol group corresponds to the other of the two PRBs for slot 2 (FIG. 17C).

17B and 17C illustrate an example in which an RS is transmitted through a fourth symbol of six SC-FDMA symbols in slot 1 and is transmitted through a fourth symbol among six SC-FDMA symbols in slot 2.

18A and 18B illustrate a 64-bit PUCCH transmission method for a case where one PRB and one DM-RS are used per slot, QPSK modulation is used, and OCC = 2 is used in a normal CP mode according to an embodiment of the present invention. A diagram illustrating encoding and modulation.

=2인 스프레딩이 사용되는 경우에, 슬롯 당 1개의 PRB만 사용되더라도 64 비트 페이로드 전송은 충분하다.

=2는 OCC=2에 대응한다.

When spreading with = 2 is used, 64-bit payload transmission is sufficient even if only one PRB per slot is used.

= 2 corresponds to OCC = 2.

As illustrated in FIGS. 18A and 18B, a coding process, a rate matching process, a modulation process, and a DFT precoding process are performed.

는, 아래의 표 9(The orthogonal sequence

)와 같이 정의될 수 있다.OCC sequence for spreading applied to the embodiment of FIGS. 18A and 18B

Table 9 (The orthogonal sequence)

Can be defined as

Sequence index n _oc Orthogonal sequence [w_noc (0) ... w_noc (N ^ PUCCH_SF -1)] N ^ PUCCH_SF = 2 0  [1 1] One  [1 -1]

이고, N^PUCCH_SF는

이다.In Table 9, w_noc () is

N ^ PUCCH_SF is

to be.

In addition, the interleaving process is performed after the TBCC process, the rate matching process, and the scrambling process. The output of the scrambled bit stream is subjected to interleaving of Equation 5. The value of N in Equation 5 is 144 in the case of normal CP.

The output of the interleaved bit stream is then modulated with the QPSK symbol s (). RE mapping and spreading based on Equation 13 below are applied to the QPSK symbols s (), and the symbols that have undergone resource mapping are finally mapped and transmitted to the SC-FDMA symbol n.

The CRC process (S280), the TBCC and rate matching process (S281), the scrambling and interleaving process (S282), and the modulation process (S283) illustrated in FIG. 18A are each S220 process, S221 process, S222 process, and Similar to each S223 process.

18B, the phase rotation process (S284), the spreading process (S285), the resource mapping process (S286), the cyclic shift process (S287), the DFT process (S288), the IFFT process (S289), and the SC-FDMA Each signal transmission process S290 after symbol generation is similar to each of S224 process, S225 process, S226 process, S227 process, S228 process, S229 process, and S230 process illustrated in FIG. 14B. 18A and 18B, however, one PRB per slot is used and OCC = 2.

The 72 symbols modulated by the S283 process are divided into 6 symbol groups. Each symbol group includes 12 symbols. Three of the six symbol groups correspond to slot 1 (containing seven SC-FDMA symbols), and the rest correspond to slot 2 (containing seven SC-FDMA symbols).

18B illustrates an example in which an RS is transmitted through a fourth symbol of seven SC-FDMA symbols in slot 1 and is transmitted through a fourth symbol among seven SC-FDMA symbols in slot 2.

19A and 19B illustrate a 64-bit PUCCH transmission method for a case where one PRB and two DM-RSs are used per slot, QPSK modulation is used, and OCC = 2 is used in a normal CP mode according to an embodiment of the present invention. A diagram illustrating encoding and modulation.

In the embodiment of Figs. 19A and 19B, since two DM-RSs are transmitted per slot, the usable RE is reduced. Decreasing the available RE affects the interleaving process.

The output of the scrambled bit stream is subjected to interleaving of Equation 5. The value of N in Equation 5 is 120 in the case of a normal CP or an extended CP.

After the rate matching, the QPSK modulated symbol is subjected to an RE mapping process based on Equation 14 below.

The CRC process (S300), TBCC and rate matching process (S301), the scrambling and interleaving process (S302), and the modulation process (S303) illustrated in FIG. 19A are respectively the S280 process, the S281 process, the S282 process, and the process of FIG. Similar to each of the S283 processes. However, 120 bits are output by the process S301 and 60 symbols are output by the process S303.

The phase rotation process (S304), the spreading process (S305), the resource mapping process (S306), the cyclic shift process (S307), the DFT process (S308), the IFFT process (S309), and the SC-FDMA illustrated in FIG. 19B Each signal transmission process S310 after symbol generation is similar to each of S284, S285, S286, S287, S288, S289, and S290 illustrated in FIG. 18B. However, in the embodiment of Figs. 19A and 19B, two RSs are transmitted per slot.

The 60 symbols modulated by the S303 process are divided into 6 symbol groups. Each symbol group includes ten symbols. Three of the six symbol groups correspond to slot 1 (containing seven SC-FDMA symbols), and the rest correspond to slot 2 (containing seven SC-FDMA symbols).

19B illustrates an example in which an RS is transmitted through 2nd and 6th symbols of 7 SC-FDMA symbols of slot 1 and is transmitted through 2nd and 6th symbols of 7 SC-FDMA symbols of slot 2. It is.

=2 이지만, 다수의 SC-FDMA 심볼에 걸쳐 스프레딩이 적용되는 것이 아니고 1개의 SC-FDMA 심볼에 한정하여 스프레딩하는 기법에 대하여 설명한다.Next, if the number of payload bits is 64, 58 and 52

Although = 2, spreading is not applied over a plurality of SC-FDMA symbols, and a technique of spreading to only one SC-FDMA symbol will be described.

As described above, when 64 information payload bits to be transmitted by a device (eg, a terminal) may be transmitted using one PRB per slot. In more detail, a device (eg, a terminal) may modulate a symbol by using a QPSK modulation scheme, and may map and transmit the QPSK-modulated symbol to an SC-FDMA symbol.

20A, 20B, and 20C illustrate 64-bit PUCCH transmission for a case where one PRB and one DM-RS are used per slot, QPSK is used, and normal CP and OCC = 2 are used according to an embodiment of the present invention. It is a figure which shows a method.

In detail, FIGS. 20A and 20B illustrate a process in which one PRB is used per slot to map a QPSK modulation symbol to one subframe.

In the embodiment of FIGS. 20A and 20B, an interleaving process is performed. Specifically, the output of the scrambled bit stream is subjected to the interleaving of Equation 5. The value of N in Equation 5 is 144 in the case of normal CP.

Interleaved rate matching output is modulated via QPSK.

(단, i=0, 1)이 적용된다.

는 n_oc의 값에 따라, 표 9를 사용한다. Spreading with OCC = 2 in Modulation Symbols

(I = 0, 1) applies.

Uses Table 9, depending on the value of n _oc .

RE mapping based on Equation 15 is applied to the symbols to which the spreading is applied. Equation 15 shows a process until the DFT precoding is applied to the signal to which QPSK modulation and spreading are applied.

=2 이다. 또한

와

는 아래의 표와 같이 정의될 수 있다. here

= 2. Also

Wow

Can be defined as shown in the table below.

와

는 각각 6으로 결정된다. here

Wow

Are each determined to be 6.

The CRC process (S320), the TBCC and rate matching process (S321), the scrambling and interleaving process (S322), and the modulation process (S323) illustrated in FIG. 20A are each performed by the process S280, process S281, process S282, and process S282 of FIG. Similar to each of the S283 processes. However, 64 bits are input in step S320 to output 72 bits, 144 bits are output in step S321, and 72 symbols are output in step S323. In some cases, the scrambling and interleaving process S322 may be skipped.

는

이다.20B, the phase rotation process S324, the spreading process S325, the resource mapping process S326, the cyclic shift process S327, the DFT process S328, the IFFT process S329, and SC-FDMA After the symbol generation, the signal transmission process S330 is similar to each of the S284 process, the S285 process, the S286 process, the S287 process, the S288 process, the S289 process, and the S290 process illustrated in FIG. 18B. However, in the embodiments of FIGS. 20A and 20B, spreading is not limited to a plurality of SC-FDMAs but is limited to one SC-FDMA symbol. In some cases, the phase rotation process S324 may be skipped. Used in the process S325 of Figure 20b

Is

to be.

In the DFT process, as shown in Equation 16 below, DFT precoding is applied (S328).

The 72 symbols modulated through the S323 process are divided into two symbol groups. Each symbol group contains 36 symbols. One of the two symbol groups corresponds to slot 1 (containing seven SC-FDMA symbols), and the other corresponds to slot 2 (containing seven SC-FDMA symbols).

20B illustrates an example in which an RS is transmitted through a fourth symbol of seven SC-FDMA symbols in slot 1 and is transmitted through a fourth symbol among seven SC-FDMA symbols in slot 2.

을 위한 매핑 과정을 나타낸다. 여기서, n은 시간 축 SC-FDMA 심볼 인덱스이고 i는 주파수 축 부반송파 인덱스이다. 예를 들어, 1개의 심볼 s(0)가 OCC=2 인 스프레딩을 거친 후 SC-FDMA 심볼의 부반송파 0번과 6번에 매핑된다. 따라서 SC-FDMA 심볼 0번에는 6개의 심볼 s(0)~s(5)가 OCC=2인 스프레딩을 거친 후 매핑된다. 즉, {w(0)s(0), w(0)s(1), ..., w(0)s(5)}가 SC-FDMA 심볼 0번의 12개의 부반송파 중에서 처음 6개의 부반송파에 매핑되고, {w(1)s(0), w(1)s(1), ..., w(1)s(5)}가 SC-FDMA 심볼 0번의 12개의 부반송파 중에서 나머지 6개의 부반송파에 매핑된다. 이와 유사한 방법으로, SC-FDMA 심볼 1번에는 6개의 심볼 s(6)~s(11)가 OCC=2인 스프레딩을 거친 후 매핑된다. 이와 유사한 방법으로, SC-FDMA 심볼 13번에는 6개의 심볼 s(66)~s(71)가 OCC=2인 스프레딩을 거친 후 매핑된다. 한편, 도 20c의 매핑 과정은 OCC=2가 아닌 경우(예, OCC=3, OCC=4 등)에도 유사하게 적용될 수 있다.In FIG. 20C, when a region is divided into time and frequency, a process of mapping a bundle unit of six symbols to which spreading is applied is sequentially mapped to the frequency axis and then mapped to the time axis is illustrated. That is, FIG. 20C shows the final equation 15

It shows the mapping process for. Where n is the time axis SC-FDMA symbol index and i is the frequency axis subcarrier index. For example, one symbol s (0) is mapped to subcarriers 0 and 6 of an SC-FDMA symbol after spreading with OCC = 2. Accordingly, six symbols s (0) to s (5) are mapped to SC-FDMA symbol 0 after spreading with OCC = 2. That is, {w (0) s (0), w (0) s (1), ..., w (0) s (5)} are assigned to the first six subcarriers of the 12 subcarriers of the SC-FDMA symbol 0. Mapped and {w (1) s (0), w (1) s (1), ..., w (1) s (5)} are the remaining 6 subcarriers out of the 12 subcarriers of SC-FDMA symbol 0. Is mapped to. In a similar manner, six symbols s (6) to s (11) are mapped to SC-FDMA symbol 1 after spreading with OCC = 2. In a similar manner, the SC-FDMA symbol 13 is mapped after six symbols s (66) to s (71) are subjected to spreading with OCC = 2. Meanwhile, the mapping process of FIG. 20C may be similarly applied to a case where OCC = 2 (eg, OCC = 3, OCC = 4, etc.).

21A and 21B illustrate one PRB and one DM-RS per slot, QPSK used, normal CP, OCC = 2, and shortened PUCCH subframe (SRS through one SC-FDMA symbol) according to an embodiment of the present invention. A diagram illustrating a 58-bit PUCCH transmission method for a case in which a (sounding reference signal) transmission is used.

When one DM-RS is transmitted per slot, the same signal processing as that of the embodiment of FIGS. 21A and 21B is performed.

In the embodiment of FIGS. 21A and 21B, an interleaving process is performed. Specifically, the output of the scrambled bit stream is subjected to the interleaving of Equation 5. The value of N in Equation 5 is 132 in the case of a normal CP.

Interleaved rate matching output is modulated via QPSK.

(단, i=0,1,...,

-1) 이 적용된다.

는 n_oc의 값에 따라, 표 9를 사용한다. 상기 표 9에는 주파수 축에 적용될 길이 2를 가지는 스프레딩 시퀀스가 정의되어 있다. 스프레딩이 적용된 심볼들에는 수학식 15에 기초한 RE 매핑이 적용된다. 도 20c의 매핑 과정이 도 21a 및 도 21b의 실시예에 유사하게 적용될 수 있다. 수학식 15는 QPSK 변조와 스프레딩이 적용된 신호에 DFT 프리코딩이 적용되기 직전까지의 과정을 나타낸다. 여기서

와

는 각각 6과 5로 결정된다. 그리고 DFT과정에서 상기의 수학식 16과 같이, DFT 프리코딩이 적용된다.Spreading with OCC = 2 in Modulation Symbols

(Where i = 0,1, ...,

-1) applies.

Uses Table 9, depending on the value of n _oc . In Table 9, a spreading sequence having a length of 2 to be applied to a frequency axis is defined. RE mapping based on Equation 15 is applied to the symbols to which the spreading is applied. The mapping process of FIG. 20C may be similarly applied to the embodiment of FIGS. 21A and 21B. Equation 15 shows a process until the DFT precoding is applied to the signal to which QPSK modulation and spreading are applied. here

Wow

Are determined to be 6 and 5, respectively. In the DFT process, as in Equation 16, DFT precoding is applied.

The CRC process (S340), TBCC and rate matching process (S341), the scrambling and interleaving process (S342), and the modulation process (S343) illustrated in FIG. 21A are respectively S320 process, S321 process, S322 process, and Similar to each of the S323 process. However, 66 bits are output by the S341 process and 66 symbols are output by the S343 process. In some cases, the scrambling and interleaving process S322 may be skipped.

는

이다.The phase rotation process S344, the spreading process S345, the resource mapping process S346, the cyclic shift process S347, the DFT process S348, the IFFT process S349, and the SC-FDMA illustrated in FIG. 21B Each signal transmission process (S350) after symbol generation is similar to each of S324, S325, S326, S327, S328, S329, and S330 illustrated in FIG. 20B. However, in the embodiment of FIGS. 21A and 21B, the total number of transmitted symbols is 66. In some cases, the phase rotation process S324 may be skipped. Used in the process of S345 of Figure 21b

Is

to be.

The 66 symbols modulated by the S343 process are divided into two symbol groups. The first symbol group includes 36 symbols and the second symbol group includes 30 symbols. One of the two symbol groups corresponds to slot 1 (containing seven SC-FDMA symbols), and the other corresponds to slot 2 (containing seven SC-FDMA symbols).

In FIG. 21B, a case where an RS is transmitted through a fourth symbol of seven SC-FDMA symbols in slot 1 and is transmitted through a fourth symbol among seven SC-FDMA symbols in slot 2 is illustrated. The last SC-FDMA symbol in slot 2 is then allocated for SRS signal transmission.

22A and 22B illustrate a 52-bit PUCCH transmission method for a case where one PRB and one DM-RS are used per slot, QPSK is used, and extended CP and OCC = 2 are used according to an embodiment of the present invention. to be.

When the extended CP is set, the same signal processing procedure as the embodiment of FIGS. 21A and 21B except for the total number of modulated symbols and the number of symbols divided into each slot, as illustrated in FIGS. 22A and 22B. This is done.

Signals having undergone the process based on Equations 5 and 15 are mapped to the REs of the SC-FDMA symbol n for transmitting data and transmitted. The mapping process of FIG. 20C may be similarly applied to the embodiment of FIGS. 22A and 22B.

The CRC process (S360), TBCC and rate matching process (S361), the scrambling and interleaving process (S362), and the modulation process (S363) illustrated in FIG. 22A are respectively S340 process, S341 process, S342 process, and Similar to each S343 process.

는

이다.The phase rotation process (S364), spreading process (S365), resource mapping process (S366), cyclic shift process (S367), DFT process (S368), IFFT process (S369), and SC-FDMA illustrated in FIG. 22B Each signal transmission process (S370) after symbol generation is similar to each of the processes S344, S345, S346, S347, S348, S349, and S350 illustrated in FIG. 21B. However, in the embodiments of FIGS. 22A and 22B, 30 modulation symbols are transmitted in each slot. Used in the process of S365 of Figure 22b

Is

to be.

The 60 symbols modulated by the S363 process are divided into two symbol groups. Each symbol group contains 30 symbols. One of the two symbol groups corresponds to slot 1 (containing five SC-FDMA symbols) and the other corresponds to slot 2 (containing five SC-FDMA symbols).

In FIG. 22B, a case in which an RS is transmitted through a fourth symbol of six SC-FDMA symbols in slot 1 and is transmitted through a fourth symbol among six SC-FDMA symbols in slot 2 is illustrated.

Next, the case where the number of payload bits is 128 will be described.

If the number of payload bits is large (e.g. 128), the spreading process is not performed after QPSK modulation.

23A and 23B illustrate a 128-bit PUCCH transmission method for a case in which one PRB and one DM-RS are used per slot, QPSK is used, and normal CP and OCC = 1 are used according to an embodiment of the present invention. to be.

In the embodiments of FIGS. 23A and 23B, the spreading process is not performed after the QPSK modulation.

The output of the scrambled bit stream is subjected to interleaving of Equation 5. The value of N in Equation 5 is 288 in the case of a normal CP.

Interleaved rate matching output is modulated via QPSK.

The RE mapping based on Equation 17 below is applied to the modulation symbols. Equation 17 shows the process up until the DFT precoding is applied to the QPSK modulated signal.

The CRC process (S380), TBCC and rate matching process (S381), the scrambling and interleaving process (S382), and the modulation process (S383) illustrated in FIG. 23A are each S320 process, S321 process, S322 process, and FIG. Similar to each of the S323 process. However, 128 bits are input in step S380 to output 130 bits, 288 bits are output in step S381, and 144 symbols are output in step S383.

23B, each of the phase rotation process S384, the cyclic shift process S386, the DFT process S387, the IFFT process S388, and the signal transmission process S389 after generating the SC-FDMA symbol are illustrated in FIG. 20B. Similar to each of the S324 process, S327 process, S328 process, S329 process, and S330 process illustrated in FIG. 23A and 23B, the resource mapping process S385 is based on Equation 17, and OCC = 1.

The 144 symbols modulated by the S383 process are divided into two symbol groups. Each symbol group contains 72 symbols. One of the two symbol groups corresponds to slot 1 (containing seven SC-FDMA symbols), and the other corresponds to slot 2 (containing seven SC-FDMA symbols).

In FIG. 23B, a case in which an RS is transmitted through a fourth symbol of seven SC-FDMA symbols in slot 1 and is transmitted through a fourth symbol among seven SC-FDMA symbols in slot 2 is illustrated.

24A and 24B illustrate a 128-bit PUCCH transmission method for a case in which one PRB and two DM-RSs are used per slot, QPSK is used, and normal CP and OCC = 1 are used according to an embodiment of the present invention. to be.

When two DM-RSs are transmitted per slot, the same signal processing procedure as that of the embodiment of FIGS. 24A and 24B is performed.

The output of the scrambled bit stream is subjected to interleaving of Equation 5. The value of N in Equation 5 is 240 in the case of a normal CP.

Interleaved rate matching output is modulated via QPSK.

The RE mapping based on Equation 18 below is applied to the modulation symbols. Equation 18 shows the process up until the DFT precoding is applied to the QPSK modulated signal.

The CRC process (S400), TBCC and rate matching process (S401), the scrambling and interleaving process (S402), and the modulation process (S403) illustrated in FIG. 24A are each of the S380 process, the S381 process, the S382 process, and the process of FIG. Similar to each of the S383 processes. However, 240 bits are output by the S401 process, and 120 symbols are output by the S403 process.

24B, the phase rotation process (S404), the resource mapping process (S405), the cyclic shift process (S406), the DFT process (S407), the IFFT process (S408), and the signal transmission process after SC-FDMA symbol generation ( S409) are each similar to the S384 process, S385 process, S386 process, S387 process, S388 process, and S389 process illustrated in FIG. 23B. 24A and 24B, the resource mapping process S405 is based on Equation 18, and two RSs are transmitted per slot.

120 symbols modulated by the S403 process are divided into two symbol groups. Each symbol group contains 60 symbols. One of the two symbol groups corresponds to slot 1 (containing seven SC-FDMA symbols), and the other corresponds to slot 2 (containing seven SC-FDMA symbols).

24B illustrates an example in which an RS is transmitted through 2nd and 6th symbols of 7 SC-FDMA symbols of slot 1 and is transmitted through 2nd and 6th symbols of 7 SC-FDMA symbols of slot 2. It is.

On the other hand, the _ai value, which is the bit size of the payload, is described in the embodiments of the present invention described above (e.g., FIGS. 7A-7B, 8A-8B, 10A-10B, 11A-11C, 12A to 12C, 13A to 13C, 14A to 14C, 16A to 16C, 17A to 17C, 18A to 18B, 19A to 19B, 20A to 20B, and 21A. 21B, 22A-22B, 23A-23B, 24A-24B, etc.) are not limited to the payload bit size illustrated in FIGS. For example, in the embodiment of FIGS. 19A to 19B, payload bits (eg, a _i = 32, etc.) having a size other than 64 bits may be similarly applied.

Meanwhile, Equations 10 to 18 may be replaced by Equation 19 below.

-1 이고,

=2 or 3 or 4 이다.In equation (19), n = 0, ..., 9 or n = 0, ..., 11, and i = 0,1, ...,

-1

= 2 or 3 or 4

는

의 값에 따라, 표 5, 표 8, 및 표 9 중 하나를 사용한다.In Equation 19,

Is

Depending on the value of, use one of Tables 5, 8, and 9.

25 is a diagram illustrating input and output relationships between a DFT unit and an IFFT unit included in a terminal according to an embodiment of the present invention.

The terminal U100 includes a modulator U110, a DFT unit U120a and U120b, an IFFT unit U130, a pulse shaping unit U140, a digital-to-analog signal conversion and an RF (radio frequency) unit U150, And an antenna U160.

를 DFT부(U120a)에 출력한다.The modulator U110 applies the above-described CRC, coding, rate matching, and modulation to a _k , which is a bit stream to be transmitted by the terminal U100 through the PUCCH. Through this, the modulator U110

Is output to the DFT unit U120a.

에 상술한 DFT 프리코딩을 적용한다. 이를 통해, DFT부(U120a)는

를 IFFT부(U130)에 출력한다. DFT 프리코딩된 신호

는 IFFT부(U130)의 입력을 위한 주파수 대역과 지정된 OFDM(또는 SC-FDMA) 심볼 번호(즉, (k, l))에 매핑된다.The DFT unit U120a

The above-described DFT precoding is applied. Through this, the DFT unit U120a

Is output to the IFFT unit U130. DFT precoded signal

Is mapped to a frequency band for input of the IFFT unit U130 and a designated OFDM (or SC-FDMA) symbol number (ie, (k, l)).

The DFT unit U120b receives data to be transmitted by the terminal U100 through another channel (eg, a physical uplink shared channel (PUSCH)).

The pulse shaping unit U140 applies parallel-to-serial conversion, CP insertion, and pulse shaping to the signal output from the IFFT unit U130.

The RF unit U150 applies a digital signal-to-analog conversion and an RF conversion to the signal output from the pulse shaping unit U140.

The PUCCH signal is multiplexed (frequency multiplexed) with a signal of another channel (eg, PUSCH). The multiplexed signal is transmitted through the antenna U160 in the form of a single carrier via the IFFT unit U130.

FIG. 26 is a diagram illustrating a method of mapping a PUCCH to a frequency domain according to the number of PRBs used per slot according to an embodiment of the present invention.

26, a frequency domain corresponding to m = 0, a frequency domain corresponding to m = 1, a frequency domain corresponding to m = 2, a frequency domain corresponding to m = 3, a frequency domain corresponding to m = 4, and The frequency domain corresponding to m = 5 is illustrated.

In the PUCCH transmission mode in which one PRB is used per slot, the PUCCH is mapped and transmitted in a frequency domain corresponding to m = 0 or m = 1.

In the PUCCH transmission mode in which two PRBs are used per slot, the PUCCH is mapped and transmitted in a frequency domain corresponding to (m = 0 and m = 2) or a frequency domain corresponding to (m = 1 and m = 3).

In FIG. 26, n _PRB represents an index of a plurality of frequency blocks resulting from dividing the total system bandwidth by one PRB. Specifically, n _PRB represents the index from the low frequency block to the high frequency block.

는 단말에 의해 사용되는 전체 시스템 대역을 나타내고, 단위는 PRB 이다.In Figure 26,

Denotes the entire system band used by the terminal, and the unit is PRB.

Meanwhile, the various payload bits a _i described above are determined by the base station. The base station informs the terminal of the determined payload bit a _i . A method (method M100, M110, M120) for determining payload bit a _i will be described. At least one of the methods M100 to M120 may be used.

The method M100 is a method of determining the payload bit a _i based on the total number of component carriers (CCs) allocated by radio resource control (RRC) configuration including a carrier aggregation function. For example, if 10 CCs are configured for one UE, the payload bit a _i may be determined to be 40 bits (= 4 bit x 10 CC). Here, the reason of 4 bits per carrier is that in case of TDD, 1 bit of ACK / NACK for up to 4 DCIs (downlink control information) per CC is considered.

The method M110 is a method of determining the payload bit a _i based on the number of activated CCs among the total CCs allocated by the RRC setting including the carrier aggregation function. Method M110 is similar to method M100, but differs from method M100 in that method M110 considers DCI of the number of activated CCs. That is, in method M110, ACK / NACK of de-activated CC is not taken into account.

Method M120 is a method in which a base station informs a user equipment of a DCI of a CC actually scheduled among CCs activated by an RRC configuration including a carrier aggregation function through a downlink. That is, the base station determines the actual CC to be used out of the total possible CC, and then records the schedule information in the downlink control information (DCI) of each CC and transmits to the terminal through the downlink. The terminal receives the DCI through the downlink for each CC. As many as n number of successful DCI demodulation for each CC, the UE informs the base station of n ACK / NACK through the uplink.

However, the number of DCIs for each CC successfully received by the UE may be different from the total number of DCIs transmitted by the actual base station. In this case, a method of inferring the total number of DCIs transmitted by the actual base station and informing the base station by determining that the terminal is equal to the sum of total DCIs transmitted by the actual base station will be described. In the method M120, the total number of downlink assignment indexes (DAI) in the DCI information is counted, and the payload bit a _i is determined based on the counted value.

The method M120 will be described in detail with reference to FIGS. 27 and 28.

FIG. 27 is a diagram illustrating a CC-specific DAI mapping method (hereinafter, referred to as a 'first DAI mapping method') for an FDD type according to an embodiment of the present invention.

Specifically, FIG. 27 exemplifies a case where the total CCs allocated by activation of the SCell (CC) after the RRC setup is 13 (CC1 to CC13).

The first (or last) four CCs (or DCIs) out of the 13 CCs (or DCIs) transmit a reversed bit order 8-bit CRC output value. The CRC output expressed corresponding to the number of CCs actually transmitted is shown in Table 10 below. For example, as shown in FIG. 27, when nine CCs are actually used and transmitted, the CRC output value is 11011100. This value is actually bit reversed by the base station to form 00111011. As shown in FIG. 27, 00111011 is divided into 2 bits for four CCs (CC1, CC2, CC4, and CC5) and mapped to the DAI. The DAI is included in the DCI and transmitted to the terminal through downlink. The CRC bit 8 bits (eg, 00111011) transmitted in reversed bit order are referred to as total DAI.

#CCs CRC input CRC output Counter / total DAI signaling from eNB (CRC bit reversed) One N / A N / A 00 2 N / A N / A 0001 3 N / A N / A 000110 4 11111111 00000000 00000000 5 111111111 10011011 1101100100 6 1111111111 00110110 011011000001 7 11111111111 11110111 11101111000110 8 111111111111 11101110 0111011100011011 9 1111111111111 11011100 001110110001101100 10 11111111111111 10111000 00011101000110110001 11 111111111111111 01110000 0000111000011011000110 12 1111111111111111 01111011 110111100001101100011011 13 11111111111111111 01101101 10110110000110110001101100 14 111111111111111111 01000001 1000001000011011000110110001 15 1111111111111111111 00011001 100110000001101100011011000110 16 11111111111111111111 10101001 10010101000110110001101100011011 ... ... ... ... 32 111111111111111111111111111111111111 10001011 1101000100011011000110110001101100011011000110110001101100011011 ... ... ... ... 64 11111111111111111111111111111111111111111111111111111111111111111111 01000111 11100010000110110001101100011011000110110001101100011011000110110001101100011011000110110001101100011011000110110001101100011011

The remaining five CCs (eg, CC7, CC9, CC10, CC12, and CC13) for which transmission is valid are recorded in the DAI in the form of increasing the 2-bit counter value in the order of the number of CCs to be transmitted. That is, as the index for n CCs (or DCIs) increases, the 2-bit counter for n CCs (or DCIs) increases (eg, 00-> 01-> 10-> 11-> 00). Here, DAI values (eg, 0001101100) transmitted over n CCs (eg, CC7, CC9, CC10, CC12, and CC13) are referred to as a counter DAI area.

FIG. 27 illustrates a case where only 9 base stations (CC1, CC2, CC4, CC5, CC7, CC9, CC10, CC12, and CC13) of 13 activated CCs transmit data to the UE. Here, four CCs (CC1, CC2, CC4, and CC5) correspond to total DAI, and transmit the reversed CRC output bit through DAI (DAI is included in DCI). In FIG. 27, five CCs CC7, CC9, CC10, CC12, and CC13 correspond to a counter DAI region.

27 illustrates a case where a reception demodulation error of two CCs CC9 and CC13 occurs when the terminal receives Total DAI and Counter DAI from the base station. The terminal determines that the pattern of the counter DAI is abnormal and determines that an error exists in the counter DAI area. Through this, the terminal determines that a reception error has occurred. In addition to determining the reception error, the UE may determine that the four CCs (CC3, CC6, CC8, CC11) is not transmitted through the pattern of total DAI and counter DAI defined in Table 10. Accordingly, the terminal determines that the codebook size is 9 at last, and the ACKnowledgement (A) or Not ACKnowledged (N) response is transmitted to the base station through the uplink in the CC index order (from small index to large index) for the valid CC. send.

FIG. 28 is a diagram illustrating a total and counter DAI mapping method (hereinafter, referred to as a 'second DAI mapping method') for a TDD type according to an embodiment of the present invention.

The second DAI mapping method is similar to the first DAI mapping method.

However, in the second DAI mapping method, a situation in which the maximum number of acceptable DCIs that can bundle and transmit a plurality of subframes is increased should be considered. As a result, the total number of DCIs used by the base station (or the corresponding number of ACK / NACKs to which the terminal should respond) may increase. Accordingly, the second DAI mapping method determines a subframe range (eg, up to four subframes) and expresses the number of DCIs actually transmitted within the subframe range as total CRC (total DAI). It is different from the method.

FIG. 28 illustrates a case in which the number of activated CCs CC1 to CC10 is 10 and a total of 15 DCIs are allocated and transmitted to the UE during 4 subframe times. In FIG. 28, the total DAI value transmitted to the terminal is 10011000. As illustrated in Table 10, the counter DAI is 0001101100011011000110 and is transmitted to the UE through 11 DAIs.

29 is a diagram illustrating a transmitter according to an embodiment of the present invention.

The transmitter Tx100 includes a processor Tx110, a memory Tx120, and an RF converter Tx130.

The processor Tx110 may be configured to implement the procedures, functions, and methods described herein in connection with transmission (eg, transmission of a base station, transmission of a terminal). In addition, the processor Tx110 may control each component of the transmitter Tx100.

The memory Tx120 is connected to the processor Tx110 and stores various information related to the operation of the processor Tx110.

The RF converter Tx130 is connected to the processor Tx110 and transmits or receives a radio signal. The transmitter Tx100 may have a single antenna or multiple antennas.

The transmitter Tx100 may be a base station or a terminal.

30 is a diagram illustrating a receiver according to an embodiment of the present invention.

The receiver Rx200 includes a processor Rx210, a memory Rx220, and an RF converter Rx230.

The processor Rx210 may be configured to implement the procedures, functions, and methods described herein with respect to reception (eg, reception of a base station, reception of a terminal). In addition, the processor Rx210 may control each component of the receiver Rx200.

The memory Rx220 is connected to the processor Rx210 and stores various information related to the operation of the processor Rx210.

The RF converter Rx230 is connected to the processor Rx210 and transmits or receives a radio signal. The receiver Rx200 may have a single antenna or multiple antennas.

The receiver Rx200 may be a terminal or a base station.

On the other hand, the embodiment of the present invention is not implemented only through the apparatus and / or method described so far, but may be implemented through a program that realizes a function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded. Such implementations can be readily implemented by those skilled in the art from the description of the above-described embodiments.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (20)

A transmitter transmits feedback information through an uplink control channel. Modulating the feedback information into a plurality of symbols; Spreading the plurality of symbols using a spreading orthogonal sequence of length less than 5; And Mapping the spread symbols to a plurality of resource elements (REs) Transmission method of the transmitter comprising a. The method of claim 1, The modulating step, Generating first information by adding cyclic redundancy check (CRC) information to the feedback information; Generating second information by applying tail biting convolutional channel coding (TBCC) and rate matching to the first information; And Generating the plurality of symbols by modulating the second information through at least one of quadrature phase shift keying (QPSK), phase shift keying (8-PSK), quadrature amplitude modulation (4-QAM), and 16-QAM. Containing steps Method of transmission of the transmitter. The method of claim 2, Generating the plurality of symbols includes: Generating a second bit stream by applying a scrambling sequence to the first bit stream of the second information as shown in Equation 1 below. Method of transmission of the transmitter. [Equation 1]

(

The second bit stream, e (i): The first bit stream, c (i): The scrambling sequence obtained based on c _init of Equation 2 below) [Equation 2]

(n _s : slot number,

Physical cell ID, n _RNTI : radio network temporary identifier (RNTI) of the transmitter The method of claim 1, A first spreading orthogonal sequence having a length of 3 among the spreading orthogonal sequences is: [1 1 1], [1

], And [1

At least one of Method of transmission of the transmitter. The method of claim 1, Mapping to the plurality of REs, Mapping the spread symbols to the plurality of REs based on Equation 1 below; Method of transmission of the transmitter. [Equation 1]

(

Are the mapped symbols, n is the index and n = 0, ...,

-1, i is the index of the subcarrier and i = 0,1, ...,

-One,

,

Is an antenna port, s () is the plurality of symbols,

Is one physical resource block (PRB) bandwidth,

Is the value of the cell-specific phase rotation, n _s is the slot number, l is the index of the time domain symbol,

Is the value of the spreading factor,

Is the spreading orthogonal sequence) The method of claim 1, The spread symbols include a plurality of first symbols and a plurality of second symbols, Mapping to the plurality of REs, Sequentially mapping the plurality of first symbols to remaining time domain symbols except time domain symbols for a reference signal among the plurality of time domain symbols for a first slot; And Sequentially mapping the plurality of second symbols to time domain symbols next to the time domain symbol to which the plurality of first symbols are mapped among the remaining time domain symbols; Method of transmission of the transmitter. The method of claim 1, The modulating step, Grouping the plurality of symbols into a plurality of first symbol groups mapped to a plurality of PRBs for a first slot and a plurality of second symbol groups mapped to a plurality of PRBs for a second slot. Method of transmission of the transmitter. The method of claim 1, Mapping to the plurality of REs, Assigning a plurality of first reference signals for the feedback information to some of the plurality of time domain symbols for a first slot; And Assigning a plurality of second reference signals for the feedback information to some of the plurality of time domain symbols for a second slot; Method of transmission of the transmitter. The method of claim 1, A first spreading orthogonal sequence having a length of 4 among the spreading orthogonal sequences is: At least one of [1 1 1 1], [1 -1 1 -1], [1 1 -1 -1], and [1 -1 -1 1] Method of transmission of the transmitter. The method of claim 1, Mapping to the plurality of REs, Mapping the spread symbols to the plurality of REs based on Equation 1 below; Method of transmission of the transmitter. [Equation 1]

(

Is the mapped symbols, n is the index and n = 0,1, ..., 23, i is the index of the subcarrier and i = 0,1, ...,

-One,

, v = n mod 6,

Is an antenna port, s () is the plurality of symbols,

Is one physical resource block (PRB) bandwidth,

Is the value of the cell-specific phase rotation, n _s is the slot number, l is the index of the time domain symbol,

Is the value of the spreading factor,

Is the spreading orthogonal sequence) The method of claim 1, The spread symbols include a plurality of first symbols and a plurality of second symbols, Mapping to the plurality of REs, Sequentially mapping the plurality of first symbols to a plurality of subcarriers for a first slot; And Sequentially mapping the plurality of second symbols to subcarriers subsequent to the subcarrier to which the plurality of first symbols are mapped among the plurality of subcarriers for the first slot. Method of transmission of the transmitter. The method of claim 1, A first spreading orthogonal sequence having a length of 2 among the spreading orthogonal sequences is: At least one of [1 1] and [1 -1] Method of transmission of the transmitter. A transmitter transmits feedback information through an uplink control channel. Modulating the feedback information into a plurality of first symbols through one of quadrature phase shift keying (QPSK) and quadrature amplitude modulation (4-QAM); Doubling the plurality of first symbols based on a spreading orthogonal sequence of length 2 to generate a plurality of second symbols; And Mapping the plurality of second symbols to a plurality of resource elements (REs) based on a mapping order in which the frequency axis comes first and the time axis comes later Transmission method of the transmitter comprising a. The method of claim 13, The plurality of REs includes a plurality of REs for a first slot and a plurality of REs for a second slot after the first slot, Mapping to the plurality of REs, Mapping a portion of the plurality of second symbols to a plurality of REs for a first time domain symbol among the plurality of REs for the first slot; And Mapping another portion of the plurality of second symbols to a plurality of REs for a second time domain symbol next to the first time domain symbol among a plurality of REs for the first slot Method of transmission of the transmitter. The method of claim 13, Mapping to the plurality of REs, Mapping the plurality of second symbols to the plurality of REs based on Equation 1 below; Method of transmission of the transmitter. [Equation 1]

(y _n () is the mapped symbols, n is the index,

= 6 or 5,

= 6, 5, or 4, i is the index of the subcarrier, s () is the plurality of first symbols,

Is one physical resource block (PRB) bandwidth,

Is the value of the cell-specific phase rotation, n _s is the slot number, l is the index of the time domain symbol,

= 2,

Is the spreading orthogonal sequence) The method of claim 13, The plurality of REs includes a plurality of first REs corresponding to PRBs for a first slot and a plurality of second REs corresponding to PRBs for a second slot next to the first slot, Mapping to the plurality of REs, Mapping at least one reference signal for the feedback information to a portion of the plurality of first REs; And Mapping a portion of the plurality of second symbols to a remainder of the plurality of first REs based on the mapping order. Method of transmission of the transmitter. The method of claim 13, The modulating step, Generating first information by adding cyclic redundancy check (CRC) information to the feedback information; Generating second information by applying tail biting convolutional channel coding (TBCC) and rate matching to the first information; Modulating the second information through QPSK to generate the plurality of first symbols; And Grouping the plurality of first symbols into a first symbol group mapped to a first slot and a second symbol group mapped to a second slot Method of transmission of the transmitter. A transmitter transmits feedback information through an uplink control channel. Generating first information by applying cyclic redundancy check (CRC) and tail biting convolutional channel coding (TBCC) to first feedback information larger than 22 bits of the feedback information; Generating a plurality of symbols by modulating the first information; And Mapping the plurality of symbols to a plurality of resource elements (REs) Transmission method of the transmitter comprising a. The method of claim 18, Mapping to the plurality of REs, Mapping the plurality of symbols to the plurality of REs based on Equation 1 below; Method of transmission of the transmitter. [Equation 1]

(

Are the mapped symbols,

Is an antenna port, n = 0,1, ..., 11, i = 0,1, ...,

-1, v = n mod 6, s () is the plurality of symbols,

Is one physical resource block (PRB) bandwidth,

Is the value of the cell-specific phase rotation, n _s is the slot number, and l is the index of the time domain symbol) The method of claim 18, The plurality of symbols includes a plurality of first symbols mapped to a first slot and a plurality of second symbols mapped to a second slot next to the first slot, Mapping to the plurality of REs, Applying phase rotation to the plurality of first symbols; Applying a cyclic shift to the phase rotated symbols; And Applying discrete Fourier transform (DFT) precoding to the cyclically shifted symbols Method of transmission of the transmitter.

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