WO2017008550A1 - Excess loop delay compensation circuit and method, storage medium and analog-to-digital converter - Google Patents

Abstract

An ELD compensation circuit is used to perform ELD compensation for the ELD time of a continuous time Δ-Σ analog-to-digital converter. The circuit comprises: a delay module (200) and a compensation module (201), wherein the delay module (200) is configured to select one delay time from a plurality of preset delay times, and output an own received signal in a delay manner on the basis of the selected delay time; and the compensation module (201) is configured to perform ELD compensation according to the signal output by the delay module (200) in a delay manner. Also disclosed are an ELD compensation method, a computer storage medium and a continuous time Δ-Σ analog-to-digital converter.

Description

Additional loop delay compensation circuit, method, storage medium and analog to digital converter Technical field

The present invention relates to the field of analog-to-digital converter design, and more particularly to an additional loop delay (ELD) compensation circuit, method, computer storage medium, and continuous-time delta-sigma analog-to-digital converter.

Background technique

In the field of wireless communication, continuous-time delta-sigma analog-to-digital converters have received increasing attention. Compared to discrete-time delta-sigma analog-to-digital converters, continuous-time delta-sigma analog-to-digital converters reduce the bandwidth requirements of the op amp, which in turn reduces the power consumption of the circuit. In addition, due to the inherent anti-aliasing characteristics of the continuous-time delta-sigma analog-to-digital converter and insensitivity to process variations, it is highly advantageous for use in radio frequency (RF) receivers.

1 is a schematic structural diagram of a continuous-time delta-sigma analog-to-digital converter in the prior art. As shown in FIG. 1, the continuous-time delta-sigma analog-to-digital converter includes: a quantizer 100, and a first-order digital-to-analog converter. The DAC1 to nth digital-to-analog converter DACn, the first-stage adder Σ1 to the n-th stage adder Σn, and the first-stage integrator S1 to the n-th stage integrator Sn, n in sequence are connected in series, wherein n is a natural number; The input end of the first stage integrator S1 is for receiving an analog signal that needs to be analog-to-digital converted, the input end of the quantizer 100 is connected to the output end of the nth stage integrator Sn, and the i-th digital-to-analog converter DACI is connected to the quantization. Between the output of the device 100 and the Si input of the i-th stage integrator, i takes 1 to n; the i-th digital-to-analog converter DACI is used to receive the quantizer output signal, and perform digital-to-analog conversion on the quantizer output signal. The digital signal generated after the analog conversion is fed back to the input end of the i-th stage integrator Si; the i-th adder Σi is used to sum the output signal of the i-th digital-to-analog converter DACI and the input signal of the i-th stage integrator Operation, the summed signal is input to the i-th stage integrator. Here, the digital signal quantized by the quantizer 100 is a digital signal finally outputted by the continuous-time delta-sigma analog-to-digital converter. number.

In an actual continuous time delta-sigma analog-to-digital converter, there is a delay time from the sampling instant of the quantizer 100 to the corresponding output of each digital-to-analog converter due to the limited switching speed of the MOS device. This delay time is called the ELD time, where the ELD time is expressed as . The ELD time may cause loss of dynamic range of the continuous-time delta-sigma analog-to-digital converter, and even affect the stability of the loop in the continuous-time delta-sigma analog-to-digital converter.

In the prior art, ELD compensation can be performed for ELD time. As shown in FIG. 1, the prior art ELD compensation scheme is: adding a post-stage adder Σ and a compensation circuit 101 for compensating the ELD time, and the input end of the compensation circuit 101 is connected to the output end of the quantizer 100, The output signal of the compensation circuit 101 is summed with the output signal of the nth stage integrator and sent to the input of the quantizer 100.

However, the above ELD compensation scheme has the following problems: ELD time is affected by various factors in the actual circuit, and it is difficult to accurately quantize, thereby affecting the effect of ELD compensation.

Summary of the invention

In order to solve the above technical problem, embodiments of the present invention are expected to provide an ELD compensation circuit, method, computer storage medium, and continuous-time delta-sigma analog-to-digital converter capable of flexibly performing ELD compensation on a continuous-time delta-sigma analog-to-digital converter. To meet the needs of a variety of application scenarios.

The technical solution of the present invention is implemented as follows:

An embodiment of the present invention provides an ELD compensation circuit for performing ELD compensation on an ELD time of a continuous-time delta-sigma analog-to-digital converter, where the circuit includes: a delay module and a compensation module;

The delay module is configured to select a delay time among a plurality of preset delay times, and delay outputting the signal received by itself according to the selected delay time;

The compensation module is configured to perform ELD compensation according to the delayed output signal of the delay module Reimbursement.

In the above solution, the continuous-time delta-sigma analog-to-digital converter includes a quantizer, a first-stage digital-to-analog converter DAC to an n-th DAC, and a first-stage integrator to an n-th integrator sequentially connected in series , n is a natural number; wherein, the i-th DAC is connected between the quantizer output and the i-th integrator input, i takes 1 to n;

The compensation module is configured to perform digital-to-analog conversion on the delayed output signal of the delay module, and feed the digital-to-analog conversion result to the input end of the n-th stage integrator in a differential form for the summation operation.

In the above solution, the compensation module is configured to perform digital-to-analog conversion on the delayed output signal of the delay module by multiplexing the n-th digital-to-analog converter of the continuous-time delta-sigma analog-to-digital converter.

In the above solution, the compensation module is configured to perform digital-to-analog conversion on the delayed output signal of the delay module according to the set ELD compensation coefficient, and send the digital-to-analog converted analog signal to the continuous time Δ in differential form. - The virtual location of the nth stage integrator of the Σ-analog converter.

In the above solution, the circuit further includes a delay phase locked loop DLL, and the DLL is configured to keep the delay time selected by the delay module unchanged.

In the above solution, the delay module is configured to receive an output signal of the quantizer of the continuous-time delta-sigma analog-to-digital converter, perform delay processing on the received signal, and send the delayed processed signal. To the compensation module; or,

The delay module is configured to receive an input clock signal of the continuous time delta-sigma analog-to-digital converter, perform delay processing on the received clock signal, and send the delayed processed clock signal to the continuous The clock signal input of the quantizer of the time Δ-Σ analog-to-digital converter.

Embodiments of the present invention also provide a continuous time delta-sigma analog-to-digital converter, including any of the ELD compensation circuits described above.

An embodiment of the present invention further provides an additional loop delay ELD compensation method, including:

Setting a delay module for the continuous time delta-sigma analog-to-digital converter, the delay module is preset in multiple Selecting a delay time in the delay time, and delaying the output of the signal received by itself according to the selected delay time;

ELD compensation is performed on the ELD time of the continuous time delta-sigma analog-to-digital converter according to the delayed output signal of the delay module.

In the above solution, the continuous-time delta-sigma analog-to-digital converter includes a quantizer, a first-stage digital-to-analog converter to an n-th digital-to-analog converter, and a first-stage integrator to an n-th stage that are sequentially connected in series Integral, n is a natural number; wherein, the i-th digital-to-analog converter is configured to receive the quantizer output signal, perform digital-to-analog conversion on the quantizer output signal, and feed back the digital signal generated by the digital-to-analog conversion to the i-th level integral Input of the device, i takes 1 to n;

Performing ELD compensation on the ELD time of the continuous time Δ-Σ analog-to-digital converter according to the delayed output signal of the delay module, including: performing digital-to-analog conversion on the delayed output signal of the delay module, and The digital-to-analog conversion result is fed back to the input of the n-th stage integrator in a differential form for the summation operation.

In the above solution, the digital-to-analog conversion of the delayed output signal of the delay module includes: multiplexing the delay by multiplexing the n-th digital-to-analog converter of the continuous-time delta-sigma analog-to-digital converter The signal of the module delay output is digital-to-analog converted.

An embodiment of the present invention provides a computer storage medium, where the computer storage medium stores a computer program for performing the ELD compensation method described above.

The ELD compensation circuit, the method, the computer storage medium and the continuous-time delta-sigma analog-to-digital converter according to the embodiment of the invention select a delay time among a plurality of preset delay times, and perform continuous time based on the delay time. The ELD compensation of the delta-sigma analog-to-digital converter makes it possible to flexibly perform ELD compensation on the continuous-time delta-sigma analog-to-digital converter to meet the needs of various application scenarios.

DRAWINGS

1 is a schematic structural diagram of a structure of a continuous-time delta-sigma analog-to-digital converter in the prior art;

2 is a schematic structural view of a first embodiment of an ELD compensation circuit of the present invention;

3 is a first specific structural diagram of a first embodiment of an ELD compensation circuit of the present invention;

4 is a schematic diagram of a first component structure of a delay module in a first embodiment of an ELD compensation circuit according to the present invention;

5 is a schematic diagram showing a second composition structure of a delay module in the first embodiment of the ELD compensation circuit of the present invention;

6 is a schematic structural diagram of a delay phase locked loop in a first embodiment of an ELD compensation circuit according to the present invention;

Figure 7 is a block diagram showing the signal processing of the first embodiment of the ELD compensation circuit of the present invention;

8 is a schematic diagram showing a second specific structural structure of a first embodiment of an ELD compensation circuit according to the present invention;

Figure 9 is a schematic diagram of the effects of various embodiments of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings.

First embodiment

Embodiments of the present invention provide an ELD compensation circuit for ELD compensation of ELD time of a continuous time delta-sigma analog-to-digital converter. As shown in FIG. 1, the continuous-time delta-sigma analog-to-digital converter includes a quantizer 100, a first-stage digital-to-analog converter DAC1 to an n-th digital-to-analog converter DACn, and a first-stage adder Σ1 to an n-th adder. Σn, and the first-stage integrator S1 to the n-th stage integrator Sn, n in sequence are connected in series, and n is a natural number.

2 is a schematic structural diagram of a first embodiment of an ELD compensation circuit according to the present invention. As shown in FIG. 2, the circuit includes a delay module 200 and a compensation module 201.

The first embodiment of the ELD compensation circuit of the present invention will be described below in two cases.

In the first case, the delay module 200 is disposed between the quantizer 100 and the compensation module 201.

3 is a first specific structural diagram of the first embodiment of the ELD compensation circuit of the present invention. As shown in FIG. 3, the ELD compensation circuit is configured to perform ELD compensation on the ELD time of the continuous-time delta-sigma analog-to-digital converter; The time Δ-Σ analog-to-digital converter includes a first-stage digital-to-analog converter DAC1 to an n-th digital-to-analog converter DACn, where each stage of the digital-to-analog converter has a differential output function, that is, each stage of the digital-to-analog converter Each has a Vout+ terminal and a Vout- terminal, wherein the Vout+ terminal of each stage of the digital-to-analog converter is used to output a first differential output signal, and the Vout- terminal of each stage of the digital-to-analog converter is used to output a second differential output signal.

Here, the continuous-time delta-sigma analog-to-digital converter further includes a first-stage integrator S1 to an n-th integrator Sn, wherein the i-th stage integrator Si includes an i-th stage fully differential amplifier OPi and two ith capacitors Ci And two ith resistors Ri, i take 1 to n; an ith capacitor Ci is connected in series between the positive input terminal and the negative output terminal of the i-th full differential amplifier OPi, and the negative of the i-th full differential amplifier OPi There is another ith capacitor Ci connected in series between the input terminal and the positive output terminal, and an ith resistor Ri is connected to the positive input terminal of the i-th stage fully differential amplifier OPi, and the negative input terminal of the ith-stage fully differential amplifier OPi is connected to another An ith resistor Ri; a fully differential amplifier has various implementations, but is not part of the present invention and will not be described in detail herein.

Here, the continuous-time delta-sigma analog-to-digital converter is for receiving an analog signal in a differential form, and the analog signal of the differential form is input to the first resistor R1 of the first-stage integrator.

Here, the continuous time delta-sigma analog-to-digital converter includes a quantizer 100 configured to receive a differential output signal of the nth stage integrator, and the digital signal quantized by the quantizer is sent to the delay module, quantized The quantized digital signal is the digital signal finally output by the continuous-time delta-sigma analog-to-digital converter.

The delay module 200 is disposed between the quantizer 100 and the compensation module 201, configured to select a delay time among a plurality of preset delay times, and delay the output of the signal received by itself according to the selected delay time. .

Specifically, the delay module 200 is configured to receive the continuous time delta-sigma analog-to-digital converter The output signal of the quantizer performs delay processing on the received signal, and sends the delayed processed signal to the compensation module and the first-stage digital-to-analog converter DAC1 to the n-th digital-to-analog converter DACn. Input. Obviously, the delay module can delay outputting the quantized signal compared to the case where the delay module is not set.

Here, according to the application scenario, a delay time may be selected in a preset plurality of delay times; further, the delay module may adjust the delay time under the control of the external control signal, thereby flexibly selecting the delay time.

The following two implementations of the delay module are described.

4 is a schematic structural diagram of a first implementation manner of a delay module in the first embodiment of the ELD compensation circuit of the present invention. As shown in FIG. 4, the delay module includes: a decoder 400 and a first delay unit. D1 to Nth delay unit DN, N is a natural number greater than 1, each delay unit is used for delay output of the input signal, and the delay values of each delay unit are different from each other. IN is the input signal of the delay module, OUT represents the output signal of the delay module; the input signals of the delay module are respectively sent to the first delay unit D1 to the Nth delay unit DN; ctrl<M:1> The input signal of the decoder is used to control the output value of the decoder; the output of the decoder 400 is connected to the input terminals of the first delay unit D1 to the Nth delay unit DN, respectively.

Here, the decoder can select a delay unit among the N delay units by its own output value, and the input signal of the delay module is output to the next stage circuit through the selected delay unit, for example, selected. The delay unit is the kth delay unit, 1≤k≤N; that means that the input signal IN of the delay module is only delayed by the kth delay unit.

5 is a schematic structural diagram of a second implementation manner of a delay module in the first embodiment of the ELD compensation circuit of the present invention. As shown in FIG. 5, the delay module includes: a decoder 500 and a first delay unit. The D1 to Nth delay unit DN, and the first switch S1 to the Nth switch SN, N are natural numbers greater than 1, wherein the jth switch is connected in parallel with the jth delay unit Dj, and j takes 1 to N. Each delay unit is configured to delay output the input signal, and the delay values of the respective delay units are not mutually the same. IN is the input signal of the delay module, OUT represents the output signal of the delay module; ctrl<M:1> is the input signal of the decoder, configured to control the output value of the decoder; the decoder 500 is configured to separately control The on and off state of each switch.

Here, the decoder can control a switch to be in an off state according to its own output value, and control other switches to be in an on state; thus, the delay unit of the switch in the off state is connected to the circuit, and the delay module The input signal is output to the next stage circuit through the selected delay unit. For example, the switch in the off state is the kth switch, 1≤k≤N; that means that the input signal IN of the delay module only passes the first The k delay unit performs delay processing.

Since the delay module is affected by external factors such as process deviation, temperature, voltage, etc., the delay time selected by the delay module may change, that is, it is different from the delay time selected under ideal conditions. In order to solve the problem, a Delay-Locked Loop (DLL) 301 may be disposed in the ELD compensation circuit of the embodiment of the present invention. As shown in FIG. 3, the delay-locked loop 301 is connected to the delay module 200, and configured as The delay time selected by the delay module is kept constant, and precise control of the selected delay time is achieved.

6 is a schematic structural diagram of a delay phase-locked loop in a first embodiment of an ELD compensation circuit according to the present invention. As shown in FIG. 6, the delay phase-locked loop includes a phase frequency detector (PFD) 600 and a charge pump. (Charge Pump) 601, Loop Filter (LPF) 602 and N+1 delay unit 603, wherein the phase frequency detector 600, the charge pump 601 and the loop filter 602 are sequentially connected, and the loop The output terminal Vctrl of the filter 602 is respectively connected to the power supply of the N+1th delay unit 603 and the power supply of the N delay units in the delay module, where the N+1th delay unit 603 and the delay module are Any one of the delay units has exactly the same circuit structure and implementation. The phase frequency detector 600 is configured to receive a reference clock and a feedback clock from the loop filter, and send a corresponding signal to the charge pump by comparing the reference clock with the feedback clock; here, the phase frequency detector 600, the charge pump 601, and Loop filter 602 has a variety of existing implementations and will not be described in detail herein.

It should be noted that FIG. 6 only exemplarily illustrates an implementation manner of a delay phase-locked loop. In the embodiment of the present invention, other implementation manners of the delay-locked loop may be adopted according to actual conditions, which are not described herein.

Here, for the delay module, different delay times can be selected according to the application scenario and the performance index of the nth stage integrator.

The compensation module 201 is configured to perform ELD compensation according to the delayed output signal of the delay module.

Specifically, the compensation module 201 is configured to perform digital-to-analog conversion on the delayed output signal of the delay module, and feed back the digital-to-analog conversion result to the n-th stage integrator in a differential form, and convert the differential-form digital-to-analog conversion result. A summation operation is performed with the input of the nth stage integrator, where the summation operation can be implemented by an adder.

表示连续时间Δ-Σ模数转换器的ELD时间。Figure 7 is a block diagram showing the signal processing of the first embodiment of the ELD compensation circuit of the present invention. As shown in Figure 7, x(t) represents an analog signal received by a continuous-time delta-sigma analog-to-digital converter, and k _i s ^-1 represents continuous The transfer function of the i-th stage integrator of the time Δ-Σ analog-to-digital converter, the output signal of the n-th stage integrator is quantized by the quantizer and becomes the signal y[n],

Indicates the ELD time of the continuous-time delta-sigma analog-to-digital converter.

Here, the ELD compensation coefficient is k, and the compensation module can perform digital-to-analog conversion on the delayed output signal of the delay module based on the set ELD compensation coefficient. After performing digital-to-analog conversion on the delayed output signal of the delay module, summing the digital-to-analog converted analog signal with the output of the n-th digital-to-analog converter of the continuous-time Δ-Σ analog-to-digital converter to generate The feedback signal is input to the input of the nth stage integrator to perform the summation operation again.

Here, the signal processed by the delay module is also sent to the input of the first-stage digital-to-analog converter to the n-th digital-to-analog converter; each stage of the digital-to-analog converter is processed by the input delay module. The signal is digital-to-analog converted, and the analog signal output from each stage of the digital-to-analog converter is sent to the input of the stage integrator.

所示的延时单元，在进行数模转换；补偿模块中两次数模转换后生成的模拟信号作差，生成差分形式的模拟信号。这里，补偿模块中的数模转换过程可通过两个数模转换器实现。The compensation module is configured to perform ELD compensation according to the signal processed by the delay module. Here, the analog signal output by the compensation module may be an analog signal in a differential form. Specifically, there are two differential digital-to-analog converters in the compensation module. In the compensation module, one signal directly performs digital-to-analog conversion, and the other signal passes through FIG.

The delay unit shown is performing digital-to-analog conversion; the analog signal generated by the two-times mode conversion in the compensation module is made to generate an analog signal in a differential form. Here, the digital-to-analog conversion process in the compensation module can be implemented by two digital-to-analog converters.

Here, the transfer function of the ELD compensation can be expressed as TF(z), TF(z)=1-z ^-τ/Ts (τ≤Ts-τ _eld ), where z represents an independent variable and Ts represents a continuous time Δ-Σ The sampling period of the analog-to-digital converter, it should be noted that if τ ≤ Ts - τ _eld , the ELD compensation cannot be realized by the single proportional coefficient k shown in FIG. 7 .

In an embodiment, the compensation module 201 is configured to count the delayed output signals of the delay module by multiplexing the n-th digital-to-analog converter of the continuous-time delta-sigma analog-to-digital converter. Mode conversion. That is to say, the signals processed by the delay module are respectively sent to the first-stage digital-to-analog converter to the n-1th digital-to-analog converter and the compensation module; that is, two digital-modules in the compensation module The converter is multiplexed with the nth stage digital-to-analog converter. At this time, the n-th digital-to-analog converter can be omitted.

The structure inside the compensation module will be further described below with reference to FIG.

As shown in FIG. 3, the compensation module 201 includes a D flip-flop (Trigger DEF) 302, an nth digital-to-analog converter DACn, and an n+1th digital-to-analog converter 303, wherein the nth digital-to-analog converter DACn and the nth The +1 digital-to-analog converter 303 is respectively used to implement a two-times analog conversion process in the compensation module; the D flip-flop 302 is used to implement a delay processing process in the compensation module.

It should be noted that the n+1th digital-to-analog converter 303 has the same internal structure as the n-th digital-to-analog converter DACn, and the Vout+ and n-th digital-to-analog conversion of the n+1th digital-to-analog converter 303 The common node of the Vout- terminal of the DACn is connected to the positive input terminal of the n-th full-differential amplifier OPn, and the Vout-end of the n+1-th digital-to-analog converter 303 and the common node of the Vout+ terminal of the n-th digital-to-analog converter DACn are connected. The negative input of the nth full differential amplifier OPn.

Here, the compensation module 201 in FIG. 3 can implement an ELD feedback path in the form of a differentiator. The phases of the control clocks of the nth digital-to-analog converter DACn and the n+1th digital-to-analog converter 303 are 180 degrees out of phase, and the control clock of the D flip-flop 302 is the same as the control clock of the nth digital-to-analog converter DACn. If k represents the ELD compensation coefficient when the ELD compensation circuit is connected between the input end and the output end of the quantizer, the ELD compensation coefficient k' when the compensation module of the embodiment of the present invention is connected to the input end of the last stage integrator is :k'=(k/c)×(1-τ _eld /Ts) ^-1 , where c represents a known constant and is a constant related to the output swing of the last stage integrator, which can be performed on a case-by-case basis. The ELD compensation coefficient k' is realized by the current signals output by the nth digital-to-analog converter DACn and the n+1th digital-to-analog converter 303, which is due to the nth digital-to-analog converter DACn and the n+1th digital-to-analog conversion. The 303 can be used to output a plurality of different sized current signals.

It can be seen that when the compensation module multiplexes the nth-stage digital-to-analog converter of the continuous-time Δ-Σ analog-to-digital converter, the n-th stage integrator of the continuous-time Δ-Σ analog-to-digital converter is included in the ELD compensation In the loop, the extra delay time due to the limited bandwidth of the nth stage integrator of the continuous-time delta-sigma analog-to-digital converter will be counted in the ELD time. Therefore, when the delay module selects the delay time, the nth The extra delay time due to the finite bandwidth of the stage integrator is taken into account, thus reducing the performance requirements of the continuous-time delta-sigma analog-to-digital converter for the n-stage integrator and maintaining the stability of the continuous-time delta-sigma analog-to-digital converter. And reduce the design difficulty and power consumption of the ELD compensation circuit.

In an embodiment, the output of the compensation module can be connected to the virtual location (V _p , V _n ) of the nth stage integrator, so that the summation process of the analog signal output by the compensation module at the input end of the nth stage integrator can be In the virtual location of the nth stage integrator, it is clear that there is no need to set up an additional adder circuit, thereby reducing the area and power consumption of the ELD compensation circuit.

In the second case, the delay module 200 is disposed at the clock signal input end of the quantizer 100.

8 is a second specific structural diagram of the first embodiment of the ELD compensation circuit of the present invention. As shown in FIG. 8, the second case of the first embodiment of the ELD compensation circuit of the present invention is substantially the same as the first case. The difference is that the delay module 200 is disposed at the clock signal input end of the quantizer 100.

Here, the delay module 200 is configured to receive an input clock signal of the continuous-time delta-sigma analog-to-digital converter, perform delay processing on the received clock signal, and send the delayed-processed clock signal to the The clock signal input of the quantizer. In this way, the quantizer quantizes the input signal based on the clock signal after the delay processing, and the quantized signal can be delayed output compared to the case where the delay module is not provided.

Second embodiment

Embodiments of the present invention also provide a continuous time delta-sigma analog-to-digital converter including any of the ELD compensation circuits of the first embodiment of the present invention.

Third embodiment

The ELD compensation circuit is further provided by the embodiment of the present invention, and the method further includes:

The delay module is set for the continuous time delta-sigma analog-to-digital converter. The delay module selects one delay time among the preset multiple delay times, and delays the output of the signal received by itself according to the selected delay time.

ELD compensation is performed on the ELD time of the continuous time delta-sigma analog-to-digital converter according to the delayed output signal of the delay module.

Here, the continuous-time delta-sigma analog-to-digital converter includes a quantizer, a first-stage digital-to-analog converter to an n-th digital-to-analog converter, and a first-stage integrator to an n-th integrator sequentially connected in series , n is a natural number; wherein, the i-th digital-to-analog converter is configured to receive the quantizer output signal, perform digital-to-analog conversion on the quantizer output signal, and feed back the digital signal generated by the digital-to-analog conversion to the i-th stage integrator At the input, i takes 1 to n.

In an embodiment, the ELD time of the ELD time of the continuous time Δ-Σ analog-to-digital converter is ELD compensated according to the delayed output signal of the delay module, including: a delayed output signal to the delay module The digital-to-analog conversion is performed, and the digital-to-analog conversion result is fed back to the n-th stage integrator in a differential form, and the differential-form digital-to-analog conversion result is summed with the input end of the n-th stage integrator.

In another embodiment, the digital-to-analog conversion of the delayed output signal of the delay module includes: multiplexing the n-th digital-to-analog converter of the continuous-time delta-sigma analog-to-digital converter The signal outputted by the delay module delay is digital-to-analog converted.

The embodiment of the invention further describes a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used in the ELD compensation method described in the third embodiment.

FIG. 9 is a schematic diagram of the effects of various embodiments of the present invention. As shown in FIG. 9, the beneficial effects of various embodiments of the present invention are illustrated in three aspects. First, with respect to the existing ELD compensation mode shown in FIG. 1, the present invention advances the ELD compensation path to the input end of the last stage integrator, and sets the digital-to-analog converter in the compensation module to the difference form; Second, according to the specific application requirements, the delay value is flexibly selected by the delay module to make the ELD compensation flexible, reduce the performance requirement of the ELD compensation circuit for the last stage integrator, and further reduce the design difficulty and work of the ELD compensation circuit. Consumption; third, the delay value of the delay module is controlled by the DLL, thereby achieving accurate ELD compensation.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. The work specified in one or more blocks of a flow or a flow and/or a block diagram of a flowchart Able device.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Industrial applicability

In the embodiment of the present invention, one of the preset plurality of delay times is selected, and the ELD compensation of the continuous time Δ-Σ analog-to-digital converter is performed based on the delay time, so that the continuous time Δ- can be flexibly The Σ-analog converter performs ELD compensation to meet the needs of various application scenarios.

Claims (11)

An additional loop delay ELD compensation circuit for performing ELD compensation on an ELD time of a continuous time delta-sigma analog-to-digital converter, the circuit comprising: a delay module and a compensation module; wherein The delay module is configured to select a delay time among a plurality of preset delay times, and delay outputting the signal received by itself according to the selected delay time; The compensation module is configured to perform ELD compensation according to the delayed output signal of the delay module. The circuit of claim 1 wherein said continuous time delta-sigma analog to digital converter comprises a quantizer, a first stage digital to analog converter DAC to an nth stage DAC, and a first stage integration connected in series in series. To the nth stage integrator, n is a natural number; wherein the i-th DAC is connected between the quantizer output and the i-th integrator input, i takes 1 to n; The compensation module is configured to perform digital-to-analog conversion on the delayed output signal of the delay module, and feed the digital-to-analog conversion result to the input end of the n-th stage integrator in a differential form for the summation operation. The circuit of claim 2, wherein the compensation module is configured to delay output of the delay module by multiplexing an nth-stage digital-to-analog converter of the continuous-time delta-sigma analog-to-digital converter The signal is digital-to-analog converted. The circuit according to claim 3, wherein the compensation module is configured to perform digital-to-analog conversion on the delayed output signal of the delay module according to the set ELD compensation coefficient, and to convert the digital-to-analog converted analog signal into a differential form. A virtual location sent to the nth stage integrator of the continuous time delta-sigma analog to digital converter. The circuit of claim 1 wherein said circuit further comprises a delay phase locked loop DLL, said DLL being configured to maintain a selected delay time of said delay module. The circuit according to any one of claims 1 to 5, wherein the delay module is configured to receive an output signal of a quantizer of the continuous-time delta-sigma analog-to-digital converter, for receiving The signal is delayed, and the delayed signal is sent to the compensation module; or, The delay module is configured to receive an input clock signal of the continuous time delta-sigma analog-to-digital converter, perform delay processing on the received clock signal, and send the delayed processed clock signal to the continuous The clock signal input of the quantizer of the time Δ-Σ analog-to-digital converter. A continuous time delta-sigma analog-to-digital converter comprising the ELD compensation circuit of any one of claims 1 to 6. An additional loop delay ELD compensation method, the method comprising: The delay module is set for the continuous time delta-sigma analog-to-digital converter, and the delay module selects one delay time among the preset multiple delay times, and delays the output of the signal received by itself according to the selected delay time; ELD compensation is performed on the ELD time of the continuous time delta-sigma analog-to-digital converter according to the delayed output signal of the delay module. The method according to claim 8, wherein said continuous time delta-sigma analog-to-digital converter comprises a quantizer, a first-stage digital-to-analog converter to an n-th digital-to-analog converter, and a first in series connection From the integrator to the nth integrator, n is a natural number; wherein, the i-th digital-to-analog converter is used to receive the quantizer output signal, perform digital-to-analog conversion on the quantizer output signal, and convert the digital-to-analog-generated number The signal is fed back to the input of the i-th stage integrator, i takes 1 to n; Performing ELD compensation on the ELD time of the continuous time Δ-Σ analog-to-digital converter according to the delayed output signal of the delay module, including: performing digital-to-analog conversion on the delayed output signal of the delay module, and The digital-to-analog conversion result is fed back to the input of the n-th stage integrator in a differential form for the summation operation. The method according to claim 9, wherein said digital-to-analog conversion of said delay-output module delayed output signal comprises: multiplexing said n-th digital-to-analog conversion of said continuous-time delta-sigma analog-to-digital converter And performing digital-to-analog conversion on the delayed output signal of the delay module. A computer storage medium storing computer executable in the computer storage medium A line of instructions for executing the method of any one of claims 8 to 10.

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