WO2017000274A1

WO2017000274A1 - Devices and methods for multi-clock-domain testing

Info

Publication number: WO2017000274A1
Application number: PCT/CN2015/083054
Authority: WO
Inventors: Shuo-Fen Kuo; Jian-Guo Ren
Original assignee: MediaTek Inc
Current assignee: MediaTek Inc
Priority date: 2015-07-01
Filing date: 2015-07-01
Publication date: 2017-01-05
Anticipated expiration: 2018-01-01

Abstract

A device for testing a digital circuit including a first path operating in a first frequency and a second path operating in a second frequency includes a functional circuit, a clock-dividing circuit, an on-chip clocking controller, and a first integrated clock-gating cell. The functional circuit generates a first dividing factor. The clock-dividing circuit generates an internal frequency by dividing a system frequency by a fixed dividing factor when a selection signal is in a first selection state. The on-chip clocking controller selects the internal frequency or an external frequency to be the second frequency. The first integrated clock-gating cell generates the first frequency by dividing the second frequency by the first dividing factor. When at-speed testing the intra-domain first path and the inter-domain second-to-first path, the first and second frequencies are the system frequency divided by the fixed dividing factor.

Description

DEVICES AND METHODS FOR MULTI-CLOCK-DOMAIN TESTING

TECHNICAL FIELD

The disclosure relates generally to devices and methods for providing for multi-clock-domain frequencies, and more particularly it relates to devices and methods for intra-domain and inter-domain at-speed testing of a digital circuit.

BACKGROUND

An Automatic Test Pattern Generator (ATPG) is a software design tool that simulates the overall functionality of the design or individual circuits within the design of an integrated circuit and generates test vectors for testing the overall functionality of the design. Through the use of these at-speed test vectors, an Automatic Testing Equipment (ATE) may provide a particular degree of fault coverage or fault simulation for the circuitry in the product. Specifically, automatic test pattern generation (ATPG) techniques may provide test patterns for stuck-at faults, transition faults and path delay faults. Conventionally, these test vectors are provided in a computer readable file to the ATE or other testers. The ATE is used in a manufacturing environment to test the die at wafer sort and in packaged tests. During wafer-level testing of a die, test signals are provided through input or input/output (I/O) bond pads on the die, and the test results are monitored on output or I/O bond pads.

Testing of digital systems, such as the core logic of an integrated circuit, is typically performed by loading a test pattern or stimulus into scannable memory elements in the system, launching the test data into the system, operating the system in normal mode for one or more clock cycles of the system clock, capturing the response of the system to the test stimulus, unloading the test response from the system, and then comparing the response to the response which should have been obtained if the system was operating according to design.

To improve test coverage of individual circuits, DFT tools have been developed to embed test circuitry into the SoC. For example, Built-In Self-Test (BIST) circuitry may be embedded in the IC design to test individual circuit blocks. BIST circuitry is particularly useful for testing circuit blocks that are not readily accessible through the bond pads of the device under test (DUT) . Automated DFT tools that generate BIST circuitry, such as memory BIST for testing memory blocks and logic BIST for testing logic blocks, are well known. External I/Os directly receive the results of tests conducted by BIST circuitry. In the alternative, external I/Os receive these results indirectly through boundary scan circuitry embedded in the design. Additional internal embedded test circuitry such as scan chain circuitry may also be added to the design to increase the internal testability of internal sequential designs.

This separate embedded test circuitry requires input and output ports that are separate from the input and output ports of the programmed functions. During normal operations, the functional circuitry operates. In the alternative, during the testing mode of operations, a separate set of test circuitry using the test inputs and outputs are used. Each core and sub-core embedded on a SoC includes its own test input and output ports and needs to be tested individually, without interference from adjacent cores. Wrapper cell is the circuitry attached to the functional elements of a core to provide paths for test data to flow. The test ports are part of the wrapper cell. It generally includes a flip-flop and a multiplexer, and is able to function in a functional mode and a test mode. In the functional mode, the wrapper cell is transparent and normal functional signals are passed through the multiplexer to the functional core. In the test mode, the wrapper cell changes the input signal causing the test input to be passed through the multiplexer.

Scan testing is implemented by chaining several wrapper cells together in a chip register in order to scan test data in and out of the circuit. There are many different schemes for scan testing, but the predominant method is the monolithic scan path approach where the scan elements, such as the wrapper cell and scan chains, are connected in a straight path and serial manner.

Scan-in ports may connect directly to scan-in terminals for each core. This makes it possible to select specific internal scan chains or subsets of internal scan chains, however, this is difficult to implement because the total number of available scan ports at the integrated circuit chip boundary are typically exceeded by the total number of scan paths requiring access to these ports.

Moreover, difficulties arise in systems having multiple clock domains when the clock sources differ from the test clock signal used to perform the test, when these domains have different clock rates, and/or when signals cross the boundary between these clock domains have different clock frequencies. More particularly, it is not uncommon for a SoC integrated circuit (IC) to include several digital modules having a variety of clocking domains and clock frequencies. Since the elements in one domain operate at a different frequency from that of other domains in the system, special provisions must be made during testing to ensure that signals traversing clock domains are synchronized. Otherwise, the test response from the system will not be repeatable and test results will be unreliable.

In order to detect speed-related defects in an advanced process node, an on-chip clocking (OCC) controller, which is configured to generate at least 2 pulses for at-speed testing, is generally used. If there are many frequency domains in a design, the design needs to insert multi-OCCs by each frequency domain. Since it is difficult to synchronize the phase among frequency domains when multi-OCCs are inserted by each frequency domain, the paths between different frequency domains or different phases can’ t be tested.

Even though a synchronization signal between 2 OCCs could be adopted for synchronization, the path of the synchronization signal should be as short as possible to minimize the delay, and the delay is not under the sustainable level otherwise. It makes the layout of the path of the synchronization signal and the 2 OCCs become more difficult. In addition, the larger the multiplier of a first frequency to a second frequency is, the more clock cycles are stored in the Automatic Testing Equipment (ATE) , and the larger the capability of the ATE required for testing. Recently, the intra-domain at-speed testing and the inter-domain at-speed testing are separated into two parts to mitigate the loading of the ATE and to lower the storing requirement of the ATE.

The present invention is directed to overcoming, or at least reducing, the effects of one or more of the problems set forth above.

SUMMARY

To solve the aforementioned problems, the invention provides a multi-clock generating device and method for mitigating the loading of the ATE and allowing intra-domain and inter-domain at-speed testing to be accomplished in a serial sequence.

In an embodiment, a multi-clock generating device for testing a digital circuit which comprises a first path operating in a first frequency of a first clock and a second path operating in a second frequency of a second clock comprises a functional circuit, a clock-dividing circuit, an on-chip clocking controller, and a first integrated clock-gating cell. The functional circuit generates a first dividing signal with a first dividing factor. The clock-dividing circuit generates an internal clock with an internal frequency by a system clock with a system frequency. The internal frequency is equal to the system frequency divided by a fixed dividing factor when a selection signal is in a first selection state. The on-chip clocking controller selects one of the internal clock and an external clock from an automatic test equipment to be the second clock. The first integrated clock-gating cell generates the first clock with the first frequency by dividing the second frequency by the first dividing factor, wherein when at-speed testing the intra-domain first path and the inter-domain second-to-first path, the first and second frequencies are equal to the system frequency divided by the fixed dividing factor.

In an embodiment of the multi-clock generating device, when at-speed testing the intra-domain first path and the inter-domain second-to-first path, a scan-mode signal is in a second scan-mode state, an OCC-mode signal is in a second OCC-mode state, and a frequency-controlled register is in a second frequency-controlled state.

In an embodiment of the multi-clock generating device, when at-speed testing the intra-domain second path and the inter-domain first-to-second path, the selection signal is in a second selection state and the internal frequency is equal to the system frequency.

In an embodiment of the multi-clock generating device, when at-speed testing the intra-domain second path and the inter-domain first-to-second path, the scan-mode signal is in the second scan-mode state, the OCC-mode signal is in the second OCC-mode state, and the frequency-controlled register is in a first frequency-controlled state.

In an embodiment of the multi-clock generating device, the functional circuit comprises a configurable frequency divider and a first mux. The configurable frequency divider generates a configurable dividing signal with a configurable dividing factor, wherein when the OCC-mode signal is in the second OCC-mode state and the frequency-controlled register is in the second frequency-controlled state, the configurable dividing factor is a positive integer not less than 2, and the configurable dividing factor is 1 otherwise. The first mux selects the configurable dividing signal to be the first dividing signal when the scan-mode signal is in the second scan-mode state, and selects the fixed dividing factor to be the first dividing signal when the scan-mode signal is in a first scan-mode state.

In an embodiment of the multi-clock generating device, the configurable frequency divider comprises a first combinational logic circuit and a configurable counter. The first combinational logic circuit generates a blocking signal in a second blocking state when the OCC-mode signal is in the second OCC-mode state and the frequency-controlled register is in the second frequency-controlled state, and generates the blocking signal in a first blocking state otherwise. The configurable counter counts a number of pulses on the system clock according to the blocking signal and generates a pulse on the configurable dividing signal when the number is equal to the configurable dividing factor, wherein when the blocking signal is in the second blocking state, the configurable dividing factor is a positive integer not less than 2.

In an embodiment of the multi-clock generating device, the clock-dividing circuit comprises a second combinational logic circuit, a fixed frequency divider, a second mux, and a second integrated clock-gating cell. The second combinational logic circuit generates the selection signal in a second selection state when either the OCC-mode signal is in a first OCC-mode state or the frequency-controlled register is in the second frequency-controlled state, and generates the selection signal in a first selection state otherwise. The fixed frequency divider generates a fixed dividing signal with the fixed dividing factor by the system clock. The second mux selects the fixed dividing signal to be a second dividing signal with a second dividing factor when the selection signal is in the first selection state, and selects a keep signal to be the second dividing signal when the selection signal is in the second selection state, wherein the second dividing factor is equal to 1 when the keep signal is selected. The second integrated clock-gating cell generates an internal clock with an internal frequency by dividing the system frequency by the second dividing signal.

In an embodiment of the multi-clock generating device, the fixed frequency divider comprises a fixed counter. The fixed counter counts a number of pulses on the system clock and generates a pulse on the fixed dividing signal when the number is equal to the fixed dividing factor.

In an embodiment of the multi-clock generating device, when the scan-mode signal is in the second scan-mode state and the OCC-mode signal is in the first OCC-mode state, the on-chip clocking controller selects the external clock to be the second clock for scan testing the first and second paths, and the first clock is equal to the external clock.

In an embodiment of the multi-clock generating device, when the scan-mode signal is in the first scan-mode state, the digital circuit operates in a normal operation mode, the on-chip clocking controller selects the internal clock to be the second clock, and the first integrated clock-gating cell generates the first frequency by dividing the second frequency by the first dividing factor.

In an embodiment, a method for testing a digital circuit, which comprises a first path operating in a first frequency of a first clock and a second path operating in a second frequency of a second clock, comprises: generating a first dividing signal with a first factor； generating an internal clock with an internal frequency by a system clock with a system frequency, wherein the internal frequency is equal to the system frequency divided by a fixed dividing factor when a selection signal is in a first selection state； selecting, by an on-chip clocking controller, one of the internal clock and an external clock from an automatic test equipment to be the second clock； and generating, by a first integrated clock-gating cell, the first clock with the first frequency by dividing the second frequency by the first dividing factor, wherein when at-speed testing the intra-domain first path and the inter-domain second-to-first path, the first and second frequencies are equal to the system frequency divided by the fixed dividing factor.

In an embodiment of the multi-clock generating method, when at-speed testing the intra-domain first path and the inter-domain second-to-first path, a scan-mode signal is in a second scan-mode state, an OCC-mode signal is in a second OCC-mode state, and a frequency-controlled register is in a second frequency-controlled state.

In an embodiment of the multi-clock generating method, when at-speed testing the intra-domain second path and the inter-domain first-to-second path, the selection signal is in a second selection state and the internal frequency is equal to the system frequency.

In an embodiment of the multi-clock generating method, when at-speed testing the intra-domain second path and the inter-domain first-to-second path, the scan-mode signal is in the second scan-mode state, the OCC-mode signal is in the second OCC-mode state, and the frequency-controlled register is in a first frequency-controlled state.

In an embodiment of the multi-clock generating method, the generating the first dividing signal step further comprises: generating a configurable dividing signal with a configurable dividing factor, wherein when the OCC-mode signal is in the second OCC-mode state and the frequency-controlled register is in the second frequency-controlled state, the configurable dividing factor is a positive integer not less than 2, and the configurable dividing factor is 1 otherwise； selecting the configurable dividing signal to be the first dividing signal when the scan-mode signal is in the second scan-mode state； and selecting the fixed dividing factor to be the first dividing signal when the scan-mode signal is in a first scan-mode state.

In an embodiment of the multi-clock generating method, the step of generating the configurable dividing signal also comprises: generating a blocking signal in a second blocking state when the OCC-mode signal is in the second OCC-mode state and the frequency-controlled register is in the second frequency-controlled state； generating the blocking signal in a first blocking state otherwise； and counting a number of pulses on the system clock according to the blocking signal and generating a pulse on the configurable dividing signal when the number is equal to the configurable dividing factor, wherein when the blocking signal is in the second blocking state, the configurable dividing factor is a positive integer not less than 2.

In an embodiment of the multi-clock generating method, the step of generating the internal clock further comprises: generating the selection signal in a second selection state when either the OCC-mode signal is in a first OCC-mode state or the frequency-controlled register is in the second frequency-controlled state； generating the selection signal in a first selection state otherwise； generating a fixed dividing signal with the fixed dividing factor by the system clock； selecting the fixed dividing signal to be a second dividing signal with a second dividing factor when the selection signal is in the first selection state； selecting a keep signal to be the second dividing signal when the selection signal is in the second selection state, wherein the second dividing factor is equal to 1 when the keep signal is selected； and generating an internal clock with an internal frequency equal to the system frequency divided by the second dividing signal.

In an embodiment of the multi-clock generating method, the step of generating the fixed dividing signal also comprises: counting a number of pulses on the system clock； and generating a pulse on the fixed dividing signal when the number is equal to the fixed dividing factor.

In an embodiment of the multi-clock generating method, when the scan-mode signal is in the second scan-mode state and the OCC-mode signal is in the first OCC-mode state, the first clock and the second clock are equal to the external clock for scan testing the first and second paths.

In an embodiment of the multi-clock generating method, when the scan-mode signal is in a first scan-mode state, the digital circuit operates in a normal operation mode, the internal clock is selected to be the second clock, and the first frequency is the second frequency divided by the first dividing factor by the first integrated clock-gating cell.

In an embodiment, a multi-clock generating device for testing a digital circuit comprising a first path operating in a first frequency of a first clock and a second path operating in a second frequency of a second clock comprises a functional circuit, an on-chip clocking controller, a first integrated clock-gating cell, a second integrated clock-gating cell, and a second mux. The functional circuit generates a first dividing signal with a first dividing factor. The on-chip clocking controller selects one of an internal clock with an internal frequency and an external clock from an automatic test equipment to be the second clock. The first integrated clock-gating cell generates the first clock with the first frequency by dividing the second frequency by the first dividing factor. The second integrated clock-gating cell generates the internal clock by dividing the system frequency by a second dividing signal with a second dividing factor. The second mux selects a fixed dividing signal with a fixed dividing factor or a keep signal to be the second dividing signal by the selection signal.

In an embodiment of the multi-clock generating device, the second mux selects the fixed dividing signal to be the second dividing signal when the selection signal is in the first selection state, and the second mux selects the keep signal to be the second dividing signal when the selection signal is in the second selection state, wherein the second dividing factor is equal to 1 when the keep signal is selected.

In an embodiment of the multi-clock generating device, the functional circuit comprises a configurable frequency divider, frequency-controlled state, and a first mux. The configurable frequency divider generates a configurable dividing signal with a configurable dividing factor, wherein when an OCC-mode signal is in a second OCC-mode state and a frequency-controlled register is in a second frequency-controlled state, the configurable dividing factor is a positive integer not less than 2, and the configurable dividing factor is 1 otherwise. The first mux selects the configurable dividing signal to be the first dividing signal when a scan-mode signal is in a second scan-mode state, and selects the fixed dividing factor to be the first dividing signal when the scan-mode signal is in a first scan-mode state.

In an embodiment of the multi-clock generating device, the configurable frequency divider comprises a first combinational logic circuit and a configurable counter. The first combinational logic circuit generates a blocking signal in a second blocking state when the OCC-mode signal is in the second OCC-mode state and the frequency-controlled register is in the second frequency-controlled state, and generates the blocking signal in a first blocking state otherwise. The configurable counter counts a number of pulses on the system clock according to the blocking signal and generating a pulse on the configurable dividing signal when the number is equal to the configurable dividing factor, wherein when the blocking signal is in the second blocking state, the configurable dividing factor is a positive integer not less than 2.

In an embodiment of the multi-clock generating device, the multi-clock generating device further comprises a second combinational logic circuit and a fixed frequency divider. The second combinational logic circuit generates the selection signal in a second selection state when either the OCC-mode signal is in a first OCC-mode state or the frequency-controlled register is in the second frequency-controlled state, and generates the selection signal in a first selection state otherwise. The fixed frequency divider generates a fixed dividing signal with the fixed dividing factor by the system clock.

In an embodiment of the multi-clock generating device, when the scan-mode signal is in the first scan-mode state and regardless of the OCC-mode signal and the frequency-controlled register, the digital circuit operates in a normal operation mode, the on-chip clocking controller selects the internal clock to be the second clock, and the first integrated clock-gating cell generates the first frequency by dividing the second frequency by the first dividing factor.

In an embodiment of the multi-clock generating device, when the digital circuit operates in a normal operation mode, the first mux selects the fixed dividing factor to be the first dividing factor, the second integrated clock-gating cell passes the system clock to the internal clock since the keep signal is selected, the on-chip clocking controller selects the internal clock to be the second clock, and the first integrated clock-gating cell generates the first clock by dividing the second frequency by the first dividing factor equal to the fixed dividing factor.

In an embodiment of the multi-clock generating device, when the scan-mode signal is in the second scan-mode state, the OCC-mode signal is in the first OCC-mode state, and regardless of the frequency-controlled register, the digital circuit operates in a scan test mode, and the on-chip clocking controller selects the external clock to be the second clock for scan testing the first and second paths, wherein the first clock is equal to the external clock.

In an embodiment of the multi-clock generating device, when the digital circuit operates in a scan test mode, the first mux selects the configurable dividing factor equal to 1 to be the first dividing factor, the on-chip clocking controller selects the external clock to be the second clock, and the first integrated clock-gating cell passes the second clock to the first clock.

In an embodiment of the multi-clock generating device, when the scan-mode signal is in the second scan-mode state, the OCC-mode signal is in the second OCC-mode state, and the frequency-controlled register is in a first frequency-controlled state, the digital circuit operates in an at-speed 1st mode for at-speed testing the intra-domain first path and the inter-domain second-to-first path.

In an embodiment of the multi-clock generating device, when the digital circuit operates in an at-speed 1st mode, the first mux selects the configurable dividing factor equal to 1 to be the first dividing factor, the second integrated clock-gating cell generates the internal clock by dividing the system frequency by the fixed dividing factor, the on-chip clocking controller selects the internal clock to be the second clock, and the first integrated clock-gating cell passes the second clock to the first clock.

In an embodiment of the multi-clock generating device, when the scan-mode signal is in the second scan-mode state, the OCC-mode signal is in a second OCC-mode state, and the frequency-controlled register is in a second frequency-controlled state, the digital circuit operates in an at-speed 2nd mode for at-speed testing the intra-domain second path and the inter-domain first-to-second path.

In an embodiment of the multi-clock generating device, when the digital circuit operates in an at-speed 2nd mode, the first mux selects the configurable dividing factor equal to the positive integer not less than 2 to be the first dividing factor, the second integrated clock-gating cell passes the system clock to the internal clock since the keep signal is selected, the on-chip clocking controller selects the internal clock to be the second clock, and the first integrated clock-gating cell generates the first clock by dividing the second frequency by the first dividing factor equal to the positive integer.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

Fig. 1 is a block diagram of a multi-clock generating device in accordance with an embodiment of the invention；

Fig. 2 is a block diagram of the functional circuit 110 shown in Fig. 1 in accordance with an embodiment of the invention；

Fig. 3 is a schematic diagram of the first combinational logic circuit 203 in Fig. 2 in accordance with an embodiment of the invention；

Fig. 4 is a block diagram of the clock-dividing circuit 120 shown in Fig. 1 in accordance with an embodiment of the invention；

Fig. 5 is a schematic diagram of the second combinational logic circuit 401 in Fig. 4 in accordance with an embodiment of the invention；

Fig. 6 is a schematic diagram of at-speed testing of the transition faults and path delay faults when receiving at the first path of the digital circuit 160 in accordance with an embodiment of the invention； and

Fig. 7 is a schematic diagram of at-speed testing of the transition faults and path delay faults when receiving at the second path of the digital circuit 160 in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

Fig. 1 is a block diagram of a multi-clock generating device in accordance with an embodiment of the invention. As shown in Fig. 1, the multi-clock generating device 100 includes the functional circuit 110, the clock-dividing circuit 120, the on-chip clocking (OCC) controller 130, and the first integrated clock-gating (ICG) cell 140. The multi-clock generating device 100 is configured to test the digital circuit 160, and the digital circuit 160 includes a first path, which operates in the first frequency f_CLK1 of the first clock S_CLK1 in the normal operation, and a second path, which operates in the second frequency f_CLK2 of the second clock S_CLK2 in the normal operation. For the sake of clear explanation, the digital circuit 160 only including the first and second paths is for illustration herein, and it is assumed that the second frequency f_CLK2 is faster than the first frequency f_CLK1 when the digital circuit 160 operates in the normal operation. In another embodiment of the invention, the digital circuit 160 includes N paths operating in N individual frequencies, in which N is a positive integer.

The functional circuit 110 is controlled by the scan-mode signal S_{SCAN_MODE}, the OCC-mode signal S_{OCC_MODE}, and the frequency-controlled signal S_FCR which is stored in the frequency-controlled register 150 to generate the first dividing signal S_DIV1 with the first dividing factor F_DIV1. The clock-dividing circuit 120 generates the internal clock S_{CLK_INT} with the internal frequency f_{CLK_INT} by the system clock S_{CLK_SYS} with the system frequency f_{CLK_SYS} according to the selection signal S_SEL. According to an embodiment of the invention, the internal frequency f_{CLK_INT} is equal to the system frequency f_{CLK_SYS} divided by the fixed dividing factor F_{DIV_FIX} when the selection signal S_SEL is in the logic “0” state. The selection signal S_SEL is generated according to the OCC-mode signal S_{OCC_MODE} and the frequency-controlled signal S_FCR, and the detail will be explained in the following description.

The OCC controller 130 selects one of the internal clock S_{CLK_INT} and the external clock S_{CLK_EXT} from the automatic test equipment (ATE) to be the second clock S_CLK2. In an embodiment of the invention, the scan-mode signal S_{SCAN_MODE} and the OCC-mode signal S_{OCC_MODE} are both in the logic “1” state for at-speed testing the digital circuit 160, and the OCC controller 130 selects the internal clock S_{CLK_INT} to be the second clock S_CLK2. In another embodiment of the invention, the scan-mode signal S_{SCAN_MODE} is in the logic “1” state while the OCC-mode signal S_{OCC_MODE} is in the logic “0” state for testing stuck-at fault of the digital circuit 160, and the OCC controller 130 selects the external clock S_{CLK_EXT} to be the second clock S_CLK2. In yet another embodiment of the invention, the scan-mode signal S_{SCAN_MODE} is in the logic “0”state for the digital circuit 160 operating in a normal operation mode, and the OCC controller 130 selects the internal clock S_{CLK_INT} to be the second clock S_CLK2.

The first integrated clock-gating cell 140 includes the EN node and the CK node. The first integrated clock-gating cell 140 receives the first dividing signal S_DIV1 by the EN node and the second clock S_CLK2 by the CK node to generate the first clock S_CLK1 with the first frequency f_CLK1. The first frequency f_CLK1 is the second frequency f_CLK2 divided by the first dividing factor F_DIV1.

Fig. 2 is a block diagram of the functional circuit 110 shown in Fig. 1 in accordance with an embodiment of the invention. As shown in Fig. 2, the functional circuit 110 includes the configurable frequency divider 201, the first mux 202, and the first combinational logic circuit 203. The configurable frequency divider 201 is controlled by the blocking signal S_BLK to generate the configurable dividing signal S_{DIV_CON} with the configurable dividing factor F_{DIV_CON} by the system clock S_{CLK_SYS}. In an embodiment of the invention, the configurable dividing factor F_{DIV_CON} is a positive integer not less than 2 or 1. The process of generating the configurable dividing signal S_{DIV_CON} is clearly expressed in the following description.

The first mux 202 selects the configurable dividing signal S_{DIV_CON} or the fixed dividing signal S_{DIV_FIX} to be the first dividing signal S_DIV1 by the scan-mode signal S_{SCAN_MODE}. In an embodiment of the invention, the multi-clock generating device 100 and the digital circuit 160 operate in the normal operation mode when the scan-mode signal S_{SCAN_MODE} is in the logic “0” state, and operate in the test mode when the scan-mode signal S_{SCAN_MODE} is in the logic “1” state. Therefore, the first dividing factor F_DIV1 is equal to the fixed dividing factor S_{DIV_FIX} when the scan-mode signal S_{SCAN_MODE} is in the logic “0” state, and the first dividing factor F_DIV1 is equal to the configurable dividing factor S_{DIV_CON} when the scan-mode signal S_{SCAN_MODE} is in the logic “1” state.

In another embodiment of the invention, the multi-clock generating device 100 and the digital circuit 160 operate in the normal operation mode when the scan-mode signal S_{SCAN_MODE} is in the logic “1” state, and they operate in the test mode when the scan-mode signal S_{SCAN_MODE} is in the logic “0” state. Therefore, the first dividing factor F_DIV1 is equal to the fixed dividing factor S_{DIV_FIX} when the scan-mode signal S_{SCAN_MODE} is in the logic “1” state, and the first dividing factor F_DIV1 is equal to the configurable dividing factor S_{DIV_CON} when the scan-mode signal S_{SCAN_MODE} is in the logic “0” state. One with skill in the art understands that the logic states could be arbitrarily changed according to the design requirement. Details of the operation of the configurable frequency divider 201 will be clearly explained in the following description.

According to an embodiment of the invention, the configurable frequency divider 201 is a configurable counter which counts the pulse number of the system clock S_{CLK_SYS} to generate a pulse on the configurable dividing signal S_{DIV_CON} when the pulse number is equal to the configurable dividing factor F_{DIV_CON}.

The first combinational logic circuit 203 generates the blocking signal S_BLK according to the states of the OCC-mode signal S_{OCC_MODE} and the frequency-controlled signal S_FCR stored in the frequency-controlled register 150. According to the embodiment of the invention, when intra-domain at-speed testing the first path and inter-domain at-speed testing the second-to-first path, the OCC-mode signal S_{OCC_MODE} is in the logic “1” state and the frequency-controlled signal S_FCR is in the logic “1” state. The first combinational logic circuit 203 generates the blocking signal S_BLK to be in the logic “1” state according to the OCC-mode signal S_{OCC_MODE} and the frequency-controlled signal S_FCR, and the configurable dividing factor F_{DIV_CON} is thus configured to be a positive integer not less than 2. Otherwise, the configurable dividing factor F_{DIV_CON} is configured to be 1.

Fig. 3 is a schematic diagram of the first combinational logic circuit 203 in Fig. 2 in accordance with an embodiment of the invention. As shown in Fig. 3, the first combinational circuit 203 is implemented as an AND logic gate 301. When the OCC-mode signal S_{OCC_MODE} is in the logic “1” state and the frequency-controlled signal S_FCR is in the logic “1” state for intra-domain at-speed testing the first path and inter-domain at-speed testing the second-to-first path, the blocking signal S_BLK is in the logic “1” state. Otherwise, the blocking signal S_BLK is in the logic “0” state.

According to another embodiment of the invention, when intra-domain at-speed testing the first path and inter-domain at-speed testing the second-to-first path, the OCC-mode signal S_{OCC_MODE} is in the logic “0” state and the frequency-controlled signal S_FCR is in the logic “0” state. Therefore, the logic states should be modified accordingly so that the configurable dividing factor remains the same as stated above. Therefore, the logic states stated herein are only for the purpose of illustration and are not intended to be limiting.

Fig. 4 is a block diagram of the clock-dividing circuit 120 shown in Fig. 1 in accordance with an embodiment of the invention. As shown in Fig. 4, the clock-dividing circuit 120 includes the second combinational logic circuit 401, the fixed frequency divider 402, the second mux 403, and the second ICG cell 404.

The second combinational logic circuit 401 generates the selection signal S_SEL according to the states of the OCC-mode signal S_{OCC_MODE} and the frequency-controlled signal S_FCR. According to an embodiment of the invention, the selection signal S_SEL is in the logic “1” state when the OCC-mode signal S_{OCC_MODE} is in the logic “0” state or the frequency-controlled signal S_FCR is in the logic “1” state. Otherwise, the selection signal S_SEL is in the logic “0” state.

Fig. 5 is a schematic diagram of the second combinational logic circuit 401 in Fig. 4 in accordance with an embodiment of the invention. As shown in Fig. 5, the second combinational circuit 401 is implemented as the OR logic gate 501 with an input inverted by an inverter 502. Therefore, when either the OCC-mode signal S_{OCC_MODE} is in the logic “0” state or the frequency-controlled signal S_FCR is in the logic “1” state, the selection signal is in the logic “1” state. Otherwise, the selection signal S_SEL is in the logic “0” state. The logic states stated herein are only for the purpose of illustration and are not intended to be limiting.

The fixed frequency divider 402 generates the fixed dividing signal S_{DIV_FIX} with the fixed dividing factor F_{DIV_FIX} by the system clock S_{CLK_SYS}. According to an embodiment of the invention, the fixed frequency divider 402 is a fixed counter counting the pulse number of the system clock S_{CLK_SYS}. When the pulse number is equal to the fixed dividing factor F_{DIV_FIX}, a pulse is generated on the fixed dividing signal S_{DIV_FIX}.

The second mux 403 selects the fixed dividing signal S_{DIV_FIX} or the keep signal S_K to be the second dividing signal S_DIV2 according to the selection signal S_SEL. According to the embodiment of the invention, the second mux 403 selects the fixed dividing signal S_{DIV_FIX} to be the second dividing signal S_DIV2 with the second dividing factor F_DIV2 when the selection signal is in the logic “0” state, and selects the keep signal S_K with the dividing factor equal to 1 to be the second dividing signal S_DIV2 when the selection signal is in the logic “1” state.

The second ICG cell 404 includes the EN node and the CK node. The second ICG cell 404 receives the second dividing signal S_DIV2 by the EN node and the system clock S_{CLK_SYS} by the CK node to generate the internal clock S_{CLK_INT} with the internal frequency f_{CLK_INT}. The internal frequency f_{CLK_INT} is the system frequency f_{CLK_SYS} divided by the second dividing factor F_DIV2.

The multi-clock generating device 100 and the digital circuit 160 are operated in different operation modes which are controlled by the scan-mode signal S_{SCAN_MODE}, the OCC-mode signal S_{OCC_MODE} and the frequency-controlled signal S_FCR. The operation modes and testing items, which are corresponding to the scan-mode signal S_{SCAN_MODE}, the OCC-mode signal S_{OCC_MODE} and the frequency-controlled signal S_FCR, are listed in Table 1 in accordance with an embodiment of the invention.

All the operation modes and the testing items will be explained in the following description according to an embodiment of the invention. The logic states of the scan-mode signal S_{SCAN_MODE}, the OCC-mode signal S_{OCC_MODE} and the frequency-controlled signal S_FCR corresponding to the operation modes and testing items are used for illustration, but not limited thereto. In the following description, Figs. 1, 2, and 4 are referenced for further explanation.

Table 1

Normal Operation Mode

When the scan-mode signal S_{SCAN_MODE} is in the logic “0” state, the multi-clock generating device 100 and the digital circuit 160 operate in normal operation. Since the scan-mode signal S_{SCAN_MODE} is in the logic “0” state and regardless of the states of the OCC-mode signal S_{OCC_MODE} and the frequency-controlled signal S_FCR, the first mux 202 in Fig. 2 selects the fixed dividing factor S_{DIV_FIX} to be the first dividing factor F_DIV1, and the OCC controller 130 in Fig. 1 selects the system clock S_{CLK_SYS} to be the second clock S_CLK2.

According to the embodiment of the invention, the first ICG cell 140 in Fig. 1 generates the first frequency f_CLK1 by dividing the second frequency f_CLK2 by the first dividing factor S_DIV1 which is equal to the fixed dividing factor S_{DIV_FIX}. The multi-clock generating device 100 therefore provides the first clock S_CLK1 with the first frequency f_CLK1 and the second clock S_CLK2 with the second frequency f_CLK2 for the digital circuit 160.

Scan Test Mode

When the scan-mode signal S_{SCAN_MODE} is in the logic “1” state, the OCC-mode signal S_{OCC_MODE} is in the logic “0” state, and regardless of the state of the frequency-controlled signal S_FCR, the multi-clock generating device 100 and the digital circuit 160 are in the scan test mode for testing all stuck-at faults of the digital circuit 160.

For testing all stuck-at faults of the digital circuit 160, the OCC controller 130 in Fig. 1 selects the external clock S_{CLK_EXT} from the Automatic Testing Equipment to be the second clock S_CLK2, and the first mux 202 selects the configurable dividing factor F_{DIV_CON} to be the first dividing factor S_DIV1. As mentioned above, the first combinational logic circuit 203 is an AND logic gate in accordance with the illustrated embodiment of the invention. Since the OCC-mode signal S_{OCC_MODE} is in the logic “0” state, the blocking signal S_BLK is in the logic “0” state regardless of the state of the frequency-controlled signal S_FCR.

Therefore, the configurable dividing factor F_{DIV_CON} is 1 since the blocking signal S_BLK is in the logic “0” state. That is, when testing all stuck-at faults, the first dividing factor S_DIV1 is 1, and first clock S_CLK1 and the second clock S_CLK2 are both equal to the external clock S_{CLK_EXT} from the Automatic Testing Equipment.

At-Speed Test 1^st Mode

When the scan-mode signal S_{SCAN_MODE} is in the logic “1” state, the OCC-mode signal S_{OCC_MODE} is in the logic “1” state, and the frequency-controlled signal S_FCR is in the logic “0” state, the multi-clock generating device 100 and the digital circuit 160 are configured for intra-domain at-speed testing the first path and inter-domain at-speed testing the second-to-first path. In other words, that is at-speed testing of the transition faults and path delay faults when receiving at the first path of the digital circuit 160.

Fig. 6 is a schematic diagram of at-speed testing of the transition faults and path delay faults when receiving at the first path of the digital circuit 160 in accordance with an embodiment of the invention. As shown in Fig. 6, the OCC controller 130 in Fig. 1 generates 2 pulses on the second clock S_CLK2, and the first ICG cell 140 generates the first clock S_CLK1 with the first frequency F_CLK1 equal to the second frequency F_CLK2 divided by the first dividing factor F_DIV1 equal to 1. That is, the clock dividing circuit 120 generates the internal clock S_{CLK_INT} with the internal frequency f_{CLK_INT} equal to the first frequency f_CLK1 for the first path operating in the normal operation mode. In the following description, the behaviors of the functional circuit 110 and the clock-dividing circuit 120 in the at-speed 1^st mode will be explained in detail.

Referring to Fig. 2, when the scan-mode signal S_{SCAN_MODE} is in the logic “1” state, the OCC-mode signal S_{OCC_MODE} is in the logic “1” state, and the frequency-controlled signal S_FCR is in the logic “0” state, the first dividing factor F_DIV1 is equal to the configurable dividing factor F_{DIV_CON} which is configured to be 1 by the OCC-mode signal S_{OCC_MODE} and the frequency-controlled signal S_FCR. In other words, the first ICG cell 140 in Fig. 1 merely passes the second clock S_CLK2 to the first clock S_CLK1, since the first dividing factor F_DIV is 1.

Referring to Fig. 4, since the scan-mode signal S_{SCAN_MODE} is in the logic “1” state, the OCC-mode signal S_{OCC_MODE} is in the logic “1” state, and the frequency-controlled signal S_FCR is in the logic “0” state, the selection signal S_SEL is in the logic “0”state, such that the second mux 403 selects the fixed dividing factor F_{DIV_FIX} to be the second dividing factor F_DIV2. Therefore, the second ICG cell 404 generates the internal frequency f_{CLK_INT} by dividing the system frequency f_{CLK_SYS} by the fixed dividing factor F_{DIV_FIX}. In other words, the internal frequency f_{CLK_INT} is equal to the first frequency f_CLK1 for the first path operating in the normal operation mode.

As shown in Fig. 6, the OCC controller 130 generates 2 pulses with the internal frequency f_{CLK_INT} on the second clock S_CLK2. Since the first dividing factor F_DIV is 1, the first ICG cell 140 passes the second clock S_CLK2 to the first clock S_CLK1. Therefore, the first clock S_CLK1 and the second clock S_CLK2 are automatically synchronized. Then, the intra-domain testing 601 and the inter-domain testing 602 are executed in a serial process.

When executing the intra-domain testing 601, the data is launched and received at the first path of the digital circuit 160. Accordingly, the transition faults and path delay faults in the first path are tested. When executing the inter-domain testing 602, the data is launched at the second path and received at the first path of the digital circuit 160. Therefore, the inter-domain at-speed testing from the second path to the first path could be accomplished in the inter-domain testing 602, and the transition faults and path delay faults of the second-to-first path are tested.

At-Speed Test 2^nd Mode

When the scan-mode signal S_{SCAN_MODE} is in the logic “1” state, the OCC-mode signal S_{OCC_MODE} is in the logic “1” state, and the frequency-controlled signal S_FCR is in the logic “1” state, the multi-clock generating device 100 and the digital circuit 160 are configured for intra-domain at-speed testing the second path and inter-domain at-speed testing the first-to-second path. In other words, that is at-speed testing of the transition faults and path delay faults when receiving at the second path of the digital circuit 160.

Fig. 7 is a schematic diagram of at-speed testing of the transition faults and path delay faults when receiving at the second path of the digital circuit 160 in accordance with an embodiment of the invention. As shown in Fig. 1, the OCC controller 130 in Fig. 1 generates 2 pulses on the second clock S_CLK2, and the first ICG cell 140 generates the first clock S_CLK1 with the first frequency F_CLK1 by dividing the second frequency F_CLK2 by the first dividing factor F_DIV1 equal to the fixed dividing factor F_{DIV_FIX}. That is, the clock dividing circuit 120 generates the internal clock S_{CLK_INT} with the internal frequency f_{CLK_INT} equal to the second frequency f_CLK2 for the second path operating in the normal operation mode. In the following description, the behaviors of the functional circuit 110 and the clock-dividing circuit 120 in the at-speed 2^nd mode will be explained in detail.

Referring to Fig. 2, when the scan-mode signal S_{SCAN_MODE} is in the logic “1” state, the OCC-mode signal S_{OCC_MODE} is in the logic “1” state, and the frequency-controlled signal S_FCR is in the logic “1” state, the first dividing factor F_DIV1 is equal to the configurable dividing factor F_{DIV_CON} which is configured to be a positive integer not less than 2 by the OCC-mode signal S_{OCC_MODE} and the frequency-controlled signal S_FCR. For simplifying the explanation of the invention, it is assumed that the configurable dividing factor F_{DIV_CON} is 2. Therefore, the first ICG cell 140 in Fig. 1 generates the second f S_CLK2 by dividing the first frequency f_CLK1 by 2.

Referring to Fig. 4, since the scan-mode signal S_{SCAN_MODE} is in the logic “1” state, the OCC-mode signal S_{OCC_MODE} is in the logic “1” state, and the frequency-controlled signal S_FCR is in the logic “1” state, the selection signal S_SEL is in the logic “1”state, such that the second mux 403 selects the keep signal S_K to be the second dividing factor F_DIV2. That is, the second dividing factor F_DIV2 is 1, and the second ICG cell 404 merely passes the system clock S_{CLK_SYS} to the internal clock S_{CLK_INT}. In other words, the internal frequency f_{CLK_INT} is equal to the second frequency f_CLK2 for the second path operating in the normal operation mode.

As shown in Fig. 7, since the first dividing factor F_DIV1 is 2 according to the assumption above, the first ICG cell 140 generates the first clock S_CLK1 by dividing the second frequency f_CLK2 by 2, such that only 1 pulse is generated on the first clock S_CLK1. In addition, the frequency of the first clock S_CLK1 is faster than that in the normal operation mode in this case. In order to prevent from over-testing, the first clock S_CLK1 should be stopped after 1 pulse. Since the first clock S_CLK1 is generated by the second clock S_CLK2, the first clock S_CLK1 and the second clock S_CLK2 are synchronous.

When executing the intra-domain testing 701, the data is launched and received at the second path of the digital circuit 160. Accordingly, the transition faults and path delay faults in the second path are tested. When executing the inter-domain testing 702, the data is launched at the first path and received at the second path of the digital circuit 160. Therefore, the inter-domain at-speed testing from the first path to the second path could be accomplished in the inter-domain testing 702, and the transition faults and path delay faults of the second-to-first path are tested.

Since the OCC controller is reduced to one, the complexity of the multi-clock generating circuit is lowered, and the synchronization between the first clock and second clock is easily accomplished. In addition, since only 2 pulses on each clock at most are required, the loading of the ATE should be mitigated, and the storing requirement of the ATE is lowered as well. The devices and methods provided in the invention mean the intra-domain and inter-domain at-speed testing could be accomplished in a serial process. The at-speed time for testing does not need to be separated into two parts, and the time for at-speed testing should be shortened.

While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.

Claims

A multi-clock generating device for testing a digital circuit comprising a first path operating in a first frequency of a first clock and a second path operating in a second frequency of a second clock comprising:

a functional circuit, generating a first dividing signal with a first dividing factor；

a clock-dividing circuit, generating an internal clock with an internal frequency by a system clock with a system frequency, wherein the internal frequency is equal to the system frequency divided by a fixed dividing factor when a selection signal is in a first selection state；

an on-chip clocking controller, selecting one of the internal clock and an external clock from an automatic test equipment to be the second clock； and

a first integrated clock-gating cell, generating the first clock with the first frequency by dividing the second frequency by the first dividing factor, wherein when at-speed testing the intra-domain first path and the inter-domain second-to-first path, the first and second frequencies are equal to the system frequency divided by the fixed dividing factor.
The multi-clock generating device of claim 1, wherein when at-speed testing the intra-domain first path and the inter-domain second-to-first path, a scan-mode signal is in a second scan-mode state, an OCC-mode signal is in a second OCC-mode state, and a frequency-controlled register is in a second frequency-controlled state.
The multi-clock generating device of claim 2, wherein when at-speed testing the intra-domain second path and the inter-domain first-to-second path, the selection signal is in a second selection state and the internal frequency is equal to the system frequency.
The multi-clock generating device of claim 3, wherein when at-speed testing the intra-domain second path and the inter-domain first-to-second path, the scan-mode signal is in the second scan-mode state, the OCC-mode signal is in the second OCC-mode state, and the frequency-controlled register is in a first frequency-controlled state.
The multi-clock generating device of claim 4, wherein the functional circuit comprises:

a configurable frequency divider, generating a configurable dividing signal with a configurable dividing factor, wherein when the OCC-mode signal is in the second OCC-mode state and the frequency-controlled register is in the second frequency-controlled state, the configurable dividing factor is a positive integer not less than 2, and the configurable dividing factor is 1 otherwise； and

a first mux, selecting the configurable dividing signal to be the first dividing signal when the scan-mode signal is in the second scan-mode state, and selecting the fixed dividing factor to be the first dividing signal when the scan-mode signal is in a first scan-mode state.
The multi-clock generating device of claim 4, wherein the configurable frequency divider comprises:

a first combinational logic circuit, generating a blocking signal in a second blocking state when the OCC-mode signal is in the second OCC-mode state and the frequency-controlled register is in the second frequency-controlled state, and generating the blocking signal in a first blocking state otherwise； and

a configurable counter, counting a number of pulses on the system clock according to the blocking signal and generating a pulse on the configurable dividing signal when the number is equal to the configurable dividing factor, wherein when the blocking signal is in the second blocking state, the configurable dividing factor is a positive integer not less than 2.
The multi-clock generating device of claim 5, wherein the clock-dividing circuit comprises:

a second combinational logic circuit, generating the selection signal in a second selection state when either the OCC-mode signal is in a first OCC-mode state or the frequency-controlled register is in the second frequency-controlled state, and generating the selection signal in a first selection state otherwise；

a fixed frequency divider, generating a fixed dividing signal with the fixed dividing factor by the system clock；

a second mux, selecting the fixed dividing signal to be a second dividing signal with a second dividing factor when the selection signal is in the first selection state, and selecting a keep signal to be the second dividing signal when the selection signal is in the second selection state, wherein the second dividing factor is equal to 1 when the keep signal is selected； and

a second integrated clock-gating cell, generating an internal clock with an internal frequency by dividing the system frequency by the second dividing signal.
The multi-clock generating device of claim 7, wherein the fixed frequency divider comprises:

a fixed counter, counting a number of pulses on the system clock and generating a pulse on the fixed dividing signal when the number is equal to the fixed dividing factor.
The multi-clock generating device of claim 7, wherein when the scan-mode signal is in the second scan-mode state and the OCC-mode signal is in the first OCC-mode state, the on-chip clocking controller selects the external clock to be the second clock for scan testing the first and second paths, and the first clock is equal to the external clock.
The multi-clock generating device of claim 7, wherein when the scan-mode signal is in the first scan-mode state, the digital circuit operates in a normal operation mode, the on-chip clocking controller selects the internal clock to be the second clock, and the first integrated clock-gating cell generates the first frequency by dividing the second frequency by the first dividing factor.
A method for testing a digital circuit comprising a first path operating in a first frequency of a first clock and a second path operating in a second frequency of a second clock comprising:

generating a first dividing signal with a first factor；

generating an internal clock with an internal frequency by a system clock with a system frequency, wherein the internal frequency is equal to the system frequency divided by a fixed dividing factor when a selection signal is in a first selection state；

selecting, by an on-chip clocking controller, one of the internal clock and an external clock from an automatic test equipment to be the second clock； and

generating, by a first integrated clock-gating cell, the first clock with the first frequency by dividing the second frequency by the first dividing factor, wherein when at-speed testing the intra-domain first path and the inter-domain second-to-first path, the first and second frequencies are equal to the system frequency divided by the fixed dividing factor.
The multi-clock generating method of claim 11, wherein when at-speed testing the intra-domain first path and the inter-domain second-to-first path, a scan-mode signal is in a second scan-mode state, an OCC-mode signal is in a second OCC-mode state, and a frequency-controlled register is in a second frequency-controlled state.
The multi-clock generating method of claim 12, wherein when at-speed testing the intra-domain second path and the inter-domain first-to-second path, the selection signal is in a second selection state and the internal frequency is equal to the system frequency.
The multi-clock generating method of claim 13, wherein when at-speed testing the intra-domain second path and the inter-domain first-to-second path, the scan-mode signal is in the second scan-mode state, the OCC-mode signal is in the second OCC-mode state, and the frequency-controlled register is in a first frequency-controlled state.
The multi-clock generating method of claim 14, wherein the generating the first dividing signal step further comprises:

generating a configurable dividing signal with a configurable dividing factor, wherein when the OCC-mode signal is in the second OCC-mode state and the frequency-controlled register is in the second frequency-controlled state, the configurable dividing factor is a positive integer not less than 2, and the configurable dividing factor is 1 otherwise；

selecting the configurable dividing signal to be the first dividing signal when the scan-mode signal is in the second scan-mode state； and

selecting the fixed dividing factor to be the first dividing signal when the scan-mode signal is in a first scan-mode state.
The multi-clock generating method of claim 14, wherein the step of generating the configurable dividing signal further comprises:

generating a blocking signal in a second blocking state when the OCC-mode signal is in the second OCC-mode state and the frequency-controlled register is in the second frequency-controlled state；

generating the blocking signal in a first blocking state otherwise； and

counting a number of pulses on the system clock according to the blocking signal and generating a pulse on the configurable dividing signal when the number is equal to the configurable dividing factor, wherein when the blocking signal is in the second blocking state, the configurable dividing factor is a positive integer not less than 2.
The multi-clock generating method of claim 15, wherein the step of generating the internal clock further comprises:

generating the selection signal in a second selection state when either the OCC-mode signal is in a first OCC-mode state or the frequency-controlled register is in the second frequency-controlled state；

generating the selection signal in a first selection state otherwise；

generating a fixed dividing signal with the fixed dividing factor by the system clock；

selecting the fixed dividing signal to be a second dividing signal with a second dividing factor when the selection signal is in the first selection state；

selecting a keep signal to be the second dividing signal when the selection signal is in the second selection state, wherein the second dividing factor is equal to 1 when the keep signal is selected； and

generating an internal clock with an internal frequency by dividing the system frequency by the second dividing signal.
The multi-clock generating method of claim 17, wherein the step of generating the fixed dividing signal further comprises:

counting a number of pulses on the system clock； and

generating a pulse on the fixed dividing signal when the number is equal to the fixed dividing factor.
The multi-clock generating method of claim 17, wherein when the scan-mode signal is in the second scan-mode state and the OCC-mode signal is in the first OCC-mode state, the first clock and the second clock are equal to the external clock for scan testing the first and second paths.
The multi-clock generating method of claim 17, wherein when the scan-mode signal is in a first scan-mode state, the digital circuit operates in a normal operation mode, the internal clock is selected to be the second clock, and the first frequency is the second frequency divided by the first dividing factor by the first integrated clock-gating cell.
A multi-clock generating device for testing a digital circuit comprising a first path operating in a first frequency of a first clock and a second path operating in a second frequency of a second clock comprising:

a functional circuit, generating a first dividing signal with a first dividing factor；

an on-chip clocking controller, selecting one of an internal clock with an internal frequency and an external clock from an automatic test equipment to be the second clock；

a first integrated clock-gating cell, generating the first clock with the first frequency by dividing the second frequency by the first dividing factor；

a second integrated clock-gating cell, generating the internal clock by dividing the system frequency by a second dividing signal with a second dividing factor； and

a second mux, selecting a fixed dividing signal with a fixed dividing factor or a keep signal to be the second dividing signal by the selection signal.
The multi-clock generating device of claim 21, wherein the second mux selects the fixed dividing signal to be the second dividing signal when the selection signal is in the first selection state, and the second mux selects the keep signal to be the second dividing signal when the selection signal is in the second selection state, wherein the second dividing factor is equal to 1 when the keep signal is selected.
The multi-clock generating device of claim 22, wherein the functional circuit comprises:

a configurable frequency divider, generating a configurable dividing signal with a configurable dividing factor, wherein when an OCC-mode signal is in a second OCC-mode state and a frequency-controlled register is in a second frequency-controlled state, the configurable dividing factor is a positive integer not less than 2, and the configurable dividing factor is 1 otherwise； and

a first mux, selecting the configurable dividing signal to be the first dividing signal when a scan-mode signal is in a second scan-mode state, and selecting the fixed dividing factor to be the first dividing signal when the scan-mode signal is in a first scan-mode state.
The multi-clock generating device of claim 23, wherein the configurable frequency divider comprises:

a first combinational logic circuit, generating a blocking signal in a second blocking state when the OCC-mode signal is in the second OCC-mode state and the frequency-controlled register is in the second frequency-controlled state, and generating the blocking signal in a first blocking state otherwise； and

a configurable counter, counting a number of pulses the system clock according to the blocking signal and generating a pulse on the configurable dividing signal when the number is equal to the configurable dividing factor, wherein when the blocking signal is in the second blocking state, the configurable dividing factor is a positive integer not less than 2.
The multi-clock generating device of claim 23, further comprising:

a second combinational logic circuit, generating the selection signal in a second selection state when either the OCC-mode signal is in a first OCC-mode state or the frequency-controlled register is in the second frequency-controlled state, and generating the selection signal in a first selection state otherwise； and

a fixed frequency divider, generating a fixed dividing signal with the fixed dividing factor by the system clock.
The multi-clock generating device of claim 25, wherein the fixed frequency divider comprises:

a fixed counter, counting a number of pulses the system clock and generating a pulse on the fixed dividing signal when the number is equal to the fixed dividing factor.
The multi-clock generating device of claim 25, wherein when the scan-mode signal is in the first scan-mode state and regardless of the OCC-mode signal and the frequency-controlled register, the digital circuit operates in a normal operation mode, the on-chip clocking controller selects the internal clock to be the second clock, and the first integrated clock-gating cell generates the first frequency by dividing the second frequency by the first dividing factor.
The multi-clock generating device of claim 27, wherein when the digital circuit operates in a normal operation mode, the first mux selects the fixed dividing factor to be the first dividing factor, the second integrated clock-gating cell passes the system clock to the internal clock since the keep signal is selected, the on-chip clocking controller selects the internal clock to be the second clock, and the first integrated clock-gating cell generates the first clock by dividing the second frequency by the first dividing factor equal to the fixed dividing factor.
The multi-clock generating device of claim 25, wherein when the scan-mode signal is in the second scan-mode state, the OCC-mode signal is in the first OCC-mode state, and regardless of the frequency-controlled register, the digital circuit operates in a scan test mode, and the on-chip clocking controller selects the external clock to be the second clock for scan testing the first and second paths, wherein the first clock is equal to the external clock.
The multi-clock generating device of claim 29, wherein when the digital circuit operates in a scan test mode, the first mux selects the configurable dividing factor equal to 1 to be the first dividing factor, the on-chip clocking controller selects the external clock to be the second clock, and the first integrated clock-gating cell passes the second clock to the first clock.
The multi-clock generating device of claim 25, wherein when the scan-mode signal is in the second scan-mode state, the OCC-mode signal is in the second OCC-mode state, and the frequency-controlled register is in a first frequency-controlled state, the digital circuit operates in an at-speed 1st mode for at-speed testing the intra-domain first path and the inter-domain second-to-first path.
The multi-clock generating device of claim 31, wherein when the digital circuit operates in an at-speed 1st mode, the first mux selects the configurable dividing factor equal to 1 to be the first dividing factor, the second integrated clock-gating cell generates the internal clock by dividing the system frequency by the fixed dividing factor, the on-chip clocking controller selects the internal clock to be the second clock, and the first integrated clock-gating cell passes the second clock to the first clock.
The multi-clock generating device of claim 25, wherein when the scan-mode signal is in the second scan-mode state, the OCC-mode signal is in a second OCC-mode state, and the frequency-controlled register is in a second frequency-controlled state, the digital circuit operates in an at-speed 2nd mode for at-speed testing the intra-domain second path and the inter-domain first-to-second path.
The multi-clock generating device of claim 33, wherein when the digital circuit operates in an at-speed 2nd mode, the first mux selects the configurable dividing factor equal to the positive integer not less than 2 to be the first dividing factor, the second integrated clock-gating cell passes the system clock to the internal clock since the keep signal is selected, the on-chip clocking controller selects the internal clock to be the second clock, and the first integrated clock-gating cell generates the first clock by dividing the second frequency by the first dividing factor equal to the positive integer.