WO2016117225A1 - Memory cell and memory device - Google Patents

Abstract

A memory cell is provided with: an antifuse inserted into each of a plurality of paths, said paths being connected to each other at one end thereof; a resistive element that is inserted into at least one of the plurality of paths; and a selective transistor that connects a first connection terminal and the one ends of the plurality of paths when turned on.

Description

Memory cell and memory device

The present disclosure relates to a memory cell having an antifuse, and a memory device including such a memory cell.

Electronic devices are often integrated with non-volatile memories that can store information even when the power is turned off. Such a nonvolatile memory includes, for example, an OTP (One Time Programmable) memory in which data can be written only once. One of the memory elements constituting the OTP memory is an antifuse. The anti-fuse changes its resistance state from a high resistance state (non-conduction state) to a low resistance state (conduction state) by applying stress. For example, Patent Documents 1 and 2 disclose memory devices using antifuses.

Special table 2006-510203 JP2012-174863

Incidentally, it is generally desired that the memory device be formed in a small area, and further reduction in size is expected.

Therefore, it is desirable to provide a memory cell and a memory device that can be reduced in size.

A memory cell according to an embodiment of the present disclosure includes an antifuse, a resistance element, and a selection transistor. The antifuse is inserted into each of a plurality of paths whose one ends are connected to each other. The resistance element is inserted into at least one of the plurality of paths. When the selection transistor is turned on, the selection transistor connects the first connection terminal and one end of the plurality of paths.

The memory device according to an embodiment of the present disclosure includes a memory cell and a control unit that controls the memory cell. The memory cell includes an antifuse, a resistance element, and a selection transistor. The antifuse is inserted into each of a plurality of paths whose one ends are connected to each other. The resistance element is inserted into at least one of the plurality of paths. When the selection transistor is turned on, the selection transistor connects the first connection terminal and one end of the plurality of paths.

In the memory cell and the memory device according to the embodiment of the present disclosure, the antifuse is inserted into each of the plurality of paths, and the resistance element is inserted into at least one of the plurality of paths. One ends of the plurality of paths are connected to each other, and a selection transistor is connected to one end thereof.

According to the memory cell and the memory device in an embodiment of the present disclosure, the antifuse is inserted into each of the plurality of paths whose one ends are connected to each other, and the resistance element is inserted into at least one of the plurality of paths. So the size can be reduced. In addition, the effect described here is not necessarily limited, and there may be any effect described in the present disclosure.

3 is a block diagram illustrating a configuration example of a memory device according to a first embodiment of the present disclosure. FIG. FIG. 2 is a circuit diagram illustrating a configuration example of a memory cell illustrated in FIG. 1. FIG. 3 is a cross-sectional view illustrating a cross-sectional structure of a main part of the memory element illustrated in FIG. 2. FIG. 3 is a cross-sectional view illustrating a main-part cross-sectional structure after a write operation of the memory element illustrated in FIG. 2. It is a timing waveform diagram showing a write operation. It is explanatory drawing showing an example of write-in operation | movement. It is explanatory drawing showing another example of write-in operation | movement. FIG. 3 is an explanatory diagram illustrating a characteristic example of the memory cell illustrated in FIG. 2. It is explanatory drawing showing an example of read-out operation | movement. It is explanatory drawing showing other examples of read-out operation. It is explanatory drawing showing other examples of read-out operation. It is another explanatory view showing an example of the reading operation. It is explanatory drawing showing the relationship between the size of a memory device, and the number of bits. FIG. 10 is a circuit diagram illustrating a configuration example of a memory cell according to a modification. It is a circuit diagram showing one structural example of the memory cell which concerns on another modification. It is sectional drawing showing the principal part sectional structure of the memory element which concerns on another modification. FIG. 10 is a block diagram illustrating a configuration example of a memory device according to a second embodiment of the present disclosure. FIG. 14 is a circuit diagram illustrating a configuration example of a memory cell illustrated in FIG. 13. It is explanatory drawing showing an example of write-in operation | movement. It is explanatory drawing showing another example of write-in operation | movement. It is explanatory drawing showing another example of write-in operation | movement. It is explanatory drawing showing an example of read-out operation | movement. It is explanatory drawing showing other examples of read-out operation. It is a block diagram showing the example of 1 structure of the memory device which concerns on a modification. FIG. 18 is a circuit diagram illustrating a configuration example of a memory cell illustrated in FIG. 17. It is a circuit diagram showing one structural example of the memory cell which concerns on another modification. It is explanatory drawing showing an example of the write-in operation | movement in the memory device which concerns on a modification.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order.
1. First embodiment (memory device having redundancy)
2. Second embodiment (memory device storing a plurality of bit data in each memory cell)

<1. First Embodiment>
[Configuration example]
FIG. 1 illustrates a configuration example of the memory device (memory device 1) according to the first embodiment. The memory device 1 is a redundant memory device using an antifuse as a storage element. The memory device 1 includes a memory cell array 10, a word line driving unit 11, a bit line driving unit 12, and a sense amplifier 13.

The memory cell array 10 has a plurality of memory cells 20 arranged in a matrix. The memory cell array 10 includes a plurality of word lines WL extending in the row direction (lateral direction), a plurality of bit lines BL and a plurality of source lines SL extending in the column direction (vertical direction). One end of each word line WL is connected to the word line drive unit 11, one end of each bit line BL is connected to the bit line drive unit 12, and one end of each source line SL is connected to the sense amplifier 13. Each memory cell 20 is connected to a word line WL, a bit line BL, and a source line SL.

FIG. 2 shows a configuration example of the memory cell 20. The memory cell 20 includes storage elements 21A and 21B, resistance elements 22A and 22B, and a selection transistor 23.

Memory elements 21A and 21B function as antifuses. The memory elements 21A and 21B have two terminals. One end of the storage element 21A is connected to one end of the storage element 21B and the bit line BL, and the other end is connected to one end of the resistance element 22A. One end of the storage element 21B is connected to one end of the storage element 21A and the bit line BL, and the other end is connected to one end of the resistance element 22B. The memory elements 21A and 21B change their resistance state from a high resistance state (non-conduction state) to a low resistance state (conduction state) by applying a stress voltage between both terminals. As described above, the storage elements 21A and 21B store information (bit data) according to the resistance state.

Further, the memory elements 21A and 21B have different stress voltages (threshold values Vth) necessary for changing the resistance state. Specifically, the threshold value VthA of the memory element 21A is set lower than the threshold value VthB of the memory element 21B. Thereby, in the memory device 1, as described later, the size of the selection transistor 23, the driver of the bit line driving unit 12, and the sense amplifier 13 can be reduced.

3A and 3B show an example of a cross-sectional structure of a main part of the memory element 21A. FIG. 3A shows a structure in a high resistance state, and FIG. 3B shows a structure in a low resistance state. The memory element 21A is formed in a region surrounded by the element isolation insulating layer 102 on the insulating layer 101 uniformly formed on the P-type semiconductor substrate 100P. That is, the memory device 1 has an SOI (Silicon on Insulator) structure. The memory device 1 can be formed using a general CMOS (Complementary Metal Metal Oxide Semiconductor) manufacturing process.

The memory element 21A includes semiconductor layers 110P, 111N, and 112N, a dielectric film 121, a conductive film 122, and electrodes 131 and 132. The memory element 21A has a so-called MOS structure.

The semiconductor layer 110P is a P-type semiconductor layer formed in a region surrounded by the insulating layer 102, and constitutes a so-called P well. The semiconductor layer 110P functions as a so-called back gate of the memory element 21A. The semiconductor layer 110P is made of a semiconductor material obtained by doping silicon (Si) with an impurity such as boron (B). A voltage of 0 V is applied to the semiconductor layer 110P via a contact (not shown).

The semiconductor layers 111N and 112N are N-type semiconductor layers formed in the semiconductor layer 110P. The semiconductor layer 111N and the semiconductor layer 112N are disposed separately at a predetermined interval. The semiconductor layers 111N and 112N are made of, for example, a semiconductor material obtained by doping silicon with impurities such as arsenic (As) and phosphorus (P), and the thickness thereof is about 50 nm to 200 nm. Such semiconductor layers 111N and 112N can be easily formed by, for example, a method using self-alignment (self-alignment) or a method using a mask pattern such as a photoresist or an oxide film. It is desirable that the distance L between the semiconductor layer 111N and the semiconductor layer 112N be as short as possible. Specifically, for example, the minimum processing dimension in the manufacturing process can be set. Alternatively, it is preferable that the semiconductor layer 111N and the semiconductor layer 112N be made shorter than the minimum processing dimension within a range in which the semiconductor layer 111N and the semiconductor layer 112N are normally separated. Thereby, the element size of the memory element 21A can be reduced, and the filament F described later can be more easily formed.

The dielectric film 121 is formed on the semiconductor layer 110P in a region between the semiconductor layer 111N and the semiconductor layer 112N and on a part of the semiconductor layers 111N and 112N. The dielectric film 121 is made of, for example, silicon oxide (SiO ₂ ) or the like and has a thickness of about several nm to 20 nm.

The conductive film 122 is formed on the dielectric film 121. The conductive film 122 is made of a conductive material such as polycrystalline silicon or silicide metal and has a thickness of about 50 nm to 500 nm. In this example, the conductive film 122 is in an electrically floating state.

The insulating layer 130 is provided so as to cover the semiconductor layers 111N to 113N, the conductive film 12, the insulating layer 102, and the like. The insulating layer 130 is made of an insulating material such as silicon oxide, and has a thickness of about 50 nm to 1000 nm.

The electrode 131 is provided on the semiconductor layer 111N so as to be electrically connected to the semiconductor layer 111N. The electrode 131 is formed so as to penetrate the insulating layer 130 and is connected to a conductive film 141 provided on the insulating layer 130. The conductive film 141 is led to the bit line BL. Similarly, the electrode 132 is provided on the semiconductor layer 112N so as to be electrically connected to the semiconductor layer 112N. The electrode 132 is formed so as to penetrate the insulating layer 130 and is connected to a conductive film 142 provided on the insulating layer 130. The conductive film 142 is led to one end of the resistance element 22A. The electrodes 131 and 132 are made of, for example, tungsten (W), and the conductive films 141 and 142 are made of, for example, aluminum (Al).

In the memory element 21A as shown in FIG. 3A, the resistance value between the electrodes 131 and 132 is high. When a stress voltage is applied between the electrodes 131 and 132 in such a write operation to such a memory element 21A, filaments F are formed on the surfaces of the semiconductor layers 111N, 110P, and 112N as shown in FIG. 3B. The Specifically, first, a current flows between the electrodes 131 and 132 due to the stress voltage between the electrodes 131 and 132, and heat is generated. A part of the electrodes 131 and 132 is melted by this heat generation to form a filament F. That is, the filament F contains a conductive material. Therefore, after the writing operation, the resistance value between the electrodes 131 and 132 becomes low. As described above, in the memory element 21A, the resistance state is changed from the high resistance state to the low resistance state by forming the filament F in the writing operation.

The storage element 21A has been described above as an example, but the same applies to the storage element 21B. However, in order to make the threshold value VthA of the memory element 21A lower than the threshold value VthB of the memory element 21B, the memory element 21A is configured so that, for example, heat is less likely to escape than the memory element 21B. . Thereby, in the memory element 21A, the filament F can be easily formed in the writing operation as compared with the memory element 21B, and thus the threshold value VthA can be lowered. Specifically, for example, the areas of the conductive films 141 and 142 connected to the storage element 21A can be made smaller than the areas of the conductive films 141 and 142 connected to the storage element 21B. Further, the volume (active volume) of the semiconductor layer 110P in the memory element 21A can be made smaller than the volume of the semiconductor layer 110P in the memory element 21B.

Further, the distance L between the semiconductor layer 111N and the semiconductor layer 112N in the memory element 21A may be shorter than the distance L between the semiconductor layer 111N and the semiconductor layer 112N in the memory element 21B. Thereby, in the memory element 21A, since the electric field is stronger than in the memory element 21B, the filament F can be more easily formed, and the threshold value VthA can be lowered.

Also, for example, the threshold value VthA of the memory element 21A may be made lower than the threshold value VthB of the memory element 21B by forming the memory elements 21A and 21B under different process conditions. In this case, it is necessary to add or change the manufacturing process.

One end of the resistance element 22A (FIG. 2) is connected to the other end of the memory element 21A, and the other end is connected to the other end of the resistance element 22B and to the drain of the selection transistor 23. One end of the resistance element 22B is connected to the other end of the memory element 21B, and the other end is connected to the other end of the resistance element 22A and to the drain of the selection transistor 23. The resistance elements 22A and 21B are made of, for example, polysilicon. However, the present invention is not limited to this, and instead of this, for example, a so-called diffused resistor or ballast resistor may be used. In this example, the resistance value of the resistance element 22A is made equal to the resistance value of the resistance element 22B. The resistance value R of the resistance elements 22A and 22B is set so as to satisfy the following expression using the resistance value Rtrm in the low resistance state of the memory elements 21A and 21B and the resistance value Ron in the on state of the selection transistor 23. .
Rtrm + R >> Ron (1)
Thereby, as will be described later, the filament F can be easily formed in the memory element 21B.

The selection transistor 23 is an N-type MOS transistor in this example, the drain is connected to the other end of the resistance element 22A and the other end of the resistance element 22B, the gate is connected to the word line WL, and the source is connected to the source line SL. It is connected. The gate width W of the selection transistor 23 is, for example, 40 [μm].

The word line driving unit 11 (FIG. 1) controls a writing operation and a reading operation in the memory cell array 10 by driving the word line WL. Specifically, in this example, the word line driving unit 11 sets the voltage of the word line WL to a high level, thereby including one row (one word) including the memory cells 20 targeted for the writing operation and the reading operation. ) Is to be selected.

The bit line driving unit 12 controls the writing operation in the memory cell array 10 by driving the bit line BL. Specifically, the bit line driving unit 12 sets the voltage VBL of the bit line BL to the positive voltage VW (VW> 0), and thus becomes a target of the writing operation in the selected one row. While the memory cell 20 is selected, a stress voltage is applied to the storage elements 21A and 21B of the memory cell 20. The voltage VW can be 6 [V], for example. Further, the bit line driving unit 12 is configured to set the voltage VBL of all the bit lines BL to 0V when performing the read operation.

The sense amplifier 13 controls the read operation in the memory cell array 10 by driving the source line SL. Specifically, the sense amplifier 13 sets the voltage VSL of the source line SL to a positive voltage VR (VR> 0), and detects the read current IR flowing through the source line SL, thereby performing the read operation target. The information stored in the memory cell 20 is read out. The voltage VR can be set to 1.8 [V], for example. Further, the sense amplifier 13 sets the voltage VSL of all the source lines SL to 0V when performing the write operation.

With this configuration, in the memory cell 20 to be subjected to the write operation, the voltage VW (stress voltage) is applied to one end of the storage elements 21A and 21B, and the selection transistor 23 is provided to the other end of the resistance elements 22A and 22B. 0V is applied via As a result, the resistance states of the two memory elements 21A and 21B change from the high resistance state to the low resistance state. Thus, the memory cell 20 has redundancy. That is, for example, in the write operation, even if the resistance state of one of the two memory elements 21A and 21B cannot be changed to the low resistance state for some reason, the other resistance state is changed to the low resistance state. The resistance state of the entire memory cell 20 can be changed to a low resistance state by changing to. Further, for example, even when one of the two storage elements 21A and 21B is in an open state for some reason after changing the resistance state of the two storage elements 21A and 21B to the low resistance state, the memory The resistance state of the entire cell 20 can be set to a low resistance state. As described above, since the memory device 1 has redundancy, it is possible to reduce the possibility of losing data even if an unexpected situation occurs.

In the memory cell 20 to be read, 0 V is applied to one end of the memory elements 21A and 21B, and the voltage VR is applied to the other end of the resistance elements 22A and 22B via the selection transistor 23. . Thereby, in memory cell 20, read current IR corresponding to the resistance state in memory elements 21A and 21B is generated. That is, when both of the resistance states of the memory elements 21A and 21B are in the high resistance state, the resistance state of the entire memory cell 20 is in the high resistance state, so that the read current IR becomes small. On the other hand, when the resistance state of at least one of the memory elements 21A and 21B is the low resistance state, the resistance state of the entire memory cell 20 is the low resistance state, and thus the read current IR becomes large. The sense amplifier 13 reads the information stored in the memory cell 20 by detecting the read current IR.

Here, the memory elements 21A and 21B correspond to a specific example of “antifuse” in the present disclosure.

[Operation and Action]
Next, the operation and action of the memory device 1 of the present embodiment will be described.
(Overview of overall operation)
First, an overall operation overview of the memory device 1 will be described with reference to FIG. In the write operation, the word line drive unit 11 controls the write operation in the memory cell array 10 by driving the word line WL. The bit line driving unit 12 controls the writing operation in the memory cell array 10 by driving the bit line BL. In the memory cell 20 that is the target of the write operation, the voltage VW (stress voltage) is applied to one end of the memory elements 21A and 21B, and 0 V is applied to the other end of the resistance elements 22A and 22B via the selection transistor 23. Applied. As a result, the resistance states of the two memory elements 21A and 21B change from the high resistance state to the low resistance state, and information is written into the memory cell 20.

In the read operation, the word line driving unit 11 controls the read operation in the memory cell array 10 by driving the word line WL. The sense amplifier 13 controls the read operation in the memory cell array 10 by driving the source line SL. In the memory cell 20 to be read, 0 V is applied to one end of the memory elements 21A and 21B, and the voltage VR is applied to the other end of the resistance elements 22A and 22B via the selection transistor 23. Thereby, in memory cell 20, read current IR corresponding to the resistance state in memory elements 21A and 21B is generated. The sense amplifier 13 reads the information stored in the memory cell 20 by detecting the read current IR.

(Write operation)
Next, the write operation for the memory cell 20 will be described in detail.

FIG. 4 shows a timing waveform diagram of the memory cell 20 in the write operation. 5A and 5B show a write operation to the memory cell 20, FIG. 5A shows a state at a certain timing, and FIG. 5B shows a state at a later timing than FIG. 5A. 5A and 5B, the selection transistor 23 is shown as a switch indicating an on / off state.

In the write operation, the sense amplifier 13 sets the voltage VSL of the source line SL to 0 V, and the bit line driving unit 12 sets the voltage VBL of the bit line BL to the voltage VW as shown in FIG. At this time, the voltage VBL changes with a time constant corresponding to the resistance component and load of the bit line BL itself.

At timing t1, when the voltage VBL of the bit line BL reaches the threshold value VthA of the storage element 21A, as shown in FIG. 5A, a large write current is sequentially applied to the storage element 21A, the resistance element 22A, and the selection transistor 23. IWA flows. That is, at this time, the filament F is formed in the memory element 21A, and the resistance state of the memory element 21A changes from the high resistance state to the low resistance state (resistance value Rtrm). Thereafter, as shown in FIG. 4, the current value of the write current IWA decreases and becomes a value corresponding to the resistance value Rtrm in the low resistance state.

Next, when the voltage VBL of the bit line BL reaches the threshold value VthB of the storage element 21B at the timing t2, as shown in FIG. 5B, the large write is performed in the order of the storage element 21B, the resistance element 22B, and the selection transistor 23. Current IWB flows. That is, at this time, the filament F is formed in the memory element 21B, and the resistance state of the memory element 21B changes from the high resistance state to the low resistance state (resistance value Rtrm). Thereafter, as shown in FIG. 4, the current value of the write current IWB decreases and becomes a value corresponding to the resistance value Rtrm in the low resistance state.

Thus, the write current IWA and the write current IWB flow through the memory circuit 20. In other words, the write current IW (= IWA + IWB) (FIG. 4) that is the sum of the write current IWA and the write current IWB flows through the selection transistor 23. The driver of the bit line driving unit 12 supplies the write current IW to the memory circuit 20, and the sense amplifier 13 sinks the write current IW.

As described above, in the memory device 1, the threshold value VthA of the storage element 21A and the threshold value VthB of the storage element 21B are made different from each other. Thereby, in the memory device 1, the timing t1 at which the large write current IWA flows in the storage element 21A and the timing t2 at which the large write current IWB flows in the storage element 21B can be shifted. As a result, the memory device 1 can keep the peak value of the write current IW (= IWA + IWB) low as shown in FIG.

That is, for example, if the threshold value VthA of the memory element 21A and the threshold value VthB of the memory element 21B are equal to each other, the filament F is formed in the memory elements 21A and 21B at the same timing. Large write currents IWA and IWB flow at the same timing. That is, the peak value of the write current IW (= IWA + IWB) becomes large. Therefore, it is necessary to increase the gate width W of the select transistor 23 so that such a large write current can flow, and the size of the memory cell may be increased. Furthermore, since it is necessary for the driver of the bit line driving unit 12 and the sense amplifier 13 to handle such a large write current, the size of the bit line driving unit 12 and the sense amplifier 13 is increased. There is a fear.

On the other hand, in the memory device 1, since the threshold value VthA of the storage element 21A and the threshold value VthB of the storage element 21B are made different from each other, the timing at which the large write currents IWA and IWB flow can be shifted from each other. The peak value of the write current IW can be kept low. As a result, in the memory device 1, the gate width W of the selection transistor 23 can be reduced, and the size of the memory cell 20 can be reduced. Further, the size of the bit line driving unit 12 and the sense amplifier 13 can be reduced.

As described above, in order to shift the timings when the large write currents IWA and IWB flow from each other, it is necessary to consider, for example, process variations in the manufacturing process at the design stage.

FIG. 6 shows a distribution DA at a timing t1 when the write current IWA reaches a peak and a distribution DB at a timing t2 when the write current IWB reaches a peak. Considering process variations in the manufacturing process, the timing t1 is distributed as a distribution DA, and similarly, the timing t2 is distributed as a distribution DB. In such a case, it is desirable that the distribution DA and the distribution DB do not overlap on the time axis. Furthermore, it is preferable to provide a margin M so that the distribution DA and the distribution DB do not overlap on the time axis. Thereby, for example, even when the process varies, the timings at which the large write currents IWA and IWB flow can be shifted from each other.

In the memory device 1, the resistance element 22A is connected to the memory element 21A having a low threshold value. Thereby, for example, as shown in FIG. 5A, even when the filament F is formed in the memory element 21A and the resistance state of the memory element 21A becomes the low resistance state (resistance value Rtrm), Since the voltage difference between both ends can be maintained at a large value, the filament F can be formed in the memory element 21B. That is, for example, when the resistance element 22A is not provided, when the resistance state of the memory element 21A becomes a low resistance state (resistance value Rtrm), the voltage difference between both ends of the memory element 21B decreases. In this case, the filament F may not be formed in the memory element 21B, and the significance of redundancy is lost. On the other hand, in the memory device 1, since the resistance element 22A is provided, the filament F can be easily formed in the memory element 21B.

Specifically, for example, the voltage VBL of the bit line BL is set to 6 [V], the resistance value Ron in the ON state of the selection transistor 23 is set to 150 [Ω], and the resistance value Rtrm in the low resistance state of the storage element 21A is set to 1 k. When [Ω] is set and the resistance value R of the resistance element 22A is 3 k [Ω], the voltage difference between one end of the memory element 21A and the other end of the resistance element 22A is 5.8 [V]. In this way, by setting the resistance value R of the resistance element 22A to the resistance value R that satisfies Equation 1, the voltage difference between both ends of the memory element 21B can be maintained at a large value. For example, when the resistance element 22A having a resistance value R of 3 k [Ω] is configured using polysilicon having a sheet resistance of 2 k [Ω / □], the size of the resistance element 22A is, for example, a width of 3 The size is [μm] and the length is [2 μm]. In other words, even if such a resistance element 22A is provided, the element size is sufficiently smaller than the element size of the selection transistor 23, and thus the influence on the size of the memory cell 20 is small. That is, by providing the resistance element 22A, it is possible to easily form the filament F in the memory element 21B while suppressing the influence on the size of the memory cell 20. If the resistance value R of the resistance element 22A is too large, it is difficult to form the filament F in the memory element 21A. Therefore, it is desirable that the resistance value R of the resistance element 22A satisfies the expression 1 and can form the filament F in the memory element 21A.

Further, in the memory device 1, the resistance element 22B having the same resistance value R as that of the resistance element 22A is provided, so that the design can be facilitated. That is, the timing t1 at which the write current IWA reaches a peak is affected not only by the threshold value VthA of the storage element 21A but also by the resistance value of the resistance element 22A. Similarly, the timing t2 at which the write current IWB reaches its peak is influenced not only by the threshold value VthB of the storage element 21B but also by the resistance value of the resistance element 22B. In the memory device 1, since the resistance values of the resistance elements 22A and 22B are equal to each other, the influence of the resistance elements 22A and 22B on the timing difference between the timing t1 and the timing t2 can be reduced, so that the design is facilitated. Can do.

(Read operation)
In the memory cell 20 in which the writing operation is not performed, both the resistance states of the memory elements 21A and 21B are in the high resistance state (case C1). On the other hand, in the memory cell 20 in which the writing operation has been performed, both the resistance states of the memory elements 21A and 21B are in the low resistance state (case C3). For example, when the write operation is performed but the write operation is insufficient, one of the resistance states of the memory elements 21A and 21B is the high resistance state and the other resistance state. May be in a low resistance state (Case C2). Further, after one of the storage elements 21A and 21B is opened for some reason after the writing operation is normally performed and the resistance state of both of the storage elements 21A and 21B is changed to the low resistance state. Corresponds to this case C2. Hereinafter, the reading operation in these cases C1 to C3 will be described.

FIGS. 7A to 7C show the read operation for the memory cell 20, FIG. 7A shows the case of case C1, FIG. 7B shows the case of case C2, and FIG. 7C shows the case of case C3. . Case C2 shown in FIG. 7B is a case where the resistance state of the memory element 21A is the low resistance state and the resistance state of the memory element 21B is the high resistance state. 7A to 7C, the selection transistor 23 is shown as a switch indicating an on / off state. In this example, the resistance value Ron in the ON state of the selection transistor 23 is set to 150 [Ω], the resistance value in the high resistance state of the memory elements 21A and 21B is set to 10,000 [kΩ], and the resistance value in the low resistance state is set. Rtrm is set to 1 [kΩ], and the resistance value R of the resistance elements 22A and 22B is set to 3 k [Ω].

In the read operation, the bit line driving unit 12 sets the voltage VBL of the bit line BL to 0 V, and the sense amplifier 13 sets the voltage VSL of the source line SL to the voltage VR. Thereby, in memory cell 20, read current IR corresponding to the resistance state in memory elements 21A and 21B is generated. The sense amplifier 13 reads the information stored in the memory cell 20 by detecting the read current IR.

In the case C1, as shown in FIG. 7A, the total value of the resistance value of the memory element 21A and the resistance value of the resistance element 22A is 10,003 [kΩ] (= 10,000 [kΩ] +3 [kΩ]). The total value of the resistance value of the memory element 21B and the resistance value of the resistance element 22B is 10,003 [kΩ] (= 10,000 [kΩ] +3 [kΩ]). Therefore, the resistance value of the entire memory cell 20 is 5,003 [kΩ]. A read current IR corresponding to the resistance value flows through the memory cell 20. When the voltage VR is 1.8 V, the value of the read current IR is 0.4 [μA] (= 1.8 [V] / 5,003 [kΩ]).

In the case C2, as shown in FIG. 7B, the total value of the resistance value of the storage element 21A and the resistance value of the resistance element 22A is 4 [kΩ] (= 1 [kΩ] +3 [kΩ]). The total value of the resistance value of the element 21B and the resistance value of the resistance element 22B is 10,003 [kΩ] (= 10,000 [kΩ] +3 [kΩ]). Therefore, the resistance value of the entire memory cell 20 is 5 [kΩ]. The value of the read current IR when the voltage VR is 1.8 V is 360 [μA] (= 1.8 [V] / 5 [kΩ]). That is, in this example, the value of read current IR in case C2 is about 1,000 times the value of read current IR in case C1.

In the case C3, as shown in FIG. 7C, the total value of the resistance value of the storage element 21A and the resistance value of the resistance element 22A is 4 [kΩ] (= 1 [kΩ] +3 [kΩ]). The total value of the resistance value of the element 21B and the resistance value of the resistance element 22B is 4 [kΩ] (= 1 [kΩ] +3 [kΩ]). Therefore, the resistance value of the entire memory cell 20 is 3 [kΩ]. The value of the read current IR when the voltage VR is 1.8 V is 600 [μA] (= 1.8 [V] / 3 [kΩ]). That is, in this example, the value of the read current IR in case C3 is about 1,000 times the value of the read current IR in case C1.

FIG. 8 shows the read current IR in cases C1 to C3. As shown in FIG. 8, the read current IR is larger in cases C2 and C3 than in case C1. Therefore, the sense amplifier 13 sets a threshold current Ith between the read current IR in the case C1 and the read current IR in the cases C2 and C3, and compares the read current IR with the threshold current Ith, thereby Information written in the cell 20 can be read. Thereby, in the memory device 1, the resistance state of both the storage elements 21A and 21B is the high resistance state (case C1), or the resistance state of at least one of the storage elements 21A and 21B is the low resistance state. It is possible to determine whether there is (Case C2, C3). That is, in the memory device 1, as in case C2, in the write operation, only one of the storage elements 21A and 21B can be brought into the low resistance state due to some circumstances, or Even after one of the storage elements 21A and 21B is opened for some reason after the normal write operation, the read operation is performed as in the case where the normal write operation is performed (case C3). The current IR exceeds the threshold current Ith. As described above, since the memory device 1 has redundancy, it is possible to reduce the possibility of losing data even if an unexpected situation occurs.

Further, in the memory device 1, since the storage element 21A and the storage element 21B are connected in parallel via the resistance elements 22A and 22B, the configuration can be simplified. That is, as a memory device having redundancy, for example, a memory cell may be configured using one storage element and one selection transistor, and the same information may be stored in two memory cells. However, this configuration requires a determination circuit that determines that at least one of the write operations is performed based on information read from the two memory cells. Therefore, in this case, the configuration becomes complicated, and the size of the memory device may increase. On the other hand, in the memory device 1, since the storage element 21A and the storage element 21B are connected in parallel via the resistance elements 22A and 22B, if at least one of the storage elements 21 and 21B is in the low resistance state, the memory cell 20 The overall resistance state becomes a low resistance state. Therefore, since the determination circuit can be omitted, the configuration can be simplified and the size of the memory device 1 can be reduced.

(About the size of the memory device 1)
FIG. 9 shows the relationship between the size of the memory device and the number of bits of data that can be stored in the memory device. As shown in FIG. 9, generally, in a memory device, as the number of bits increases, the number of memory cells increases and the size of the entire memory device increases. Therefore, in a memory device having a large number of bits, the area ratio of the memory cell array in the entire memory device is large. In a memory device with a small number of bits, the area ratio occupied by portions other than the memory cell array (bit line driver, word line driver, sense amplifier, etc.) in the entire memory device is large.

As described above, in the memory device 1, since the peak value of the write current IW flowing through the memory cell 20 is suppressed, the sizes of the select transistor 25 (memory cell array 10), the bit line driving unit 12, and the sense amplifier 13 are reduced. Can be reduced. Furthermore, in the memory device 1, since the storage element 21A and the storage element 21B are connected in parallel via the resistance elements 22A and 22B, the determination circuit can be omitted. Thus, in the memory device 1, both the size of the memory cell array 10 and the size of the portion other than the memory cell array 10 can be reduced. As a result, the memory device 1 can reduce the size of the entire memory device regardless of whether the number of bits that can be stored is large or small.

[effect]
As described above, in the present embodiment, since the threshold values of the memory elements 21A and 21B are different from each other, the peak value of the write current can be kept low, and the selection transistor, the bit line driver, and the sense The size of the amplifier can be reduced. As a result, the size of the entire memory device can be reduced.

In this embodiment, since the memory element 21A and the memory element 21B are connected in parallel via the resistance elements 22A and 22B, the determination circuit can be omitted, so that the configuration can be simplified and the entire memory device is also provided. Can be reduced in size.

In this embodiment, since the resistance element is connected to the memory element having the lower threshold value of the two memory elements, the filament can be easily formed in the memory element having the higher threshold value.

[Modification 1-1]
In the above embodiment, the memory cell 20 is provided with the two resistance elements 22A and 22B. However, the present invention is not limited to this. For example, the resistance element 22B is omitted as in the memory cell 20A shown in FIG. Also good. In this case, the other end of the storage element 21B is connected to the other end of the resistance element 22A and to the drain of the selection transistor 23. Even if comprised in this way, the effect equivalent to the memory cell 20 which concerns on the said embodiment can be acquired.

[Modification 1-2]
In the above embodiment, the storage element 21A, the resistance element 22A, and the selection transistor 23 are connected in this order, and the storage element 21B, the resistance element 22B, and the selection transistor 23 are connected in this order. However, the present invention is not limited to this. Instead of this, for example, the memory element 21A and the resistive element 22A may be interchanged, and the memory element 21B and the resistive element 22B may be interchanged, as in the memory cell 20B illustrated in FIG. In the memory cell 20B, one end of the resistance element 22A is connected to one end of the resistance element 22B and the bit line BL, and the other end is connected to one end of the storage element 21A. One end of the resistance element 22B is connected to one end of the resistance element 22A and the bit line BL, and the other end is connected to one end of the storage element 21B. One end of the storage element 21A is connected to the other end of the resistance element 22A, and the other end is connected to the other end of the storage element 21B and to the drain of the selection transistor 23. One end of the storage element 21B is connected to the other end of the resistance element 22B, and the other end is connected to the other end of the storage element 21A and to the drain of the selection transistor 23.

[Modification 1-3]
In the above embodiment, the memory device 1 has the SOI structure as shown in FIG. 3A, but the present invention is not limited to this. FIG. 12 shows an example of a cross-sectional structure of a main part of the memory element 31 in the memory device 1C according to this modification. FIG. 12 shows the memory element 31 in the high resistance state, and corresponds to FIG. 3A according to the above embodiment. The memory element 31 is formed in a region surrounded by the element isolation insulating layer 102 on the P-type semiconductor substrate 100P. The memory element 31 includes a semiconductor layer 210P. The semiconductor layer 210P is a P-type semiconductor layer formed on the surface of the P-type semiconductor substrate 100P, and constitutes a so-called P-well. The semiconductor layer 210P functions as a so-called back gate of the memory element 31. In the semiconductor layer 210P, semiconductor layers 111N and 112N are formed as in the memory device 1 (FIG. 3A) according to the above embodiment.

[Modification 1-4]
In the above embodiment, the two storage elements 21A and 21B having different threshold values are connected in parallel. However, the present invention is not limited to this. For example, three or more storage elements having different threshold values are connected in parallel. You may connect. In this case, a resistance element may be connected in series to each storage element as in FIG. 2 or the like, or a resistance element may be connected in series to a storage element other than the storage element having the largest threshold value as in FIG. May be.

[Other variations]
Further, two or more of these modifications may be combined.

<2. Second Embodiment>
Next, the memory device 2 according to the second embodiment will be described. The memory device 2 stores a plurality of bit data in each memory cell. Note that components that are substantially the same as those of the memory device 1 according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.

FIG. 13 shows a configuration example of the memory device 2 according to the present embodiment. The memory device 2 includes a memory cell array 40 and a bit line driving unit 42.

The memory cell array 40 has a plurality of memory cells 50 arranged in a matrix. The memory cell array 40 includes a plurality of word lines WL extending in the row direction (lateral direction), a plurality of bit lines BLA and BLB and a plurality of source lines SL extending in the column direction (vertical direction). Yes. One end of each bit line BLA, BLB is connected to the bit line driving unit 42. Each memory cell 50 is connected to a word line WL, bit lines BLA and BLB, and a source line SL.

FIG. 14 shows a configuration example of the memory cell 50. The memory cell 50 includes storage elements 21A and 21B, resistance elements 22A and 22B, and a selection transistor 23. One end of the storage element 21A is connected to the bit line BLA, and the other end is connected to one end of the resistance element 22A. One end of the storage element 21B is connected to the bit line BLB, and the other end is connected to one end of the resistance element 22B. The threshold value VthA of the storage element 21A is set lower than the threshold value VthB of the storage element 21B, as in the case of the first embodiment.

The bit line driving unit 42 controls the writing operation and the reading operation in the memory cell array 40 by driving the bit lines BLA and BLB.

Specifically, in the write operation, the bit line driving unit 42 sets the voltage VBLA of the bit line BLA to the positive voltage VW (VW> 0), thereby writing in the selected one row. A memory element 21A of the memory cell 50 to be operated is selected, and a stress voltage is applied to the memory element 21A. Similarly, the bit line driving unit 42 sets the voltage VBLB of the bit line BLB to the positive voltage VW (VW> 0), thereby selecting the memory cell that is the target of the write operation in the selected row. 50 memory elements 21B are selected, and a stress voltage is applied to the memory element 21B.

In the read operation, the bit line drive unit 42 sets the voltage VBLA of the bit line BLA to 0 V and sets the bit line BLB in a floating state, so that the target of the read operation in one selected row is set. The memory element 21A of the memory cell 50 is selected. Similarly, the bit line driving unit 42 sets the bit line BLA in a floating state and sets the voltage VBLB of the bit line BLB to 0 V, so that the memory targeted for the read operation in the selected one row is set. The memory element 21B of the cell 50 is selected.

15A to 15C show a write operation on the memory cell 50, FIG. 15A shows a case where the write operation is performed only on the storage element 21A, and FIG. 15B shows only on the storage element 21B. FIG. 15C shows a case where the write operation is performed on both the storage elements 21A and 21B.

When the write operation is performed only on the memory element 21A, as shown in FIG. 15A, the sense amplifier 13 sets the voltage VSL of the source line SL to 0 V, and the bit line drive unit 42 The voltage VBLA of BLA is set to the voltage VW, and the voltage VBLB of the bit line BLB is set to 0V. Thereby, in the memory cell 50, the write current IWA flows in the order of the storage element 21A, the resistance element 22A, and the selection transistor 23, and the resistance state of the storage element 21A changes from the high resistance state to the low resistance state.

Similarly, when the write operation is performed only on the storage element 21B, the sense amplifier 13 sets the voltage VSL of the source line SL to 0 V and the bit line driving unit 42 is set as shown in FIG. 15B. The voltage VBLA of the bit line BLA is set to 0V, and the voltage VBLB of the bit line BLB is set to the voltage VW. Thereby, in the memory cell 50, the write current IWB flows in the order of the storage element 21B, the resistance element 22B, and the selection transistor 23, and the resistance state of the storage element 21B changes from the high resistance state to the low resistance state.

On the other hand, when the write operation is performed on both the storage elements 21A and 21B, the sense amplifier 13 sets the voltage VSL of the source line SL to 0 V as shown in FIG. 42 sets the voltages VBLA and VBLB of the bit lines BLA and BLB to the voltage VW, respectively. Thereby, in the memory cell 50, as in the memory cell 20 according to the first embodiment, first, a large write current IWA flows in the order of the storage element 21A, the resistance element 22A, and the selection transistor 23. The resistance state of 21A changes from the high resistance state to the low resistance state. After that, a large write current IWB flows through the memory element 21B, the resistance element 22B, and the selection transistor 23 in this order, and the resistance state of the memory element 21B increases. Changes from a resistance state to a low resistance state.

Thus, in the memory device 2, the bit lines BLA and BLB are provided, and one end of the storage element 21A is connected to the bit line BLA and one end of the storage element 21B is connected to the bit line BLB. One bit data can be stored.

In particular, in the memory device 2, when performing a write operation on both the storage elements 21A and 21B, the write operation can be performed in one cycle. At this time, since the threshold value VthA of the storage element 21A and the threshold value VthB of the storage element 21B are made different from each other, the timing t1 at which the large write current IWA flows in the storage element 21A and the large write value in the storage element 21B. The timing t2 at which the sink current IWB flows can be shifted. As a result, the peak value of the write current IW (= IWA + IWB) flowing through the selection transistor 23 can be suppressed, and the size of the selection transistor 23 can be reduced. Furthermore, the size of the sense amplifier 13 that sinks the write current IW can also be reduced.

16A and 16B show a read operation for the memory cell 50, FIG. 16A shows a case where the read operation is performed on the memory element 21A, and FIG. 16B shows a read operation on the memory element 21B. Show the case.

When the read operation is performed on the memory element 21A, as shown in FIG. 16A, the bit line drive unit 42 sets the voltage VBLA of the bit line BLA to 0V and sets the bit line BLB in a floating state. The amplifier 13 sets the voltage VSL of the source line SL to the voltage VR. Thereby, in the memory cell 50, the read current IR flows in the order of the selection transistor 23, the resistance element 22A, and the storage element 21A. The sense amplifier 13 reads the information stored in the storage element 21A of the memory cell 50 by detecting the read current IR.

When performing the read operation on the memory element 21B, as shown in FIG. 16B, the bit line drive unit 42 sets the bit line BLA to the floating state and sets the voltage VBLB of the bit line BLB to 0V. The sense amplifier 13 sets the voltage VSL of the source line SL to the voltage VR. Thereby, in the memory cell 50, the read current IR flows in the order of the selection transistor 23, the resistance element 22B, and the storage element 21B. The sense amplifier 13 reads the information stored in the storage element 21B of the memory cell 50 by detecting the read current IR.

As described above, in this embodiment, the bit lines BLA and BLB are provided, and one end of the storage element 21A is connected to the bit line BLA, and one end of the storage element 21B is connected to the bit line BLB. Two bit data can be stored. Other effects are the same as in the case of the first embodiment.

[Modification 2-1]
In the above embodiment, the memory cell 50 is configured using the two storage elements 21A and 21B. However, the present invention is not limited to this, and the memory cell may be configured using three or more storage elements. . Hereinafter, an example in which a memory cell is configured using three storage elements will be described in detail.

FIG. 17 illustrates a configuration example of the memory device 2A according to the present embodiment. The memory device 2A includes a memory cell array 40A and a bit line driving unit 42A.

The memory cell array 40A has a plurality of memory cells 50A arranged in a matrix. The memory cell array 40A includes a plurality of bit lines BLA, BLB, BLC extending in the column direction (vertical direction). One end of each bit line BLA, BLB, BLC is connected to the bit line drive unit 42A. Each memory cell 50A is connected to a word line WL, bit lines BLA, BLB, BLC, and a source line SL.

FIG. 18 shows a configuration example of the memory cell 50A. The memory cell 50A includes storage elements 21A, 21B, and 21C and resistance elements 22A, 22B, and 22C. One end of the storage element 21A is connected to the bit line BLA, and the other end is connected to one end of the resistance element 22A. One end of the storage element 21B is connected to the bit line BLB, and the other end is connected to one end of the resistance element 22B. One end of the storage element 21C is connected to the bit line BLC, and the other end is connected to one end of the resistance element 22C. One end of the resistance element 22A is connected to the other end of the memory element 21A, and the other end is connected to the other ends of the resistance elements 22B and 22C and to the drain of the selection transistor 23. One end of the resistance element 22B is connected to the other end of the memory element 22A, and the other end is connected to the other ends of the resistance elements 22A and 22C and to the drain of the selection transistor 23. One end of the resistance element 22C is connected to the other end of the storage element 21C, and the other end is connected to the other ends of the resistance elements 22A and 22B and to the drain of the selection transistor 23. The threshold value VthA of the storage element 21A is set lower than the threshold value VthB of the storage element 21B, and the threshold value VthB of the storage element 21B is set lower than the threshold value VthC of the storage element 21C. Yes.

Similarly to the bit line driving unit 42 according to the above embodiment, the bit line driving unit 42A controls the writing operation and the reading operation in the memory cell array 40A by driving the bit lines BLA, BLB, BLC. is there.

In this example, the three resistance elements 22A to 22C are provided. However, the present invention is not limited to this. For example, the memory cell 50B shown in FIG. 18 has the highest threshold among the memory elements 21A to 21C. The resistance element 22C connected to the storage element 21C having a high value may be omitted.

[Modification 2-2]
In the above embodiment, when the write operation is performed on the two storage elements 21A and 21B, the bit line driving unit 42 sets the voltage VBLA of the bit line BLA and the voltage VBLB of the bit line BLB to the voltage VW at the same time. However, the present invention is not limited to this. For example, the voltage setting timing may be shifted. In this case, the threshold values Vth of the storage elements 21A and 21B may be different from each other or may be equal to each other. Hereinafter, an operation example in the case where the threshold values Vth of the memory elements 21A and 21B are equal to each other in the memory device 2C according to the present modification will be described.

FIG. 20 shows an example of a write operation to the memory cell 50C of the memory device 2C. When the write operation is performed on both the storage elements 21A and 21B, the bit line drive unit 42C of the memory device 2C first sets the voltage VBLA of the bit line BLA to the voltage VW, and then the bit line The voltage VBLB of BLB is set to the voltage VW. At this time, the voltage VBLA changes with a time constant corresponding to the resistance component and load of the bit line BLA itself, and similarly, the voltage VBLB changes with a time constant corresponding to the resistance component and load of the bit line BLB itself. When the voltage VBLA of the bit line BLA reaches the threshold value Vth at the timing t11, a large write current IWA flows, and the resistance state of the memory element 21A changes from the high resistance state to the low resistance state. Similarly, when the voltage VBLB of the bit line BLB reaches the threshold value Vth at timing t12, a large write current IWB flows, and the resistance state of the memory element 21B changes from the high resistance state to the low resistance state. Even if comprised in this way, the effect equivalent to the memory cell 20 which concerns on the said embodiment can be acquired.

In this example, the two resistance elements 22A and 22B are provided. However, the present invention is not limited to this. For example, the resistance element 22B guided to the bit line BLB to which a voltage is set later may be omitted. .

The present technology has been described above with some embodiments and modifications. However, the present technology is not limited to these embodiments and the like, and various modifications are possible.

For example, in each of the embodiments described above, the storage elements 21A, 21B, etc. are not limited to the configuration shown in FIG. 3, but may be any antifuse such as those shown in Patent Documents 1 and 2, for example. Any configuration may be used.

It should be noted that the effects described in this specification are merely examples and are not limited, and other effects may be obtained.

Note that the present technology may be configured as follows.

(1) an antifuse inserted in each of a plurality of paths whose one ends are connected to each other;
A resistance element inserted in at least one of the plurality of paths;
A memory cell comprising: a selection transistor that connects a first connection terminal and the one end of the plurality of paths by being turned on.

(2) Each antifuse has a first terminal and a second terminal,
The resistance state of each antifuse changes from a high resistance state to a low resistance state when the potential difference between the first terminal and the second terminal of the antifuse exceeds a predetermined threshold value.
The memory cell according to (1), wherein the threshold values of the plurality of antifuses are different from each other.

(3) The memory cell according to (2), wherein the at least one of the plurality of paths is a path in which an antifuse having the lowest threshold is inserted.

(4) The memory cell according to (2), wherein the resistance element is inserted into each of the plurality of paths.

(5) The memory cell according to any one of (2) to (4), further including a single second connection terminal connected to the other end of the plurality of paths.

(6) The memory cell according to any one of (2) to (4), further including a plurality of second connection terminals respectively connected to the other ends of the plurality of paths.

(7) The resistance state of the plurality of antifuses is changed from a high resistance state to a low resistance state by applying stress voltages to the plurality of second connection terminals at equal timings. The memory cell described.

(8) The resistance state of each anti-fuse changes from a high-resistance state to a low-resistance state based on heat generated by current flowing between the first terminal and the second terminal of the anti-fuse. Yes,
The memory cell according to any one of (2) to (7), wherein heat dissipation properties of the plurality of antifuses are different from each other.

(9) Each antifuse is
A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type connected to the first terminal of the antifuse and provided on the surface of the first semiconductor layer;
A third semiconductor layer of the second conductivity type connected to the second terminal of the antifuse and provided on the surface of the first semiconductor layer and spaced apart from the second semiconductor layer;
The dielectric film provided on the surface of the first semiconductor layer in a separation region between the second semiconductor layer and the third semiconductor layer. The method according to any one of (2) to (8), Memory cells.

(10) Each antifuse is
The memory cell according to (9), further including a first conductive film provided on the dielectric film.

(11) The memory cell according to (9) or (10), wherein the first semiconductor layer is formed on a surface of a substrate and is surrounded by an insulating layer in the substrate.

(12) Each antifuse is
A second conductive film connected to the second semiconductor layer;
A third conductive film connected to the third semiconductor layer;
Further comprising
The memory cell according to any one of (9) to (11), wherein one or both of an area of the second conductive film and an area of the third conductive film in the plurality of antifuses is different from each other.

(13) The memory cell according to any one of (9) to (12), wherein volumes of the first semiconductor layers in the plurality of antifuses are different from each other.

(14) The memory cell according to any one of (9) to (13), wherein a distance between the second semiconductor layer and the third semiconductor layer in the plurality of antifuses is different from each other.

(15) further comprising a plurality of second connection terminals respectively connected to the other ends of the plurality of paths;
The memory state according to (1), wherein the resistance state of the plurality of antifuses is changed from a high resistance state to a low resistance state by applying stress voltages to the plurality of second connection terminals at different timings. cell.

(16) The memory cell according to (15), wherein the at least one path among the plurality of paths is a path having the earliest timing at which the stress voltage is applied.

(17) a memory cell;
A control unit for controlling the memory cell,
The memory cell is
An antifuse inserted into each of a plurality of paths connected at one end to each other;
A resistance element inserted in at least one of the plurality of paths;
A memory device comprising: a selection transistor that connects a first connection terminal and the one end of the plurality of paths by being turned on.

(18) The memory cell further includes a single second connection terminal connected to the other end of the plurality of paths,
Each antifuse has a first terminal and a second terminal,
The resistance state of each antifuse changes from a high resistance state to a low resistance state when the potential difference between the first terminal and the second terminal of the antifuse exceeds a predetermined threshold value.
The thresholds of the plurality of antifuses are different from each other,
The memory device according to (17), wherein the control unit changes a resistance state of the plurality of antifuses from a high resistance state to a low resistance state by applying a stress voltage to the second connection terminal.

(19) The memory cell further includes a plurality of second connection terminals respectively connected to the other ends of the plurality of paths.
Each antifuse has a first terminal and a second terminal,
The resistance state of each antifuse changes from a high resistance state to a low resistance state when the potential difference between the first terminal and the second terminal of the antifuse exceeds a predetermined threshold value.
The thresholds of the plurality of antifuses are different from each other,
The controller changes the resistance state of the plurality of antifuses from a high resistance state to a low resistance state by applying stress voltages to the plurality of second connection terminals at equal timings. The memory device described.

(20) The memory cell further includes a plurality of second connection terminals respectively connected to the other ends of the plurality of paths.
The controller changes the resistance state of the plurality of antifuses from a high resistance state to a low resistance state by applying stress voltages to the plurality of second connection terminals at different timings. The memory device described.

This application claims priority on the basis of Japanese Patent Application No. 2015-8603 filed on January 20, 2015 at the Japan Patent Office. The entire contents of this application are hereby incorporated by reference. Incorporated into.

Those skilled in the art will envision various modifications, combinations, subcombinations, and changes, depending on design requirements and other factors, which are within the scope of the appended claims and their equivalents. It is understood that

Claims (20)

An antifuse inserted into each of a plurality of paths connected at one end to each other;
A resistance element inserted in at least one of the plurality of paths;
A memory cell comprising: a selection transistor that connects a first connection terminal and the one end of the plurality of paths by being turned on. Each antifuse has a first terminal and a second terminal,
The resistance state of each antifuse changes from a high resistance state to a low resistance state when the potential difference between the first terminal and the second terminal of the antifuse exceeds a predetermined threshold value.
The memory cell according to claim 1, wherein the threshold values of the plurality of antifuses are different from each other. The memory cell according to claim 2, wherein the at least one path among the plurality of paths is a path in which an antifuse having the lowest threshold is inserted. The memory cell according to claim 2, wherein the resistance element is inserted into each of the plurality of paths. The memory cell according to claim 2, further comprising a single second connection terminal connected to the other end of the plurality of paths. The memory cell according to claim 2, further comprising a plurality of second connection terminals respectively connected to the other ends of the plurality of paths. The memory cell according to claim 6, wherein the resistance state of the plurality of antifuses is changed from a high resistance state to a low resistance state by applying a stress voltage to the plurality of second connection terminals at the same timing. . The resistance state of each antifuse changes from a high resistance state to a low resistance state based on heat generated by current flowing between the first terminal and the second terminal of the antifuse,
The memory cell according to claim 2, wherein heat dissipation properties of the plurality of antifuses are different from each other. Each antifuse is
A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type connected to the first terminal of the antifuse and provided on the surface of the first semiconductor layer;
A third semiconductor layer of the second conductivity type connected to the second terminal of the antifuse and provided on the surface of the first semiconductor layer and spaced apart from the second semiconductor layer;
The memory cell according to claim 2, further comprising: a dielectric film provided on a surface of the first semiconductor layer in a separation region between the second semiconductor layer and the third semiconductor layer. Each antifuse is
The memory cell according to claim 9, further comprising a first conductive film provided on the dielectric film. The memory cell according to claim 9, wherein the first semiconductor layer is formed on a surface of a substrate and is surrounded by an insulating layer in the substrate. Each antifuse is
A second conductive film connected to the second semiconductor layer;
A third conductive film connected to the third semiconductor layer;
Further comprising
The memory cell according to claim 9, wherein one or both of the area of the second conductive film and the area of the third conductive film in the plurality of antifuses is different from each other. The memory cell according to claim 9, wherein volumes of the first semiconductor layers in the plurality of antifuses are different from each other. The memory cell according to claim 9, wherein distances between the second semiconductor layer and the third semiconductor layer in the plurality of antifuses are different from each other. A plurality of second connection terminals respectively connected to the other ends of the plurality of paths;
The memory cell according to claim 1, wherein the resistance state of the plurality of antifuses is changed from a high resistance state to a low resistance state by applying stress voltages to the plurality of second connection terminals at different timings. . The memory cell according to claim 15, wherein the at least one path among the plurality of paths is a path having the earliest timing at which the stress voltage is applied. A memory cell;
A control unit for controlling the memory cell,
The memory cell is
An antifuse inserted into each of a plurality of paths connected at one end to each other;
A resistance element inserted in at least one of the plurality of paths;
A memory device comprising: a selection transistor that connects a first connection terminal and the one end of the plurality of paths by being turned on. The memory cell further includes a single second connection terminal connected to the other end of the plurality of paths,
Each antifuse has a first terminal and a second terminal,
The resistance state of each antifuse changes from a high resistance state to a low resistance state when the potential difference between the first terminal and the second terminal of the antifuse exceeds a predetermined threshold value.
The thresholds of the plurality of antifuses are different from each other,
The memory device according to claim 17, wherein the control unit changes a resistance state of the plurality of antifuses from a high resistance state to a low resistance state by applying a stress voltage to the second connection terminal. The memory cell further includes a plurality of second connection terminals respectively connected to the other ends of the plurality of paths.
Each antifuse has a first terminal and a second terminal,
The resistance state of each antifuse changes from a high resistance state to a low resistance state when the potential difference between the first terminal and the second terminal of the antifuse exceeds a predetermined threshold value.
The thresholds of the plurality of antifuses are different from each other,
The control unit changes a resistance state of the plurality of antifuses from a high resistance state to a low resistance state by applying stress voltages to the plurality of second connection terminals at equal timings. Memory device. The memory cell further includes a plurality of second connection terminals respectively connected to the other ends of the plurality of paths.
The control unit changes the resistance state of the plurality of antifuses from a high resistance state to a low resistance state by applying stress voltages to the plurality of second connection terminals at different timings. Memory device.

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