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WO2016107033A1 - 一种电子设备和数据传输系统 - Google Patents

一种电子设备和数据传输系统 Download PDF

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Publication number
WO2016107033A1
WO2016107033A1 PCT/CN2015/077960 CN2015077960W WO2016107033A1 WO 2016107033 A1 WO2016107033 A1 WO 2016107033A1 CN 2015077960 W CN2015077960 W CN 2015077960W WO 2016107033 A1 WO2016107033 A1 WO 2016107033A1
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WO
WIPO (PCT)
Prior art keywords
pin
interface
electronic device
cpu
usb interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/077960
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English (en)
French (fr)
Inventor
雷振飞
孙伟
王向东
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xiaomi Inc
Original Assignee
Xiaomi Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xiaomi Inc filed Critical Xiaomi Inc
Priority to MX2015009296A priority Critical patent/MX353667B/es
Priority to BR112015016821A priority patent/BR112015016821A2/pt
Priority to RU2015129478A priority patent/RU2625442C2/ru
Priority to JP2016567114A priority patent/JP6149173B2/ja
Priority to KR1020157017517A priority patent/KR20160092481A/ko
Priority to US14/833,143 priority patent/US9984030B2/en
Publication of WO2016107033A1 publication Critical patent/WO2016107033A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]

Definitions

  • the present disclosure relates to the field of computer technologies, and in particular, to an electronic device and a data transmission system.
  • USB Universal Serial Bus
  • USB Type C interface devices the CC1 pin and VBUS (power) are connected through a resistor.
  • the voltage of VBUS is generally 5V, and the normal working voltage of the micro USB interface ID pin should be 1.8V, so for this type of USB Type C interface devices, when connected to a micro USB interface device via a patch cord, may cause damage to the micro USB interface device.
  • a first electronic device comprising a micro micro universal serial bus USB interface, a central processing unit CPU and a diode, wherein:
  • a pull-up circuit of the identity ID pin of the CPU is connected to a line between an ID pin of the CPU and an ID pin of the micro USB interface;
  • the diode is disposed on a line between an ID pin of the CPU and an ID pin of the micro USB interface, between the pull-up circuit and an ID pin of the micro USB interface;
  • the conduction direction of the diode is directed by the ID pin of the CPU to the ID pin of the micro USB interface.
  • a first resistor is serially connected to the line between the ID pin of the micro USB interface and the ID pin of the CPU.
  • the first resistor is disposed on a line between the pull-up circuit and an ID pin of the CPU.
  • the pull-up circuit includes a pull-up power supply and a second resistor.
  • the resistance of the second resistor is greater than a preset lower limit of resistance.
  • the voltage of the pull-up power supply is 1.8V.
  • the diode comprises a Schottky diode.
  • a data transmission system comprising a second electronic device and a first electronic device as described above, the second electronic device comprising a USB type Type C interface, wherein:
  • the USB Type C interface of the second electronic device is connected to the micro USB interface of the first electronic device through a patch cord.
  • the CC1 pin and the CC2 pin of the USB Type C interface are connected to the ID pin of the micro USB interface through the conversion cable;
  • a power supply VBUS pin of the USB Type C interface is connected to the VBUS pin of the micro USB interface through the conversion cable;
  • the D+ pin of the USB Type C interface is connected to the D+ pin of the micro USB interface through the conversion cable;
  • the ground GND pin of the USB Type C interface is connected to the GND pin of the micro USB interface through the conversion cable.
  • the first electronic device includes a micro USB interface, a CPU, and a diode, wherein a pull-up circuit of the ID pin of the CPU is connected to a line between the ID pin of the CPU and the ID pin of the micro USB interface, and the diode is set.
  • the conduction direction of the diode is directed by the ID pin of the CPU to the ID pin of the micro USB interface. The direction.
  • the diode can isolate the voltage of the VBUS from the voltage of the ID pin of the CPU, thereby Prevent damage to electronic equipment.
  • FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a data transmission system according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a data transmission system according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a data transmission system according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a data transmission system according to an embodiment of the present disclosure.
  • the first electronic device 200 and the second electronic device are 100.
  • the first electronic device 200 and the second electronic device are the first electronic device 200 and the second electronic device
  • micro USB interface ID pin 12 micro USB interface VBUS pin
  • an embodiment of the present disclosure provides an electronic device (which may be referred to as a first electronic device 100).
  • the first electronic device 100 includes a micro USB interface 1, a CPU (Central Processing Unit) 2, and Diode 3, where:
  • the pull-up circuit of the ID pin 21 of the CPU is connected to the line between the ID pin 21 of the CPU and the ID pin 11 of the micro USB interface; the diode 3 is disposed between the ID pin 21 of the CPU and the ID pin 11 of the micro USB interface.
  • the conduction direction of the diode 3 is directed by the ID pin 21 of the CPU to the direction of the ID pin 11 of the micro USB interface.
  • the first electronic device includes a micro USB interface, a CPU, and a diode, wherein a pull-up circuit of the ID pin of the CPU is connected to a line between the ID pin of the CPU and the ID pin of the micro USB interface, and the diode is set.
  • the conduction direction of the diode is directed by the ID pin of the CPU to the direction of the ID pin of the micro USB interface.
  • the diode can isolate the voltage of the VBUS from the voltage of the ID pin of the CPU, thereby Prevent damage to electronic equipment.
  • the embodiment of the present disclosure provides a first electronic device 100.
  • the first electronic device 100 includes a micro USB interface 1, a CPU (Central Processing Unit) 2, and a diode 3, where:
  • the pull-up circuit 4 of the ID pin 21 is connected to the line between the ID pin 21 of the CPU and the ID pin 11 of the micro USB interface;
  • the diode 3 is disposed between the ID pin 21 of the CPU and the ID pin 11 of the micro USB interface.
  • the upper side is located between the pull-up circuit 4 and the ID pin 11 of the micro USB interface; the conduction direction of the diode 3 is directed by the ID pin 21 of the CPU to the direction of the ID pin 11 of the micro USB interface.
  • the diode 3 has an electronic device with a current single-conduction characteristic.
  • the diode 3 may be a Schottky diode, and the Schottky diode has a strong forward (ie, conduction) conduction capability and a reverse (ie, opposite to the conduction direction) protection capability.
  • the first electronic device 100 can be a micro USB interface device, such as a mobile phone, a tablet, or the like.
  • the first electronic device 100 is provided with a micro USB interface 1, and the ID pin 11 of the micro USB interface is connected to the ID pin 21 of the CPU.
  • the ID pin 21 of the CPU in the first electronic device 100 is provided with a pull-up circuit 4 for pulling up the voltage of the ID pin 21 of the CPU, and the pull-up circuit 4 may be provided outside the CPU 2 or may be provided inside the CPU 2.
  • the connection point of the pull-up circuit 4 on the line connecting the ID pin 11 of the micro USB interface to the ID pin 21 of the CPU may be referred to as H, and the diode 3 may be disposed between the ID pin 11 of the micro USB interface between the H points.
  • the diode 3 can connect the voltage of the VBUS with the CPU.
  • the voltage of the ID pin 21 is isolated, and the voltage of the ID pin 21 of the CPU is not affected by the VBUS voltage and is not boosted to 5 V, so the first electronic device 100 is not damaged.
  • a first resistor 5 may be connected in series on the line between the ID pin 11 of the micro USB interface and the ID pin 21 of the CPU.
  • the first resistor 5 may be disposed at any position on the line between the ID pin 11 of the micro USB interface and the ID pin 21 of the CPU, and may be disposed between the diode 3 and the ID pin 21 of the CPU, or may be set. Between the diode 3 and the ID pin 11 of the micro USB interface. Through the setting of the first resistor 5, the ID pin 21 of the CPU can be further protected, the voltage at the ID pin 11 of the micro USB interface is large, and the diode 3 does not fail to block the reverse current very well, first The resistor 5 can further reduce the reverse current.
  • the pull-up circuit 4 includes a pull-up power supply 41 and a second resistor 42 .
  • the voltage of the pull-up power source 41 (which may be referred to as a pull-up voltage) may be 1.8V.
  • the second resistor 42 can be connected in series between the pull-up power source 41 and the H point.
  • the resistance of the second resistor 42 can be set to be greater than a preset lower limit of resistance.
  • the ID pin 21 of the CPU has an important function to identify the external electronic device accessed through the micro USB interface 1, that is, when there is an electronic device access, the voltage of the ID pin 21 of the CPU changes. Discover access to electronic devices.
  • its CC1 pin 71 is grounded through a resistor (which may be referred to as a third resistor 6), in order to increase the connection of this type of USB Type C interface device to the first electronic device 100 through the patch cord 8
  • the recognition rate of the micro USB interface 1 can set the resistance of the second resistor 42 to be greater than the specified lower limit of the resistance, and ensure the ID pin 21 of the CPU when the USB Type C interface device is connected to the first electronic device 100.
  • the magnitude of the voltage change thereby increasing the recognition rate.
  • the voltage detected by the ID pin 21 of the CPU is the voltage of the pull-up power source 41, such as 1.8V.
  • the micro USB interface 1 of the first electronic device 100 is connected to the USB Type C interface device of the above type through the patch cord 8, as shown in FIG. 2, the total resistance of the diode 3 and the third resistor 6 is formed opposite to the second resistor 42.
  • the divided voltage of the pull voltage, the ID pin 21 of the CPU detects the voltage divided by the total resistance of the diode 3 and the third resistor 6.
  • the ID pin 21 of the CPU can be used.
  • the detected voltage is controlled within 30% of the pull-up voltage, so that the first electronic device 100 can detect the access of the USB Type C interface device. Therefore, the lower limit of the resistance can be set based on this principle.
  • the first resistor 5 may be disposed on a line between the pull-up circuit 4 and the ID pin 21 of the CPU.
  • the first resistor 5 can be placed on the line between the pull-up circuit 4 and the ID pin of the CPU, that is, on the line between the H point and the ID pin of the CPU.
  • the voltage detected by the ID pin 21 of the CPU is the voltage of the pull-up power source 41 in the pull-up circuit 4, such as 1.8V.
  • the micro USB interface 1 of the first electronic device 100 is connected to the USB Type C interface device of the above type through the patch cord 8, as shown in FIG. 4, if the first resistor 5 is set between the H point and the ID pin 21 of the CPU. On the line, the CPU ID pin 21 detects the voltage divided by the total resistance of the diode 3 and the third resistor 6, however, if the first resistor 5 is placed between the H point and the ID pin 11 of the micro USB interface On the line, the first resistor 5 is divided with the diode 3 and the third resistor 6 and the second resistor 42 is divided, and the ID pin 21 of the CPU detects the total of the diode 3, the first resistor 5 and the third resistor 6.
  • the voltage divided by the resistor so that the first resistor 5 is disposed on the line between the H point and the ID pin 21 of the CPU, which is more advantageous for reducing the voltage detected by the ID pin 21 of the CPU at this time, and thus, the first electron Device 100 is more likely to detect access to this USB Type C interface device.
  • the first electronic device includes a micro USB interface, a CPU, and a diode, wherein a pull-up circuit of the ID pin of the CPU is connected to a line between the ID pin of the CPU and the ID pin of the micro USB interface, and the diode is set.
  • the conduction direction of the diode is directed by the ID pin of the CPU to the direction of the ID pin of the micro USB interface.
  • the diode can isolate the voltage of the VBUS from the voltage of the ID pin of the CPU, thereby Prevent damage to electronic equipment.
  • the embodiment of the present disclosure further provides a data transmission system, including a second electronic device 200 and a first electronic device 100 as described in the above embodiment, the second electronic device 200 includes a USB type Type C interface 7, wherein: The USB Type C interface 7 of the electronic device 200 is connected to the micro USB interface 1 of the first electronic device 100 via a patch cord 8.
  • the patch cord 8 can be a patch cord of a USB Type C interface and a micro USB interface.
  • the second electronic device 200 can be a USB Type C interface device, such as a USB flash drive, a USB speaker, or the like.
  • the second electronic device 200 can be any type of USB Type C interface device, and can be a type of USB Type C interface device that is connected to the VBUS through a resistor, as shown in FIG. 5, or can be the CC1 pin described above.
  • 71 A type of USB Type C interface device that is grounded through a resistor, as shown in Figure 6.
  • the CC1 pin 71 and the CC2 pin 72 of the USB Type C interface are connected to the ID pin 11 of the micro USB interface through the extension cable 8; the VBUS pin 73 of the USB Type C interface is passed through the adapter cable 8 Connect the VBUS pin 12 of the micro USB interface; the D-pin 74 of the USB Type C interface is connected to the D-pin 13 of the micro USB interface through the patch cable 8; the D+ pin 75 of the USB Type C interface is connected to the D+ of the micro USB interface through the patch cord 8 Pin 14; GND pin 76 of the USB Type C interface is connected to the GND pin 15 of the micro USB interface through the patch cable 8.
  • the first electronic device includes a micro USB interface, a CPU, and a diode, wherein a pull-up circuit of the ID pin of the CPU is connected to a line between the ID pin of the CPU and the ID pin of the micro USB interface, and the diode is set.
  • the conduction direction of the diode is directed by the ID pin of the CPU to the ID pin of the micro USB interface. The direction.
  • the diode can isolate the voltage of the VBUS from the voltage of the ID pin of the CPU, thereby It can prevent damage to electronic equipment.
  • a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
  • the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

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Abstract

一种电子设备和数据传输系统，属于计算机技术领域。第一电子设备（100）包括微型micro通用串行总线USB接口（1）、中央处理器CPU（2）和二极管（3），其中：所述CPU（2）的身份标识ID针（21）的上拉电路（4）连接于所述CPU（2）的ID针（21）与所述micro USB接口（1）的ID针（11）之间的线路上；所述二极管（3）设置于所述CPU（2）的ID针（21）与所述micro USB接口（1）的ID针（11）之间的线路上，位于所述上拉电路（4）与所述micro USB接口（1）的ID针（11）之间；所述二极管（3）的导通方向是由所述CPU（2）的ID针（21）指向所述micro USB接口（1）的ID针（11）的方向，可以防止电子设备损坏。

Description

一种电子设备和数据传输系统
本申请基于申请号为2014108510290、申请日为2014/12/31的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本公开涉及计算机技术领域，特别涉及一种电子设备和数据传输系统。
背景技术
随着计算机技术的飞速发展，各式各样的电子设备得到了广泛的应用，已经成为了人们日常工作、生活中非常重要的工具。为了方便在电子设备之间进行数据传输，人们为电子设备设计了各种类型的数据传输接口，USB(Universal Serial Bus，通用串行总线)接口是一种非常常用的数据传输接口。
随着技术的发展，USB接口出现了多种多样的类型，micro(微型)USB接口是一种非常常用的USB接口类型，尤其是用于手机、平板电脑等移动设备，USB Type(类型)C接口是一种最新制定的USB接口类型，在未来将取代micro USB接口。在未来的一段时间内，市场上将有USB Type C接口和micro USB接口两种接口的设备同时存在。USB Type C接口和micro USB接口的转接线可以为这两种不同接口的设备提供数据连接。在这种转接线中，一般将micro USB接口的ID(Identity，身份标识)针与USB Type C接口的CC1针(USB Type C接口中的一种针)、CC2针(USB Type C接口中的一种针)连接。
在某些USB Type C接口设备中CC1针和VBUS(电源)之间通过电阻连接，VBUS的电压一般为5V，而micro USB接口ID针的正常工作电压应该为1.8V，所以对于这类USB Type C接口设备，当与micro USB接口设备通过转接线连接时，可能会导致micro USB接口设备损坏。
发明内容
为了克服相关技术中存在的问题，本公开实施例提供了一种电子设备和数据传输系统。技术方案如下：
根据本公开实施例的第一方面，提供一种第一电子设备，所述第一电子设备包括微型micro通用串行总线USB接口、中央处理器CPU和二极管，其中：
所述CPU的身份标识ID针的上拉电路连接于所述CPU的ID针与所述micro USB接口的ID针之间的线路上；
所述二极管设置于所述CPU的ID针与所述micro USB接口的ID针之间的线路上，位于所述上拉电路与所述micro USB接口的ID针之间；
所述二极管的导通方向是由所述CPU的ID针指向所述micro USB接口的ID针的方向。
可选的，所述micro USB接口的ID针与所述CPU的ID针之间的线路上串接有第一电阻。
可选的，所述第一电阻设置于所述上拉电路与所述CPU的ID针之间的线路上。
可选的，所述上拉电路包括上拉电源和第二电阻。
可选的，所述第二电阻的阻值大于预设的阻值下限。
可选的，所述上拉电源的电压为1.8V。
可选的，所述二极管，包括肖特基二极管。
根据本公开实施例的第二方面，提供一种数据传输系统，包括第二电子设备和如上所述的第一电子设备，所述第二电子设备包括USB类型Type C接口，其中：
所述第二电子设备的USB Type C接口与所述第一电子设备的micro USB接口通过转接线相连接。
可选的，所述USB Type C接口的CC1针和CC2针通过所述转接线连接所述micro USB接口的ID针；
所述USB Type C接口的电源VBUS针通过所述转接线连接所述micro USB接口的VBUS针；
所述USB Type C接口的D-针通过所述转接线连接所述micro USB接口的D-针；
所述USB Type C接口的D+针通过所述转接线连接所述micro USB接口的D+针；
所述USB Type C接口的接地GND针通过所述转接线连接所述micro USB接口的GND针。
本公开实施例提供的技术方案带来的有益效果是：
本公开实施例中，第一电子设备包括micro USB接口、CPU和二极管，其中，CPU的ID针的上拉电路连接于CPU的ID针与micro USB接口的ID针之间的线路上，二极管设置于CPU的ID针与micro USB接口的ID针之间的线路上，位于上拉电路与micro USB接口的ID针之间，二极管的导通方向是由CPU的ID针指向micro USB接口的ID针的方向。这样，如果第一电子设备通过转接线与USB Type C接口设备连接，且在USB Type C接口设备中CC1针和VBUS连接，二极管可以将VBUS的电压与CPU的ID针的电压隔离，从而，可以防止电子设备损坏。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种电子设备的结构示意图；
图2是本公开实施例提供的一种数据传输系统的结构示意图；
图3是本公开实施例提供的一种电子设备的结构示意图；
图4是本公开实施例提供的一种数据传输系统的结构示意图；
图5是本公开实施例提供的一种数据传输系统的结构示意图；
图6是本公开实施例提供的一种数据传输系统的结构示意图。
图例说明
100、第一电子设备              200、第二电子设备
1、micro USB接口               2、CPU
3、二极管                      4、上拉电路
5、第一电阻                    6、第三电阻
7、USB Type C接口              8、转接线
11、micro USB接口的ID针        12、micro USB接口的VBUS针
13、micro USB接口的D-针        14、micro USB接口的D+针
15、micro USB接口的GND针       21、CPU的ID针
41、上拉电源                   42、第二电阻
71、USB Type C接口的CC1针      72、USB Type C接口的CC2针
73、USB Type C接口的VBUS针     74、USB Type C接口的D-针
75、USB Type C接口的D+针       76、USB Type C接口的GND针。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
实施例一
本公开实施例提供了一种电子设备(可称作第一电子设备100)，如图1所示，第一电子设备100包括micro USB接口1、CPU(Central Processing Unit，中央处理器)2和二极管3，其中：
CPU的ID针21的上拉电路连接于CPU的ID针21与micro USB接口的ID针11之间的线路上；二极管3设置于CPU的ID针21与micro USB接口的ID针11之间的线路上，位于上拉电路与micro USB接口的ID针11之间；二极管3的导通方向是由CPU的ID针21指向micro USB接口的ID针11的方向。
本公开实施例中，第一电子设备包括micro USB接口、CPU和二极管，其中，CPU的ID针的上拉电路连接于CPU的ID针与micro USB接口的ID针之间的线路上，二极管设置于CPU的ID针与micro USB接口的ID针之间的线路上，位于上拉 电路与micro USB接口的ID针之间，二极管的导通方向是由CPU的ID针指向micro USB接口的ID针的方向。这样，如果第一电子设备通过转接线与USB Type C接口设备连接，且在USB Type C接口设备中CC1针和VBUS连接，二极管可以将VBUS的电压与CPU的ID针的电压隔离，从而，可以防止电子设备损坏。
实施例二
本公开实施例提供了一种第一电子设备100，如图1所示，第一电子设备100包括micro USB接口1、CPU(Central Processing Unit，中央处理器)2和二极管3，其中：CPU的ID针21的上拉电路4连接于CPU的ID针21与micro USB接口的ID针11之间的线路上；二极管3设置于CPU的ID针21与micro USB接口的ID针11之间的线路上，位于上拉电路4与micro USB接口的ID针11之间；二极管3的导通方向是由CPU的ID针21指向micro USB接口的ID针11的方向。
其中，二极管3具有电流单向导通特性的电子器件。本实施例中，二极管3可以为肖特基二极管，肖特基二极管具有很强的正向(即导通方向)导通能力和反向(即与导通方向相反的方向)防护能力。
在实施中，第一电子设备100可以为micro USB接口设备，如手机、平板电脑等。第一电子设备100上设置有micro USB接口1，micro USB接口的ID针11与CPU的ID针21连接。第一电子设备100中对CPU的ID针21设置有上拉电路4，用于上拉CPU的ID针21的电压，上拉电路4可以设置在CPU2的外部也可以设置在CPU2内部。上拉电路4在micro USB接口的ID针11与CPU的ID针21的连线上的连接点可称为H，二极管3可以设置在micro USB接口的ID针11于H点之间。这样，当第一电子设备100通过转接线8与某个USB Type C接口设备连接，且在该USB Type C接口设备中CC1针通过电阻和VBUS连接时，二极管3可以将VBUS的电压与CPU的ID针21的电压隔离，CPU的ID针21的电压不会受到VBUS电压的影响，不会被提升到5V，所以，第一电子设备100不会受到损坏。
可选的，micro USB接口的ID针11与CPU的ID针21之间的线路上可以串接有第一电阻5。
在实施中，第一电阻5可以设置在micro USB接口的ID针11与CPU的ID针21之间的线路上的任意位置，可以设置在二极管3与CPU的ID针21之间，也可以设置在二极管3与micro USB接口的ID针11之间。通过第一电阻5的设置，可以进一步对CPU的ID针21进行保护，在micro USB接口的ID针11处电压较大，二极管3没有未能很好的阻断反向电流的情况，第一电阻5能够进一步降低反向电流。
可选的，如图1所示，上拉电路4包括上拉电源41和第二电阻42。其中，上拉电源41的电压(可称作上拉电压)可以为1.8V。第二电阻42可以串接在上拉电源41与H点之间。
可选的，可以设置第二电阻42的阻值大于预设的阻值下限。
在实施中，CPU的ID针21有一个重要的作用是对通过micro USB接口1接入的外部的电子设备进行识别，即当有电子设备接入时，通过CPU的ID针21电压的变化来发现电子设备的接入。对于某一类型的USB Type C接口设备，其CC1针71通过电阻(可称作第三电阻6)接地，为了提高这一类型USB Type C接口设备通过转接线8连接到第一电子设备100的micro USB接口1时的识别率，可以对第二电阻42的阻值进行设置，使其大于指定的阻值下限，保证此类USB Type C接口设备连接第一电子设备100时CPU的ID针21的电压变化幅度，从而提高识别率。经过对第二电阻42阻值的设置，当第一电子设备100的micro USB接口1未连接其它电子设备时，CPU的ID针21检测到的电压为上拉电源41的电压，如1.8V。当第一电子设备100的micro USB接口1通过转接线8连接上述类型的USB Type C接口设备时，如图2所示，二极管3和第三电阻6的总电阻与第二电阻42形成对上拉电压的分压，CPU的ID针21检测到的是二极管3和第三电阻6的总电阻所分的电压，如果第二电阻42的阻值足够大的话，则可以将CPU的ID针21检测到的电压控制在上拉电压的30％以内，这样，第一电子设备100则可以检测到此USB Type C接口设备的接入。所以，可以基于此原理进行阻值下限的设置。
可选的，如图3所示，第一电阻5可以设置于上拉电路4与CPU的ID针21之间的线路上。
在实施中，对于上述CC1针通过电阻接地的一类USB Type C接口设备，为了提高这一类型USB Type C接口设备通过转接线8连接到第一电子设备100的micro USB接口1时的识别率，可以将第一电阻5设置于上拉电路4与CPU的ID针之间的线路上，即设置于H点与CPU的ID针之间的线路上。这样，当第一电子设备100的micro USB接口1未连接其它电子设备时，CPU的ID针21检测到的电压为上拉电路4中上拉电源41的电压，如1.8V。当第一电子设备100的micro USB接口1通过转接线8连接上述类型的USB Type C接口设备时，如图4所示，如果将第一电阻5设置于H点与CPU的ID针21之间的线路上，CPU的ID针21检测到的是二极管3和第三电阻6的总电阻所分的电压，然而，如果将第一电阻5设置于H点与micro USB接口的ID针11之间的线路上，第一电阻5就会和二极管3、第三电阻6一起与第二电阻42分压，CPU的ID针21检测到的是二极管3、第一电阻5和第三电阻6的总电阻所分的电压，所以，将第一电阻5设置于H点与CPU的ID针21之间的线路上，更有利于降低此时CPU的ID针21检测到的电压，这样，第一电子设备100更容易检测到此USB Type C接口设备的接入。
本公开实施例中，第一电子设备包括micro USB接口、CPU和二极管，其中，CPU的ID针的上拉电路连接于CPU的ID针与micro USB接口的ID针之间的线路上，二极管设置于CPU的ID针与micro USB接口的ID针之间的线路上，位于上拉 电路与micro USB接口的ID针之间，二极管的导通方向是由CPU的ID针指向micro USB接口的ID针的方向。这样，如果第一电子设备通过转接线与USB Type C接口设备连接，且在USB Type C接口设备中CC1针和VBUS连接，二极管可以将VBUS的电压与CPU的ID针的电压隔离，从而，可以防止电子设备损坏。
实施例三
本公开实施例还提供了一种数据传输系统，包括第二电子设备200和如上述实施例所述的第一电子设备100，第二电子设备200包括USB类型Type C接口7，其中：第二电子设备200的USB Type C接口7与第一电子设备100的micro USB接口1通过转接线8相连接。
其中，转接线8可以为USB Type C接口与micro USB接口的转接线。
在实施中，第二电子设备200可以为USB Type C接口设备，如U盘、USB音箱等。第二电子设备200可以是任意类型的USB Type C接口设备，可以是上述的CC1针71通过电阻与VBUS连接的一类USB Type C接口设备，如图5所示，也可以是上述的CC1针71通过电阻接地的一类USB Type C接口设备，如图6所示。
可选的，如图5、图6所示，USB Type C接口的CC1针71和CC2针72通过转接线8连接micro USB接口的ID针11；USB Type C接口的VBUS针73通过转接线8连接micro USB接口的VBUS针12；USB Type C接口的D-针74通过转接线8连接micro USB接口的D-针13；USB Type C接口的D+针75通过转接线8连接micro USB接口的D+针14；USB Type C接口的GND针76通过转接线8连接micro USB接口的GND针15。
本公开实施例中，第一电子设备包括micro USB接口、CPU和二极管，其中，CPU的ID针的上拉电路连接于CPU的ID针与micro USB接口的ID针之间的线路上，二极管设置于CPU的ID针与micro USB接口的ID针之间的线路上，位于上拉电路与micro USB接口的ID针之间，二极管的导通方向是由CPU的ID针指向micro USB接口的ID针的方向。这样，如果第一电子设备通过转接线8与USB Type C接口设备连接，且在USB Type C接口设备中CC1针和VBUS连接，二极管可以将VBUS的电压与CPU的ID针的电压隔离，从而，可以防止电子设备损坏。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本公开的较佳实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (9)

  1. 一种第一电子设备，其特征在于，所述第一电子设备包括微型micro通用串行总线USB接口、中央处理器CPU和二极管，其中：
    所述CPU的身份标识ID针的上拉电路连接于所述CPU的ID针与所述micro USB接口的ID针之间的线路上；
    所述二极管设置于所述CPU的ID针与所述micro USB接口的ID针之间的线路上，位于所述上拉电路与所述micro USB接口的ID针之间；
    所述二极管的导通方向是由所述CPU的ID针指向所述micro USB接口的ID针的方向。
  2. 根据权利要求1所述的第一电子设备，其特征在于，所述micro USB接口的ID针与所述CPU的ID针之间的线路上串接有第一电阻。
  3. 根据权利要求2所述的第一电子设备，其特征在于，所述第一电阻设置于所述上拉电路与所述CPU的ID针之间的线路上。
  4. 根据权利要求1所述的第一电子设备，其特征在于，所述上拉电路包括上拉电源和第二电阻。
  5. 根据权利要求4所述的第一电子设备，其特征在于，所述第二电阻的阻值大于预设的阻值下限。
  6. 根据权利要求4所述的第一电子设备，其特征在于，所述上拉电源的电压为1.8V。
  7. 根据权利要求1所述的第一电子设备，其特征在于，所述二极管，包括肖特基二极管。
  8. 一种数据传输系统，其特征在于，包括第二电子设备和如权利要求1-7任一项所述的第一电子设备，所述第二电子设备包括USB类型Type C接口，其中：
    所述第二电子设备的USB Type C接口与所述第一电子设备的micro USB接口通过转接线相连接。
  9. 根据权利要求1所述的数据传输系统，其特征在于，所述USB Type C接口的CC1针和CC2针通过所述转接线连接所述micro USB接口的ID针；
    所述USB Type C接口的电源VBUS针通过所述转接线连接所述micro USB接口的VBUS针；
    所述USB Type C接口的D-针通过所述转接线连接所述micro USB接口的D-针；
    所述USB Type C接口的D+针通过所述转接线连接所述micro USB接口的D+针；
    所述USB Type C接口的接地GND针通过所述转接线连接所述micro USB接口的GND针。
PCT/CN2015/077960 2014-12-31 2015-04-30 一种电子设备和数据传输系统 Ceased WO2016107033A1 (zh)

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104881391B (zh) * 2015-06-10 2017-09-19 赛尔康技术（深圳）有限公司 一种USB Type‑C接口的识别电路
CN106887832B (zh) * 2015-12-16 2019-10-22 中兴通讯股份有限公司 一种保护终端芯片usb接口的电路
CN105630724B (zh) * 2016-01-27 2017-03-15 深圳慧能泰半导体科技有限公司 一种USB Type‑C系统控制电路
CN106502939B (zh) * 2016-09-23 2020-01-10 北京小米移动软件有限公司 一种usb转接头及数据传输设备
CN106774596B (zh) * 2017-01-20 2019-04-23 深圳市金立通信设备有限公司 一种电源管理电路、电子设备及电子设备控制方法
TWI662740B (zh) * 2018-01-09 2019-06-11 和碩聯合科技股份有限公司 外接式天線及無線通訊系統
CN110825682B (zh) * 2019-11-05 2022-08-02 维沃移动通信有限公司 一种usb控制方法和电子设备
CN111525349B (zh) * 2020-04-13 2021-07-30 深圳慧能泰半导体科技有限公司 一种充电线缆、充电装置以及充电线缆保护系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102065160A (zh) * 2010-12-02 2011-05-18 惠州Tcl移动通信有限公司 一种利用手机外接扬声器的电路
CN102778918A (zh) * 2011-05-09 2012-11-14 鸿富锦精密工业（深圳）有限公司 便携式电子装置
CN202798652U (zh) * 2012-06-27 2013-03-13 青岛海信移动通信技术股份有限公司 一种信号转换电路及接口转接设备
CN103138071A (zh) * 2011-12-02 2013-06-05 联想(北京)有限公司 一种usb接口插座

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6813650B1 (en) * 1999-10-26 2004-11-02 International Business Machines Corporation Multimode non-standard universal serial bus computer input device
JP5034466B2 (ja) * 2006-12-05 2012-09-26 株式会社ニコン デバイス機器、ホスト機器およびインターフェースシステム
JP4961999B2 (ja) * 2006-12-25 2012-06-27 株式会社ニコン 電子機器
TWI381276B (zh) * 2009-02-19 2013-01-01 Inventec Corp 電腦裝置
CN201638203U (zh) * 2010-04-30 2010-11-17 青岛海信移动通信技术股份有限公司 万能数据线
CN201733438U (zh) * 2010-07-15 2011-02-02 广东欧珀移动通信有限公司 一种耳机插拔检测电路
JP5742406B2 (ja) * 2011-04-08 2015-07-01 富士通株式会社 情報処理装置、接続方法、およびプログラム
CN103237189B (zh) * 2013-03-26 2016-01-13 小米科技有限责任公司 电子设备、mhl连接器、mhl系统和连接器检测方法
KR102048222B1 (ko) * 2013-05-21 2019-11-25 삼성전자주식회사 통신 시스템에서 외부 장치를 인식하는 장치 및 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102065160A (zh) * 2010-12-02 2011-05-18 惠州Tcl移动通信有限公司 一种利用手机外接扬声器的电路
CN102778918A (zh) * 2011-05-09 2012-11-14 鸿富锦精密工业（深圳）有限公司 便携式电子装置
CN103138071A (zh) * 2011-12-02 2013-06-05 联想(北京)有限公司 一种usb接口插座
CN202798652U (zh) * 2012-06-27 2013-03-13 青岛海信移动通信技术股份有限公司 一种信号转换电路及接口转接设备

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