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WO2016106879A1 - Substrat de réseau et dispositif d'affichage - Google Patents

Substrat de réseau et dispositif d'affichage Download PDF

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Publication number
WO2016106879A1
WO2016106879A1 PCT/CN2015/071044 CN2015071044W WO2016106879A1 WO 2016106879 A1 WO2016106879 A1 WO 2016106879A1 CN 2015071044 W CN2015071044 W CN 2015071044W WO 2016106879 A1 WO2016106879 A1 WO 2016106879A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
pixel unit
gate line
pixel
array substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/071044
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English (en)
Chinese (zh)
Inventor
衣志光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Publication of WO2016106879A1 publication Critical patent/WO2016106879A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of display technologies, and in particular to an array substrate and a display device.
  • TFT Thin Film Transistor
  • LCD Liquid Crystal Display
  • a gate line driver also called a gate line driver circuit
  • a data driver also called a data driving circuit
  • timing control Composed of a gamma voltage generator and a backlight.
  • the liquid crystal panel is composed of an array substrate, a color filter substrate, and a liquid crystal.
  • the data lines and the gate lines are formed on the array substrate, and the TFTs disposed at the intersections of the data lines and the gate lines are used to transmit the data signals output by the data driver to the pixel electrodes of the array substrate to drive the liquid crystals corresponding to the pixel electrodes.
  • the gate line driver connects the gate lines through the fan-shaped traces to provide gate line drive signals for the respective gate lines.
  • the gate line driving signals at each position have a certain RC Delay (resistance and capacitance delay), resulting in the end of the same gate line.
  • the driving time of the TFT is smaller than the driving time of the TFT of the initial stage.
  • the charging amount of the pixel electrode corresponding to the initial segment is larger than the charging amount of the pixel electrode corresponding to the last segment, and the pixel electrode corresponding to the initial segment may even be overcharged, so that the amount of light emitted by each sub-pixel unit in the same row is deviated. , reducing the display effect of the LCD.
  • a first aspect of the present invention provides an array substrate including a plurality of sub-pixel units arranged in an array and a gate line driver disposed on one side of the array substrate, wherein each sub-pixel unit is provided with a pixel electrode and a common electrode line.
  • the pixel electrode and the common electrode line portion form a storage capacitor opposite to each other;
  • the storage capacitor of each sub-pixel unit is away from the end near the gate line driver One end of the gate line driver is gradually reduced.
  • the ratio of the storage capacitance of the two is equal to The ratio of the actual charging duration of the pixel electrode is reciprocal.
  • the ratio of the sub-pixel unit having the smallest distance from the gate line driver and the storage capacitance of the sub-pixel unit having the largest distance from the gate line driver is:
  • T1 is the theoretical charging duration of each sub-pixel unit
  • T2 is the delay charging period of each sub-pixel unit
  • n is the number of sub-pixel units in the sub-pixel unit row.
  • the theoretical charging duration of each sub-pixel unit is a ratio of the display duration of each frame of image to the number of gate lines of the array substrate.
  • the delay duration of each sub-pixel unit is a product of a gate line resistance and a parasitic capacitance corresponding to the sub-pixel unit, and the parasitic capacitance is formed by a gate line, a source, and a drain.
  • a relative area of the pixel electrode and the common electrode line of each sub-pixel unit gradually decreases from an end near the gate line driver to an end away from the gate line driver.
  • a storage capacitor of a sub-pixel unit that is closer to the gate line driver and a storage capacitor of a sub-pixel unit that is farther from the gate line driver The difference is fixed.
  • the ratio of the storage capacitances of the two is the reciprocal of the ratio of the actual charging times of the two.
  • each sub-pixel unit row includes 5760 sub-pixel units.
  • the present invention brings about the following beneficial effects: in the technical solution of the embodiment of the present invention, in order to ensure that the charging effects of the pixel electrodes of the sub-pixel units in the same sub-pixel unit row are the same or approximately the same, the storage capacitance of each sub-pixel unit It can be gradually reduced from one end close to the gate line driver to one end away from the gate line driver.
  • the driving time of the TFT of each sub-pixel unit does not change, the size of the storage capacitor is different, and the storage capacity of the sub-pixel unit in which the driving time of the TFT is longer is larger.
  • the presence of a storage capacitor extends the time the pixel electrode is charged to a specified potential. By adjusting the size of the storage capacitor, the pixel electrodes of each sub-pixel unit in the same sub-pixel unit row can be charged to a specified potential, thereby ensuring the display effect of the display device.
  • a second aspect of the present invention provides a display device including the above array substrate and a color filter substrate mated with the array substrate.
  • 1 is a schematic structural view of an array substrate
  • FIG. 2 is a schematic structural view of a sub-pixel unit.
  • the present invention provides an array substrate.
  • the array substrate includes a plurality of arrayed sub-pixel units and a gate line driver disposed on one side of the array substrate.
  • each sub-pixel unit 1 is provided with a pixel electrode 7 and a common electrode line 8, and the pixel electrode 7 and the common electrode line 8 partially form a storage capacitor.
  • one gate line 3 is disposed corresponding to one sub-pixel unit row, and drives a thin film transistor (TFT) of each sub-pixel unit in the sub-pixel unit row.
  • TFT thin film transistor
  • Each of the TFTs is driven by the gate line 3 to turn on the source 5 and the drain 6 of the TFT, and the pixel electrode 7 connected to the drain 6 is supplied with an electric signal from the data line 4 perpendicular to the gate line 3 to charge the pixel electrode 7. .
  • the pixel electrode 7 and the common electrode have a certain potential difference, which can jointly drive the liquid crystal molecules in the display device to deflect.
  • the potentials of the pixel electrodes 7 are different everywhere, so that the degree of deflection of the liquid crystal molecules throughout the display device is different, and thus the display device can display an image.
  • the corresponding gate line driving signals of the respective sub-pixel units have a certain resistance-capacitance delay.
  • the resistance-capacitance delay is caused by the resistance of the gate line 3 itself and the parasitic capacitance in the sub-pixel unit, wherein the parasitic capacitance is the overlap of the source 5, the drain 6 and the gate line 3 of the TFT in the sub-pixel unit. Forming.
  • the resistor-capacitor delay will cause the driving time of the TFT of the sub-pixel unit farthest from the gate line driver to be smaller than the driving time of the TFT of the sub-pixel unit closest to the gate line driver, which may result in the farthest distance from the gate line driver.
  • the potential of the pixel electrode 7 of the pixel unit after charging does not reach the specified potential, and the pixel electrode 7 of the sub-pixel unit closest to the gate line driver may continue to charge after charging saturation, which affects the display effect of the display device.
  • the brightness of the sub-pixel unit in the same row may be different.
  • the display effect of the sub-pixel unit close to the gate line driver is white.
  • the storage capacitance of each sub-pixel unit may be close to the gate line driver. One end gradually decreases toward the end remote from the gate line driver.
  • the driving time of the TFT of each sub-pixel unit does not change, the size of the storage capacitor is different, and the storage capacity of the sub-pixel unit in which the driving time of the TFT is longer is larger.
  • the presence of a storage capacitor extends the time the pixel electrode is charged to a specified potential. By adjusting the size of the storage capacitor, the pixel electrodes of each sub-pixel unit in the same sub-pixel unit row can be charged to a specified potential, thereby ensuring the display effect of the display device.
  • the sub-pixel unit having the smallest distance from the gate line driver will be simply referred to as the first sub-pixel unit 1
  • the sub-pixel unit having the largest distance from the gate line driver will be simply referred to as the second sub-pixel unit 2 .
  • the storage capacitances of the first sub-pixel unit 1 and the second sub-pixel unit 2 in the same row of sub-pixel unit rows may be first determined. Then, according to the storage capacitance of the two sub-pixel units of the first end, the size of the storage capacitor of each sub-pixel unit located between the two sub-pixel units is determined by a gradual design. Specifically, in any two adjacent sub-pixel units of the same sub-pixel unit row, the storage capacitance of the sub-pixel unit closer to the gate line driver and the storage capacitance of the sub-pixel unit farther from the gate line driver The difference is fixed.
  • the ratio of the storage capacitances of the two sub-pixel units 1 and the second sub-pixel unit 2 should be the inverse of the ratio of the actual charging durations of the pixel electrodes of the two sub-pixel units 1 and the second sub-pixel unit 2 To adjust the charging effect of the pixel electrodes 7 of the first sub-pixel unit 1 and the second sub-pixel unit 2 by using the storage capacitor.
  • the actual charging duration of the first sub-pixel unit 1 is the driving duration of the gate line 3, that is, the theoretical charging duration of each sub-pixel unit.
  • the second sub-pixel unit 2 is away from the gate line driver, and is affected by the resistance-capacitance delay of the gate line 3 corresponding to the plurality of sub-pixel units including the first sub-pixel unit 1, and the actual charging of the second sub-pixel unit 2 is performed.
  • the duration should be the difference between the theoretical charging duration of each sub-pixel unit and the delayed charging duration of each sub-pixel unit. That is, the ratio of the storage capacitances of the first sub-pixel unit 1 and the second sub-pixel unit 2 should be:
  • T1 is the theoretical charging duration of each sub-pixel unit
  • T2 is the delay charging period of each sub-pixel unit
  • n is the number of sub-pixel units in the sub-pixel unit row.
  • the theoretical charging duration of each sub-pixel unit is a ratio of the display duration of each frame of image to the number of gate lines 3 of the array substrate.
  • the delay time of each sub-pixel unit is the resistance and the gate line 3 corresponding to the sub-pixel unit
  • the product of the capacitance, the parasitic capacitance is composed of the gate line 3, the source 5, and the drain 6.
  • the display time of each frame of the high definition display device is 1/60 second. Since the display driving method is progressive scanning, the theoretical charging time of each sub-pixel unit is 1/(60 ⁇ 1080).
  • the actual charging duration of the second sub-pixel unit 2 is:
  • the ratio of the storage capacitances of the first sub-pixel unit 1 and the second sub-pixel unit 2 is:
  • any two adjacent sub-pixel units of the same sub-pixel unit row may also be made.
  • the ratio of the storage capacitors of the two is the reciprocal of the ratio of the actual charging times of the two.
  • the storage capacitance of each sub-pixel unit can be adjusted by adjusting the relative areas of the pixel electrode 7 and the common electrode line 8. That is, in the same sub-pixel unit row, the relative areas of the pixel electrode 7 and the common electrode line 8 of each sub-pixel unit gradually decrease from one end close to the gate line driver to one end away from the gate line driver.
  • a second aspect of the present invention provides a display device including the above array substrate and a color filter substrate mated with the array substrate.
  • the display device can be a display device such as a liquid crystal television, a liquid crystal display, a mobile phone, or a tablet computer.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

L'invention concerne un substrat de réseau et un dispositif d'affichage, qui se rapportent au domaine technique de l'affichage et peuvent atténuer le phénomène d'incohérence au niveau de la quantité sortante de lumière d'unités de sous-pixel (1, 2) dans la même rangée. Le substrat de réseau comprend une pluralité d'unités de sous-pixel (1, 2) qui sont disposées dans un mode réseau et un pilote de ligne de grille disposé sur un côté du substrat de réseau. Les unités de sous-pixel (1, 2) comportent de manière correspondante des électrodes de pixel et des lignes d'électrode commune, et les électrodes de pixel et les lignes d'électrode commune sont partiellement opposées les unes aux autres de façon à former une capacité de stockage ; la capacité de stockage des unités de sous-pixel (1, 2) dans la même rangée d'unités de sous-pixel est progressivement réduite de l'extrémité proche du pilote de ligne de grille à l'extrémité éloignée du pilote de ligne de grille. Le substrat de réseau peut être utilisé pour des télévisions à affichage à cristaux liquides, des dispositifs d'affichage à cristaux liquides, des téléphones mobiles, des tablettes électroniques et autres dispositifs d'affichage.
PCT/CN2015/071044 2014-12-31 2015-01-19 Substrat de réseau et dispositif d'affichage Ceased WO2016106879A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410856588.0A CN104464680B (zh) 2014-12-31 2014-12-31 一种阵列基板和显示装置
CN201410856588.0 2014-12-31

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WO2016106879A1 true WO2016106879A1 (fr) 2016-07-07

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WO (1) WO2016106879A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105825803B (zh) * 2016-05-06 2018-12-28 深圳市华星光电技术有限公司 显示装置
CN105974700B (zh) * 2016-06-30 2019-10-18 维沃移动通信有限公司 一种显示屏及电子设备
CN106297707A (zh) * 2016-09-06 2017-01-04 武汉华星光电技术有限公司 一种液晶显示面板及其驱动电路
CN106896606A (zh) * 2017-04-24 2017-06-27 武汉华星光电技术有限公司 一种显示面板及显示装置
CN106896607A (zh) * 2017-04-27 2017-06-27 武汉华星光电技术有限公司 一种阵列基板及显示装置
CN109491151A (zh) * 2018-12-17 2019-03-19 惠科股份有限公司 一种显示面板和显示装置
CN110109307A (zh) * 2019-04-28 2019-08-09 深圳市华星光电半导体显示技术有限公司 阵列基板及显示面板

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Publication number Priority date Publication date Assignee Title
TW432252B (en) * 1996-07-19 2001-05-01 Nippon Electric Co Liquid crystal display apparatus with uniform feed-through voltage in panel
CN1383497A (zh) * 2000-06-16 2002-12-04 松下电器产业株式会社 有源矩阵型显示装置及其驱动方法和显示元件
US20030098934A1 (en) * 2001-11-23 2003-05-29 Hsin-Ta Lee Liquid crystal display panel having reduced flicker
CN1971910A (zh) * 2005-11-22 2007-05-30 奇美电子股份有限公司 液晶显示装置、像素阵列基板及防止显示面板闪烁的方法
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CN104464680B (zh) 2018-01-23

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