WO2016104713A1 - 半導体装置用基板、半導体装置用配線部材及びそれらの製造方法、並びに、半導体装置用基板を用いた半導体装置の製造方法 - Google Patents
半導体装置用基板、半導体装置用配線部材及びそれらの製造方法、並びに、半導体装置用基板を用いた半導体装置の製造方法 Download PDFInfo
- Publication number
- WO2016104713A1 WO2016104713A1 PCT/JP2015/086254 JP2015086254W WO2016104713A1 WO 2016104713 A1 WO2016104713 A1 WO 2016104713A1 JP 2015086254 W JP2015086254 W JP 2015086254W WO 2016104713 A1 WO2016104713 A1 WO 2016104713A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- plating layer
- semiconductor device
- metal plating
- layer
- metal plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Images
Classifications
-
- H10P72/74—
-
- H10W70/095—
-
- H10W70/435—
-
- H10W70/60—
-
- H10W70/635—
-
- H10W70/69—
-
- H10W72/00—
-
- H10W72/073—
-
- H10W74/012—
-
- H10W74/019—
-
- H10W74/10—
-
- H10W74/15—
-
- H10W74/40—
-
- H10W90/701—
-
- H10W90/811—
-
- H10P72/7424—
-
- H10W70/65—
-
- H10W72/0198—
-
- H10W72/072—
-
- H10W72/07253—
-
- H10W72/234—
-
- H10W72/252—
-
- H10W72/884—
-
- H10W72/90—
-
- H10W74/00—
-
- H10W74/114—
-
- H10W90/724—
-
- H10W90/726—
-
- H10W90/734—
-
- H10W90/754—
Definitions
- the present invention relates to a substrate for a semiconductor device, a wiring member for a semiconductor device, a method of manufacturing the same, and a method of manufacturing a semiconductor device using the substrate for a semiconductor device.
- a substrate for a semiconductor device for example, an internal terminal is used on a metal plate which is a substrate, which is used for manufacturing a surface mount type sealing resin type semiconductor device having an ELP (Etched Leadless Package) structure.
- ELP Etched Leadless Package
- the external terminal and the wiring portion are formed by metal plating.
- Patent Document 1 a semiconductor device using such a type of substrate for a semiconductor device and a semiconductor device using the substrate for a semiconductor device are described, for example, in the following Patent Document 1.
- an external terminal surface having an external terminal portion is formed by plating on a metal plate from the metal plate side, and an intermediate layer is formed by plating in the same shape thereon, and further formed thereon.
- a substrate for a semiconductor device is disclosed in which the inner terminal surface having the inner terminal portion is plated in the same shape.
- the semiconductor device substrate is formed such that the internal terminal surface having the internal terminal portion electrically connected to the semiconductor element is the uppermost surface, and the height from the metal plate to the uppermost surface is almost the same. It is configured to be formed at the height.
- the external terminal surface is in contact with the surface on the metal plate side, and the internal terminal surface is exposed to the surface on the opposite side to the metal plate.
- the semiconductor element is mounted on the inner terminal surface side of the semiconductor device substrate, and after the electrode of the semiconductor element and the inner terminal portion are connected, the semiconductor element mounting portion is sealed with resin.
- the metal plate is removed by dissolution by etching etc., so that the external connection surface in the plating formation part is exposed with the internal terminal part, wiring part and external terminal part on the back surface of the sealed resin Make it Thereafter, a resin covering the entire exposed external connection surface is formed to form an opening where only the external terminal portion is exposed.
- the external terminal surface is formed from the metal plate side and the internal terminal surface is formed by plating in the uppermost layer
- variations in plating thickness occur.
- the plating thickness is about 30 ⁇ m Since a height difference of about 8 ⁇ m occurs, when the semiconductor element is mounted and electrically connected to the internal terminal portion, the semiconductor element may be mounted in an inclined state or conduction failure may occur in the electric connection. There is sex.
- the height difference due to production variation is the height of the internal terminal surface on which the semiconductor element is mounted in the uppermost layer and the internal terminal portion electrically connected to the semiconductor element.
- the internal terminal surface on which the semiconductor element is mounted and the internal terminal electrically connected to the semiconductor element are reduced by using a semiconductor element substrate which can make the height of the portion uniform and omit the step of forming the opening where only the external terminal portion is exposed.
- An object of the present invention is to provide a substrate for a semiconductor device capable of manufacturing a highly reliable resin-sealed semiconductor device and a method of manufacturing the same.
- the present invention is a wiring member for a semiconductor device which can make uniform the heights of an internal terminal surface on which the semiconductor device is mounted and an internal terminal portion electrically connected to the semiconductor device, and further a metal plate in the manufacturing process of the semiconductor device.
- the wiring member for a semiconductor device can omit the process of removing the etching and forming the opening where only the external terminal portion is exposed, thereby reducing the number of steps in manufacturing the semiconductor device and achieving a highly reliable resin-sealed type.
- An object of the present invention is to provide a wiring member for a semiconductor device capable of manufacturing a semiconductor device and a method of manufacturing the same.
- the present invention eliminates height differences due to variations in height of the internal terminal portions electrically connected to the semiconductor element, prevents inclination of the semiconductor element to be mounted, and finally causes conduction failure due to connection failure such as bonding. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of solving the problem and a method of manufacturing a semiconductor device capable of omitting the step of forming an opening where only the external terminal portion is exposed.
- a plating layer to be an internal terminal is formed at a predetermined portion on a predetermined surface, and an external terminal is partially formed on the plating layer to be the internal terminal.
- the height of the surface of the plating layer to be the external terminal from the predetermined surface is higher than the height of the surface of the other plating layer from the predetermined surface.
- the plating layer to be the internal terminal is a first noble metal plating layer formed on a predetermined portion on a metal plate, and the first noble metal plating layer A metal plating layer is formed on the first metal plating layer in the same shape as the first noble metal plating layer, and a plating layer to be the external terminal is formed of a second noble metal plating layer partially formed on the metal plating layer.
- the height of the surface of the second noble metal plated layer from the metal plate surface is higher than the height of the surface of the metal plated layer from the metal plate surface.
- the plating layer to be the internal terminal is a first noble metal plating layer formed on a predetermined portion on a metal plate, and the first noble metal plating layer A metal plating layer is formed on the first metal plating layer in the same shape as the first noble metal plating layer, and a plating layer to be the external terminal is formed of a second noble metal plating layer partially formed on the metal plating layer. And a resin layer is formed on the portion of the metal plate and the metal plating layer where the second noble metal plating layer is not formed, with the upper surface of the second noble metal plating layer exposed. .
- the plating layer to be the internal terminal is a first noble metal plating layer formed on a predetermined portion on a metal plate, and the first noble metal plating layer A metal plating layer is formed on the metal plating layer in the same shape as the first noble metal plating layer, and a permanent resist is formed on the metal plate and the metal plating layer, with a predetermined portion of the metal plating layer opened.
- the plating layer to be the external terminal is formed of a second noble metal plating layer formed on the metal plating layer located in the opening of the permanent resist.
- a second metal plating layer is formed between the metal plating layer and the second noble metal plating layer in the same shape as the second noble metal plating layer. It is formed.
- an Au plating layer as the first noble metal plating layer, a Pd plating layer, the metal plating layer, and the second metal plating are sequentially arranged from the metal plate side.
- a Ni plating layer as a layer, a Pd plating layer as the second noble metal plating layer, and an Au plating layer are formed.
- the permanent resist is formed to have an opening for exposing the upper surface of the second noble metal plating layer, and the second noble metal plating layer The upper surface of is located below the upper surface of the permanent resist.
- the wiring member for a semiconductor device according to the present invention is a wiring member for a semiconductor device manufactured using the substrate for a semiconductor device according to the present invention, wherein the plating layer to be the internal terminal is one surface of the resin layer. And the first noble metal plating layer formed on the first noble metal plating layer with the lower surface exposed flush with one surface of the resin layer, and the first noble metal plating layer on the first noble metal plating layer A metal plating layer is formed in the same shape as the layer, and a plating layer to be the external terminal is formed on the metal plating layer with the upper surface partially exposed from the other surface of the resin layer It is characterized in that it consists of the precious metal plating layer of 2.
- a second metal plating layer is formed between the metal plating layer and the second noble metal plating layer in the same shape as the second noble metal plating layer. It is formed.
- the Au plated layer as the first noble metal plated layer, the Pd plated layer, the metal plated layer, and the above-mentioned first noble metal plated layer are sequentially arranged from one surface side of the resin layer.
- a Ni plating layer as a second metal plating layer, a Pd plating layer as the second noble metal plating layer, and an Au plating layer are formed.
- a step of forming a resist mask having an opening of pattern A on a metal plate and a step of forming a first noble metal plating layer in the opening of pattern A A step of forming a metal plating layer in the same shape as the first noble metal plating layer on the first noble metal plating layer, a step of peeling the resist mask, and after peeling the resist mask, Forming a second resist mask having an opening of a pattern B in which a part of the metal plating layer is exposed; and forming a second noble metal plating layer or a second metal plating layer in the opening of the pattern B; Forming a noble metal plated layer of the second metal layer;
- a semiconductor device substrate preferably, after forming the second noble metal plating layer or the second metal plating layer and the second noble metal plating layer in the opening of the pattern B. And peeling the second resist mask, and after peeling the second resist mask, the metal plate and the metal plating layer on portions of the metal plating layer where the second noble metal plating layer is not formed. Forming a resin layer to expose the upper surface of the second noble metal plating layer.
- the second resist mask is made of a permanent resist.
- the upper surface of the second noble metal plated layer is located lower than the upper surface of the second resist mask.
- a method of manufacturing a wiring member for a semiconductor device according to the present invention is a method of manufacturing a wiring member for a semiconductor device manufactured using the method of manufacturing a substrate for a semiconductor device according to the present invention. After forming a second noble metal plating layer or a second metal plating layer and the second noble metal plating layer, a step of peeling the second resist mask, and after peeling the second resist mask Forming a resin layer on a portion of the metal plate and the metal plating layer where the second noble metal plating layer is not formed so as to expose the upper surface of the second noble metal plating layer; And removing the metal plate after the formation.
- a method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device manufactured using the substrate for a semiconductor device of the present invention, wherein a plating layer to be the internal terminal is formed on a metal plate, The plating layer to be the external terminal is partially formed on the plating layer, and the height of the plating layer surface to be the external terminal from the metal plate surface is higher than the height of the other plating layer from the metal plate surface Forming a resin layer in which the surface of the plating layer to be the external terminal is exposed using the substrate for a semiconductor device which is higher than the height, and a resin layer in which the surface of the plating layer to be the external terminal is exposed After the formation, the metal plate is removed, and a step of producing a wiring member in which the formed plating layer is held by the resin layer, and a step of mounting a semiconductor element on the produced wiring member are included. It features .
- a method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device manufactured using the substrate for a semiconductor device of the present invention, wherein a plating layer to be the internal terminal is formed on a metal plate, The plating layer to be the external terminal is partially formed on the plating layer, and the height of the plating layer surface to be the external terminal from the metal plate surface is higher than the height of the other plating layer from the metal plate surface
- a step of forming a resin layer in which the surface of the plating layer to be the external terminal is exposed is formed on the semiconductor device substrate which is higher than a height, and a resin layer in which the surface of the plating layer to be the external terminal is exposed is formed.
- the metal plate is removed, and a step of producing a wiring member in which the formed plating layer is held by the resin layer, and plating serving as the internal terminal which was the metal plate side of the produced wiring member Half on the side of the layer Step of mounting the body element, and comprising a.
- a method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device manufactured using the substrate for a semiconductor device of the present invention, wherein a plating layer to be the internal terminal is formed on a metal plate, The plating layer to be the external terminal is partially formed on the plating layer, and the height of the plating layer surface to be the external terminal from the metal plate surface is higher than the height of the other plating layer from the metal plate surface
- a step of forming a resin layer in which the surface of the plating layer to be the external terminal is exposed is formed on the semiconductor device substrate which is higher than a height, and a resin layer in which the surface of the plating layer to be the external terminal is exposed is formed.
- the metal plate is removed, and a step of producing a wiring member in which the formed plating layer is held by the resin layer, and plating serving as the internal terminal which was the metal plate side of the produced wiring member Half on the side of the layer
- a method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device manufactured using the above-described substrate for a semiconductor device of the present invention, wherein a permanent resist layer is formed on a metal plate with a predetermined thickness.
- a plating layer to be the internal terminal is formed facing the metal plate, and a plating layer to be the external terminal is partially formed on the plating layer to be the internal terminal,
- a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device manufactured using the above-described substrate for a semiconductor device of the present invention, wherein a permanent resist layer is formed on a metal plate with a predetermined thickness.
- a plating layer to be the internal terminal is formed on the metal plate side in a predetermined pattern, and a plating layer to be the external terminal is partially formed on the plating layer to be the internal terminal.
- the semiconductor element is mounted on the side of the prepared wiring member from which the metal plate is removed, and the portion of the plating layer to be the internal terminal exposed from the wiring member is electrically connected to the semiconductor element.
- performing a connection with, and the semiconductor element mounting side characterized in that it comprises the step of resin encapsulation, a.
- a first noble metal plating layer to be the internal terminal is formed on the metal plate in a predetermined pattern
- the metal plating layer is formed in the same shape as the first noble metal plating layer
- the second noble metal plating layer to be the external terminal is partially formed on the metal plating layer, or on the metal plating layer.
- the second metal plating layer and the second noble metal plating layer to be the external terminal are partially formed in the same shape, and the permanent resist is formed on the metal plate thicker than the plating layers. The surface of the second noble metal plating layer is exposed from the opening of the permanent resist.
- a plating layer of another metal is formed between the plating layer to be the internal terminal and the plating layer to be the external terminal.
- a substrate for a semiconductor device capable of making the height of the internal terminal surface on which the semiconductor device is mounted and the internal terminal portion electrically connected to the semiconductor device uniform, and reducing the number of steps in manufacturing the semiconductor device.
- a substrate for a semiconductor device capable of manufacturing a highly reliable resin-sealed semiconductor device capable of improving productivity can be obtained, and a method of manufacturing the same.
- it is a wiring member for a semiconductor element which can make uniform the heights of the internal terminal surface on which the semiconductor element is mounted and the internal terminal portion electrically connected to the semiconductor element.
- a wiring member for a semiconductor device that can omit the process of removing the metal plate by etching and forming the opening where only the external terminal portion is exposed, the number of steps in manufacturing the semiconductor device can be reduced, and the resin seal has high reliability.
- a wiring member for a semiconductor device capable of manufacturing a stationary semiconductor device and a method of manufacturing the same can be obtained.
- the difference in height due to the variation of the height of the internal terminal portion electrically connected to the semiconductor element is eliminated, the inclination of the mounted semiconductor element is prevented, and the conduction is finally made due to the connection failure such as bonding.
- a method of manufacturing a semiconductor device that can eliminate defects and a method of manufacturing a semiconductor device that can omit the step of forming an opening where only the external terminal portion is exposed can be obtained.
- FIGS. 2A to 2I are explanatory views showing manufacturing steps of the semiconductor device substrate shown in FIGS. 1A and 1B.
- 3A to 3E are plan views showing changes in the state of the semiconductor device substrate in the manufacturing steps of FIGS. 2A to 2I.
- 4A to 4G are explanatory views showing an example of a manufacturing process of a resin-sealed semiconductor device using the substrate for a semiconductor device of the first embodiment manufactured through the manufacturing steps shown in FIGS. 2A to 2I.
- FIGS. 5A and 5B are diagrams showing the configuration of the semiconductor device substrate according to the second embodiment of the present invention
- FIG. 5A is a plan view seen from the external terminal side
- FIG. 5B is a sectional view taken on line AA of FIG. is there.
- 7A to 7F are explanatory views showing an example of a manufacturing process of a resin-sealed semiconductor device using the semiconductor device substrate of the second embodiment manufactured through the manufacturing steps shown in FIGS. 6A to 6J ′.
- is there. 8A and 8B show the configuration of the semiconductor device substrate according to the third embodiment of the present invention, FIG.
- FIG. 8A is a plan view seen from the external terminal side
- FIG. 8B is a sectional view taken on line AA of FIG. is there.
- 9A to 9J are explanatory views showing a manufacturing process of the semiconductor device substrate shown in FIGS. 8A and 8B.
- 10A to 10G are explanatory views showing an example of a manufacturing process of a resin-sealed semiconductor device using the semiconductor device substrate of the third embodiment manufactured through the manufacturing steps shown in FIGS. 9A to 9J.
- . 11A and 11B are diagrams showing the configuration of a wiring member for a semiconductor device according to a fourth embodiment of the present invention, FIG. 11A is a plan view seen from the external terminal side, and FIG. 11B is a sectional view taken on line AA of FIG.
- FIGS. 12A to 12K are explanatory views showing the manufacturing process of the wiring member for a semiconductor device shown in FIGS. 11A and 11B.
- 13A to 13E are explanatory views showing an example of a manufacturing process of a resin-sealed semiconductor device using the wiring member for a semiconductor device of the fourth embodiment manufactured through the manufacturing steps shown in FIGS. 12A to 12K.
- 14A to 14E are explanatory views showing a manufacturing process of a conventional semiconductor device substrate according to Comparative Example 1.
- FIG. 15A to 15C are plan views showing changes in the state of the semiconductor device substrate in the manufacturing steps of FIGS. 14A to 14E.
- FIGS. 16A to 16L are explanatory views showing an example of a manufacturing process of a resin-sealed semiconductor device using the semiconductor device substrate of Comparative Example 1 manufactured through the manufacturing steps shown in FIGS. 14A to 14E.
- 17A to 17D are views showing steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention
- FIGS. 17A and 17A ′ are substrates for a semiconductor device used for manufacturing the semiconductor device of this embodiment.
- 17B and 17B ' are explanatory views showing the semiconductor device substrate shown in FIGS. 17A and 17A' and sealed with a resin so that the surface of the external terminal portion is exposed, FIG.
- FIG. 17C 17B is an explanatory view showing a state in which the metal plate is removed from the substrate for a semiconductor device shown in FIG. 17B to form a wiring member
- FIG. 17D mounts the semiconductor element on the plating layer side serving as an internal terminal of the wiring member shown in FIG.
- It is explanatory drawing which shows the state which connected the electrode of a semiconductor element, and the internal terminal part of the wiring member, and resin-sealed the side which mounts a semiconductor element.
- the semiconductor element is mounted on the plating layer side serving as the internal terminal of the wiring member shown in FIG.
- FIG. 20A to 20F are explanatory views showing an example of steps of a method of manufacturing a wiring member used in the method of manufacturing a semiconductor device according to the embodiment of FIG.
- a plating layer to be an internal terminal is formed at a predetermined site on a predetermined surface, and a plating layer to be an external terminal is partially formed on the plating layer to be an internal terminal
- the height of the surface of the plating layer from the predetermined surface is higher than the height of the surface of the other plating layer from the predetermined surface.
- the semiconductor device substrate according to the first aspect of the present invention is a semiconductor device substrate on which the semiconductor element is mounted after the metal plate is removed, and a predetermined portion on the metal plate is an internal terminal from the metal plate side.
- a first noble metal plating layer is formed, a metal plating layer is formed on the first noble metal plating layer in the same shape as the first noble metal plating layer, and a partial external terminal is formed on the metal plating layer.
- the noble metal plated layer of No. 2 is formed, and the height from the metal plate surface of the second noble metal plated layer is higher than the height from the metal plate surface of the metal plated layer.
- the internal terminal and the wiring portion have a thickness which corresponds to the opening of the resin layer provided in the manufacturing process of the semiconductor device in the conventional semiconductor device substrate. If different external terminals are provided in advance, it is possible to easily seal the internal terminals and the wiring portion with resin in the manufacturing process of the semiconductor device and expose only the external terminals. Therefore, unlike the conventional semiconductor device substrate, it is not necessary to provide an insulating layer having an opening on the connection surface with an external member in the manufacturing process of the semiconductor device, and the number of steps in manufacturing the semiconductor device is reduced accordingly. Improve productivity.
- the substrate for a semiconductor device is a substrate for a semiconductor device on which a semiconductor element is mounted after removing a metal plate, and a predetermined portion on the metal plate is provided with internal terminals from the metal plate side.
- Forming a first noble metal plating layer, forming a metal plating layer on the first noble metal plating layer in the same shape as the first noble metal plating layer, and partially forming an external terminal on the metal plating layer The resin layer is formed in a state in which the second noble metal plating layer is formed, and the upper surface of the second noble metal plating layer is exposed above the portion of the metal plate and the metal plating layer where the second noble metal plating layer is not formed. It is formed.
- the internal terminal and the wiring portion have a thickness corresponding to the opening portion of the resin layer provided in the manufacturing process of the semiconductor device in the conventional semiconductor device substrate. If different external terminals are provided in advance, and the internal terminals and the wiring portion are sealed with resin, and only the external terminals are exposed, unlike the conventional semiconductor device substrate, the connection surface with external members in the process of manufacturing the semiconductor device. It is not necessary to provide an insulating layer having an opening at the same time, and accordingly, the number of processes at the time of manufacturing the semiconductor device is reduced and the productivity is improved.
- the substrate for a semiconductor device is a substrate for a semiconductor device on which a semiconductor element is mounted after removing a metal plate, and a predetermined portion on the metal plate is provided with internal terminals from the metal plate side.
- a first noble metal plating layer is formed, a metal plating layer is formed on the first noble metal plating layer in the same shape as the first noble metal plating layer, and a metal plating layer is formed on the metal plate and the metal plating layer
- a permanent resist having an opening at a predetermined site is formed, and a second noble metal plating layer serving as an external terminal is formed on the metal plating layer located in the opening of the permanent resist.
- the resin provided in the manufacturing process of the semiconductor device in the conventional semiconductor device substrate is provided in advance as a permanent resist on the semiconductor device substrate, and in the opening of the permanent resist.
- the external terminals having different thicknesses from the internal terminals and the wiring portion are provided in advance and the internal terminals and the wiring portion are sealed with a permanent resist and only the external terminals are exposed.
- the wiring member for a semiconductor device is a wiring member for a semiconductor device on which a semiconductor element whose metal plate has been removed is mounted, and the first noble metal plating to be an internal terminal at a predetermined portion on one surface of a resin layer.
- the layer is formed with the lower surface exposed flush with one surface of the resin layer, a metal plating layer is formed on the first noble metal plating layer in the same shape as the first noble metal plating layer, and metal is further formed.
- a second noble metal plated layer, which partially serves as an external terminal, is formed on the plated layer with the upper surface exposed from the other surface of the resin layer.
- an external terminal having a thickness different from that of the internal terminal and the wiring portion is provided at a portion corresponding to the opening of the resin layer provided in the manufacturing process of the semiconductor device in the conventional substrate for a semiconductor device. If provided in advance, and the internal terminals and the wiring portion are sealed with resin, and only the external terminals are exposed from the other surface of the resin layer, unlike the conventional semiconductor device substrate, the external members It is not necessary to provide an insulating layer having an opening on the connecting surface, and accordingly, the number of steps in manufacturing the semiconductor device is reduced, and the productivity is improved.
- the present applicant has conceived through trial and error that the electrical connection surface of the internal terminal and the external terminal in the semiconductor device substrate used when manufacturing a semiconductor device is reverse to that of the conventional semiconductor device substrate. did. That is, in the conventional semiconductor device substrate, when manufacturing a semiconductor device, the external terminal surface is used in a state of exposing the surface on the metal plate side and the internal terminal surface is exposing the surface on the opposite side to the metal plate. It is configured. On the other hand, in the semiconductor device substrates according to the first to third aspects of the present invention, when manufacturing the semiconductor device, the external terminal surface is the surface opposite to the metal plate, and the internal terminal surface is the metal plate side.
- the plating layer constituting the external terminal is configured to be higher than the metal plate than the plating layer constituting the internal terminal and the wiring portion.
- a permanent resist is formed on the metal plating layer to be the metal plate and the internal terminal, in which a predetermined portion in the metal plating layer is opened. And forming a second noble metal plated layer to be an external terminal on the metal plated layer located in the opening of the permanent resist.
- the semiconductor device wiring member of the present invention when manufacturing the semiconductor device, the external terminal surface is the surface opposite to the metal plate used when manufacturing the semiconductor device substrate, and the internal terminal surface is the semiconductor device substrate.
- the plating layer that constitutes the external terminal rather than the plating layer that constitutes the internal terminal and the wiring part is used in the manufacture of the semiconductor device substrate It is configured to be high from a metal plate.
- the side on which the terminal is provided in the semiconductor device substrate of the first embodiment of the present invention is sealed with a resin, and the metal plate is removed by dissolution by etching after resin sealing, after removing the metal plate,
- the surface of the first precious metal plating layer which is the internal terminal on the side from which the metal plate is removed, follows the surface of the metal plate and is exposed in a step-less (height difference of 1 ⁇ m or less) state.
- the metal plate in the semiconductor device substrate of the second and third aspects of the present invention is removed by dissolution by etching or the like, the first internal terminal on the side from which the metal plate is removed The surface of the noble metal plated layer of the above is exposed in the state without a level difference (with a height difference of 1 ⁇ m or less) following the surface of the metal plate.
- the metal plate used for manufacturing the wiring member for a semiconductor device of the present invention is removed by dissolution by etching or the like, the first noble metal plated layer that becomes the internal terminal from which the metal plate is removed after removing the metal plate.
- This metal plate follows the surface of the metal plate and is exposed in a state without a step (height difference of 1 .mu.m or less).
- This metal plate is a general rolling material used for lead frames and the like. These metal plates are common rolling materials used for lead frames and the like.
- the semiconductor element is mounted on the first noble metal plating layer, but the surface of the first noble metal plating layer is exposed without any step. Since the connection surface is flat as a whole, the connection is stable. In this case, the external terminal needs to expose the surface opposite to the metal plate side.
- the applicant of the present invention further becomes an external terminal unlike the conventional semiconductor device substrate.
- an external terminal having a difference in height with the internal terminal and the wiring portion is formed by additionally depositing noble metal plating (or metal plating and noble metal plating) only on the site. I came to think of a substrate.
- the present applicant further exposes the upper surface of the second noble metal plating layer on a portion where the second noble metal plating layer is not formed on the substrate for a semiconductor device of the first aspect of the present invention. It came to think of the board
- the applicant of the present invention is a permanent resist in which a predetermined portion of a metal plating layer is opened on a metal plate and a metal plating layer to be an internal terminal in order to form a substrate for a semiconductor device of the first embodiment of the present invention.
- the second noble metal plated layer to be an external terminal is formed on the metal plated layer located in the opening of the permanent resist, and the substrate for a semiconductor device according to the third aspect of the present invention is conceived.
- the applicant of the present invention exposed the upper surface of the second noble metal plating layer on a portion where the second noble metal plating layer is not formed in the substrate for a semiconductor device of the first aspect of the present invention.
- the resin layer was formed in the state, and it came to think of the wiring member for semiconductor devices of this invention from which the metal plate was etched away.
- the internal terminals and the wiring portions may be made of resin or the like in the subsequent manufacturing process of the semiconductor device. It is possible to seal only and expose only the external terminal. For this reason, unlike the conventional semiconductor device substrate, there is no need for processing for forming an opening in the connection surface with the external member in the manufacturing process of the semiconductor device, and the number of steps is reduced accordingly, and productivity is improved. Do.
- a height difference is provided between the external terminal and the internal terminal and the wiring portion, and only the internal terminal and the wiring portion are sealed with resin. Therefore, unlike the conventional semiconductor device substrate, there is no need for processing to form an opening in the connection surface with the external member in the manufacturing process of the semiconductor device, and the number of processes is reduced accordingly. Improves the quality.
- a height difference is provided between the external terminal and the internal terminal and the wiring portion, and only the internal terminal and the wiring portion are sealed with a permanent resist.
- a height difference is provided between the external terminal and the internal terminal and the wiring portion, and only the internal terminal and the wiring portion are sealed with a permanent resist.
- a height difference is provided between the external terminal and the internal terminal and the wiring portion, and only the internal terminal and the wiring portion are sealed with resin and only the external terminal is exposed. If the surface is provided on the other surface of the resin layer, it is different from the conventional substrate for a semiconductor device, in the process of manufacturing the semiconductor device, processing for etching away the metal plate and forming an opening on the connection surface with the external member. Therefore, the number of processes is reduced and productivity is improved.
- a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device manufactured using the above-described substrate for a semiconductor device according to the present invention, wherein a plating layer to be an internal terminal is formed on a metal plate
- the plating layer to be an external terminal is partially formed on top of the metal plate, and the height from the metal plate surface of the plating layer to be an external terminal is higher than the height from the metal plate surface of the other plating layers
- the step of forming a resin layer in which the plating layer surface to be an external terminal is exposed and the resin layer in which the plating layer surface to be an external terminal is exposed are formed using the substrate for a semiconductor device. And a step of manufacturing a wiring member in which the formed plating layer is held by the resin layer, and a step of mounting a semiconductor element on the manufactured wiring member.
- a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device manufactured using the above-described substrate for a semiconductor device according to the present invention, wherein a plating layer to be an internal terminal is formed on a metal plate
- the plating layer to be an external terminal is partially formed on top of the metal plate, and the height from the metal plate surface of the plating layer to be an external terminal is higher than the height from the metal plate surface of the other plating layers
- a step of forming a resin layer in which the surface of the plating layer to be the external terminal is exposed is formed on the semiconductor device substrate, and a resin layer in which the surface of the plating layer to be the external terminal is exposed is formed.
- a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device manufactured using the above-described substrate for a semiconductor device of the present invention, wherein a plating layer to be an internal terminal is formed on a metal plate
- the plating layer to be an external terminal is partially formed on top of the metal plate, and the height from the metal plate surface of the plating layer to be an external terminal is higher than the height from the metal plate surface of the other plating layers
- a step of forming a resin layer in which the surface of the plating layer to be the external terminal is exposed is formed on the semiconductor device substrate, and a resin layer in which the surface of the plating layer to be the external terminal is exposed is formed.
- the substrate for a semiconductor device used in the method of manufacturing a semiconductor device of the present invention is a substrate for a semiconductor device to be a wiring member for mounting a semiconductor element after removing a metal plate, for example, a metal plate side at a predetermined portion on the metal plate.
- a first noble metal plating layer to be an internal terminal is formed, a metal plating layer is formed on the first noble metal plating layer in the same shape as the first noble metal plating layer, and a partial plating on the metal plating layer
- a second metal plating layer is formed on the second noble metal plating layer which has the same shape as the second metal plating layer and is an external terminal, and the second noble metal plating layer is formed from the metal plate surface of the second noble metal plating layer.
- the height is higher than the height from the metal plate surface of the metal plating layer surface. Since this semiconductor device substrate is provided in advance with an external terminal portion having a thickness different from that of the internal terminal portion and the wiring portion, the internal terminal and the wiring portion are sealed with resin in the manufacturing process of the semiconductor device. It can easily be exposed. For this reason, when this semiconductor device substrate is used, unlike the conventional semiconductor device substrate, the step of forming an opening in the connection surface with the external member becomes unnecessary in the manufacturing process of the semiconductor device, and accordingly, the semiconductor device The number of processes at the time of manufacturing is reduced and productivity is improved.
- the present applicant reverses the electrical connection surface of the internal terminal and the external terminal in the semiconductor device substrate used when manufacturing the semiconductor device to the conventional semiconductor device substrate.
- the conventional semiconductor device substrate when manufacturing a semiconductor device, the external terminal surface is used in a state of exposing the surface on the metal plate side and the internal terminal surface is exposing the surface on the opposite side to the metal plate. It is configured.
- the semiconductor device substrate used in the present invention when manufacturing the semiconductor device, the external terminal surface exposed the surface opposite to the metal plate, and the internal terminal surface exposed the metal plate side.
- the plating layer which is formed to be used in the state and which constitutes the external terminal portion is configured to be higher than the metal plate than the plating layer which constitutes the internal terminal portion and the wiring portion.
- the side of the semiconductor device substrate used in the method for manufacturing a semiconductor device of the present invention is sealed with a resin, and after resin sealing, the metal plate is removed by dissolution by etching, etc. Later, the surface of the first precious metal plating layer, which is the internal terminal on the side from which the metal plate is removed, follows the surface of the metal plate and is exposed in a step-less (height difference of 1 ⁇ m or less) state.
- This metal plate is a commonly available rolled material used for lead frames and the like.
- the semiconductor element is mounted on the first noble metal plating layer, but the surface of the first noble metal plating layer is exposed without any step.
- the semiconductor element Since the entire surface to be connected is flat, the semiconductor element is not inclined, and the plurality of internal terminal portions are also uniform in height, so that the connection is stable with the electrode of the semiconductor element.
- the external terminal part needs to expose the surface on the opposite side to the metal plate side, noble metal plating and metal plating were performed on the part to become the internal terminal part, the external terminal part and the wiring part on the metal plate After that, unlike the conventional substrate for a semiconductor device, metal plating and noble metal plating are further added and applied only to the part to be an external terminal, thereby providing an external terminal having a height difference with the internal terminal part and the wiring part.
- Another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device manufactured using the above-mentioned substrate for a semiconductor device according to the present invention, wherein a permanent resist layer is formed on a metal plate with a predetermined thickness.
- a plating layer is formed facing the metal plate to be an internal terminal, and a plating layer partially forming an external terminal is formed on the plating layer to be an internal terminal to become an external terminal
- Another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device manufactured using the above-mentioned substrate for a semiconductor device according to the present invention, wherein a permanent resist layer is formed on a metal plate with a predetermined thickness.
- a plating layer to be an internal terminal is formed on the metal plate side in a predetermined pattern, and a plating layer to be an external terminal is partially formed on the plating layer to be an internal terminal.
- the Process including the,.
- a substrate for a semiconductor device used in another method of manufacturing a semiconductor device according to the present invention is a substrate for a semiconductor device to be a wiring member for mounting a semiconductor element after removing a metal plate, and permanent on a metal plate with a predetermined thickness.
- a resist layer is formed, and in the permanent resist layer, a first noble metal plating layer to be an internal terminal is formed from the metal plate side at a predetermined site on the metal plate, and a first noble metal plating layer is formed on the first noble metal plating layer.
- a metal plating layer is formed in the same shape as the plating layer, and a second noble metal plating layer to be an external terminal is partially formed on the metal plating layer, or between the second noble metal plating layer and the metal plating layer
- the second metal plating layer is formed in the same shape as the second noble metal plating layer, and only the upper surface of the plating layer to be an external terminal is exposed from the opening of the upper surface of the permanent resist.
- this metal plate is an available common rolling material used for a lead frame etc.
- a plating layer is formed, and only the surface of the plating layer serving as an external terminal on the opposite surface side is exposed from the opening of the permanent resist, and a wiring member having the plating layer fixed by the permanent resist is obtained.
- Another method of manufacturing a semiconductor device according to the present invention mounts and assembles a semiconductor element on the side where the wiring member is in contact with the metal plate, using the above-mentioned wiring member.
- the surface on which the semiconductor element is mounted is This is a state of a surface formed in a state without steps (with a height difference of 1 ⁇ m or less) following the surface of the metal plate. Then, in the method for manufacturing a semiconductor device according to the present invention, the semiconductor element is mounted on the plating layer to be the internal terminal on the semiconductor element mounting surface of the wiring member, but the surface of the plating layer to be the internal terminal has no step.
- the semiconductor element Since the entire surface to be connected is flat because it is exposed in the state, the semiconductor element is not inclined, and the plurality of internal terminal portions are also uniform in height, so that the connection is stable with the electrodes of the semiconductor element.
- the semiconductor element is mounted on the side where the metal plate of the wiring member is removed, thereby preventing inclination of the semiconductor element to be mounted and connection failure such as bonding. As a result, it is possible to eliminate the eventual conduction failure.
- the surface of the external terminal is already exposed from the opening of the upper surface of the permanent resist on the external terminal side of the wiring member, the surface of the external terminal portion is exposed as in the conventional semiconductor device manufacturing method. The step of forming the opening for the purpose can be omitted.
- FIGS. 1A and 1B are diagrams showing the configuration of a substrate for a semiconductor device according to a first embodiment of the present invention
- FIG. 1A is a partial plan view seen from the external terminal side
- FIG. It is A sectional drawing.
- FIGS. 2A to 2I are explanatory views showing manufacturing steps of the semiconductor device substrate shown in FIGS. 1A and 1B.
- FIG. 3 is a plan view showing a change of the state of the semiconductor device substrate in the manufacturing process of FIG.
- a first noble metal plating layer 11 to be an internal terminal is formed at a predetermined portion on metal plate 1.
- the metal plating layer 12 is formed in the same shape as the first noble metal plating layer 11, and the second metal plating layer 13 is partially formed on the metal plating layer 12.
- a second noble metal plated layer 14 having the same shape as the second metal plated layer 12 and serving as an external terminal is formed thereon.
- the metal plate 1 is made of, for example, a copper plate.
- the first noble metal plating layer 11 is formed of, for example, an Au plating layer 11 a and a Pd plating layer 11 b formed in order from the metal plate 1 side.
- the metal plating layer 12 and the second metal plating layer 13 are made of, for example, a Ni plating layer.
- the second noble metal plated layer 14 is composed of, for example, a Pd plated layer 14 a and an Au plated layer 14 b which are sequentially formed from the metal plate 1 side.
- the height H2 of the surface of the second noble metal plating layer 14 (that is, the surface of the Au plating layer 14b) from the surface of the metal plate 1 is the height of the surface of the metal plating layer 12 from the surface of the metal plate 1 It is higher than H1.
- the semiconductor device substrate according to the first embodiment configured as described above can be manufactured, for example, as follows.
- the dry film resist for resist masks is laminated on both surfaces of the metal plate used as a board
- the plating layer is not formed on the metal plate as shown in FIG. 3A.
- a pattern (here, pattern A) for forming the inner terminal, the wiring portion, and the base of the outer terminal is formed at a predetermined position.
- the front side is exposed and developed using the above glass mask, and the back side is exposed and developed using a glass mask that irradiates the entire surface of the dry film resist on the back side.
- a resist mask of pattern A is formed on the front surface, and a resist mask covering the entire surface is formed on the back surface.
- Exposure and development are carried out by a conventionally known method. For example, ultraviolet light is irradiated in a state where it is covered with a glass mask, and the solubility of the portion of the dry film resist irradiated with the ultraviolet light that has passed through the glass mask is reduced by removing the other portion. Form a resist mask.
- a negative dry film resist is used as the resist, but a negative liquid resist may be used to form a resist mask.
- a positive type dry film resist or liquid resist the solubility of a portion of the resist irradiated with ultraviolet light that has passed through the glass mask is increased by the developer, and the portion is removed to remove the resist mask. It may be formed.
- a solder resist may be used as the resist for forming the resist mask.
- Au plating is performed as the first noble metal plating layer 11 to have a predetermined thickness in the order of, for example, the Au plating layer 11 a and the Pd plating layer 11 b. And Pd plating, respectively.
- Ni plating is performed on the Pd plating layer 11 b as the metal plating layer 12 so that, for example, the Ni plating layer has the same planar shape as the noble metal plating layer.
- FIG. 2D shows the state at this time.
- FIG. 3B is a view showing the plating layer of the pattern A applied to the semiconductor device substrate at this time
- FIG. 3C is an enlarged view showing a partial region surrounded by a rectangle in FIG. 3B.
- a dry film resist is laminated on the peeled both sides as shown in FIG. 2E.
- a pattern (here, pattern B) for forming a plating layer is formed on a portion which is a part of the Ni plating layer previously formed and becomes an external terminal.
- the front side is exposed and developed using the glass mask, and the back side is exposed and developed using a glass mask that irradiates the entire surface of the resist film on the back side.
- FIG. 2G a resist mask of pattern B is formed on the front surface, and a resist mask covering the entire surface is formed on the back surface.
- Ni plating is performed on the surface of the Ni plating constituting the metal plating layer 12 exposed from the resist mask so that, for example, a Ni plating layer is formed as the second metal plating layer 13.
- the Pd plating layer 14a and the Au plating layer 14b have a predetermined thickness in this order. , Pd plating, Au plating respectively.
- FIG. 2H shows the state at this time.
- FIG. 2I is a view showing the plating layer of the pattern B applied to the semiconductor device substrate at this time, and FIG. 3E is an enlarged view showing a partial region surrounded by a rectangle in FIG. 3D.
- FIGS. 2A to 2I are explanatory views showing an example of a manufacturing process of a resin-sealed semiconductor device using the semiconductor device substrate of the first embodiment manufactured through the manufacturing steps shown in FIGS. 2A to 2I.
- FIG. 4A are explanatory views showing an example of a manufacturing process of a resin-sealed semiconductor device using the semiconductor device substrate of the first embodiment manufactured through the manufacturing steps shown in FIGS. 2A to 2I.
- the noble metal plating layer 14 which is the second noble metal plating layer is provided on the surface of the Ni plating constituting the metal plating layer 12 without the second metal plating layer 13.
- the state of the resin sealing in the case where it had been is shown.
- the semiconductor device which provided the 2nd metal plating layer 13 on the surface of Ni plating which constitutes metal plating layer 12, and provided precious metal plating layer 14 which is the 2nd precious metal plating layer on the surface of 2nd metal plating layer 13
- the noble metal plating layer 14 protrudes from the surface of the resin when resin sealing is performed.
- the semiconductor device substrate provided with the noble metal plating layer 14 which is the second noble metal plating layer is used without providing the second metal plating layer 13.
- the plating of the terminal pattern is performed in the resin sealing.
- resin may wrap around the external terminal surface due to the uneven height of the terminals.
- the surface of the sealed resin is polished to expose the external terminal surface.
- the metal plate of the semiconductor device substrate is etched, and the metal plate is removed by dissolution or the like. Thereby, the surfaces of the internal terminal, the wiring portion, and the external terminal are flush exposed from the resin surface.
- the semiconductor element is mounted on the side of the internal terminal surface that appears by removing the metal plate, and the electrode of the semiconductor element is connected to the internal terminal exposed flush with the resin surface.
- the electrodes of the semiconductor element and the internal terminals are connected in the flip chip method.
- the wire method as shown in FIG. 4E, the electrode of the semiconductor element and the internal terminal are connected by a wire. Since the surfaces of the internal terminals exposed through the manufacturing steps of the semiconductor device shown in FIGS. 4A to 4C using the substrate for the semiconductor device of the first embodiment become flush with the resin surface, the semiconductor element is stabilized. It can be loaded with.
- FIG. 4F the surface on which the semiconductor element is mounted is sealed with a resin.
- 4A to 4F are illustrated without changing the vertical direction of the semiconductor device substrate.
- the completed semiconductor device is mounted on an external member by reversing the vertical direction from the direction shown in FIG. 4F.
- FIG. 4G shows the state at this time.
- FIG. 5A and FIG. 5B are diagrams showing the configuration of a semiconductor device substrate according to a second embodiment of the present invention
- FIG. 5A is a partial plan view seen from the external terminal side
- FIG. It is A sectional drawing. 6A to 6J 'are explanatory views showing a manufacturing process of the semiconductor device substrate shown in FIGS. 5A and 5B.
- the semiconductor device substrate according to the second embodiment further includes, in addition to substantially the same configuration as the semiconductor device substrate according to the first embodiment, a second noble metal in the metal plate 1 and the metal plating layer 12.
- the resin layer 15 is formed in a state in which the upper surface of the second noble metal plating layer 14 is exposed on the portion where the plating layer 14 is not formed.
- the semiconductor device substrate according to the second embodiment configured as described above can be manufactured, for example, as follows.
- Steps from laminating a dry film resist for a resist mask on both sides of a metal plate as a substrate (FIG. 6A) to peeling off the resist mask on both sides (FIG. 6I) are the first embodiment shown in FIGS. 2A to 2I. Is substantially the same as the manufacturing process of a semiconductor device substrate.
- FIG. 6A Steps from laminating a dry film resist for a resist mask on both sides of a metal plate as a substrate (FIG. 6A) to peeling off the resist mask on both sides
- FIG. 6J shows the case where a metal plate provided with the precious metal plating layer 14 which is the second precious metal plating layer without providing the second metal plating layer 13 on the surface of the Ni plating constituting the metal plating layer 12 Shows the state of resin sealing in FIG. A metal plate in which the second metal plating layer 13 is provided on the surface of Ni plating constituting the metal plating layer 12 and the noble metal plating layer 14 which is the second noble metal plating layer is provided on the surface of the second metal plating layer 13 In the case where is used, as shown in FIG.
- the noble metal plating layer 14 protrudes from the surface of the resin when resin sealing is performed.
- a metal plate provided with a noble metal plating layer 14 which is a second noble metal plating layer is used without providing the second metal plating layer 13.
- the terminal by plating of the terminal pattern in resin sealing Due to the uneven height of the resin, resin may wrap around the external terminal surface. In that case, the surface of the sealed resin is polished to expose the external terminal surface.
- the semiconductor device substrate of the present embodiment is completed.
- FIGS. 6A to 6J '. are explanatory views showing an example of a manufacturing process of a resin-sealed semiconductor device using the semiconductor device substrate of the second embodiment manufactured through the manufacturing steps shown in FIGS. 6A to 6J '. .
- FIG. 7A shows that the noble metal plating layer 14 which is the second noble metal plating layer is provided on the surface of the Ni plating constituting the metal plating layer 12 without providing the second metal plating layer 13 and resin sealing of a predetermined portion is performed.
- the figure shows a substrate for a semiconductor device.
- the second metal plating layer 13 is provided on the surface of the Ni plating constituting the metal plating layer 12, and the noble metal plating layer 14 which is the second noble metal plating layer is provided on the surface of the second metal plating layer 13
- the noble metal plating layer 14 protrudes from the surface of the resin.
- a substrate for a semiconductor device in which a noble metal plating layer 14 which is a second noble metal plating layer is provided and a predetermined portion is resin-sealed I assume. First, the metal plate of the semiconductor device substrate shown in FIG.
- FIG. 7A is etched, and the metal plate is removed by dissolution or the like. Thereby, the surfaces of the internal terminal, the wiring portion, and the external terminal are flush exposed from the resin surface.
- FIG. 7B shows the state at this time.
- mounting of the semiconductor element on the internal element surface side FIGGS. 7C and 7D
- resin sealing of the surface on which the semiconductor element is mounted FIGS. 7E
- mounting of the completed semiconductor device on an external member FIG. 7F.
- the respective steps are substantially the same as the steps of manufacturing a semiconductor device using the semiconductor device substrate according to the first embodiment shown in FIGS. 4D to 4G.
- FIGS. 8A and 8B are diagrams showing the configuration of a semiconductor device substrate according to a third embodiment of the present invention, FIG. It is A sectional drawing. 9A to 9J are explanatory views showing a manufacturing process of the semiconductor device substrate shown in FIGS. 8A and 8B.
- a permanent resist 16 is formed on the metal plate 1 and the metal plating layer 11 in which a predetermined portion in the metal plating layer 11 is opened.
- a second metal plating layer 13 is formed on the metal plating layer 11 located in the opening 16. The other configuration is substantially the same as that of the semiconductor device substrate of the first embodiment.
- the semiconductor device substrate according to the third embodiment configured as described above can be manufactured, for example, as follows.
- Steps from laminating a dry film resist for a resist mask on both sides of a metal plate to be a substrate (FIG. 9A) to forming a first noble metal plating layer 11 and a metal plating layer 12 (FIG. 9D) are shown in FIG. It is substantially the same as the manufacturing process of the semiconductor device substrate of the first embodiment shown in 2D.
- a film type permanent resist is laminated on the surface side on which the plating layer is formed, and a dry film resist similar to that used in FIG. 9A is laminated on the back surface side.
- a pattern (here, pattern B) for forming a plating layer is formed on a portion which is a part of the Ni plating layer previously formed and becomes an external terminal.
- the front side is exposed and developed using the glass mask, and the back side is exposed and developed using a glass mask that irradiates the entire surface of the resist film on the back side.
- a resist mask (permanent resist 16 shown in FIGS. 8A and 8B) consisting of a permanent resist of pattern B is formed on the front surface, and a resist mask covering the entire surface is formed on the back surface.
- Ni plating is performed on the surface of the Ni plating constituting the metal plating layer 12 exposed from the resist mask so that, for example, a Ni plating layer is formed as the second metal plating layer 13.
- the Pd plating layer 14a and the Au plating layer 14b have a predetermined thickness in this order. , Pd plating, Au plating respectively.
- FIG. 9H shows the state at this time.
- FIG. 9I shows the state at this time.
- the resist mask on the back surface is peeled off to complete the semiconductor device substrate of the present embodiment.
- FIGS. 9A to 9J are explanatory views showing an example of a manufacturing process of a resin-sealed semiconductor device using the semiconductor device substrate of the third embodiment manufactured through the manufacturing steps shown in FIGS. 9A to 9J.
- the metal plate of the semiconductor device substrate shown in FIG. 10A is etched, and the metal plate is removed by dissolution or the like. Thereby, the surfaces of the internal terminal, the wiring portion, and the external terminal are flush exposed from the permanent resist surface.
- FIG. 10B shows the state at this time.
- the semiconductor element is mounted on the side of the internal terminal that appears by removing the metal plate, and the electrode of the semiconductor element is connected to the internal terminal exposed flush with the surface of the permanent resist.
- the electrodes of the semiconductor element and the internal terminals are connected in the flip chip method.
- the wire method as shown in FIG. 10D, the electrodes of the semiconductor element and the internal terminals are connected by a wire. Since the surface of the internal terminal exposed through the manufacturing process of the semiconductor device shown in FIG. 10A and FIG. 10B using the substrate for semiconductor device of the third embodiment becomes flush with the permanent resist surface, the semiconductor element is stabilized. It can be loaded in the state. Here, for convenience, the description of die bonding for fixing the semiconductor element is omitted.
- FIG. 10E the surface on which the semiconductor element is mounted is sealed with a resin. Thus, the semiconductor device is completed. 10A to 10E are illustrated without changing the vertical direction of the semiconductor device substrate.
- the completed semiconductor device is mounted on an external member by reversing the vertical direction from the direction shown in FIG. 10E.
- FIG. 10F shows the state at this time.
- FIGS. 11A and 11B are diagrams showing the configuration of a wiring member for a semiconductor device according to a fourth embodiment of the present invention
- FIG. 11A is a partial plan view seen from the external terminal side
- FIG. FIG. 12A to 12K are explanatory views showing the manufacturing process of the wiring member for a semiconductor device shown in FIGS. 11A and 11B.
- the first noble metal plating layer 11 to be an internal terminal is formed on the lower surface of a predetermined portion of one surface 15 a of the resin layer 15.
- the metal plating layer 12 is formed on the first noble metal plating layer 11 in the same shape as the first noble metal plating layer 11, and the metal plating layer 12 is formed on the first noble metal plating layer 11.
- the second metal plating layer 13 is partially formed on the second metal plating layer 13, and the second noble metal plating layer 14 having the same shape as the second metal plating layer 12 and serving as an external terminal is It is formed in the state exposed from the other surface 15 b of the resin layer 15.
- the first noble metal plating layer 11 is formed of, for example, an Au plating layer 11 a and a Pd plating layer 11 b which are sequentially formed from one surface 15 a side of the resin layer 15.
- the metal plating layer 12 and the second metal plating layer 13 are made of, for example, a Ni plating layer.
- the second noble metal plated layer 14 is composed of, for example, a Pd plated layer 14 a and an Au plated layer 14 b which are sequentially formed from the side of one surface 15 a of the resin layer 15.
- the height H 2 of the surface of the second noble metal plating layer 14 (that is, the surface of the Au plating layer 14 b) from one surface 15 a of the resin layer 15 is one of the resin layers 15 on the surface of the metal plating layer 12. It is higher than the height H1 from the surface 15a.
- the semiconductor device wiring member of the fourth embodiment configured as described above can be manufactured, for example, as follows.
- the pre-processing / post-processing etc. which are implemented in each process of manufacture including chemical
- Steps from laminating a dry film resist for resist mask on both sides of a metal plate as a substrate (FIG. 12A) to peeling off the resist mask on both sides (FIG. 12I) are the first embodiment shown in FIGS. 2A to 2I. Is substantially the same as the manufacturing process of a semiconductor device substrate.
- FIG. 12A Steps from laminating a dry film resist for resist mask on both sides of a metal plate as a substrate (FIG. 12A) to peeling off the resist mask on both sides
- FIGS. 2A to 2I Is substantially the same as the manufacturing process of a semiconductor device substrate.
- FIG. 12J shows the case where a metal plate provided with the precious metal plating layer 14 which is the second precious metal plating layer without providing the second metal plating layer 13 on the surface of the Ni plating constituting the metal plating layer 12 Shows the state of resin sealing in FIG.
- the noble metal plating layer 14 protrudes from the surface of the resin when resin sealing is performed.
- a metal plate provided with a noble metal plating layer 14 which is a second noble metal plating layer is used without providing the second metal plating layer 13.
- resin may wrap around the external terminal surface.
- the surface of the sealed resin is polished to expose the external terminal surface.
- the metal plate of the semiconductor device substrate is etched, the metal plate is removed by dissolution and the like, and as shown in FIG. 12K, the surfaces of the internal terminals, wiring portions and external terminals are flush with the resin surface. Exposed. Thereby, the wiring member for a semiconductor device of the present embodiment is completed.
- FIGS. 12A to 12K are explanatory views showing an example of a manufacturing process of a resin-sealed semiconductor device using the wiring member for a semiconductor device of the fourth embodiment manufactured through the manufacturing steps shown in FIGS. 12A to 12K.
- FIG. 13A shows that the noble metal plating layer 14 which is the second noble metal plating layer is provided on the surface of the Ni plating constituting the metal plating layer 12 without providing the second metal plating layer 13 and resin sealing of a predetermined portion is performed. And a substrate for a semiconductor device in which a metal plate is dissolved and removed.
- the second metal plating layer 13 is provided on the surface of the Ni plating constituting the metal plating layer 12, and the noble metal plating layer 14 which is the second noble metal plating layer is provided on the surface of the second metal plating layer 13
- the noble metal plating layer 14 protrudes from the surface of the resin.
- the second metal plating layer 13 is not provided, the noble metal plating layer 14 as the second noble metal plating layer is provided, resin sealing is performed on a predetermined portion, and the metal plate is dissolved and removed. It is assumed that a semiconductor device substrate is used.
- the semiconductor element is mounted on the internal terminal surface side of the wiring member for a semiconductor device shown in FIG. 13A, and the electrode of the semiconductor element is connected to the internal terminal exposed flush from the resin surface.
- the electrodes of the semiconductor element and the internal terminals are connected in the flip chip method.
- the wire method as shown in FIG. 13C, the electrode of the semiconductor element and the internal terminal are connected by a wire.
- the semiconductor device wiring member of the fourth embodiment since the surface of the exposed internal terminal is flush with the resin surface, the semiconductor element can be mounted in a stable state. Here, for convenience, the description of die bonding for fixing the semiconductor element is omitted.
- FIG. 13D the surface on which the semiconductor element is mounted is sealed with a resin.
- the semiconductor device is completed. 13A to 13D are illustrated without changing the vertical direction of the semiconductor device wiring member.
- the completed semiconductor device is mounted on the external member while reversing the vertical direction from the direction shown in FIG. 13D.
- FIG. 13E shows the state at this time.
- Comparative Example 1 Next, a configuration of a conventional semiconductor device substrate will be described as a comparative example of the semiconductor device substrate and the semiconductor device wiring member of each of the above embodiments.
- 14A to 14E are explanatory views showing a manufacturing process of a conventional substrate for a semiconductor device according to Comparative Example 1.
- 15A to 15C are plan views showing changes in the state of the semiconductor device substrate in the manufacturing steps of FIGS. 14A to 14E.
- the surfaces of the internal terminals, the wiring portions, and the external terminals formed on the metal plate are formed at substantially the same height from the surface of the metal plate. .
- the semiconductor device substrate of Comparative Example 1 configured as described above is manufactured, for example, as follows. As shown in FIGS. 14A to 14D, lamination of a dry film resist for a resist mask on both sides of a metal plate to be a substrate for a semiconductor device, patterns A and B by exposure and development using a glass mask on the front and back sides. The formation of the resist mask on the entire surface and the plating of the portion of the metal plate exposed from the resist mask are substantially the same as the manufacturing process of the semiconductor device substrate of the first embodiment shown in FIGS. 2A to 2D. The substrate for a semiconductor device of Comparative Example 1 is completed by removing the resist masks on both sides from the state of FIG.
- the substrate for a semiconductor device of the first embodiment in that the steps shown in FIGS. Is different from the manufacturing process of The semiconductor device substrate of Comparative Example 1 is different from the manufacturing process of the semiconductor device substrate of the second embodiment in that the steps shown in FIGS. 6E to 6J are not performed.
- the semiconductor device substrate of the comparative example 1 is different from the manufacturing process of the semiconductor device substrate of the third embodiment in that the steps shown in FIGS. 9E to 9J are not performed.
- the semiconductor device substrate of the comparative example 1 is different from the manufacturing process of the semiconductor device wiring member of the fourth embodiment in that the process shown in FIGS. 12E to 12K is not performed.
- 16A to 16L are explanatory views showing a manufacturing process of a resin-sealed semiconductor device using the semiconductor device substrate of Comparative Example 1 manufactured through the manufacturing steps shown in FIGS. 14A to 14E.
- the semiconductor element is mounted on the side from which the plating layer to be the internal terminal, the wiring portion, and the external terminal in the metal plate of the semiconductor device substrate shown in FIGS. 16A and 16B protrudes, and the electrode of the semiconductor element is connected to the internal terminal.
- the electrode of the semiconductor element is connected to the internal terminal.
- the wire method as shown in FIG.
- the electrodes of the semiconductor element and the internal terminals are connected by a wire.
- an adhesive layer using a film-like or paste-like adhesive material is provided in the gap between the metal plate on which the semiconductor element is mounted and the semiconductor element, and when the semiconductor element is mounted, the semiconductor element contacts a part of the internal terminal. The semiconductor element is fixed to the metal plate through the adhesive layer so that the semiconductor element does not tilt.
- FIG. 16C the surface on which the semiconductor element is mounted is sealed with a resin.
- FIG. 16D shows the state at this time.
- FIG. 16E the back side of the semiconductor device is covered with a resin, and an opening is machined in the resin to form an outer insulating layer so that the surface of a part of the external terminal is exposed.
- the semiconductor device is completed.
- the formation of the outer insulating layer is performed as follows. For example, as shown in FIG. 16G, a liquid solder resist for a resist mask is applied on the side of the resin surface shown in FIG. Heat and precure (pre-cure) at slightly lower temperature (FIG. 16H). Next, as shown in FIG. 16I, the pre-cured solder resist is exposed and developed using a glass mask on which a pattern for forming an opening is formed in a portion to be an external terminal. Then, as shown in FIG. 16J, a resist mask of a pattern for forming an opening in a portion to be an external terminal is formed. Thereafter, the resist mask is subjected to a post-cure which is further heated to obtain a final strength (FIG. 16K). Thereby, the semiconductor device shown in FIG. 16L is completed.
- the completed semiconductor device is mounted on an external member.
- the external terminal is exposed inside the opening surface of the resist mask. Therefore, solder balls are embedded in the openings to electrically connect with the terminals of the external members.
- FIG. 16L shows the state at this time.
- the thicknesses of the plating layers constituting the external terminal, the internal terminal and the wiring portion are formed to be substantially the same. Therefore, in the subsequent manufacturing process of the semiconductor device, it is necessary to form an insulating layer for embedding the plating layer, and to process an opening for connecting to an external terminal in the insulating layer. As a result of the increase of the process, the production is delayed and the productivity is deteriorated.
- the substrate for a semiconductor device of the first embodiment since the height difference is provided between the external terminal and the internal terminal and the wiring portion, in the subsequent manufacturing process of the semiconductor device, the internal terminal is made of resin or the like.
- the semiconductor device substrate of Comparative Example 1 since the heights of the upper surfaces of the plurality of internal terminals are formed of a plated layer having a variation with a height difference of several ⁇ m (for example, 5 to 8 ⁇ m) When the semiconductor device is mounted and electrically connected to the internal terminal portion, the semiconductor element is mounted in an inclined state, or conduction failure occurs in the electrical connection.
- the substrate for a semiconductor device of the first embodiment the height of the internal terminal surface on which the semiconductor element is mounted and the internal terminal portion electrically connected to the semiconductor element are different in the subsequent manufacturing steps of the semiconductor device. Since it becomes uniform, the reliability of the electrical connection between the semiconductor element and the internal terminal portion is improved.
- the external terminal and the internal terminal and the wiring portion have a difference in height, and the resin is used as the internal terminal and the wiring. Since only the external portion is sealed and only the external terminal is exposed, it is not necessary to process the opening on the connection surface with the external member in the manufacturing process of the semiconductor device, unlike the semiconductor device substrate of Comparative Example 1. As a result, the number of processes is reduced and the productivity is improved.
- the substrate for a semiconductor device of the second embodiment like the substrate for a semiconductor device of the first embodiment, in the subsequent manufacturing steps of the semiconductor device, the internal terminal surface on which the semiconductor element is mounted and the semiconductor element are electrically Since the heights of the internal terminal portions to be connected become uniform, the reliability of the electrical connection between the semiconductor element and the internal terminal portions is improved.
- the external terminal and the internal terminal and the wiring portion have a height difference, and the internal terminal is made of permanent resist or the like. And, since only the wiring portion was sealed and only the external terminal was exposed, unlike the semiconductor device substrate of Comparative Example 1, an insulating layer having an opening on the connection surface with the external member in the manufacturing process of the semiconductor device. It is not necessary to provide the number of steps, and the number of processes is reduced, and the productivity is improved. Furthermore, according to the semiconductor device substrate of the third embodiment, it can be shipped as a wiring member from which the metal plate has been removed. By doing so, the etching step for removing the metal plate at the time of manufacturing the semiconductor device becomes unnecessary, and the productivity is further improved.
- the substrate for a semiconductor device of the third embodiment like the substrate for a semiconductor device of the first embodiment, in the subsequent manufacturing process of the semiconductor device, the internal terminal surface on which the semiconductor element is mounted and the semiconductor element are electrically Since the heights of the internal terminal portions to be connected become uniform, the reliability of the electrical connection between the semiconductor element and the internal terminal portions is improved.
- the wiring member for a semiconductor device of the fourth embodiment a height difference is provided between the external terminal and the internal terminal and the wiring portion, and the internal terminal is made of resin. Only the wiring portion is sealed, and only the external terminal is exposed from the other surface of the resin layer. Therefore, unlike the semiconductor device substrate of Comparative Example 1, the etching removal of the metal plate or the external member is performed in the manufacturing process of the semiconductor device. It is not necessary to process the opening on the connecting surface with the connector, and the number of processes is reduced accordingly, and the productivity is improved.
- the wiring member for a semiconductor device of the fourth embodiment like the substrate for a semiconductor device of the first embodiment, in the subsequent manufacturing steps of the semiconductor device, the internal terminal surface on which the semiconductor element is mounted and the semiconductor element are electrically Since the heights of the internal terminal portions to be connected intentionally become uniform, the reliability of the electrical connection between the semiconductor element and the internal terminal portions is improved.
- Example 1 examples of a semiconductor device substrate and a method of manufacturing the same according to the first embodiment of the present invention will be described.
- pretreatment and post-treatment including chemical solution washing, water washing and the like are carried out.
- a metal plate a copper material having a thickness of 0.15 mm, which is also used as a lead frame material, was prepared.
- a 25 ⁇ m-thick dry film resist (AQ-2558, manufactured by Asahi Kasei Corp.) was laminated on both sides of the metal plate (see FIG. 2A).
- the dry film resist on the surface side is exposed and developed using a glass mask on which the pattern A for forming the plating is formed on the surface side at a predetermined position, and the resist on which the portion to form the plating is opened A mask was formed (see FIGS. 2B and 2C).
- a resist mask was formed to cover the entire back surface of the metal plate. The exposure and development were the same as in the conventional method. A glass mask for exposure was brought into close contact with the dry film resist, and ultraviolet light was irradiated to expose the pattern A to the dry film resist and development was performed with sodium carbonate.
- the metal plate exposed from the formed resist mask is subjected to general plating pretreatment, and then Au is 0.003 ⁇ m or more, Pd is 0.01 ⁇ m or more, Ni is 6 ⁇ m or more in order Plating (see FIG. 2D).
- the resist mask on both sides was peeled off, and the same dry film resist was laminated on both sides (see FIG. 2E).
- the second metal plating layer is formed to have a thickness of 15 to 40 ⁇ m.
- a resist with a thickness of 50 ⁇ m was used only on the side, and a resist with a thickness of 25 ⁇ m was used on the back side.
- a resist mask is formed by performing exposure and development using a glass mask on which a pattern B for forming a plating is formed by overlapping a portion to be an external terminal, which is a part of the plating layer previously formed. (See FIG. 2F, FIG. 2G).
- the back surface side formed the resist mask which covers the whole similarly to the last resist mask formation process.
- Ni is plated in order of 40 ⁇ m or more, Pd is 0.01 ⁇ m or more, and Au is 0.003 ⁇ m or more on the Ni plating surface exposed from the formed resist mask (see FIG.
- the resist masks on both sides were removed to fabricate a semiconductor device substrate (see FIG. 2I).
- the surface of the precious metal plating layer to be the external terminal is exposed on the side where the plating layer corresponding to the internal terminal, wiring portion and external terminal in the metal plate of the completed semiconductor device substrate is exposed, and the other part is made of resin (See FIG. 4B), and then the metal plate (copper material) is etched away (see FIG. 4C), and the plating layer fixed with resin is used as a wire on the side that was in contact with the metal plate.
- a semiconductor device was mounted with elements connected to the internal terminals (see FIG. 4D), and the semiconductor element mounting portion was resin-sealed to obtain a semiconductor device in which the surfaces of the external terminals were exposed from the resin surface (see FIG. 4F). ).
- Example 2 Next, examples of a semiconductor device substrate and a method of manufacturing the same according to a second embodiment of the present invention will be described.
- pretreatment and post-treatment including chemical solution washing, water washing and the like are carried out.
- each process from preparation of a metal plate lamination of a dry film resist (FIG. 6A) to peeling of a resist mask on both sides (FIG. 6I) was performed.
- the other part is sealed with resin so that the surface of the precious metal plating layer which becomes an external terminal is exposed to the side where the plating layer corresponding to the internal terminal, wiring part, and external terminal in the metal plate protrudes.
- FIG. 6J A substrate for a semiconductor device was produced.
- the metal plate (copper material) of the completed semiconductor device substrate is removed by etching (see FIG. 7B), and the semiconductor element is mounted on the side that was in contact with the metal plate using the plating layer fixed with resin as wiring.
- the terminal and the terminal were electrically connected (see FIG. 7C), and the semiconductor element mounting portion was sealed with resin to obtain a semiconductor device in which the surface of the external terminal was exposed from the surface of the resin (see FIG. 7E).
- Example 3 examples of a semiconductor device substrate and a method of manufacturing the same according to a third embodiment of the present invention will be described.
- pretreatment and post-treatment including chemical solution washing, water washing and the like are carried out.
- preparation of a metal plate and lamination of a dry film resist (FIG. 9A) to plating in the order of Au, Pd and Ni (FIG. 9D) were performed.
- the resist mask on both sides is peeled off, and a film type permanent resist (manufactured by Hitachi Chemical: KI-1000T4F) is laminated on the surface side on which the plating layer was previously formed, and on the back side, the same dry film resist is laminated. (See FIG. 9E).
- the second metal plating layer is formed to have a thickness of 15 to 40 ⁇ m.
- a permanent resist with a thickness of 50 ⁇ m was used.
- a resist having a thickness of 25 ⁇ m was used on the back side.
- a resist mask is formed by performing exposure and development using a glass mask on which a pattern B for forming a plating is formed by overlapping a portion to be an external terminal, which is a part of the plating layer previously formed. (See FIG. 9F, FIG. 9G).
- the back surface side formed the resist mask which covers the whole similarly to the last resist mask formation process.
- a substrate plated with Pd to be 0.01 ⁇ m or more and Au to 0.003 ⁇ m or more in order from the formed resist mask to Ni plating surface, Ni in an order of 15 ⁇ m or more, Prepare two types of plated substrates by plating Pd to 0.01 ⁇ m or more and Au to 0.003 ⁇ m or more (see FIGS. 9H and 9I), and then, for each substrate, The resist mask on the back surface was removed to fabricate two types of substrates for semiconductor devices (see FIG. 9J).
- the metal plate (copper material) of the completed semiconductor device substrate is removed by etching (see FIG.
- Example 4 examples of a semiconductor device wiring member and a method of manufacturing the same according to a fourth embodiment of the present invention will be described.
- pretreatment and post-treatment including chemical solution washing, water washing and the like are carried out.
- each process from preparation of a metal plate lamination of a dry film resist (FIG. 12A) to peeling of a resist mask on both sides (FIG. 12I) was performed.
- the other part was sealed with resin so that the surface of the precious metal plating layer which becomes an external terminal was exposed to the side to which the plating layer corresponding to the internal terminal, wiring part, and external terminal in a metal plate protruded. (See Figure 12J).
- the metal plate (copper material) was removed by etching to fabricate a wiring member for a semiconductor device (see FIG. 12K).
- the semiconductor element is mounted on the surface side that was in contact with the metal plate using the plated layer fixed with resin of the completed wiring member for semiconductor device as the wiring, and conduction with the internal terminal (see FIG. 13C)
- the semiconductor device was sealed with resin to obtain a semiconductor device in which the surface of the external terminal was exposed from the surface of the resin (see FIG. 13E).
- a plating layer to be an internal terminal is formed on a metal plate, plating layers of different metals having the same shape are formed thereon, and a partial plating is further formed thereon.
- a plating layer is formed on the partially formed plating layer, and a plating layer to be an external terminal is formed in the same shape, and the plating layer surface to be an external terminal has a metal plate surface compared to the other plating layers.
- the surface of the external terminal portion is exposed on the metal plate of the substrate for a semiconductor device on the side where the plating layer corresponding to the internal terminal portion, the wiring portion, and the external terminal portion protrudes. And seal the other part with resin.
- the metal plate of the semiconductor device substrate is removed to obtain a wiring member in which the surface of the plating layer is exposed flush with the resin surface on the side which was in contact with the metal plate.
- the semiconductor element is mounted on the side of the plating layer that appears by removing the metal plate, and the electrode of the semiconductor element is connected to the internal terminal portion of the plating layer exposed flush with the resin surface.
- the surface side on which the semiconductor element is mounted is sealed with a resin.
- Example 5 17A to 17D are views showing steps of a method of manufacturing a semiconductor device according to an example corresponding to the fifth embodiment of the present invention, and FIGS. 17A and 17A ′ are used for manufacturing the semiconductor device of this example.
- 17B and FIG. 17B ′ show the semiconductor device substrate shown in FIG. 17A and FIG. 17A ′ sealed with a resin so that the surface of the external terminal portion is exposed.
- FIG. 17C is an explanatory view showing a state in which the metal plate is removed from the substrate for a semiconductor device shown in FIG. 17B and used as a wiring member
- FIG. 17D is a semiconductor on the plating layer side serving as an internal terminal of the wiring member shown in FIG. It is explanatory drawing which shows the state which mounted the element, connected the electrode of a semiconductor element, and the internal terminal part of the wiring member, and resin-sealed the side which mounts a semiconductor element.
- a first noble metal plated layer 11 to be an internal terminal is formed at a predetermined portion on metal plate 1;
- a metal plating layer 12 is formed on the first noble metal plating layer 11 in the same shape as the first noble metal plating layer 11, and a second metal plating layer 13 is partially formed on the metal plating layer 12.
- a second noble metal plated layer 14 having the same shape as the second metal plated layer 13 and being an external terminal is formed on the second metal plated layer 13.
- the surface from the surface of metal plate 1 is high in the surface of the 2nd precious metal plating layer 14 used as an external terminal compared with other plating layers.
- the metal plate 1 is made of, for example, a copper plate.
- the first noble metal plated layer 11 is composed of, for example, an Au plated layer and a Pd plated layer, which are sequentially formed from the metal plate 1 side.
- the metal plating layer 12 and the second metal plating layer 13 are made of, for example, a Ni plating layer.
- the second noble metal plated layer 14 is composed of, for example, a Pd plated layer and an Au plated layer, which are formed in order from the metal plate 1 side.
- the height of the surface of the second noble metal plating layer 14 (that is, the surface of the Au plating layer) from the surface of the metal plate 1 is about 40 ⁇ m, and the height of the surface of the metal plating layer 12 from the surface of the metal plate 1
- a substrate for a semiconductor device having a thickness of about 6 ⁇ m was used for manufacturing the semiconductor device of this example.
- the second metal plating layer 13 is not formed on the metal plating layer 12, and the external terminals are partially formed on the metal plating layer 12.
- the semiconductor device substrate on which the second noble metal plated layer 14 is formed may be used for manufacturing a semiconductor device.
- 17B ′ shows a state in which the other part is sealed with the resin 20 so that the surface of the second noble metal plated layer 14 serving as the external terminal is exposed on the side where the corresponding plated layer protrudes.
- resin sealing when the substrate for a semiconductor device shown in FIG. 17A ′ is used, when resin sealing is performed, resin may wrap around the external terminal surface due to the uneven height of the terminal due to the plating of the terminal pattern. In that case, the surface of the sealed resin is polished to expose the external terminal surface.
- the substrate for a semiconductor device shown in FIG. 17B is used.
- the metal plate 1 of the semiconductor device substrate is etched, and the metal plate 1 is removed by dissolution or the like.
- FIG. 17C shows the state at this time.
- the semiconductor element 40 is mounted on the internal terminal surface side appeared by removing the metal plate 1.
- the electrodes of the element 40 are connected to internal terminals exposed flush from the surface of the resin 20.
- the electrode of the semiconductor element 40 is connected to the internal terminal
- the wire method the electrode of the semiconductor element 40 is connected to the internal terminal by a wire. Since the surface of the internal terminal exposed as the wiring member 30 is flush with the surface of the resin 20, the semiconductor element 40 to be mounted can be mounted in a stable state without being inclined.
- the description of die bonding for fixing the semiconductor element 40 is omitted.
- the surface side on which the semiconductor element 40 is mounted is sealed with a resin 41.
- the semiconductor device is completed.
- cutting processing is performed to obtain individual semiconductor devices.
- the external connection terminals are already formed on the back surface side of the semiconductor device so as to be exposed from the resin 20, the processing for exposing the resin-covered external connection portion as in the conventional semiconductor device manufacturing method Is unnecessary.
- the semiconductor device substrate used in the method of manufacturing a semiconductor device of the present invention can be manufactured, for example, by the manufacturing method described in the first embodiment.
- a permanent resist layer is formed to a predetermined thickness thicker than the plating layer formed on the metal plate, and the permanent resist layer is internally formed on the metal plate.
- a plating layer to be a terminal is formed, a metal plating layer having the same shape is formed on the metal layer, and a plating layer to be a partial external terminal is further formed thereon, or a metal plating is partially formed.
- a step of mounting the semiconductor element on the side of the wiring member in contact with the metal plate, a step of connecting an electrode of the mounted semiconductor element and an internal terminal of the wiring member, and a step of resin sealing the side on which the semiconductor element is mounted Have That.
- the semiconductor element can be mounted on the surface of the wiring member without a step following the surface of the metal plate, and the surface of the external terminal is already exposed from the opening of the permanent resist. Therefore, it is possible to omit the formation of the resin layer and the conventional processing steps for exposing the part connected to the outside.
- FIG. 18 is a cross-sectional view of a wiring member used in a method of manufacturing a semiconductor device according to an example corresponding to the sixth embodiment of the present invention.
- the semiconductor element is mounted on the plating layer side serving as the internal terminal of the wiring member shown in FIG. 18, the electrode of the semiconductor element and the internal terminal portion of the wiring member are connected, and the semiconductor element mounting side is resin-sealed
- It is an explanatory view showing a state.
- 20A to 20F are explanatory views showing an example of steps of a method of manufacturing a wiring member used in the method of manufacturing a semiconductor device according to the embodiment of FIG. As shown in FIG.
- the wiring member 30 to be prepared for use in the manufacture of the semiconductor device of the present embodiment is a metal having the same shape as the first noble metal plating layer 11 and the first noble metal plating layer 11 to be internal terminals.
- the second metal plating layer 13 is partially formed on the plating layer 12 and the metal plating layer 12, and the second noble metal plating layer 14 having the same shape as the second metal plating layer 13 is formed. It is done.
- the first precious metal plating layer 11 is composed of an Au plating layer and a Pd plating layer in order from the top of FIG.
- the metal plating layer 12 is a Ni plating layer
- the second metal plating layer 13 is also a Ni plating layer
- the second noble metal plated layer 14 is composed of a Pd plated layer and an Au plated layer, and the Au plated layer is exposed on the front and back of the wiring member.
- 1-1 denotes an internal terminal portion
- 1-2 denotes a wiring portion
- 1-3 denotes an external terminal portion
- 16 denotes a permanent resist.
- the semiconductor element 40 is mounted on the surface side of the plating layer (first noble metal plating layer) 11 to be an internal terminal, and the electrode of the semiconductor element 40 is permanent resist 16 It connects with the internal terminal exposed flush from the surface of.
- the electrode of the semiconductor element 40 and the internal terminal are connected, and in the wire method, the electrode of the semiconductor element 40 and the internal terminal are connected by a wire.
- the semiconductor element 40 to be mounted can be mounted in a stable state without being inclined.
- the description of the die bonding for fixing the semiconductor element 40 and the like is omitted.
- the surface side on which the semiconductor element 40 is mounted is sealed with a resin 41.
- the semiconductor device is completed.
- cutting processing is performed to obtain individual semiconductor devices.
- the external connection terminal is already formed on the back surface side of the semiconductor device so as to be exposed from the opening of the permanent resist 16, it is covered and covered with the resin necessary in the conventional semiconductor device manufacturing method. The processing for exposing the external connection portion is unnecessary.
- the wiring member 30 used in the method of manufacturing a semiconductor device of the present invention can be manufactured, for example, as follows (see FIGS. 20A to 20F).
- a copper material having a thickness of 0.15 mm, which is also used as a lead frame material is prepared as the metal plate 1.
- a dry film resist 9 having a thickness of, for example, 25 ⁇ m is laminated on both sides of the metal plate 1, and then a surface is formed using a glass mask on which a pattern A for forming plating is formed at a predetermined position on the surface side.
- the dry film resist 9 on the side is exposed and developed to form a resist mask in which a portion to be plated is opened.
- a resist mask is formed to cover the entire back surface of the metal plate 1. This exposure and development are the same as in the conventional method.
- the metal plate 1 exposed from the formed resist mask is subjected to general pretreatment for plating, and then, as a first precious metal plating layer, Au is 0.003 ⁇ m or more, Pd is 0.01 ⁇ m in order.
- Au is 0.003 ⁇ m or more
- Pd is 0.01 ⁇ m in order.
- it metal-plates so that Ni may be set to 6 micrometers or more as a metal plating layer (refer FIG. 20A).
- the resist masks on both sides are peeled off (see FIG.
- the permanent resist 20 is laminated on the front side, and the same dry film resist 9 as described above is laminated on the back side.
- a resist mask is formed by performing exposure and development using a glass mask on which a pattern B for forming a plating is formed by overlapping a portion to be an external terminal, which is a part of the plating layer previously formed. Do.
- a resist mask is formed to cover the whole as in the previous case.
- Ni is made 30 ⁇ m or more as a second metal plating layer
- Pd is made 0.01 ⁇ m or more as a second precious metal plating layer
- Au as a second metal plating layer sequentially on the Ni plating surface which is a metal plating layer exposed from the formed resist mask
- the resist mask on the back surface is removed to leave the permanent resist 16 (see FIG. 20D), and the metal plate is removed by removing the metal plate. Obtained (see FIG. 20E).
- the second metal plating is omitted, and plating is performed on the Ni plating surface, which is a metal plating layer, so that Pd is 0.01 ⁇ m or more and Au is 0.003 ⁇ m or more as the second noble metal plating layer. good.
- the wiring member 30 is used with the lower side of the wiring member 30 turned upside down in order to mount the semiconductor element on the surface on the side of the metal plate 1 removed (see FIG. 20F).
- Comparative Example 2 Next, a method of manufacturing a conventional semiconductor device will be described as Comparative Example 2.
- a plating layer to be an external terminal is formed on a metal plate contrary to the substrate for a semiconductor device used in the present invention, the plating layer is overlapped in the same shape, and the upper layer is an internal terminal A plating layer is formed.
- These plated layers are formed at substantially the same height as a plurality of (plated) plated layers according to the number of electrodes of the semiconductor element to be mounted.
- the semiconductor element is mounted on the internal terminal of the substrate such as the semiconductor device, and the electrode of the semiconductor element is connected to the internal terminal. However, if a plurality of heights of 30 ⁇ m, 40 ⁇ m, etc.
- the semiconductor device substrate is There is a height difference in height up to the upper surface of the terminal. Therefore, when the semiconductor device is mounted, the semiconductor device may be inclined or conduction failure may occur in the connection between the electrode of the semiconductor device and the internal terminal.
- the side on which the semiconductor element is mounted is sealed with resin, and only the metal plate of the semiconductor device substrate is removed.
- the surface of the plating layer to be an external terminal in contact with the metal plate appears on the back surface side of the resin.
- the resin is covered so that the entire back surface side of the resin is covered, and then the resin is covered to expose only the external terminal portion.
- the semiconductor device is completed by exposing a part of the external terminal portion. In the type in which a large number of semiconductor devices are sealed collectively, cutting is performed to complete individual semiconductor devices.
- the embodiments and examples of the semiconductor device substrate, the semiconductor device wiring member and the method of manufacturing them, and the method of manufacturing a semiconductor device using the semiconductor device substrate according to the present invention have been described above.
- the device substrate and the semiconductor device wiring member are not limited to the configurations of the above-described embodiment and examples.
- the substrate for a semiconductor device of the first to third embodiments and in the wiring member for a semiconductor device of the fourth embodiment, Au, Pd on the first noble metal plating layer, Ni on the metal plating layer, second metal
- Ni was used for the plating layer and Pd and Au for the second noble metal plating layer
- the combination of plating used to form the second precious metal plating layer is not limited to this, and as a modification, the first precious metal plating layer plated as shown in the following Table 1, metal
- the plating layer (or the metal plating layer and the second metal plating layer) and the second noble metal plating layer may be combined to constitute the substrate for a semiconductor device and the wiring member for a semiconductor device of the present invention. In Table 1, plating is shown as being applied in order from the top of the column in each modification.
- the substrate for a semiconductor device, the wiring member for a semiconductor device and the method for manufacturing them of the present invention, and the method for manufacturing a semiconductor device using the substrate for a semiconductor device it is necessary to assemble a surface mount type sealing resin type semiconductor device It is useful in the field considered.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
そして、従来、このようなタイプの半導体装置用基板及び半導体装置用基板を用いた半導体装置は、例えば、次の特許文献1に記載されている。
本発明の半導体装置用基板は、所定面上における所定部位に内部端子となるめっき層が形成され、内部端子となるめっき層の上に部分的に外部端子となるめっき層が形成され、外部端子となるめっき層表面の所定面からの高さが、他のめっき層表面の所定面からの高さに比べて高くなっている。
本件出願人は、試行錯誤の末、半導体装置を製造する際に用いる半導体装置用基板における内部端子と外部端子の電気的な接続面を、従来の半導体装置用基板とは逆にすることを着想した。
即ち、従来の半導体装置用基板では、半導体装置を製造する際には、外部端子面は金属板側の面、内部端子面は金属板とは反対側の面を露出させた状態で用いるように構成されている。
これに対し、本発明の第1~第3の形態の半導体装置用基板では、半導体装置を製造する際には、外部端子面は金属板とは反対側の面、内部端子面は金属板側の面を露出させた状態で用いる着想のもとに、内部端子及び配線部を構成するめっき層よりも外部端子を構成するめっき層を金属板から高くなるように構成する。
また、本発明の第3の形態の半導体装置用基板では、そのために、金属板および内部端子となる金属めっき層の上に、金属めっき層における所定部位を開口させた永久レジストを形成し、更に、永久レジストの開口部に位置する金属めっき層の上に外部端子となる第2の貴金属めっき層を形成する。
また、本発明の半導体装置用配線部材では、半導体装置を製造する際には、外部端子面は半導体装置用基板の製造時に用いる金属板とは反対側の面、内部端子面は半導体装置用基板の製造時に用いる金属板側の面を露出させた状態で用いる着想のもとに、内部端子及び配線部を構成するめっき層よりも外部端子を構成するめっき層を半導体装置用基板の製造時に用いる金属板から高くなるように構成する。
また、例えば、本発明の第2、第3の形態の半導体装置用基板における金属板をエッチングによる溶解等により除去すると、金属板除去後には、金属板を除去した側の内部端子となる第1の貴金属めっき層の面が金属板の表面に倣って段差のない(高低差1μm以下の)状態で露出することになる。
また、例えば、本発明の半導体装置用配線部材の製造時に用いる金属板をエッチングによる溶解等により除去すると、金属板除去後には、金属板を除去した側の内部端子となる第1の貴金属めっき層の面が金属板の表面に倣って段差のない(高低差1μm以下の)状態で露出することになる。この金属板は、リードフレーム等に使用される一般的な圧延材である。
これらの金属板は、リードフレーム等に使用される一般的な圧延材である。
ここで、従来の半導体装置用基板を用いた半導体装置と同様に、第1の貴金属めっき層上に半導体素子を搭載するが、第1の貴金属めっき層の面が段差のない状態で露出しているので、接続面は全体がフラットであるため、接続が安定する。
この場合、外部端子は金属板側とは反対側の面を露出させる必要がある。
この半導体装置用基板は、内部端子部及び配線部とは厚みの異なる外部端子部を予め設けられているために、半導体装置の製造工程において内部端子及び配線部を樹脂で封止し、外部端子のみを露出させることが容易にできる。このため、この半導体装置用基板を用いると、従来の半導体装置用基板とは異なり半導体装置の製造過程で外部部材との接続面に開口部を形成する工程が不必要となり、その分、半導体装置の製造時の工程数が減少し生産性が向上する。
上述したように、本件出願人は、試行錯誤の末、半導体装置を製造する際に用いる半導体装置用基板における内部端子と外部端子の電気的な接続面を、従来の半導体装置用基板とは逆にすることを着想した。
即ち、従来の半導体装置用基板では、半導体装置を製造する際には、外部端子面は金属板側の面、内部端子面は金属板とは反対側の面を露出させた状態で用いるように構成されている。
これに対し、本発明に使用する半導体装置用基板では、半導体装置を製造する際には、外部端子面は金属板とは反対側の面、内部端子面は金属板側の面を露出させた状態で用いるように形成され、内部端子部及び配線部を構成するめっき層よりも外部端子部を構成するめっき層を金属板から高くなるように構成されている。
ここで、従来の半導体装置用基板を用いた半導体装置と同様に、第1の貴金属めっき層上に半導体素子を搭載するが、第1の貴金属めっき層の面が段差のない状態で露出しているので、接続する面は全体がフラットであるため、半導体素子が傾くことも無く、複数の内部端子部も均一な高さであるので半導体素子の電極とも接続が安定する。
そして、外部端子部は金属板側とは反対側の面を露出させる必要があるが、金属板上における、内部端子部、外部端子部及び配線部となる部位に貴金属めっき、金属めっきを施した後、従来の半導体装置用基板とは異なり、更に、外部端子となる部位のみに、さらに金属めっき及び貴金属めっきを積み増して施すことで、内部端子部、配線部とは高低差のある外部端子を形成させた半導体装置用基板を用いることで外部端子部の面を露出させた樹脂層を容易に形成できると共に、外部端子部の面を露出させる工程を省略することができる。
この半導体装置用基板から金属板を除去することで、永久レジスト層内に、金属板に面して内部端子となるめっき層が形成され、内部端子となるめっき層の一部に外部端子となるめっき層が形成され、反対の面側に外部端子となるめっき層の面のみが永久レジストの開口部から露出した、永久レジストによりめっき層が固定された配線部材を得る。
本発明の他の半導体装置の製造方法は、上記の配線部材を用いて、配線部材が金属板と接していた側に半導体素子を搭載して組み立てる。
そして、本発明の他の半導体装置の製造方法では、この配線部材の半導体素子搭載面における内部端子となるめっき層上に半導体素子を搭載するが、内部端子となるめっき層の面が段差のない状態で露出しているので、接続する面は全体がフラットであるため、半導体素子が傾くことも無く、複数の内部端子部も均一な高さであるので半導体素子の電極とも接続が安定する。
このように、本発明の他の半導体装置の製造方法では、この配線部材の金属板を除去した側に半導体素子を搭載することで、搭載する半導体素子の傾きを防止してボンディング等の接続不良によって最終的に導通不良となることを解消することができる。しかも、この配線部材は、外部端子側は、永久レジスト上面の開口部から外部端子の面のみが既に露出しているので、従来の半導体装置の製造方法のような外部端子部の面を露出させるための開口部を形成する工程が省略できる。
第1実施形態
図1A、図1Bは本発明の第1実施形態にかかる半導体装置用基板の構成を示す図で、図1Aは外部端子側からみた部分平面図、図1Bは図1AのA-A断面図である。図2A~図2Iは図1A、図1Bに示す半導体装置用基板の製造工程を示す説明図である。図3は図2の製造工程における半導体装置用基板の状態の変化を示す平面図である。
金属板1は、例えば、銅板で構成されている。
第1の貴金属めっき層11は、例えば、金属板1側から順に形成された、Auめっき層11aと、Pdめっき層11b上とで構成されている。
金属めっき層12、第2の金属めっき層13は、例えば、Niめっき層で構成されている。
第2の貴金属めっき層14は、例えば、金属板1側から順に形成された、Pdめっき層14aと、Auめっき層14bとで構成されている。
そして、第2の貴金属めっき層14の表面(即ち、Auめっき層14bの表面)の金属板1の面からの高さH2が、金属めっき層12の表面の金属板1の面からの高さH1に比べて高くなっている。
まず、図2Aに示すように、基板となる金属板の両面にレジストマスク用のドライフィルムレジストをラミネートする。このとき金属板には、図3Aに示すように、めっき層は形成されていない。
次に、図2Bに示すように、表面側のドライフィルムレジストに対しては、所定位置に、内部端子、配線部及び外部端子の基部を形成するパターン(ここではパターンAとする)が形成されたガラスマスクを用いて、表面側を露光・現像するとともに、裏面側のドライフィルムレジストに対しては、全面を照射するガラスマスクを用いて裏面側を露光・現像する。そして、図2Cに示すように、表面にはパターンAのレジストマスクを形成し、裏面には全面を覆うレジストマスクを形成する。なお、露光・現像は従来公知の方法により行う。例えば、ガラスマスクで覆った状態で紫外線を照射し、ガラスマスクを通過した紫外線が照射されたドライフィルムレジストの部位の現像液に対する溶解性を低下させて、それ以外の部分を除去することで、レジストマスクを形成する。なお、ここでは、レジストとしてネガ型のドライフィルムレジストを用いたが、レジストマスクの形成には、ネガ型の液状レジストを用いてもよい。さらには、ポジ型のドライフィルムレジスト又は液状レジストを用いて、ガラスマスクを通過した紫外線が照射されたレジストの部分の現像液に対する溶解性を増大させて、その部分を除去することでレジストマスクを形成するようにしてもよい。さらにまた、レジストマスクを形成するためのレジストとしては、ソルダーレジストを用いてもよい。
次に、レジストマスクから露出している金属板の部位に、第1の貴金属めっき層11として、例えば、Auめっき層11a、Pdめっき層11bの順で夫々所定の厚さとなるように、Auめっき、Pdめっきを夫々施す。
次に、Pdめっき層11bの上に金属めっき層12として、例えば、Niめっき層が貴金属めっき層と平面形状が同形状に形成されるように、Niめっきを施す。図2Dはこのときの状態を示している。
次に、図2Fに示すように、先に形成したNiめっき層の一部であって外部端子となる部位に重ねてめっき層を形成するためのパターン(ここではパターンBとする)が形成されたガラスマスクを用いて、表面側を露光・現像するとともに、裏面側のレジストフィルムに対しては、全面を照射するガラスマスクを用いて裏面側を露光・現像する。そして、図2Gに示すように、表面にはパターンBのレジストマスクを形成し、裏面には全面を覆うレジストマスクを形成する。
次に、レジストマスクから露出している、金属めっき層12を構成するNiめっきの表面に、第2の金属めっき層13として、例えば、Niめっき層が形成されるように、Niめっきを施す。
次に、第2の金属めっき層13であるNiめっき層の表面に、第2の貴金属めっき層14として、例えば、Pdめっき層14a、Auめっき層14bの順で夫々所定の厚さとなるように、Pdめっき、Auめっきを夫々施す。図2Hは、このときの状態を示している。なお、第2の金属めっき層13を設けずに、第2の貴金属めっき層14として、例えば、Pdめっき層14a、Auめっき層14bの順で夫々所定の厚さとなるように、Pdめっき、Auめっきを夫々施してもよい。
次に、図2Iに示すように、両面のレジストマスクを剥離することで、本実施形態の半導体装置用基板が完成する。図3Dは、このときの半導体装置用基板に施されたパターンBのめっき層を示す図、図3Eは図3Dにおいて矩形で囲んだ一部の領域を拡大して示す図である。
まず、図4Aに示す半導体装置用基板の金属板上で内部端子、配線部、外部端子に対応する各めっき層が突出した側に、図4Bに示すように、外部端子となる貴金属めっき層14の表面が露出するようにして、その他の部位を樹脂で封止する。図4Bは、金属めっき層12を構成するNiめっきの表面に、第2の金属めっき層13を設けずに、第2の貴金属めっき層である貴金属めっき層14を設けた半導体装置用基板を用いた場合における樹脂封止の状態を示している。金属めっき層12を構成するNiめっきの表面に、第2の金属めっき層13を設け、第2の金属めっき層13の表面に第2の貴金属めっき層である貴金属めっき層14を設けた半導体装置用基板を用いた場合は、図4B’に示すように、樹脂封止したときに樹脂の面から貴金属めっき層14が突出した状態となる。なお、以下の説明では、便宜上、第2の金属めっき層13を設けずに、第2の貴金属めっき層である貴金属めっき層14を設けた半導体装置用基板を用いるものとする。なお、第2の金属めっき層13を設けずに、第2の貴金属めっき層である貴金属めっき層14を設けた半導体装置用基板を用いた場合、樹脂封止の際には、端子パターンのめっきによる端子の高さの不均一さにより外部端子面に樹脂が回りこむことがある。その場合には、封止した樹脂の表面を研磨して外部端子面を露出させる。
次に、半導体装置用基板の金属板に対してエッチングを施し、金属板を溶解等により除去する。これにより、内部端子、配線部、外部端子の表面が樹脂面から面一に露出する。図4Cは、このときの状態を示している。
次に、半導体素子を金属板を除去したことで現れた内部端子面側に搭載し、半導体素子の電極を、樹脂面から面一に露出した内部端子と接続させる。この場合、フリップチップ方式では、図4Dに示すように、半導体素子の電極と内部端子とを接続させる。また、ワイヤー方式では、図4Eに示すように、半導体素子の電極と内部端子とをワイヤーで連結する。なお、第1実施形態の半導体装置用基板を用いて図4A~図4Cに示す半導体装置の製造工程を経て露出した内部端子の表面が樹脂面と面一となるため、半導体素子を安定した状態で搭載できる。なお、ここでは、便宜上、半導体素子を固定するダイボンディングに関しては説明を省略する。
次に、図4Fに示すように、半導体素子を搭載した面を樹脂で封止する。これにより、半導体装置が完成する。なお、図4A~図4Fは、半導体装置用基板の上下方向を変えないで図示している。
図5A、図5Bは本発明の第2実施形態にかかる半導体装置用基板の構成を示す図で、図5Aは外部端子側からみた部分平面図、図5Bは図5AのA-A断面図である。図6A~図6J’は図5A、図5Bに示す半導体装置用基板の製造工程を示す説明図である。
基板となる金属板の両面へのレジストマスク用のドライフィルムレジストのラミネート(図6A)から両面のレジストマスクの剥離(図6I)までの工程は、図2A~図2Iに示した第1実施形態の半導体装置用基板の製造工程と略同じである。
次に、図6Jに示すように、金属板における内部端子、配線部、外部端子に対応する各めっき層が突出した側に、外部端子となる貴金属めっき層14の表面が露出するようにして、その他の部位を樹脂で封止する。図6Jは、金属めっき層12を構成するNiめっきの表面に、第2の金属めっき層13を設けずに、第2の貴金属めっき層である貴金属めっき層14を設けた金属板を用いた場合における樹脂封止の状態を示している。金属めっき層12を構成するNiめっきの表面に、第2の金属めっき層13を設け、第2の金属めっき層13の表面に第2の貴金属めっき層である貴金属めっき層14を設けた金属板を用いた場合は、図6J’に示すように、樹脂封止したときに樹脂の面から貴金属めっき層14が突出した状態となる。なお、ここでは、便宜上、第2の金属めっき層13を設けずに、第2の貴金属めっき層である貴金属めっき層14を設けた金属板を用いるものとする。なお、第2の金属めっき層13を設けずに、第2の貴金属めっき層である貴金属めっき層14を設けた金属板を用いた場合、樹脂封止の際には、端子パターンのめっきによる端子の高さの不均一さにより外部端子面に樹脂が回りこむことがある。その場合には、封止した樹脂の表面を研磨して外部端子面を露出させる。これにより、本実施形態の半導体装置用基板が完成する。
まず、図7Aに示す半導体装置用基板の金属板に対してエッチングを施し、金属板を溶解等により除去する。これにより、内部端子、配線部、外部端子の表面が樹脂面から面一に露出する。図7Bは、このときの状態を示している。
以下、半導体素子の内部素子面側への搭載(図7C、図7D)、半導体素子を搭載した面の樹脂封止(図7E)、完成した半導体装置の外部部材への搭載(図7F)の各工程は、図4D~図4Gに示した第1実施形態の半導体装置用基板を用いた半導体装置の製造工程と略同じである。
図8A、図8Bは本発明の第3実施形態にかかる半導体装置用基板の構成を示す図で、図8Aは外部端子側からみた部分平面図、図8Bは図8AのA-A断面図である。図9A~図9Jは図8A、図8Bに示す半導体装置用基板の製造工程を示す説明図である。
基板となる金属板の両面へのレジストマスク用のドライフィルムレジストのラミネート(図9A)から第1の貴金属めっき層11、金属めっき層12の形成(図9D)までの工程は、図2A~図2Dに示した第1実施形態の半導体装置用基板の製造工程と略同じである。
次に、図9Fに示すように、先に形成したNiめっき層の一部であって外部端子となる部位に重ねてめっき層を形成するためのパターン(ここではパターンBとする)が形成されたガラスマスクを用いて、表面側を露光・現像するとともに、裏面側のレジストフィルムに対しては、全面を照射するガラスマスクを用いて裏面側を露光・現像する。そして、図9Gに示すように、表面にはパターンBの永久レジストからなるレジストマスク(図8A、図8Bに示す永久レジスト16)を形成し、裏面には全面を覆うレジストマスクを形成する。
次に、レジストマスクから露出している、金属めっき層12を構成するNiめっきの表面に、第2の金属めっき層13として、例えば、Niめっき層が形成されるように、Niめっきを施す。
次に、第2の金属めっき層13であるNiめっき層の表面に、第2の貴金属めっき層14として、例えば、Pdめっき層14a、Auめっき層14bの順で夫々所定の厚さとなるように、Pdめっき、Auめっきを夫々施す。図9Hは、このときの状態を示している。なお、第2の金属めっき層13を設けずに、第2の貴金属めっき層14として、例えば、Pdめっき層14a、Auめっき層14bの順で夫々所定の厚さとなるように、Pdめっき、Auめっきを夫々施してもよい。図9Iは、このときの状態を示している。
次に、図9Jに示すように、裏面のレジストマスクを剥離することで、本実施形態の半導体装置用基板が完成する。
まず、図10Aに示す半導体装置用基板の金属板に対してエッチングを施し、金属板を溶解等により除去する。これにより、内部端子、配線部、外部端子の表面が永久レジスト面から面一に露出する。図10Bは、このときの状態を示している。
次に、半導体素子を金属板を除去したことで現れた内部端子面側に搭載し、半導体素子の電極を、永久レジスト面から面一に露出した内部端子と接続させる。この場合、フリップチップ方式では、図10Cに示すように、半導体素子の電極と内部端子とを接続させる。また、ワイヤー方式では、図10Dに示すように、半導体素子の電極と内部端子とをワイヤーで連結する。なお、第3実施形態の半導体装置用基板を用いて図10A、図10Bに示す半導体装置の製造工程を経て露出した内部端子の表面が永久レジスト面と面一となるため、半導体素子を安定した状態で搭載できる。なお、ここでは、便宜上、半導体素子を固定するダイボンディングに関しては説明を省略する。
次に、図10Eに示すように、半導体素子を搭載した面を樹脂で封止する。これにより、半導体装置が完成する。なお、図10A~図10Eは、半導体装置用基板の上下方向を変えないで図示している。
図11A、図11Bは本発明の第4実施形態にかかる半導体装置用配線部材の構成を示す図で、図11Aは外部端子側からみた部分平面図、図11Bは図11AのA-A断面図である。図12A~図12Kは図11A、図11Bに示す半導体装置用配線部材の製造工程を示す説明図である。
第1の貴金属めっき層11は、例えば、樹脂層15の一方の面15a側から順に形成された、Auめっき層11aと、Pdめっき層11b上とで構成されている。
金属めっき層12、第2の金属めっき層13は、例えば、Niめっき層で構成されている。
第2の貴金属めっき層14は、例えば、樹脂層15の一方の面15a側から順に形成された、Pdめっき層14aと、Auめっき層14bとで構成されている。
そして、第2の貴金属めっき層14の表面(即ち、Auめっき層14bの表面)の樹脂層15の一方の面15aからの高さH2が、金属めっき層12の表面の樹脂層15の一方の面15aからの高さH1に比べて高くなっている。
基板となる金属板の両面へのレジストマスク用のドライフィルムレジストのラミネート(図12A)から両面のレジストマスクの剥離(図12I)までの工程は、図2A~図2Iに示した第1実施形態の半導体装置用基板の製造工程と略同じである。
次に、図12Jに示すように、金属板上で内部端子、配線部、外部端子に対応する各めっき層が突出した側に、外部端子となる貴金属めっき層14の表面が露出するようにして、その他の部位を樹脂で封止する。図12Jは、金属めっき層12を構成するNiめっきの表面に、第2の金属めっき層13を設けずに、第2の貴金属めっき層である貴金属めっき層14を設けた金属板を用いた場合における樹脂封止の状態を示している。金属めっき層12を構成するNiめっきの表面に、第2の金属めっき層13を設け、第2の金属めっき層13の表面に第2の貴金属めっき層である貴金属めっき層14を設けた金属板を用いた場合は、図12J’に示すように、樹脂封止したときに樹脂の面から貴金属めっき層14が突出した状態となる。なお、以下の説明では、便宜上、第2の金属めっき層13を設けずに、第2の貴金属めっき層である貴金属めっき層14を設けた金属板を用いるものとする。なお、第2の金属めっき層13を設けずに、第2の貴金属めっき層である貴金属めっき層14を設けた金属板を用いた場合、樹脂封止の際には、端子パターンのめっきによる端子の高さの不均一さにより外部端子面に樹脂が回りこむことがある。その場合には、封止した樹脂の表面を研磨して外部端子面を露出させる。
次に、半導体装置用基板の金属板に対してエッチングを施し、金属板を溶解等により除去し、図12Kに示すように、内部端子、配線部、外部端子の表面を樹脂面から面一に露出させる。これにより、本実施形態の半導体装置用配線部材が完成する。
まず、図13Aに示す半導体装置用配線部材の内部端子面側に半導体素子を搭載し、半導体素子の電極を、樹脂面から面一に露出した内部端子と接続させる。この場合、フリップチップ方式では、図13Bに示すように、半導体素子の電極と内部端子とを接続させる。また、ワイヤー方式では、図13Cに示すように、半導体素子の電極と内部端子とをワイヤーで連結する。なお、第4実施形態の半導体装置用配線部材では、露出した内部端子の表面が樹脂面と面一になっているため、半導体素子を安定した状態で搭載できる。なお、ここでは、便宜上、半導体素子を固定するダイボンディングに関しては説明を省略する。
次に、図13Dに示すように、半導体素子を搭載した面を樹脂で封止する。これにより、半導体装置が完成する。なお、図13A~図13Dは、半導体装置用配線部材の上下方向を変えないで図示している。
次に、上記各実施形態の半導体装置用基板、半導体装置用配線部材の比較例として、従来の半導体装置用基板の構成を説明する。図14A~図14Eは比較例1にかかる従来の半導体装置用基板の製造工程を示す説明図である。図15A~図15Cは図14A~図14Eの製造工程における半導体装置用基板の状態の変化を示す平面図である。
図14A~図14Dに示すように、半導体装置用基板となる金属板の両面へのレジストマスク用のドライフィルムレジストのラミネート、表面側及び裏面側におけるガラスマスクを用いた露光・現像によるパターンA及び全面のレジストマスクの形成、レジストマスクから露出している金属板の部位へのめっきまでは、図2A~図2Dに示した第1実施形態の半導体装置用基板の製造工程と略同じである。
比較例1の半導体装置用基板は、図14Dの状態から両面のレジストマスクを剥離することによって完成し、図2E~図2Iに示した工程を経ない点で第1実施形態の半導体装置用基板の製造工程とは異なる。また、比較例1の半導体装置用基板は、図6E~図6Jに示した工程を経ない点で第2実施形態の半導体装置用基板の製造工程とは異なる。また、比較例1の半導体装置用基板は、図9E~図9Jに示した工程を経ない点で第3実施形態の半導体装置用基板の製造工程とは異なる。また、比較例1の半導体装置用基板は、図12E~図12Kに示した工程を経ない点で第4実施形態の半導体装置用配線部材の製造工程とは異なる。
まず、図16A、図16Bに示す半導体装置用基板の金属板における内部端子、配線部、外部端子となるめっき層が突出した側に、半導体素子を搭載し半導体素子の電極を内部端子と接続させる。この場合、フリップチップ方式では、図16Aに示すように、半導体素子の電極と内部端子とを接続させる。また、ワイヤー方式では、図16Bに示すように、半導体素子の電極と内部端子とをワイヤーで連結する。なお、半導体素子を搭載する面は、めっき加工による形成された厚さのばらつきから高低差を有しているため安定した状態には搭載することが難しい。そこで、半導体素子を搭載する金属板と半導体素子との隙間にフィルム状やペースト状の接着材料を用いた接着層を設け、半導体素子を搭載した際に半導体素子と内部端子の一部が接触して半導体素子が傾くことが無いよう接着層を介して金属板に半導体素子を固定させる。
次に、図16Cに示すように、半導体素子を搭載した面を樹脂で封止する。
次に、半導体装置用基板の金属板にエッチングを施し、金属板を溶解除去する。これにより、半導体装置の裏面側には内部端子、配線部、外部端子の表面が樹脂面から面一に露出する。図16Dは、このときの状態を示している。
次に、図16Eに示すように、半導体装置の裏面側を樹脂で覆い、外部端子の一部の表面が露出するように、樹脂に開口部を加工して外部絶縁層を形成する。これにより、半導体装置が完成する。
例えば、図16Fに示す樹脂面から内部端子、配線部、外部端子の表面が面一に露出した側に、図16Gに示すように、レジストマスク用の液状ソルダーレジストを塗布し、ガラス転移点を僅かに下回る温度で加熱しプレキュア(予備硬化)を行う(図16H)。
次に、図16Iに示すように、外部端子となる部位に開口部を形成するためのパターンが形成されたガラスマスクを用いて、予備硬化したソルダーレジストを露光・現像する。そして、図16Jに示すように、外部端子となる部位に開口部を形成するためのパターンのレジストマスクを形成する。その後、レジストマスクに対し最終的な強度を得るために更に加熱するポストキュアを行う(図16K)。
これにより、図16Lに示す半導体装置が完成する。
このように、比較例1の半導体装置用基板では、外部端子と内部端子及び配線部を構成するめっき層の厚みが、ほぼ同じに形成されているため、その後の半導体装置の製造工程において、めっき層を埋設するための絶縁層を形成し、その絶縁層に外部端子と接続するための開口部を加工する必要があり、半導体装置の組立てにおける工程が増える結果、製造の遅延等を招き、生産性が悪化する。
これに対し、第1実施形態の半導体装置用基板によれば、外部端子と、内部端子及び配線部とに高低差を設けたので、その後の半導体装置の製造工程において、樹脂等で内部端子及び配線部のみを封止し、外部端子のみを露出させることが可能となる。このため、比較例1の半導体装置用基板とは異なり、半導体装置の製造工程において外部部材との接続面に開口部を加工する必要がなく、その分、工程数が減少し、生産性が向上する。
これに対し、第1実施形態の半導体装置用基板によれば、その後の半導体装置の製造工程において、半導体素子を搭載する内部端子面および半導体素子と電気的接続をする内部端子部の高さが均一になるため、半導体素子と内部端子部との電気的な接続の信頼性が向上する。
また、第2実施形態の半導体装置用基板によれば、外部端子と、内部端子及び配線部とに高低差を設け、樹脂で内部端子及び配線部のみを封止し、外部端子のみを露出させたので、比較例1の半導体装置用基板とは異なり、半導体装置の製造工程において外部部材との接続面に開口部を加工する必要がなく、その分、工程数が減少し、生産性が向上する。
また、第3実施形態の半導体装置用基板によれば、外部端子と、内部端子及び配線部とに高低差を設け、永久レジスト等で内部端子及び配線部のみを封止し、外部端子のみを露出させたので、比較例1の半導体装置用基板とは異なり、半導体装置の製造工程において、外部部材との接続面に開口部を有する絶縁層を設ける必要がなく、その分、工程数が減少し、生産性が向上する。さらに、第3実施形態の半導体装置用基板によれば、金属板を除去した配線部材として出荷することもできる。そのようにすれば、半導体装置の製造時における金属板除去のためのエッチング工程も不要となり、生産性がより一層向上する。
また、第4実施形態の半導体装置用配線部材によれば、外部端子と、内部端子及び配線部とに高低差を設け、樹脂で内部端子及び配線部のみを封止し、樹脂層の他方の面から外部端子のみを露出させたので、比較例1の半導体装置用基板とは異なり、半導体装置の製造工程において金属板のエッチング除去や外部部材との接続面に開口部を加工する必要がなく、その分、工程数が減少し、生産性が向上する。
次に、本発明の第1実施形態に対応する半導体装置用基板及びその製造方法の実施例を説明する。
なお、各工程には、薬液洗浄や水洗浄等を含む前処理・後処理を実施するが一般的な処理であるので記載を省略する。
まず、金属板として、リードフレーム材としても使用されている板厚0.15mmの銅材を用意した。
レジストマスク形成工程においては、金属板の両面に、厚さ25μmのドライフィルムレジスト(旭化成製:AQ-2558)をラミネートした(図2A参照)。
次に、表面側に所定の位置にめっきを形成するためのパターンAが形成されたガラスマスクを用いて表面側のドライフィルムレジストに露光・現像を行い、めっきを形成する部分が開口されたレジストマスクを形成した(図2B、図2C参照)。裏面側のドライフィルムレジストに対しては、金属板の裏面全体を覆うレジストマスクを形成した。この露光・現像は従来工法と同様で、露光用のガラスマスクをドライフィルムレジストに密着させ、紫外線を照射することによって、パターンAをドライフィルムレジストに露光し、炭酸ナトリウムにより現像を行なった。
次のめっき工程では、形成したレジストマスクから露出している金属板に一般的なめっき前処理を行なった後、順にAuを0.003μm以上、Pdを0.01μm以上、Niを6μm以上となるようにめっきを施した(図2D参照)。
次に、両面のレジストマスクを剥離し、両面に同じドライフィルムレジストをラミネートした(図2E参照)。このとき、形成する第2の金属めっき層の厚さに応じてレジストの厚さを選定する必要があるが、本実施例では第2の金属めっき層を15~40μmとなるよう形成するため表面側のみ厚さが50μmのレジストを用い、裏面側は厚さが25μmのレジストを用いた。
そして、先に形成しためっき層の一部であって、外部端子となる部分に重ねてめっきを形成するためのパターンBが形成されたガラスマスクを用いて露光・現像を行ってレジストマスクを形成した(図2F、図2G参照)。なお、裏面側は、前回のレジストマスク形成工程と同様、全体を覆うレジストマスクを形成した。
次のめっき工程では、形成したレジストマスクから露出しているNiめっき面に順にNiを40μm以上、Pdを0.01μm以上、Auを0.003μm以上となるようにめっきを施し(図2H参照)、次に、両面のレジストマスクを除去して、半導体装置用基板を作製した(図2I参照)。
完成した半導体装置用基板の金属板における内部端子、配線部、外部端子に対応するめっき層が突出した側に、外部端子となる貴金属めっき層の表面が露出するようにして、その他の部位を樹脂で封止し(図4B参照)、次に、金属板(銅材)をエッチング除去し(図4C参照)、樹脂で固定されためっき層を配線として、金属板と接していた面側に半導体素子を搭載して内部端子と導通をとり(図4D参照)、半導体素子搭載部を樹脂封止することで外部端子の表面が樹脂の面から露出した状態の半導体装置を得た(図4F参照)。
次に、本発明の第2実施形態に対応する半導体装置用基板及びその製造方法の実施例を説明する。
なお、各工程には、薬液洗浄や水洗浄等を含む前処理・後処理を実施するが一般的な処理であるので記載を省略する。
実施例1と略同様に、金属板の用意、ドライフィルムレジストのラミネート(図6A)から両面のレジストマスクの剥離(図6I)までの各工程を行った。
次に、金属板における内部端子、配線部、外部端子に対応するめっき層が突出した側に、外部端子となる貴金属めっき層の表面が露出するようにして、その他の部位を樹脂で封止し(図6J参照)、半導体装置用基板を作製した。
完成した半導体装置用基板の金属板(銅材)をエッチング除去し(図7B参照)、樹脂で固定されためっき層を配線として、金属板と接していた面側に半導体素子を搭載して内部端子と導通をとり(図7C参照)、半導体素子搭載部を樹脂封止することで外部端子の表面が樹脂の面から露出した状態の半導体装置を得た(図7E参照)。
次に、本発明の第3実施形態に対応する半導体装置用基板及びその製造方法の実施例を説明する。
なお、各工程には、薬液洗浄や水洗浄等を含む前処理・後処理を実施するが一般的な処理であるので記載を省略する。
実施例1と略同様に、金属板の用意、ドライフィルムレジストのラミネート(図9A)からAu、Pd、Niの順でのめっき(図9D)までの各工程を行った。
次に、両面のレジストマスクを剥離し、先にめっき層を形成した表面側にフィルムタイプの永久レジスト(日立化成製:KI-1000T4F)をラミネートし、裏面側は上記同様のドライフィルムレジストをラミネートした(図9E参照)。このとき、形成する第2の金属めっき層の厚さに応じて永久レジストの厚さを選定する必要があるが、本実施例では第2の金属めっき層を15~40μmとなるよう形成するため厚さが50μmの永久レジストを用いた。また、裏面側は厚さが25μmのレジストを用いた。
そして、先に形成しためっき層の一部であって、外部端子となる部分に重ねてめっきを形成するためのパターンBが形成されたガラスマスクを用いて露光・現像を行ってレジストマスクを形成した(図9F、図9G参照)。なお、裏面側は、前回のレジストマスク形成工程と同様、全体を覆うレジストマスクを形成した。
次のめっき工程では、形成したレジストマスクから露出しているNiめっき面に順にPdを0.01μm以上、Auを0.003μm以上となるようにめっきを施した基板と、順にNiを15μm以上、Pdを0.01μm以上、Auを0.003μm以上となるようにめっきを施した基板の2種類のめっきが施された基板を作り(図9H、図9I参照)、次に、夫々の基板の裏面のレジストマスクを除去して、2種類の半導体装置用基板を作製した(図9J参照)。
完成した半導体装置用基板の金属板(銅材)をエッチング除去し(図10B参照)、永久レジストで固定されためっき層を配線として、金属板と接していた面側に半導体素子を搭載して内部端子と導通をとり(図10C参照)、樹脂封止することで外部端子の表面が永久レジストの面からほぼ面一に露出した状態(図10E参照)と、永久レジストの面から凹となった状態(図10Gに示すように、開口部に半田ボールを埋設することで外部部材の接続用端子と電気的に接続させることのできる状態)の2種類の半導体装置を得た。
次に、本発明の第4実施形態に対応する半導体装置用配線部材及びその製造方法の実施例を説明する。
なお、各工程には、薬液洗浄や水洗浄等を含む前処理・後処理を実施するが一般的な処理であるので記載を省略する。
実施例1と略同様に、金属板の用意、ドライフィルムレジストのラミネート(図12A)から両面のレジストマスクの剥離(図12I)までの各工程を行った。
次に、金属板における内部端子、配線部、外部端子に対応するめっき層が突出した側に、外部端子となる貴金属めっき層の表面が露出するようにして、その他の部位を樹脂で封止した(図12J参照)。
次に、金属板(銅材)をエッチング除去し、半導体装置用配線部材を作製した(図12K参照)。
完成した半導体装置用配線部材の樹脂で固定されためっき層を配線として、金属板と接していた面側に半導体素子を搭載して内部端子と導通をとり(図13C参照)、半導体素子搭載部を樹脂封止することで外部端子の表面が樹脂の面から露出した状態の半導体装置を得た(図13E参照)。
本実施形態の半導体装置の製造方法は、金属板上に内部端子となるめっき層が形成され、その上に同一形状で異なる金属のめっき層が形成され、更にその上に部分的にめっき層が形成され、部分的に形成されためっき層の上に同一形状で外部端子となるめっき層が形成され、外部端子となるめっき層表面が、他のめっき層に比べて金属板面からの高さが高くなっている半導体装置用基板を準備する。
次にこの半導体装置用基板を用いて、半導体装置用基板の金属板上で内部端子部、配線部、外部端子部に対応するめっき層が突出した側に、外部端子部の表面が露出するようにして、その他の部位を樹脂で封止する。
次に、半導体装置用基板の金属板を除去して、金属板と接していた面側にめっき層の面が樹脂面から面一に露出した配線部材を得る。
次に、金属板を除去したことで現れためっき層側に半導体素子を搭載し、半導体素子の電極を、樹脂面から面一に露出しためっき層の内部端子部と接続させる。
次に、半導体素子を搭載した面側を樹脂で封止する。
このような工程により、金属板の表面に倣って段差のない状態の面に半導体素子を搭載することができ、既に外部接続部が樹脂から露出した部材であることから、外部接続部を露出させる従来の加工工程を省略することができる。
図17A~図17Dは本発明の第5実施形態に対応する実施例にかかる半導体装置の製造方法の工程を示した図で、図17A、図17A’は本実施例の半導体装置の製造に使用する半導体装置用基板の構成を示す説明図、図17B、図17B’は図17A、図17A’に示す半導体装置用基板に、外部端子部の面が露出するよう樹脂で封止した状態を示す説明図、図17Cは図17Bに示す半導体装置用基板から金属板を除去し、配線部材とした状態を示す説明図、図17Dは図17Cに示す配線部材の内部端子となるめっき層側に半導体素子を搭載し、半導体素子の電極と配線部材の内部端子部を接続し、半導体素子を搭載した側を樹脂封止した状態を示す説明図である。
金属板1は、例えば、銅板で構成されている。
第1の貴金属めっき層11は、例えば、金属板1側から順に形成された、Auめっき層とPdめっき層とで構成されている。
金属めっき層12、第2の金属めっき層13は、例えば、Niめっき層で構成されている。
第2の貴金属めっき層14は、例えば、金属板1側から順に形成された、Pdめっき層とAuめっき層とで構成されている。
そして、第2の貴金属めっき層14の表面(即ち、Auめっき層の表面)の金属板1の面からの高さを約40μm、金属めっき層12の表面の金属板1の面からの高さを約6μmとした半導体装置用基板を本実施例の半導体装置の製造に用いた。
なお、本実施例の変形例として、図17A’に示すように、金属めっき層12の上に第2の金属めっき層13が形成されず、金属めっき層12の上に部分的に外部端子となる第2の貴金属めっき層14が形成された半導体装置用基板を半導体装置の製造に用いてもよい。
次に、半導体装置用基板の金属板1に対してエッチングを施し、金属板1を溶解等により除去する。これにより、金属板1と接していた面側に内部端子部1-1、配線部1-2、外部端子部1-3の面が樹脂面から面一に露出した配線部材30が得られる。図17Cは、このときの状態を示している。
次に、半導体素子40を搭載した面側を樹脂41で封止する。これにより、半導体装置が完成する。なお、複数の半導体装置を一括で封止する場合は、切断加工を行って個々の半導体装置が得られることになる。
この時既に半導体装置の裏面側には外部接続端子が樹脂20から露出した状態に形成されていることから、従来の半導体装置の製造方法におけるような樹脂で覆われた外部接続部を露出させる加工は不要となる。
本実施形態の半導体装置の製造方法は、金属板上に形成されるめっき層より厚く所定の厚さで永久レジスト層が形成され、永久レジスト層内には、金属板上に内部端子となるめっき層が形成され、その上に同一形状で金属のめっき層が重ねて形成され、更にその上に、部分的に外部端子となるめっき層が形成され、あるいは部分的に金属のめっき層とその上に外部端子となるめっき層が形成されている半導体装置用基板から、金属板を除去することで得られる、永久レジストによりめっき層が固定された配線部材を作製又は準備する工程と、配線部材の金属板と接していた側に半導体素子を搭載する工程と搭載した半導体素子の電極と配線部材の内部端子とを接続する工程と半導体素子を搭載した側を樹脂封止する工程を有している。
このような工程により、金属板の表面に倣って段差のない状態の配線部材の面に半導体素子を搭載することができ、既に外部端子の面が永久レジストの開口部から露出した配線部材であることから、樹脂層の形成及び外部と接続する部分を露出させる従来の加工工程を省略することができる。
図18は本発明の第6実施形態に対応する実施例にかかる半導体装置の製造方法に使用する配線部材の断面図である。図19は図18に示す配線部材の内部端子となるめっき層側に半導体素子を搭載し、半導体素子の電極と配線部材の内部端子部を接続し、半導体素子を搭載した側を樹脂封止した状態を示す説明図である。図20A~図20Fは図18の実施例にかかる半導体装置の製造方法に使用する配線部材の製造方法の工程の一例を示す説明図である。
図18に示すように、本実施例の半導体装置の製造に用いるために準備する配線部材30は、内部端子となる第1の貴金属めっき層11、第1の貴金属めっき層11と同一形状で金属めっき層12、更に金属めっき層12に対して部分的に第2の金属めっき層13が形成され、第2の金属めっき層13と同一形状で外部端子となる第2の貴金属めっき層14が形成されている。
そして、図18の上から順に、例えば第1の貴金属めっき層11は、Auめっき層とPdめっき層で構成され、金属めっき層12はNiめっき層、第2の金属めっき層13もNiめっき層で構成され、第2の貴金属めっき層14は、Pdめっき層とAuめっき層とで構成され、Auめっき層が配線部材の表裏に露出している。図18中、1-1は内部端子部、1-2は配線部、1-3は外部端子部、16は永久レジストである。
次に、半導体素子40を搭載した面側を樹脂41で封止する。これにより、半導体装置が完成する。なお、複数の半導体装置を一括で封止する場合は、切断加工を行って個々の半導体装置が得られることになる。
この時既に半導体装置の裏面側には外部接続端子が永久レジスト16の開口部から露出した状態に形成されていることから、従来の半導体装置の製造方法において必要であった樹脂で覆い、覆われた外部接続部を露出させる加工は不要となる。
まず、金属板1として、リードフレーム材としても使用されている、例えば板厚0.15mmの銅材を用意する。
次に金属板1の両面に、例えば厚さ25μmのドライフィルムレジスト9をラミネートし、次に、表面側に所定の位置にめっきを形成するためのパターンAが形成されたガラスマスクを用いて表面側のドライフィルムレジスト9に露光・現像を行い、めっきを形成する部分が開口されたレジストマスクを形成する。裏面側のドライフィルムレジスト9に対しては、金属板1の裏面全体を覆うレジストマスクを形成する。この露光・現像は従来工法と同様である。
次のめっき工程では、形成したレジストマスクから露出している金属板1に一般的なめっき前処理を行なった後、順に第1の貴金属めっき層としてAuを0.003μm以上、Pdを0.01μm以上、金属めっき層としてNiを6μm以上となるようにめっきを施す(図20A参照)。
次に、両面のレジストマスクを剥離し(図20B参照)、表面側には永久レジスト20、裏面には前述と同じドライフィルムレジスト9をラミネートする。このとき、形成する第2の金属めっき層の厚さに応じて永久レジスト16の厚さを選定する必要があるが、第2の金属めっき層を15~35μmとなるよう形成するため表面側のみ厚さが40μmの永久レジスト16を用い、裏面側は厚さが25μmレジスト9を用いる。
そして、先に形成しためっき層の一部であって、外部端子となる部分に重ねてめっきを形成するためのパターンBが形成されたガラスマスクを用いて露光・現像を行ってレジストマスクを形成する。裏面側は、前回と同様に全体を覆うレジストマスクを形成する。
次に、形成したレジストマスクから露出している金属めっき層であるNiめっき面に順に第2の金属めっき層としてNiを30μm以上、第2の貴金属めっき層としてPdを0.01μm以上、Auを0.003μm以上となるようにめっきを施した(図20C参照)後、裏面のレジストマスクを除去して永久レジスト16を残し(図20D参照)、金属板を除去することで、配線部材30が得られる(図20E参照)。
なお、第2の金属めっきを省略し、金属めっき層であるNiめっき面に、第2の貴金属めっき層としてPdを0.01μm以上、Auを0.003μm以上となるようにめっきを施しても良い。
そして配線部材30は、除去した金属板1側の面に半導体素子を搭載するために配線部材30の下側を上側にひっくり返して使用する(図20F参照)。
次に、比較例2として従来の半導体装置の製造方法について説明する。
従来の半導体装置用基板は、本発明に使用する半導体装置用基板とは逆に金属板上に外部端子となるめっき層が形成され、同一形状でめっき層が重ねられ、上層に内部端子となるめっき層が形成されている。これらめっき層は、搭載する半導体素子の電極数に応じて複数個(本)のめっき層としてほぼ同じ高さに形成されている。
この半導体装置等基板の内部端子の上に半導体素子を搭載し、半導体素子の電極と内部端子との接続を行う。
しかし、めっき加工により厚さとして30μm、40μm等の高さを複数個形成すると、めっき生産時のばらつきとして5~8μm程度の高低差が生じるため、従来の半導体装置用基板は、金属板から内部端子上面までの高さに高低差が生じていることになる。
そのため、半導半導体素子を搭載した際に、半導体素子に傾きが生じたり、半導体素子の電極と内部端子との接続において導通不良が発生する場合があった。
金属板を除去したことで、樹脂の裏面側には金属板と接していた外部端子となるめっき層の面が現れることになる。
そして、現れた外部端子面の一部を外部と接続するための外部端子部として使用するために、樹脂の裏面側全面を樹脂で覆い、次に、外部端子部のみが露出するよう覆った樹脂の一部を開口する加工を行い、外部端子部を露出させて半導体装置が完成する。多数個の半導体装置を一括して封止するタイプでは、切断加工を行って個々の半導体装置が完成する。
例えば、第1実施形態~第3実施形態の半導体装置用基板、第4実施形態の半導体装置用配線部材では、第1の貴金属めっき層にAu、Pd、金属めっき層にNi、第2の金属めっき層にNi、第2の貴金属めっき層にPd、Auを用いたが、本発明の半導体装置用基板における第1の貴金属めっき層、金属めっき層(又は金属めっき層と第2の金属めっき層)、第2の貴金属めっき層の形成に用いるめっきの組み合わせは、これに限定されるものではなく、変形例として、次の表1に示すようなめっきを施した第1の貴金属めっき層、金属めっき層(又は金属めっき層と第2の金属めっき層)、第2の貴金属めっき層を組み合わせて、本発明の半導体装置用基板、半導体装置用配線部材を構成してもよい。なお表1では、めっきが各変形例において欄の上から順に施されるものとして示してある。
1-1 内部端子部
1-2 配線部
1-3 外部端子部
9 レジスト
11 内部端子となるめっき層(第1の貴金属めっき層)
11a Auめっき層(第1の貴金属めっき層)
11b Pdめっき層(第1の貴金属めっき層)
12 Niめっき層(金属めっき層)
13 Niめっき層(第2の金属めっき層)
14 外部端子となるめっき層(第2の貴金属めっき層)
14a Pdめっき層(第2の貴金属めっき層)
14b Auめっき層(第2の貴金属めっき層)
15 樹脂層
15a 一方の面
15b 他方の面
16 永久レジスト
20 樹脂
30 配線部材
40 半導体素子
41 樹脂
Claims (23)
- 所定面上における所定部位に内部端子となるめっき層が形成され、前記内部端子となるめっき層の上に部分的に外部端子となるめっき層が形成され、前記外部端子となるめっき層表面の前記所定面からの高さが、他のめっき層表面の該所定面からの高さに比べて高くなっていることを特徴とする半導体装置用基板。
- 前記内部端子となるめっき層が、金属板上における所定部位に形成された第1の貴金属めっき層からなり、
前記第1の貴金属めっき層の上に該第1の貴金属めっき層と同一形状で金属めっき層が形成され、
前記外部端子となるめっき層が、前記金属めっき層の上に部分的に形成された第2の貴金属めっき層からなり、
前記第2の貴金属めっき層表面の前記金属板面からの高さが、前記金属めっき層表面の前記金属板面からの高さに比べて高くなっていることを特徴とする請求項1に記載の半導体装置用基板。 - 前記内部端子となるめっき層が、金属板上における所定部位に形成された第1の貴金属めっき層からなり、
前記第1の貴金属めっき層の上に該第1の貴金属めっき層と同一形状で金属めっき層が形成され、
前記外部端子となるめっき層が、前記金属めっき層の上に部分的に形成された第2の貴金属めっき層からなり、
更に前記金属板および前記金属めっき層における前記第2の貴金属めっき層が形成されていない部位の上に前記第2の貴金属めっき層の上面を露出させた状態で樹脂層が形成されていることを特徴とする請求項1に記載の半導体装置用基板。 - 前記内部端子となるめっき層が、金属板上における所定部位に形成された第1の貴金属めっき層からなり、
前記第1の貴金属めっき層の上に該第1の貴金属めっき層と同一形状で金属めっき層が形成され、
前記金属板および前記金属めっき層の上に、該金属めっき層における所定部位を開口させた永久レジストが形成され、
前記外部端子となるめっき層が、前記永久レジストの開口部に位置する前記金属めっき層の上に形成された第2の貴金属めっき層からなることを特徴とする請求項1に記載の半導体装置用基板。 - 前記金属めっき層と前記第2の貴金属めっき層との間に、該第2の貴金属めっき層と同一形状で第2の金属めっき層が形成されていることを特徴とする請求項2~4のいずれかに記載の半導体装置用基板。
- 前記金属板側から順に、前記第1の貴金属めっき層としてのAuめっき層、Pdめっき層、前記金属めっき層および前記第2の金属めっき層としてのNiめっき層、前記第2の貴金属めっき層としてのPdめっき層、Auめっき層が形成されていることを特徴とする請求項2~4のいずれかに記載の半導体装置用基板。
- 前記永久レジストは、前記第2の貴金属めっき層の上面を露出させるための開口部を有して形成され、
前記第2の貴金属めっき層の上面は、前記永久レジストの上面よりも下側に位置することを特徴とする請求項4に記載の半導体装置用基板。 - 請求項1に記載に記載の半導体装置用基板を用いて製造された半導体装置用配線部材であって、
前記内部端子となるめっき層が、樹脂層の一方の面における所定部位に下面を該樹脂層の一方の面と面一に露出させた状態で形成された第1の貴金属めっき層からなり、
前記第1の貴金属めっき層の上に該第1の貴金属めっき層と同一形状で金属めっき層が形成され、
前記外部端子となるめっき層が、前記金属めっき層の上に部分的に上面を前記樹脂層の他方の面から露出させた状態で形成された第2の貴金属めっき層からなることを特徴とする半導体装置用配線部材。 - 前記金属めっき層と前記第2の貴金属めっき層との間に、第2の貴金属めっき層と同一形状で第2の金属めっき層が形成されていることを特徴とする請求項8に記載の半導体装置用配線部材。
- 前記樹脂層の一方の面側から順に、前記第1の貴金属めっき層としてのAuめっき層、Pdめっき層、前記金属めっき層および前記第2の金属めっき層としてのNiめっき層、前記第2の貴金属めっき層としてのPdめっき層、Auめっき層が形成されていることを特徴とする請求項8または9に記載の半導体装置用配線部材。
- 金属板上にパターンAの開口部を有するレジストマスクを形成する工程と、
前記パターンAの開口部に第1の貴金属めっき層を形成する工程と、
前記第1の貴金属めっき層の上に該第1の貴金属めっき層と同一形状で金属めっき層を形成する工程と、
前記レジストマスクを剥離する工程と、
前記レジストマスクを剥離した後、前記金属めっき層の一部が露出するパターンBの開口部を有する第2のレジストマスクを形成する工程と、
前記パターンBの開口部に第2の貴金属めっき層或いは第2の金属めっき層と前記第2の貴金属めっき層を形成する工程、
を有することを特徴とする半導体装置用基板の製造方法。 - 前記パターンBの開口部に第2の貴金属めっき層或いは第2の金属めっき層と前記第2の貴金属めっき層を形成した後、前記第2のレジストマスクを剥離する工程、を有することを特徴とする請求項11に記載の半導体装置用基板の製造方法。
- 前記パターンBの開口部に第2の貴金属めっき層或いは第2の金属めっき層と前記第2の貴金属めっき層を形成した後、前記第2のレジストマスクを剥離する工程と、
前記第2のレジストマスクを剥離した後、前記金属板および前記金属めっき層における前記第2の貴金属めっき層が形成されていない部位の上に該第2の貴金属めっき層の上面を露出させるように樹脂層を形成する工程、
を有することを特徴とする請求項11に記載の半導体装置用基板の製造方法。 - 前記第2のレジストマスクが、永久レジストからなることを特徴とする請求項11に記載の半導体装置用基板の製造方法。
- 前記第2の貴金属めっき層の上面は、前記第2のレジストマスクの上面よりも下側に位置することを特徴とする請求項14に記載の半導体装置用基板の製造方法。
- 請求項11に記載の半導体装置用基板の製造方法を用いて製造する半導体装置用配線部材の製造方法であって、
前記パターンBの開口部に第2の貴金属めっき層或いは第2の金属めっき層と前記第2の貴金属めっき層を形成した後、前記第2のレジストマスクを剥離する工程と、
前記第2のレジストマスクを剥離した後、前記金属板および前記金属めっき層における前記第2の貴金属めっき層が形成されていない部位の上に該第2の貴金属めっき層の上面を露出させるように樹脂層を形成する工程と、
前記樹脂層を形成した後、前記金属板を除去する工程、
を有することを特徴とする半導体装置用配線部材の製造方法。 - 請求項1に記載の半導体装置用基板を用いて製造する半導体装置の製造方法であって、
金属板上に前記内部端子となるめっき層が形成され、前記めっき層の上に部分的に前記外部端子となるめっき層が形成され、前記外部端子となるめっき層表面の前記金属板面からの高さが、他のめっき層の前記金属板面からの高さに比べて高くなっている前記半導体装置用基板を用いて、前記外部端子となるめっき層表面が露出する樹脂層を形成する工程と、
前記外部端子となるめっき層表面が露出する樹脂層を形成した後、前記金属板を除去して、形成されためっき層が前記樹脂層により保持された配線部材を作製する工程と、
作製した前記配線部材に半導体素子を搭載する工程、
を含むことを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置用基板を用いて製造する半導体装置の製造方法であって、
金属板上に前記内部端子となるめっき層が形成され、前記めっき層の上に部分的に前記外部端子となるめっき層が形成され、前記外部端子となるめっき層表面の前記金属板面からの高さが、他のめっき層の前記金属板面からの高さに比べて高くなっている前記半導体装置用基板に、前記外部端子となるめっき層表面が露出する樹脂層を形成する工程と、
前記外部端子となるめっき層表面が露出する樹脂層を形成した後、前記金属板を除去して、形成されためっき層が前記樹脂層により保持された配線部材を作製する工程と、
作製した前記配線部材の前記金属板側であった前記内部端子となるめっき層の面側に半導体素子を搭載する工程、
を含むことを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置用基板を用いて製造する半導体装置の製造方法であって、
金属板上に前記内部端子となるめっき層が形成され、前記めっき層の上に部分的に前記外部端子となるめっき層が形成され、前記外部端子となるめっき層表面の前記金属板面からの高さが、他のめっき層の前記金属板面からの高さに比べて高くなっている前記半導体装置用基板に、前記外部端子となるめっき層表面が露出する樹脂層を形成する工程と、
前記外部端子となるめっき層表面が露出する樹脂層を形成した後、前記金属板を除去して、形成されためっき層が前記樹脂層により保持された配線部材を作製する工程と、
作製した前記配線部材の前記金属板側であった前記内部端子となるめっき層の面側に半導体素子を搭載して該半導体素子の電極と前記内部端子との導通を取る工程と、
半導体素子搭載部分を樹脂封止する工程、
を含むことを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置用基板を用いて製造する半導体装置の製造方法であって、
金属板上に所定の厚さで永久レジスト層が形成され、前記永久レジスト層内に、前記金属板に面して前記内部端子となるめっき層が形成され、前記内部端子となるめっき層の上に部分的に前記外部端子となるめっき層が形成され、前記外部端子となるめっき層の上面のみが前記永久レジスト上面の開口部から露出した半導体装置用基板から、前記金属板を除去して前記永久レジストによりめっき層が固定された配線部材を作製する工程と、
作製した前記配線部材の前記金属板を除去した側に半導体素子を搭載する工程、
を含むことを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置用基板を用いて製造する半導体装置の製造方法であって、
金属板上に所定の厚さで永久レジスト層が形成され、前記永久レジスト層内に、所定のパターンで金属板側に前記内部端子となるめっき層が形成され、前記内部端子となるめっき層の上に部分的に前記外部端子となるめっき層が形成され、前記外部端子となるめっき層の上面のみが前記永久レジスト上面の開口部から露出した半導体装置用基板から、前記金属板を除去して前記永久レジストによりめっき層が固定された配線部材を準備する工程と、
準備した前記配線部材の前記金属板を除去した側に半導体素子を搭載し、前記配線部材から露出している前記内部端子となるめっき層の部分に前記半導体素子の電極との接続を行う工程と、
半導体素子搭載側を樹脂封止する工程、
を含むことを特徴とする半導体装置の製造方法。 - 前記半導体装置用基板は、前記金属板上に所定のパターンで前記内部端子となる第1の貴金属めっき層が形成され、その上に前記第1の貴金属めっき層と同一形状で前記金属めっき層が形成され、前記金属めっき層の上に部分的に前記外部端子となる前記第2の貴金属めっき層が、又は前記金属めっき層の上に部分的に前記第2の金属めっき層と前記外部端子となる前記第2の貴金属めっき層が同一形状で、形成され、
これらめっき層より厚く前記金属板上に前記永久レジストが形成されており、前記永久レジストの開口部から前記第2の貴金属めっき層の面が露出していることを特徴とする請求項21に記載の半導体装置の製造方法。 - 前記内部端子となるめっき層と前記外部端子となるめっき層の間に、別の金属によるめっき層が形成されていることを特徴とする請求項17~22のいずれかに記載の半導体装置の製造方法。
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020177017444A KR102403960B1 (ko) | 2014-12-25 | 2015-12-25 | 반도체 장치용 기판, 반도체 장치용 배선부재 및 그 제조 방법 및 반도체 장치용 기판을 이용한 반도체 장치의 제조 방법 |
| US15/539,481 US10276422B2 (en) | 2014-12-25 | 2015-12-25 | Semiconductor device substrate, semiconductor device wiring member and method for manufacturing them, and method for manufacturing semiconductor device using semiconductor device substrate |
| CN201580071178.8A CN107112289B (zh) | 2014-12-25 | 2015-12-25 | 半导体装置用基板、半导体装置用布线构件及它们的制造方法、以及利用半导体装置用基板进行的半导体装置的制造方法 |
Applications Claiming Priority (12)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014263553A JP2016122807A (ja) | 2014-12-25 | 2014-12-25 | 半導体装置用基板及びその製造方法 |
| JP2014-263555 | 2014-12-25 | ||
| JP2014-263553 | 2014-12-25 | ||
| JP2014263555A JP2016122809A (ja) | 2014-12-25 | 2014-12-25 | 半導体装置用配線部材及びその製造方法 |
| JP2014-263554 | 2014-12-25 | ||
| JP2014263554A JP2016122808A (ja) | 2014-12-25 | 2014-12-25 | 半導体装置用基板及びその製造方法 |
| JP2014-263556 | 2014-12-25 | ||
| JP2014263556A JP6562493B2 (ja) | 2014-12-25 | 2014-12-25 | 半導体装置用基板及びその製造方法 |
| JP2014-265373 | 2014-12-26 | ||
| JP2014-265374 | 2014-12-26 | ||
| JP2014265373A JP6562494B2 (ja) | 2014-12-26 | 2014-12-26 | 半導体装置の製造方法 |
| JP2014265374A JP6562495B2 (ja) | 2014-12-26 | 2014-12-26 | 半導体装置の製造方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2016104713A1 true WO2016104713A1 (ja) | 2016-06-30 |
Family
ID=56150725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2015/086254 Ceased WO2016104713A1 (ja) | 2014-12-25 | 2015-12-25 | 半導体装置用基板、半導体装置用配線部材及びそれらの製造方法、並びに、半導体装置用基板を用いた半導体装置の製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US10276422B2 (ja) |
| KR (1) | KR102403960B1 (ja) |
| CN (1) | CN107112289B (ja) |
| TW (1) | TWI677944B (ja) |
| WO (1) | WO2016104713A1 (ja) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001168130A (ja) * | 1999-12-14 | 2001-06-22 | Dainippon Printing Co Ltd | 転写用配線部材とその製造方法、および配線基板 |
| JP2002261190A (ja) * | 2001-02-28 | 2002-09-13 | Sony Corp | 半導体装置、その製造方法及び電子機器 |
| JP2005026452A (ja) * | 2003-07-02 | 2005-01-27 | North:Kk | 電子装置とその製造方法 |
| JP2008091719A (ja) * | 2006-10-03 | 2008-04-17 | Shinko Electric Ind Co Ltd | 半導体装置 |
| JP2009164594A (ja) * | 2007-12-11 | 2009-07-23 | Dainippon Printing Co Ltd | 半導体装置用基板、樹脂封止型半導体装置、半導体装置用基板の製造方法および樹脂封止型半導体装置の製造方法 |
| JP2011238964A (ja) * | 2006-12-14 | 2011-11-24 | Advanpack Solutions Pte Ltd | 半導体パッケージおよびこの製造方法 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200507131A (en) | 2003-07-02 | 2005-02-16 | North Corp | Multi-layer circuit board for electronic device |
| JP2005244033A (ja) | 2004-02-27 | 2005-09-08 | Torex Semiconductor Ltd | 電極パッケージ及び半導体装置 |
| JP4431123B2 (ja) * | 2006-05-22 | 2010-03-10 | 日立電線株式会社 | 電子装置用基板およびその製造方法、並びに電子装置およびその製造方法 |
| CN107369668B (zh) * | 2011-07-22 | 2020-08-25 | 先进封装技术私人有限公司 | 用于制造半导体封装元件的半导体结构 |
| CN103165566B (zh) * | 2011-12-19 | 2016-02-24 | 先进封装技术私人有限公司 | 基板结构、半导体封装件及半导体封装件的制造方法 |
-
2015
- 2015-12-25 WO PCT/JP2015/086254 patent/WO2016104713A1/ja not_active Ceased
- 2015-12-25 KR KR1020177017444A patent/KR102403960B1/ko active Active
- 2015-12-25 TW TW104143751A patent/TWI677944B/zh not_active IP Right Cessation
- 2015-12-25 US US15/539,481 patent/US10276422B2/en active Active
- 2015-12-25 CN CN201580071178.8A patent/CN107112289B/zh active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001168130A (ja) * | 1999-12-14 | 2001-06-22 | Dainippon Printing Co Ltd | 転写用配線部材とその製造方法、および配線基板 |
| JP2002261190A (ja) * | 2001-02-28 | 2002-09-13 | Sony Corp | 半導体装置、その製造方法及び電子機器 |
| JP2005026452A (ja) * | 2003-07-02 | 2005-01-27 | North:Kk | 電子装置とその製造方法 |
| JP2008091719A (ja) * | 2006-10-03 | 2008-04-17 | Shinko Electric Ind Co Ltd | 半導体装置 |
| JP2011238964A (ja) * | 2006-12-14 | 2011-11-24 | Advanpack Solutions Pte Ltd | 半導体パッケージおよびこの製造方法 |
| JP2009164594A (ja) * | 2007-12-11 | 2009-07-23 | Dainippon Printing Co Ltd | 半導体装置用基板、樹脂封止型半導体装置、半導体装置用基板の製造方法および樹脂封止型半導体装置の製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20170095897A (ko) | 2017-08-23 |
| CN107112289A (zh) | 2017-08-29 |
| KR102403960B1 (ko) | 2022-05-30 |
| US10276422B2 (en) | 2019-04-30 |
| CN107112289B (zh) | 2020-01-07 |
| US20170358477A1 (en) | 2017-12-14 |
| TWI677944B (zh) | 2019-11-21 |
| TW201635448A (zh) | 2016-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6863846B2 (ja) | 半導体素子搭載用基板及びその製造方法 | |
| JP6927634B2 (ja) | 半導体素子搭載用基板及びその製造方法 | |
| JP6524526B2 (ja) | 半導体素子実装用基板及び半導体装置、並びにそれらの製造方法 | |
| JP2017163106A (ja) | リードフレーム集合基板及び半導体装置集合体 | |
| KR102570206B1 (ko) | 다열형 반도체 장치용 배선 부재 및 그 제조 방법 | |
| JP6676854B2 (ja) | リードフレーム、並びにリードフレーム及び半導体装置の製造方法 | |
| WO2016104713A1 (ja) | 半導体装置用基板、半導体装置用配線部材及びそれらの製造方法、並びに、半導体装置用基板を用いた半導体装置の製造方法 | |
| CN108155170A (zh) | 引线框 | |
| JP6485777B2 (ja) | 多列型半導体装置用配線部材及びその製造方法 | |
| JP2016122808A (ja) | 半導体装置用基板及びその製造方法 | |
| KR102570204B1 (ko) | 다열형 반도체 장치용 배선 부재 및 그 제조 방법 | |
| JP6562493B2 (ja) | 半導体装置用基板及びその製造方法 | |
| TWI631671B (zh) | 半導體元件安裝用基板、半導體裝置及其製造方法 | |
| JP6476494B2 (ja) | リードフレーム及び半導体装置、並びにそれらの製造方法 | |
| JP2016122809A (ja) | 半導体装置用配線部材及びその製造方法 | |
| JP2016122807A (ja) | 半導体装置用基板及びその製造方法 | |
| JP2016127075A (ja) | 半導体装置の製造方法 | |
| JP6460407B2 (ja) | 半導体素子搭載用基板、半導体装置及びそれらの製造方法 | |
| JP2018088512A (ja) | 半導体装置用配線部材 | |
| KR102570205B1 (ko) | 다열형 반도체 장치용 배선 부재 및 그 제조 방법 | |
| JP2017034094A (ja) | 半導体素子搭載用基板、半導体装置及びそれらの製造方法 | |
| JP2017216366A (ja) | 多列型半導体装置用配線部材及びその製造方法 | |
| JP2016127076A (ja) | 半導体装置の製造方法 | |
| JP2018093157A (ja) | 半導体装置用配線部材 | |
| JP2017216364A (ja) | 多列型半導体装置用配線部材及びその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 15873281 Country of ref document: EP Kind code of ref document: A1 |
|
| ENP | Entry into the national phase |
Ref document number: 20177017444 Country of ref document: KR Kind code of ref document: A |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 15539481 Country of ref document: US |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 15873281 Country of ref document: EP Kind code of ref document: A1 |