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WO2016101299A1 - Circuit de pilote source d'un panneau d'affichage à cristaux liquides et dispositif d'affichage à cristaux liquides - Google Patents

Circuit de pilote source d'un panneau d'affichage à cristaux liquides et dispositif d'affichage à cristaux liquides Download PDF

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Publication number
WO2016101299A1
WO2016101299A1 PCT/CN2014/095476 CN2014095476W WO2016101299A1 WO 2016101299 A1 WO2016101299 A1 WO 2016101299A1 CN 2014095476 W CN2014095476 W CN 2014095476W WO 2016101299 A1 WO2016101299 A1 WO 2016101299A1
Authority
WO
WIPO (PCT)
Prior art keywords
data line
switching element
buffer amplifier
analog buffer
liquid crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2014/095476
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English (en)
Chinese (zh)
Inventor
秦杰辉
国春朋
卢宇程
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Publication of WO2016101299A1 publication Critical patent/WO2016101299A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of displays, and in particular to a source driving circuit and a liquid crystal display of a liquid crystal display panel.
  • the liquid crystal display panel includes an array substrate, as described in FIG. 1, wherein the array substrate includes a data line 12, a scan line 11, and a plurality of pixel units 13 defined by the data line 12 and the scan line 11;
  • the source driving circuit in the display panel comprises a plurality of analog-to-digital converters 14, a plurality of analog buffer amplifiers 15, each of which is provided with an analog-to-digital converter 14 and an analog buffer amplifier 15, and the analog-to-digital converter 14 signals
  • the analog input signal of the source input is converted into a digital signal; after the digital signal is amplified by the analog buffer amplifier 15, the digital signal after the amplification operation is transmitted to the corresponding data line to drive the pixel array of the liquid crystal display panel.
  • the pixel array requires a large range of charging voltage (i.e., pixel voltage), and black indicates that the pixel unit voltage is positive, gray. It means that the voltage of the pixel unit is negative, which causes the power consumption of the source driving circuit to be large, which causes the heat of the analog buffer amplifier to be severe and the loss to increase.
  • Embodiments of the present invention provide a source driving circuit of a liquid crystal display panel, wherein the liquid crystal display panel includes an array substrate, the array substrate includes a data line, a scan line, and a defined by the data line and the scan line Multiple pixel units;
  • the source driving circuit includes a plurality of source driving units, and each of the data lines is correspondingly provided with the source driving unit;
  • the source driving unit includes:
  • An analog to digital converter for converting an analog signal input from a signal source into a digital signal
  • An analog buffer amplifier group including a first analog buffer amplifier and a second analog buffer amplifier; the analog buffer amplifier group for amplifying a digital signal of the analog to digital converter and amplifying the data after the operation Signal transmission to the corresponding data line;
  • the selection signal Controlling, by the selection signal, the first analog buffer amplifier and the second analog buffer amplifier to alternately drive a plurality of rows of pixel units on the data line in units of rows; the selection signal is generated according to a clock signal;
  • the source driving unit further includes: a first switching element and a second switching element;
  • the first analog buffer amplifier is connected to the data line through the first switching element, and the second analog buffer amplifier is connected to the data line through a second switching element;
  • the selection signal controls whether the first analog buffer element and the second switching element are connected to the data line to control the first analog buffer amplifier and the second analog buffer amplifier to alternately drive in units of rows A plurality of rows of pixel units on the data line.
  • the first switching element when the selection signal is at a high level, the first switching element is connected to the data line, and the second switching element is disconnected from the data line .
  • the first switching element when the selection signal is at a low level, the first switching element is disconnected from the data line, and the second switching element is connected to the data line .
  • the first switching element is an N-type metal oxide semiconductor field effect transistor
  • the second switching element is a P-type metal oxide semiconductor field effect transistor
  • the first switching element includes a first gate, a first source, and a first drain;
  • the second switching element includes a second gate, a second source, and a second drain;
  • the first gate and the second gate are connected to the selection signal, the first source is connected to the data line, and the first drain is connected to an output end of the first analog buffer amplifier;
  • the second source is coupled to the data line, and the second drain is coupled to an output of the second analog buffer amplifier.
  • Embodiments of the present invention provide a source driving circuit of a liquid crystal display panel, wherein the liquid crystal display panel includes an array substrate, the array substrate includes a data line, a scan line, and a defined by the data line and the scan line Multiple pixel units;
  • the source driving circuit includes a plurality of source driving units, and each of the data lines is correspondingly provided with the source driving unit;
  • the source driving unit includes:
  • An analog to digital converter for converting an analog signal input by a signal source into a digital signal
  • An analog buffer amplifier group including a first analog buffer amplifier and a second analog buffer amplifier; the analog buffer amplifier group for amplifying a digital signal of the analog to digital converter and amplifying the data after the operation Signal transmission to the corresponding data line;
  • the first analog buffer amplifier and the second analog buffer amplifier are controlled to alternately drive a plurality of rows of pixel units on the data line in units of rows according to a selection signal.
  • the source driving unit further includes: a first switching element and a second switching element;
  • the first analog buffer amplifier is connected to the data line through the first switching element, and the second analog buffer amplifier is connected to the data line through a second switching element;
  • the selection signal controls whether the first analog buffer element and the second switching element are connected to the data line to control the first analog buffer amplifier and the second analog buffer amplifier to alternately drive in units of rows A plurality of rows of pixel units on the data line.
  • the first switching element when the selection signal is at a high level, the first switching element is connected to the data line, and the second switching element is disconnected from the data line .
  • the first switching element when the selection signal is at a low level, the first switching element is disconnected from the data line, and the second switching element is connected to the data line .
  • the first switching element is an N-type metal oxide semiconductor field effect transistor
  • the second switching element is a P-type metal oxide semiconductor field effect transistor
  • the first switching element includes a first gate, a first source, and a first drain;
  • the second switching element includes a second gate, a second source, and a second drain;
  • the first gate and the second gate are connected to the selection signal, the first source is connected to the data line, and the first drain is connected to an output end of the first analog buffer amplifier;
  • the second source is coupled to the data line, and the second drain is coupled to an output of the second analog buffer amplifier.
  • the selection signal is generated based on a clock signal.
  • An embodiment of the present invention further provides a liquid crystal display, including: a liquid crystal display panel, the liquid crystal display panel includes an array substrate, the array substrate includes a data line, a scan line, and is defined by the data line and the scan line Multiple pixel units;
  • the source driving circuit includes a plurality of source driving units, and each of the data lines is correspondingly provided with the source driving unit;
  • the source driving unit includes:
  • An analog to digital converter for converting an analog signal input by a signal source into a digital signal
  • An analog buffer amplifier group including a first analog buffer amplifier and a second analog buffer amplifier, the analog buffer amplifier group for amplifying a digital signal of the analog to digital converter, and amplifying the data after the operation Signal transmission to the corresponding data line;
  • the first analog buffer amplifier and the second analog buffer amplifier are controlled to alternately drive a plurality of rows of pixel units on the data line in units of rows according to a selection signal.
  • the source driving unit further includes: a first switching element and a second switching element;
  • the first analog buffer amplifier is connected to the data line through the first switching element, and the second analog buffer amplifier is connected to the data line through a second switching element;
  • the selection signal controls whether the first analog buffer element and the second switching element are connected to the data line to control the first analog buffer amplifier and the second analog buffer amplifier to alternately drive in units of rows A plurality of rows of pixel units on the data line.
  • the first switching element when the selection signal is at a high level, the first switching element is connected to the data line, and the second switching element is disconnected from the data line;
  • the first switching element When the selection signal is low, the first switching element is disconnected from the data line, and the second switching element is connected to the data line.
  • the first switching element is an N-type metal oxide semiconductor field effect transistor
  • the second switching element is a P-type metal oxide semiconductor field effect transistor
  • the first switching element includes a first gate, a first source, and a first drain;
  • the second switching element includes a second gate, a second source, and a second drain;
  • the first gate and the second gate are connected to the selection signal, the first source is connected to the data line, and the first drain is connected to an output end of the first analog buffer amplifier;
  • the second source is coupled to the data line, and the second drain is coupled to an output of the second analog buffer amplifier.
  • the selection signal is generated based on a clock signal.
  • the source driving circuit and the liquid crystal display of the liquid crystal display panel of the present invention reduce the power consumption of a single analog buffer amplifier by adding an analog buffer amplifier to each data line, thereby reducing power consumption.
  • FIG. 1 is a schematic structural view of a first array substrate of the prior art
  • FIG. 2 is a schematic structural view of a second array substrate of the prior art
  • FIG. 3 is a schematic structural view of a first array substrate of the present invention.
  • FIG. 4 is a schematic enlarged view of the source driving unit of FIG. 3;
  • FIG. 5 is a schematic structural view of a second array substrate of the present invention.
  • Figure 6 is a timing diagram of the selection signal of the present invention.
  • FIG. 3 is a schematic structural diagram of a first array substrate of the present invention.
  • the liquid crystal display panel of the present invention comprises: a color film substrate, an array substrate, and a liquid crystal layer between the color film substrate and the array substrate, wherein the array substrate comprises a data line 22, as described in FIG. a scan line 21, and a plurality of pixel units 23 defined by the data line 22 and the scan line 21; the array substrate further includes a source drive circuit 24;
  • the source driving circuit 24 includes a plurality of source driving units 25, each of the data lines corresponding to the source driving unit 25;
  • the source driving unit 25 includes: an analog-to-digital converter 26 and an analog buffer amplifier group 27.
  • the signal source inputs a video signal to the liquid crystal display panel, the video signal is an analog signal, and the analog-to-digital converter Converting a video signal input by the signal source into a digital signal; then the analog buffer amplifier group 27 amplifies the digital signal obtained by the analog-to-digital converter (such as a load driving capability of amplifying the digital signal, Driving the pixel array load on the data line, and transmitting the data signal after the amplification operation to the corresponding data line;
  • the analog buffer amplifier group 27 amplifies the digital signal obtained by the analog-to-digital converter (such as a load driving capability of amplifying the digital signal, Driving the pixel array load on the data line, and transmitting the data signal after the amplification operation to the corresponding data line;
  • the analog buffer amplifier group 27 includes a first analog buffer amplifier 28 and a second analog buffer amplifier 29;
  • the array substrate is further provided with a selection signal input line 30 for providing a selection signal, and the source driving circuit of the present invention can control the first analog buffer amplifier 28 according to the selection signal input by the selection signal input line 30.
  • the second analog buffer amplifier 29 alternately drives a plurality of rows of pixel units on the data line in units of rows.
  • the first analog buffer amplifier is separately operated, that is, the digital signal corresponding to the first row of pixel units on the first data line is processed to The first row of pixel units on the data line is driven to display the pixel unit, and then the second analog buffer amplifier is separately operated, that is, the digital signal corresponding to the second row of pixel units on the first data line.
  • the source driving unit 25 further includes: a first switching element 31 and a second switching element 32; the first analog buffer amplifier 28 can be connected to the data line through the first switching element 31, The second analog buffer amplifier 29 can be connected to the data line through the second switching element 32;
  • the selection signal controls whether the first analog buffer element and the second switching element are connected to the data line to control the first analog buffer amplifier and the second analog buffer amplifier to alternately drive in units of rows A plurality of rows of pixel units on the data line. Specifically, when the selection signal is at a high level, the first switching element 31 is connected to the data line, the second switching element 32 is disconnected from the data line; when the selection signal is low level The first switching element 31 is disconnected from the data line, and the second switching element 32 is connected to the data line.
  • the first switching element 31 may be an N-type MOS transistor (metal oxide semiconductor field effect transistor), the second switching element 32 may be a P-type MOS transistor, and the first switching element 31 includes a first gate, a first source, a first drain; the second switching element 32 includes a second gate, a second source, and a second drain;
  • N-type MOS transistor metal oxide semiconductor field effect transistor
  • P-type MOS transistor metal oxide semiconductor field effect transistor
  • the first gate and the second gate are connected to the selection signal, the first source is connected to the data line, and the first drain is connected to an output end of the first analog buffer amplifier 28;
  • the second source is connected to the data line, and the second drain is connected to an output of the second analog buffer amplifier 29.
  • the selection signal is generated based on a clock signal.
  • the selection signal can be provided by a timing controller on the liquid crystal display panel, and the waveform thereof is as shown in FIG. 6.
  • the timing controller provides a clock signal, and the timing chart of the clock signal Clock is shown in FIG. 6, and the scan signal input on the scan line is also based on A clock signal is generated, the selection signal Select being generated with reference to the clock signal, preferably generated from the scan signal.
  • the selection signal is high, such that the first switch is closed, the second switch is off, the first analog buffer amplifier is operating, and the second analog buffer is The amplifier does not operate, the first analog buffer amplifier transmits the data signal after the amplification operation to the first row of pixel units on the data line corresponding thereto; between time t2-t3, the selection signal is low Leveling, causing the second switch to be closed, the first switch to be turned off, the second analog buffer amplifier to operate, the first analog buffer amplifier not operating, ie, the second analog buffer amplifier to be amplified
  • the subsequent data signal is transmitted to the second row of pixel units on the data line corresponding thereto, and between time t3-t4, the selection signal is at a high level, so that the first switch is closed, the second The switch is turned off, the first analog buffer amplifier operates, the second analog buffer amplifier does not operate, and the first analog buffer amplifier transmits the data signal after the amplification operation to the corresponding a third row of pixel units on the data line; between times t1-t2, the
  • the input signal on the data line of the present invention is alternately output by two buffer amplifiers, that is, alternately outputted alternately, which lowers the temperature of each amplifier and reduces power consumption in the case of line inversion and dot inversion. .
  • FIG. 3 shows a schematic diagram of row inversion of the pixel array
  • FIG. 5 shows a schematic diagram of dot inversion of the pixel array.
  • the present invention ensures the normal operation of the liquid crystal display panel, and In the prior art, only one analog buffer amplifier comparison is set, and the operating time of the analog buffer amplifier is reduced by half, so that the temperature of each analog buffer amplifier is greatly reduced, and the power consumption is reduced.
  • the source driving circuit of the liquid crystal display panel of the present invention reduces the power consumption of a single analog buffer amplifier by adding an analog buffer amplifier to each data line, thereby reducing power consumption.
  • the present invention also provides a liquid crystal display comprising a liquid crystal display panel and a backlight module, the liquid crystal display panel comprising an array substrate, the array substrate comprising a data line, a scan line, and a defined by the data line and the scan line Multiple pixel units;
  • the source driving circuit includes a plurality of source driving units, and each of the data lines is correspondingly provided with the source driving unit;
  • the source driving unit includes:
  • An analog to digital converter for converting an analog signal input by a signal source into a digital signal
  • An analog buffer amplifier group including a first analog buffer amplifier and a second analog buffer amplifier, the analog buffer amplifier group for amplifying a digital signal of the analog to digital converter, and amplifying the data after the operation Signal transmission to the corresponding data line;
  • the first analog buffer amplifier and the second analog buffer amplifier are controlled to alternately drive a plurality of rows of pixel units on the data line in units of rows according to a selection signal.
  • the source driving unit further includes: a first switching element and a second switching element;
  • the first analog buffer amplifier is connected to the data line through the first switching element, and the second analog buffer amplifier is connected to the data line through a second switching element;
  • the selection signal controls whether the first analog buffer element and the second switching element are connected to the data line to control the first analog buffer amplifier and the second analog buffer amplifier to alternately drive in units of rows A plurality of rows of pixel units on the data line.
  • the first switching element When the selection signal is high level, the first switching element is connected to the data line, and the second switching element is disconnected from the data line;
  • the first switching element When the selection signal is low, the first switching element is disconnected from the data line, and the second switching element is connected to the data line.
  • the first switching element is an N-type MOS transistor, and the second switching element is a P-type MOS transistor;
  • the first switching element includes a first gate, a first source, and a first drain;
  • the second switching element includes a second gate, a second source, and a second drain;
  • the first gate and the second gate are connected to the selection signal, the first source is connected to the data line, and the first drain is connected to an output end of the first analog buffer amplifier;
  • the second source is coupled to the data line, and the second drain is coupled to an output of the second analog buffer amplifier.
  • the selection signal is generated based on a clock signal.
  • the liquid crystal display of the present invention can employ any of the above-described source driving circuits, and since the source driving circuit has been described above, it will not be described in detail herein.
  • the liquid crystal display of the present invention reduces the power consumption of a single analog buffer amplifier by adding an analog buffer amplifier to each data line, thereby reducing power consumption.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

L'invention concerne un circuit de pilote source (24) d'un panneau d'affichage à cristaux liquides et un dispositif d'affichage à cristaux liquides, le circuit de pilote source (24) comprenant une pluralité d'unités de pilote source (25) correspondant à une ligne de données (22) ; l'unité de pilote source (25) comprend : un convertisseur analogique-numérique (26) ; une unité d'amplificateur de tampon analogique (27) comprenant un premier amplificateur de tampon analogique (28) et un second amplificateur de tampon analogique (29) ; amener un premier amplificateur de tampon analogique (28) et un second amplificateur de tampon analogique (29) à piloter de manière alternée de multiples rangées d'unités de pixel (23) sur la ligne de données (22) dans une unité de comportement selon un signal sélectionné.
PCT/CN2014/095476 2014-12-25 2014-12-30 Circuit de pilote source d'un panneau d'affichage à cristaux liquides et dispositif d'affichage à cristaux liquides Ceased WO2016101299A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410820007.8 2014-12-25
CN201410820007.8A CN104575421A (zh) 2014-12-25 2014-12-25 一种液晶显示面板的源极驱动电路及液晶显示器

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Publication Number Publication Date
WO2016101299A1 true WO2016101299A1 (fr) 2016-06-30

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PCT/CN2014/095476 Ceased WO2016101299A1 (fr) 2014-12-25 2014-12-30 Circuit de pilote source d'un panneau d'affichage à cristaux liquides et dispositif d'affichage à cristaux liquides

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CN (1) CN104575421A (fr)
WO (1) WO2016101299A1 (fr)

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CN110335562A (zh) * 2019-05-09 2019-10-15 京东方科技集团股份有限公司 源驱动装置及驱动方法、显示装置

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TWI567721B (zh) * 2015-08-18 2017-01-21 矽創電子股份有限公司 源極驅動器及液晶顯示裝置
CN107274847B (zh) * 2017-06-26 2023-10-24 北京集创北方科技股份有限公司 显示装置、源极驱动电路及其控制方法
CN107578740B (zh) * 2017-09-26 2019-11-08 北京集创北方科技股份有限公司 显示装置、源极驱动电路和显示系统
KR102450738B1 (ko) * 2017-11-20 2022-10-05 삼성전자주식회사 소스 구동 회로 및 이를 포함하는 디스플레이 장치
CN110910843B (zh) * 2019-12-20 2021-08-13 京东方科技集团股份有限公司 背光驱动电路及驱动方法、显示面板
US11521559B2 (en) * 2020-03-27 2022-12-06 Beijing Boe Technology Development Co., Ltd. Display panel having a switch unit between a digital-to-analog converter and an amplifier for improving driving and driving method thereof
CN111432520B (zh) * 2020-04-02 2022-04-19 晟合微电子(肇庆)有限公司 一种低功耗驱动oled面板的均衡方法

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CN110335562B (zh) * 2019-05-09 2023-03-10 京东方科技集团股份有限公司 源驱动装置及驱动方法、显示装置

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