WO2016194083A1 - Ultrasonice probe and ultrasonic diagnostic apparatus using same - Google Patents

Abstract

An ultrasonic probe which includes multiple transducers arranged in an array and multiple element circuits that correspond to each of the multiple transducers and drive the multiple transducers, the ultrasonic probe having a first set of control lines connected to the multiple element circuits, a second control line commonly connected to the multiple element circuits, and a control circuit to which the first set of control lines and the second control line are connected. Each of the element circuits is configured from: a transmission reception circuit connected to the first set of control lines; an individual control circuit that controls the transmission reception circuit; and a branch line that branches off of a corresponding control line of the first set of control lines and is connected to the individual control circuit. The individual control circuit is connected to the branch line and the second control line. The individual control circuit switches the transmission reception circuit on and off individually on the basis of a signal from the branch line and a signal from the second control line.

Description

Ultrasonic probe and ultrasonic diagnostic apparatus using the same

The present invention relates to an ultrasonic probe and an ultrasonic diagnostic apparatus using the same.

Japanese Patent Laid-Open No. 2004-260688 discloses that the transducers arranged in an array and the control circuit of the transducers are connected one-on-one so that switching of the transducers arranged in an array can be controlled for each transducer. A configured 2D array probe for an ultrasonic diagnostic apparatus is disclosed.

In Patent Document 2, for a transmission / reception circuit that is connected to a transducer on a one-to-one basis and transmits / receives an ultrasonic wave, a transmission / reception group arranged on vertical or horizontal lines is commonly controlled by one control line per line. A method is disclosed.

Japanese Patent Laid-Open No. 5-146444 JP 2005-304692 A

During semiconductor manufacturing or when mounting a vibrator on a 2D array IC, adjacent vibrators are electrically short-circuited due to problems such as contamination of foreign matter, or the output of a transmission circuit that drives the vibrator is connected to a power source or the like. A short circuit or the like may occur. When the vibrator is driven in this state, an excessive current flows from the output of the transmission circuit, thereby increasing power consumption. As a result, heat generation of the ultrasonic probe increases. Generally, a medical ultrasonic probe is controlled from an ultrasonic diagnostic apparatus so as to stop at a preset temperature so as not to burn the patient. Accordingly, heat generation increases due to the increase in power consumption, and problems such as immediate stoppage occur, which necessitates selection of the ultrasonic probe as a defective product. On the other hand, by stopping the transmission circuit that has been affected by foreign matter or the like, it is possible to prevent an excessive current from flowing from the output of the transmission circuit due to a short circuit between the vibrators. In addition, since the receiving circuit cannot correctly receive ultrasonic waves, it is possible to reduce wasteful power consumption by turning off the receiving circuit.

As a result of examination by the present inventors, in order to individually power on / off each transmission circuit arranged in the 2D array IC, Patent Document 1 requires switches corresponding to the number of vibrators. Accordingly, a control line for controlling the switch from the switching controller is also required. Therefore, as the number of vibrators and transmission / reception circuits increases, the number of switches and control lines for controlling the switches also increases. Therefore, when the vibrator is configured with N × M (N rows × M columns), the switches and switches are controlled. The number of control lines to be performed is N × M, and a large-scale 2D array IC has a problem that the wiring area increases.

In Patent Document 2, when the vibrator is configured by N × M (N rows × M columns), N + M (N rows + M columns), so even if the number of vibrators increases, the number of control lines is almost the same. Will not Increase. However, when stopping a defective transmission circuit, the transmission circuits on the same line are commonly controlled, so if a defect such as a short circuit occurs between the transmission circuit or the output of the transmission circuit and the vibrator, there is a defect. Since the non-defective transmission circuit existing on the line is also stopped at the same time, there is a possibility that ultrasonic waves are not output from many vibrators and the desired ultrasonic image quality cannot be obtained.

The present invention provides an ultrasonic probe that solves these problems, can individually control a transmission circuit with a small area, and can improve the yield of 2D array ICs by turning off a defective transmission circuit. The purpose is to do.

The present invention includes a plurality of means for solving the above problems. To give one example, the plurality of vibrators arranged in an array and the plurality of vibrators correspond to each of the plurality of vibrators. An ultrasonic probe including a plurality of element circuits that drive the plurality of element circuits, a first control line group connected to the plurality of element circuits, and a second commonly connected to the plurality of element circuits. And a control circuit to which the first control line group and the second control line are connected, and each of the element circuits is a transmission / reception circuit connected to the first control line group. And an individual control circuit that controls the transmission / reception circuit, and a branch line that branches from a corresponding control line of the first control line group and is connected to the individual control circuit. Connected to the branch line and the second control line, Individual control circuit comprises a signal from the branch line, based on a signal from the second control line, and switches the individual on-off of the transmission and reception circuit.

As another example, an ultra-compact including a plurality of transducers arranged in an array and a plurality of element circuits corresponding to each of the plurality of transducers and driving the plurality of transducers. A sound wave probe, wherein a vertical control line group connected to the plurality of element circuits, a horizontal control line group connected to the plurality of element circuits, and a second commonly connected to the plurality of element circuits A control line, and a control circuit to which the vertical control line group and the horizontal control line group are connected to the second control line, and each of the element circuits includes the vertical control line group and the horizontal control line group. A transmission / reception circuit connected to the control circuit, an individual control circuit for controlling the transmission / reception circuit, a first branch line branched from the corresponding control line of the vertical control line group and connected to the individual control circuit, and the horizontal Branch from the corresponding control line of the control line group, and the individual control circuit And the individual control circuit is connected to the first branch line, the second branch line, and the second control line, and the individual control circuit includes: The transmission / reception circuit is individually switched on / off based on a signal from the first branch line and the second branch line and a signal from the second control line.

According to the present invention, the transmission circuit can be individually controlled with a small area. Further, the yield of the 2D array IC can be improved by turning off the defective transmission circuit.

Problems, configurations, and effects other than those described above will be clarified by the following description of the embodiments.

It is the figure which showed the ultrasonic diagnosing device which concerns on Example 1 of this invention. It is a figure explaining 2D array IC of FIG. It is a figure explaining the structure of the element circuit of Example 1 of this invention, and the connection of a control line. FIG. 4 is a diagram illustrating a circuit example of an individual control circuit in FIG. 3. 5 is a truth table of the individual control circuit shown in FIG. It is a circuit diagram explaining Example 1 of the present invention. 7 is a timing chart for explaining the circuit operation of FIG. 6. It is a figure explaining the structure of the element circuit of Example 2 of this invention, and the connection of a control line. It is a figure which shows the circuit example of the separate control circuit of FIG. It is a figure which shows the circuit example of Example 2 of this invention. It is a truth table of the individual control circuit shown in FIG. It is a timing chart for demonstrating the circuit operation | movement of FIG. It is a figure which shows the circuit example of Example 3 of this invention. 14 is a timing chart for explaining the circuit operation of FIG. 13.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that components having the same function are denoted by the same names and reference numerals in the drawings for describing the embodiments, and repetitive description thereof is omitted.

FIG. 1 is a diagram showing an ultrasonic diagnostic apparatus according to Embodiment 1 of the present invention. As shown in FIG. 1, the ultrasonic diagnostic apparatus includes an apparatus main body 11 and an ultrasonic probe 12.

The apparatus main body 11 includes, for example, a CPU (Central Processor Unit) that performs overall control of the ultrasonic diagnostic apparatus, an HDD (Hard Disk Drive) that stores a program executed by the CPU, and data to be processed. A storage device such as a RAM for temporarily storing data, and a communication IF (IF) device for communicating with an external device. In addition, the apparatus main body 11 includes, for example, various power supply circuits and an image processing circuit that performs image processing on signals from the ultrasonic probe. Moreover, the apparatus main body 11 has input devices, such as a keyboard and a mouse | mouth, and output devices, such as a liquid crystal display device, for example. The input device may be, for example, a touch panel provided in a liquid crystal display device. The apparatus main body 11 has a structure that can be freely moved on the floor surface by a caster or the like attached to the bottom surface.

The ultrasonic probe 12 has a 2D (Dimension) array transducer 12a and a 2D array IC (Integrated Circuit) 12b. The 2D array transducer 12a has a plurality of transducers that emit ultrasonic waves on the surface of the ultrasonic probe 12 that comes into contact with the human body. The plurality of transducers of the 2D array transducer 12a are arranged two-dimensionally (planar). The 2D array IC 12b includes a plurality of circuits that drive the transducers of the 2D array transducer 12a so as to face the 2D array transducer 12a. The plurality of circuits of the 2D array IC 12b are two-dimensionally arranged. The plurality of circuits of the 2D array IC 12b are provided corresponding to the plurality of vibrators of the 2D array vibrator 12a. For example, one circuit of the 2D array IC 12b is electrically connected to one vibrator of the 2D array vibrator 12a.

FIG. 2 is a diagram illustrating the configuration of the 2D array IC 12b. The 2D array IC 12 b includes a plurality of element circuits 31 and a control circuit 23. The element circuit 31 and the control circuit 23 are formed on, for example, one IC substrate. In FIG. 2, four (element circuits 31a, 31b, 31c, 31d) element circuits 31 are formed on the IC substrate. In FIG. 2, one control circuit 23 is formed on the IC substrate.

The control circuit 23 has an IF circuit for communicating with the apparatus main body 11. The control circuit 23 includes a control circuit that controls the plurality of element circuits 31 based on instructions from the apparatus main body 11. The control circuit 23 includes a vertical delay control line 25 that controls the plurality of element circuits 31 and a switching control line 26.

Each element circuit 31 is connected to the vertical delay control line 25 and the switching control line 26. The plurality of transducers of the 2D array transducer 12a are downsized in response to a demand for high image quality, and the number thereof is increasing. Accordingly, the number of element circuits 31 reaches, for example, about 10,000. Therefore, it is important to reduce the size of the element circuit 31 and the power consumption. In FIG. 2, the illustration is simplified and an example of 2 × 2 element circuits 31 is shown.

FIG. 3 is a diagram showing the configuration of the element circuit and the connection of control lines. The element circuit 31 includes a transmission / reception circuit 32, an individual control circuit 36, an individual control line 37, and a branch line 38. The transmission / reception circuit 32 includes a delay control circuit 33, a transmission circuit 34, and a reception circuit 35. FIG. 3 shows a configuration example of the element circuit 31a of FIG. FIG. 3 also shows the vibrator 41 of the 2D array vibrator 12a connected to the element circuit 31.

The delay control circuit 33 outputs an output timing of a drive signal for driving the vibrator 41 output from the wave transmission circuit 34 according to the value of the vertical delay control line 25 via the control circuit 23 according to the control from the apparatus body 11. To control. For example, the delay control circuit 33 is driven by the transmission circuit 34 so as to scan a plurality of focal points (points where ultrasonic waves overlap) output from a plurality of transducers of the 2D array transducer 12a. The signal output timing is controlled by the vertical delay control line 25. In addition, the delay control circuit 33 outputs the timing of the signal input from the reception circuit 35 so that an appropriate image of the target can be obtained from the plurality of reflected waves received by the plurality of transducers of the 2D array transducer 12a, for example. Is controlled by the vertical delay control line 25 and output to the control circuit 23. Although not shown, the control circuit adds signals output from the element circuits 31 and transmits the added signals to the apparatus main body 11 via the buffer. Accordingly, the apparatus main body 11 can perform image processing on the signal received from the delay control circuit 33 and display the target image on the output apparatus.

The wave transmission circuit 34 amplifies the signal output from the delay control circuit 33 and outputs a drive signal for driving the vibrator 41.

The receiving circuit 35 amplifies the signal received by the vibrator 41 and outputs the amplified signal to the delay control circuit 33.

The individual control circuit 36 receives a switching control line 26 output from the control circuit 22 or the control circuit 23 and a branch line 38 that branches the delay control line 25 input to the delay control circuit 33.

FIG. 4 is a diagram showing a configuration of the individual control circuit 36 included in the circuit of FIG. The individual control circuit 36 includes a storage circuit 51, a determination circuit 53, an inverter 52, and an internal control line 39.

The memory circuit 51 receives signals from the branch line 38 and the switching control line 26 and outputs signals to the internal control line 39. The memory circuit 51 switches between holding the value of the output signal to the internal control line 39 and outputting the signal according to the branch line 38 in accordance with the input signal from the switching control line 26.

The inverter 52 inputs a signal from the switching control line 26 and outputs a signal corresponding to the input signal to the determination circuit 53.

The determination circuit 53 receives a signal from the storage circuit 51 and the inverter 52 and outputs a signal corresponding to the input signal to the individual control line 37.

FIG. 5 shows a truth table of the individual control circuit 36.
The memory circuit 51 outputs the signal state of the branch line 38 to the internal control line 39 when the signal of the switching control line 26 is “1 state”. The memory circuit 51 holds a signal output to the internal control line 39 immediately before the switching control line is switched to the “0 state” when the switching control line 26 is in the “0 state”.
The determination circuit 53 outputs the signal state of the internal control line 39 to the individual control line 37 only when the signal of the switching control line 26 is “0 state”.
As described above, the individual control circuit 36 can switch the transmission / reception circuit 32 on and off according to the values of the switching control line 25 and the branch line 38.

FIG. 6 is a block diagram showing a connection example between the element circuit 31, the vertical delay control line 25, and the switching control line 26 when N element circuits 31 are arranged on the vertical line. A 2D array IC is configured by arranging a plurality of blocks in FIG. 6 in the horizontal direction.

6 includes a control circuit 23, a vertical delay control line 25, a switching control line 26, and element circuits 31a to 31N. Each element circuit 31 includes a transmission / reception circuit 32 and an individual control circuit 36.

The vertical delay control line 25 includes N-bit signal lines S [N−1] to S [0] and is connected to the transmission / reception circuit 32 of the element circuits 31a to 31N. The switching control line 26 is connected in common to the individual control circuits 36 of the element circuits 31a to 31N.

The branch line 38a input to the individual control circuit 36a branches from the S [N-1] line of the vertical delay control line 25. The branch line 38b input to the individual control circuit 36b branches from the S [N-2] line of the vertical delay control line 25. Similarly, branch lines 38c to 38N input to the individual control circuits 36c to 36N branch from S [N-3] to S [0] of the vertical delay control line 25, respectively. That is, branch lines 38 branched from different lines from a plurality of vertical delay control lines are input to the individual control circuits 36 of the element circuits 31 arranged on the vertical lines.

Fig. 7 shows a time chart of the operation when element circuits are arranged in a line. The ultrasonic probe 12 has a transmission / reception period in which ultrasonic transmission / reception is performed and an idle period in which transmission / reception is not performed. Internal control lines 39a to 39c show signal waveforms of the respective internal control lines 39 in the individual control circuits 36a to 36c of FIG. Hereinafter, a specific operation of the idle period and the transmission / reception period of the 2D array IC will be described with reference to FIG.

In the idle period 1, since the switching control line 26 is in “1 state”, the individual control line 37 is in “0 state”, and all the transmission / reception circuits 32 are powered off.

Since the vertical delay control line 25S [N−1] is “1 state”, the internal control line 39a becomes “1 state”. Since the vertical delay control line 25S [N-2] is in the “0 state”, the internal control line 39b is in the “0 state”. Since the vertical delay control line 25S [N-3] is “1 state”, the internal control line 39c is “1 state”. Since all the individual control lines 37 are in the “0 state” during the idle period regardless of the signal state of the internal control line 39, all the transmission / reception circuits 32 are in the power-off state.

Next, in the transmission / reception period 1, the switching control line 26 becomes “0”, and a signal for performing delay control is input to the vertical delay control line 25. The value of the internal control line 39 holds the signal value set when the switching control line 26 is in the “1 state”. Therefore, the internal control lines 39a and 39c hold “1 state” and the internal control line 39b holds “0 state” without being affected by the vertical delay control line 25. The values of the individual control lines 37a and 37c are "1 state", the transmission / reception circuits 32a and 32c are powered on, amplify the input signal to the transmission circuit delayed according to the delay control, and drive the vibrator. Since the value of the individual control line 37b is “0”, the transmission / reception circuit 32b remains powered off, and the transmission / reception circuit does not drive the vibrator.

Next, in the idle period 2, since the switching control line 26 is in the “1 state”, all the transmission / reception circuits 32 are powered off. Further, since the vertical delay control line 25S [N−1] is “0 state”, the internal control line 39a changes from “1 state” to “0 state”. Since the vertical delay control line 25S [N-2] is “1 state”, the internal control line 39b changes from “0 state” to “1 state”. Since the vertical delay control line 25S [N-3] is in the “1 state”, the internal control line 39c continues to be in the “1 state”.

Next, in the transmission / reception period 2, the switching control line 26 becomes “0 state”, and a signal is input to the vertical delay control line 25 for delay control. The value of the internal control line 39 holds the signal value set when the switching control line 26 is in the “1 state”. Each individual control line 37 becomes “0 state” or “1 state” according to the signal state of the internal control line 39. The transmission / reception circuit 32 is turned on / off according to the signal state of the individual control line 37.

For example, in the case of FIG. 6, the branch line 38a input to the individual control circuit 36a of the element circuit 31a branches off from the control line 25S [N−1]. The branch line 38b input to the individual control circuit 36b of the element circuit 31b branches off from the control line 25S [N-2]. The branch line 38N input to the individual control circuit 36N of the element circuit 31N branches from the control line 25S [0], and all the branch lines 38 branch from different control lines 25. I understand.

The branch line 38 which is one of the control lines of the individual control circuit 36 is a control line branched from the vertical delay control line 25 of the transmission / reception circuit 32. Since the branch line 38 branches from the vertical delay control line 25 in the element circuit 31 and is connected to the individual control circuit 36, the handling is easy. When the control line of the individual control circuit is laid out using the conventional method of Patent Document 2, two control lines in the vertical direction and one in the horizontal direction are required for each individual control circuit. From this, the method of patent document 2 requires the wiring area for a total of two. Next, a control line area for wiring to the individual control circuit in the present invention will be considered. For example, when the wiring length of the branch line is assumed to be 1/4 of the element circuit length, when the wiring according to the method of the present invention is used, 1/4 of the branch line and the switching control line 26 that is a common control line are 1 This is necessary. Thus, in the method of the present invention, the total wiring area is 1.25. When the wiring area of the present invention is compared with the wiring area of Patent Document 2, the present invention can reduce the wiring area of 37.5% from Patent Document 2.

Further, since the control lines 25 are branched from different control lines 25, as shown in FIG. 7, during the idle period, different signals of “1 state” or “0 state” are individually input simultaneously to the respective memory circuits 39. Is possible. Therefore, it is possible to shorten the idle period as compared with the method of rewriting each memory circuit 39 in order.

As described above, by using the method of the present invention, since the control line can be wired with a small area, an ultrasonic probe including a 2D array IC in which each transmission / reception circuit can be individually powered on / off with a small area is realized. Is possible.

Further, since different signals can be simultaneously input to each memory circuit 39, the idle period can be shortened as compared with the method of rewriting each memory circuit 39 in order.

According to this embodiment, the delay control line group that supplies a signal for controlling the output timing of the vibrator drive signal is used to hold information in the individual control circuit during the idle period, and to transmit / receive using this information during the transmission / reception period. Since individual power-on / power-off of the circuit can be switched, individual control of the transmission circuit can be performed with a small area, and the yield of the 2D array IC can be improved by turning off the defective transmission circuit. Can do.

In the second embodiment, a control example in the case where the number of element circuits 31 arranged in a vertical line is larger than the number of vertical delay control lines 25 arranged in one vertical column will be described.

FIG. 8 is a diagram showing the configuration of the element circuit and the connection of the control lines. Compared to the configuration of FIG. 3, the lateral delay control line 24 is newly wired to the delay control circuit 33. The lateral delay control line 24 is connected to the individual control circuit 36 by a branch line 40.

FIG. 9 is a diagram showing a configuration of the individual control circuit 36 included in the circuit of FIG. Compared to the configuration of FIG. 4, a determination circuit 54 and a branch line 40 are added.
The determination circuit 54 inputs a signal from the switching control line 26 and the branch line 40 and outputs a signal to the storage circuit 51.
The memory circuit 51 receives signals from the branch line 38 and the determination circuit 54 and outputs signals to the internal control line 39. The storage circuit 51 switches between holding the value of the output signal to the internal control line 39 and outputting the signal according to the branch line 38 in accordance with the input signal from the determination circuit 54.
The inverter 52 receives a signal from the control line 26 and outputs a signal corresponding to the input signal to the determination circuit 53.
The determination circuit 53 receives signals from the storage circuit 51 and the inverter 52 and outputs a signal corresponding to the input signal to the individual control line 37.

FIG. 10 shows a circuit example of a 2D array IC for controlling the element circuits 31 arranged in an array.
The 2D array IC of FIG. 10 is characterized in that horizontal delay control lines 24a to 24d wired in the horizontal direction are added to FIG.

Hereinafter, the configuration of FIG. 10 will be described.
The 2D array IC shown in FIG. 10 includes eight element circuits 31 arranged in an array (vertical 4 × horizontal 2), a horizontal delay control line 24 and a vertical delay control line for delay control of the transmission / reception circuit 32 of the element circuit 31. 25, and control circuits 22 and 23 for controlling signals input to the horizontal delay control line 24 and the vertical delay control line 25. In addition, a switching control line 26 connected to each individual control circuit 36 is provided. The element circuit 31 includes a transmission / reception circuit 32 and an individual control circuit 36.

The control circuit 22 is connected to the lateral delay control lines 24a, 24b, 24c, and 24d. The control circuit 22 individually inputs “1 state” or “0 state” signals to the lateral delay control lines 24a, 24b, 24c, and 24d.
The lateral delay control line 24a is connected to the transmission / reception circuits 32a and 32b and the individual control circuits 36a and 36b.
The lateral delay control line 24b is connected to the transmission / reception circuits 32c and 32d and the individual control circuits 36c and 36d.
The lateral delay control line 24c is connected to the transmission / reception circuits 32e and 32f and the individual control circuits 36e and 36f.
The lateral delay control line 24d is connected to the transmission / reception circuits 32g and 32h and the individual control circuits 36g and 36h.

The control circuit 23 is connected to the vertical delay control lines 25a, 25b, 25c, and 25d. The control circuit 23 individually inputs “1 state” or “0 state” signals to the vertical delay control lines 25a, 25b, 25c, and 25d.
The vertical delay control line 25a is connected to the transmission / reception circuits 32a, 32c, 32e, and 32g and the individual control circuits 36a and 36e.
The vertical delay control line 25b is connected to the transmission / reception circuits 32a, 32c, 32e, and 32g and the individual control circuits 36c and 36g.
The vertical delay control line 25c is connected to the transmission / reception circuits 32b, 32d, 32f, and 32h and the individual control circuits 36b and 36f.
The vertical delay control line 25d is connected to the transmission / reception circuits 32b, 32d, 32f, and 32h and the individual control circuits 36d and 36h.

The control circuit 23 is connected to the switching control line 26. The switching control line 26 is connected to an individual control circuit 36 included in each element circuit 31. The control circuit 23 inputs a “1 state” or “0 state” signal to the switching control line 26.

The individual control circuit 36 transmits / receives a “1 state” or “0 state” signal according to the input signals of the switching control line 26, the horizontal delay control line 24, and the vertical delay control line 25 during the idle period. To 32.

FIG. 11 is a truth table showing the relationship between the switching control line 25, the lateral delay control line 24 (branch line 40), the input signal of the branch line 38, and the output signals of the individual control line 37 and the internal control line 39. Show.

The write timing to the memory circuit 51 is controlled by the switching control line 26 and the lateral delay control line 24. During the writable period, the signal state of the branch line 38 is written into the memory circuit 51. Outside the write time, the signal of the branch line 38 is not written to the memory circuit 51, and the signal state written until immediately before is held.

Signal output to the transmission / reception circuit 32 is controlled by the switching control line 26. The switching control line 26 controls the signal of the individual control line 37 to “0 state” so that the transmission / reception circuit 32 does not operate during the idle period. On the other hand, during the transmission / reception period, the switching control line 26 is controlled so that the signal held in the storage circuit 51 is output to the transmission / reception circuit 32.
For example, when the signals of both the switching control line 26 and the lateral delay control line 24 are “1 state”, the storage circuit 51 is in a writable period. The storage circuit 51 stores the signal state of the branch line 38, “0 state” or “1 state”, and outputs the stored signal state to the internal control line 39.

When the switching control line 26 is in the “1 state” and the horizontal delay control line 24 is in the “0 state”, the writing period to the storage circuit 51 is not completed. The storage circuit 51 holds the previously stored state regardless of the state of the branch line 38 and outputs the stored signal to the internal control line 39.

When the switching control line 26 is in the “0 state”, regardless of the state of the lateral delay control line 24 and the branch line 38, the writing period to the storage circuit 51 is not completed and the state of the internal control line 39 is output to the transmission / reception circuit 32. . For example, when the signal of the individual control line 37 is “1 state”, the transmission / reception circuit 32 is powered on, and when the signal of the individual control line 37 is “0 state”, the transmission / reception circuit 32 is powered off.

FIG. 12 shows a timing chart of the 2D array IC shown in FIG.
Hereinafter, a specific operation example of the 2D array IC of FIG. 10 will be described with reference to FIG.

In the idle period 11, since the switching control line 26 is in the “1 state”, all the element circuits are in a power-off state, and no signal is output.
Since the horizontal delay control lines 24a and 24b and the vertical delay control lines 25a and 25c are "1 state", the individual control line 37a which is the output of the individual control circuit 36a to which the horizontal delay control line 24a and the vertical delay control line 25a are connected. The individual control line 37b, which is the output of the individual control circuit 36b to which the horizontal delay control line 24b and the vertical delay control line 25c are connected, becomes “1 state” in the transmission / reception period 11, and the other individual control lines 37c, 37d Becomes “0 state”.

In the idle period 12, since the switching control line 26 is in the “1 state”, all element circuits are in a power-off state, and no signal is output. Further, since the horizontal delay control lines 24a and 24b are switched to the “0 state”, the values of the individual control lines 37a, 37b, 37c, and 37d are held.
Since the horizontal delay control lines 24c and 24d and the vertical delay control lines 25b and 25c are in the “1 state”, the individual control line 37g which is the output of the individual control circuit 36g to which the horizontal delay control line 24d and the vertical delay control line 25b are connected. The individual control line 37f, which is the output of the individual control circuit 36f to which the horizontal delay control line 24c and the vertical delay control line 25c are connected, becomes “1 state” in the transmission / reception period 11, and the other individual control lines 37e and 37h. Becomes “0 state”.

In the transmission / reception period 11, the switching control line 26 is in the “0 state”, so writing to the storage circuit 51 becomes impossible, and the signal stored in the storage circuit 51 is output to the transmission / reception circuit 32. In accordance with the signal output to the transmission / reception circuit 32, the transmission / reception circuit enters a power-on / off state.

For example, when the number of vertical delay control lines arranged in an element circuit group on a certain vertical line is smaller than the number of element circuits existing on a certain vertical line, the method described in the first embodiment Then, since all the branch lines 38 cannot be created by branching from different control lines, it is not possible to power on or power off each of the transmission / reception circuits 32 individually.

In the present embodiment, both the horizontal delay control line wired in the horizontal direction and the vertical delay control line wired in the vertical direction are connected to the individual control circuit, so that the element circuit group on one vertical line is wired. Even if the number of connected vertical delay control lines is smaller than the number of element circuits existing on one vertical line, it is possible to individually power on or power off each transmission / reception circuit.

Therefore, in the case of a 2D array IC in which delay control lines are wired in the vertical direction and the horizontal direction, the signal lines necessary for the input of the individual control circuit 36 are the delay control lines wired in the vertical direction and the horizontal direction. Therefore, power transmission / reception circuits can be individually turned on / off with a small wiring area.

FIG. 13 shows a specific connection example of the delay control circuit 33, the transmission circuit 34, and the individual control circuit 36 included in the circuit of FIG. FIG. 13 shows the internal configuration of the transmission circuit 34 compared to FIG. Further, a resistor R1 and a switch SW1 are added to the output section of the wave transmission circuit 34. For example, the transmission circuit 34 is a circuit including determination circuits 61 and 62, a positive level shifter 63, a negative level shifter 64, a positive driver 65, and a negative driver 66.

The delay control circuit 33 sends the signal inp of “1 state” or “0 state” to the determination circuit 61 in accordance with the signals input from the reception circuit 35, the horizontal delay control line 24, and the vertical delay control line 25. The “in state” or “0 state” signal inn is output to the decision circuit 62.

The individual control circuit 36 sends a signal of “1 state” or “0 state” through the individual control line 37 according to the signals input from the lateral delay control line 24, the branch line 38, and the switching control line 26. Output to determination circuits 61 and 62 and SW1. For example, the configuration of the individual control circuit 36 is the circuit of FIG.

The determination circuit 61 is a circuit connected as an input to the individual control line 37 and the signal inp and connected as an output to the positive level shifter 63. The determination circuit 61 outputs a “1 state” or “0 state” signal to the positive level shifter 63 in accordance with the input signal of the individual control line 37 and the signal inp. For example, a signal of “1 state” is output to the positive level shifter 63 only when both the individual control line 37 and the signal inp are “1 state”.

The positive level shifter 63 is a circuit connected to the determination circuit 61 as an input and connected to the positive driver 65 as an output. The positive level shifter 63 is a circuit that shifts the level of the signal input from the determination circuit 61 to a high voltage signal. The signal level-shifted to the high voltage signal is output to the positive driver 65.

The positive driver 65 is connected to the positive level shifter 63 as an input, and is connected to the vibrator 41, the resistor R1, and the receiving circuit 35 as an output. A signal having a positive amplitude amplified to the vibrator 41 is output from the positive driver 65.

The determination circuit 62 is a circuit connected as an input to the individual control line 37 and the signal inn and connected as an output to the negative level shifter 64. The determination circuit 62 outputs a “1 state” or “0 state” signal to the negative level shifter 64 according to the individual control line 37 and the input signal of the signal inn. For example, the signal “1 state” is output to the negative level shifter 64 only when both the individual control line 37 and the signal inn are “1 state”.

The negative level shifter 64 is a circuit connected as an input to the determination circuit 62 and as an output connected to the negative driver 66. The negative level shifter 64 is a circuit that shifts the level of the signal input from the determination circuit 62 to a high voltage signal. The signal level-shifted to the high voltage signal is output to the negative driver 66.

The negative driver 66 is connected to the negative level shifter 64 as an input, and is connected to the vibrator 41, the resistor R1, and the receiving circuit 35 as an output. The negative driver 66 outputs a signal having a negative amplitude amplified to the vibrator 41.

One terminal of the resistor R1 is connected to the positive driver 65, the negative driver 66, the vibrator 41, and the receiving circuit 35. The other terminal of the resistor R1 is connected to the switch SW1. The resistor R1 is installed to send the electric charge accumulated at the output OUT to the GND.
The switch SW1 is controlled by the individual control line 37, and is connected between the resistor R1 and GND. When there is an input to the switch SW1 (when the signal of the “1 state” individual control line 37 is input to the switch SW1), the resistor R1 and GND are electrically connected. When there is no input to the switch SW1 (when the signal of the individual control line 37 in the “0 state” is input to the switch SW1), the resistor R1 and GND are opened. By opening the switch SW1, for example, even if a power supply line or the like is accidentally connected between the drivers 65 and 66 and the vibrator 41, the current passing through the resistor R1 can be suppressed.

14 is a timing chart of FIG. 13 for explaining the circuit operation.

The determination circuit 61 outputs the “1 state” signal to the positive level shifter 63 only when the signal inp and the input signal from the individual control line 37 are “1 state”, and the signal inp and the input from the individual control line 37. When either or both of the signals are in the “0 state”, the “0 state” signal is output to the positive level shifter 63.

The determination circuit 62 outputs the “1 state” signal to the level shifter 64 only when the signal inp and the input signal from the individual control line 37 are “1 state”, and the signal inn and the input signal from the individual control line 37 are output. When either or both are in the “0 state”, a “0 state” signal is output to the level shifter 64.

In the transmission / reception period 21 shown in FIG. 14, the signal of the individual control signal 37 is “1 state”. At this time, when a positive pulse signal that is “1 state” from the signal inp is input to the determination circuit 61, a positively amplified pulse waveform is output from the positive driver 65 as an output OUT signal. .

When a positive pulse signal that is “1 state” from the signal inn is input to the determination circuit 62, a negatively amplified pulse waveform is output from the negative driver 66 as an output signal OUT.
Since the signal of the individual control signal 37 is “1 state”, SW1 is in a conductive state. For this reason, the charge in the output OUT portion in which negative charges are accumulated by the signal inn moves to GND through the resistors R1 and SW1, and the voltage of the output OUT returns to 0V.

Suppose that “0 state” is written in the memory circuit 51 in the individual control circuit 36 during the idle period 21 and control is performed so that the signal of the individual control line 37 becomes “0 state” in the transmission / reception period 22.

In the transmission / reception period 22, the signal of the individual control signal 37 is “0 state”. At this time, even if a positive pulse signal is input to the determination circuits 61 and 62 from the signals inp and inn, the “1 state” signal is not output from the determination circuit, and the “0 state” signal is not converted to the level shifter. 63 and 64. When the “0 state” signal is input, the level shifters 63 and 64 do not operate, so the voltage at the output OUT section remains at 0V.

Thus, it is possible to drive / stop the transmission circuit 34 according to the signal state of the individual control line 37. Moreover, even if a power source or the like is miswired to the output OUT portion of the transmission circuit 34, leakage current can be suppressed by opening SW1.

As described above, in the example shown in the present invention, the vertical delay control line 25 is used for the input of the individual control circuit 36. However, the present invention is not limited to this. That is, even if the signal value changes during the idle period when the transmission / reception circuit 32 is powered off, a control line that does not affect the output of the transmission / reception circuit 32 can be substituted. For example, when there is a variable gain amplifier in the transmission / reception circuit, a control line for controlling the gain or a current control line for controlling the amount of current may be used.
Further, if the value of the switching control line 26 is “1 state”, the transmission / reception circuit is powered off. If it is “0 state”, the output of the individual control circuit 36 set in “1 state” is followed, but this is not restrictive. . For example, if the value of the switching control line 26 is “0 state”, the transmission / reception circuit 32 is powered off, and if it is “1 state”, the transmission / reception circuit 32 is configured to follow the output of the individual control circuit 36 set in “0 state”. May be.

11: Device main body 12: Ultrasonic probe 12a: 2D array transducer 12b: 2D array IC
22, 23: control circuit 24: horizontal delay control line 25: vertical delay control line 26: switching control line 31: element circuit 32: transmission / reception circuit 33: delay control circuit 34: transmission circuit 35: reception circuit 36: individual control circuit 37: individual control line 38: branch line 39: internal control line 40: branch line 41: vibrator 51: storage circuit 52: inverter 53, 54: determination circuit 61, 62: determination circuit 63: positive level shifter 64: negative Level shifter 65: Positive driver 66: Negative driver

Claims (15)

An ultrasonic probe comprising a plurality of transducers arranged in an array and a plurality of element circuits corresponding to each of the plurality of transducers and driving the plurality of transducers,
A first control line group connected to the plurality of element circuits;
A second control line commonly connected to the plurality of element circuits;
A control circuit to which the first control line group and the second control line are connected;
Each of the element circuits is
A transmission / reception circuit connected to the first control line group;
An individual control circuit for controlling the transceiver circuit;
A branch line branched from a corresponding control line of the first control line group and connected to the individual control circuit;
Consisting of
The individual control circuit is connected to the branch line and the second control line,
The ultrasonic probe according to claim 1, wherein the individual control circuit switches individual on / off of the transmission / reception circuit based on a signal from the branch line and a signal from the second control line. The ultrasonic probe according to claim 1,
The individual control circuit has a memory circuit,
The ultrasonic probe according to claim 1, wherein the individual control circuit stores the value of the branch line in the storage circuit during an idle period and outputs the value stored during the transmission / reception period as an on / off switching signal. The ultrasonic probe according to claim 1,
The transceiver circuit is
A delay control circuit that controls an output timing of a drive signal that is input with a signal from the first control line group and that is output from the transmission circuit;
A transmission circuit for outputting a drive signal of the vibrator;
A receiving circuit for inputting and amplifying a signal from the vibrator;
An ultrasonic probe comprising: The ultrasonic probe according to claim 1,
The ultrasonic probe, wherein the plurality of element circuits and the control circuit are formed on one IC substrate. The ultrasonic probe according to claim 1,
The ultrasonic probe according to claim 1, wherein the first control line group is a delay control line, and the second control line is a switching control line. The ultrasonic probe according to claim 1,
The transmission / reception circuit is in a power-on or power-off state according to a signal input from the second control line,
When the power is on, the vibrator is driven in accordance with a signal from the first control line group,
When the power is off, the vibrator is not driven.
An ultrasonic probe characterized by that. The ultrasonic probe according to claim 1,
The individual control circuit has a memory circuit, an inverter circuit, and a determination circuit,
The memory circuit has the branch line and the second control line as inputs, and outputs a signal to the determination circuit,
The inverter circuit receives the second control line as an input, and outputs a signal to the determination circuit.
The determination circuit receives a signal from the storage circuit and the inverter circuit, and outputs a signal to the transmission / reception circuit.
An ultrasonic probe characterized by that. The ultrasonic probe according to claim 1,
The individual control circuit switches between holding the value of the individual output signal of the first control line group or outputting the held signal in accordance with an input signal from the second control line. A characteristic ultrasonic probe. The ultrasonic probe according to claim 1,
The branch line branches from the first control line group in the element circuit.
An ultrasonic probe characterized by that. An ultrasonic probe comprising a plurality of transducers arranged in an array and a plurality of element circuits corresponding to each of the plurality of transducers and driving the plurality of transducers,
A group of vertical control lines connected to the plurality of element circuits;
A lateral control line group connected to the plurality of element circuits;
A second control line commonly connected to the plurality of element circuits;
A control circuit to which the vertical control line group and the horizontal control line group and the second control line are connected;
Each of the element circuits is
A transmission / reception circuit connected to the vertical control line group and the horizontal control line group;
An individual control circuit for controlling the transceiver circuit;
A first branch line branched from a corresponding control line of the vertical control line group and connected to the individual control circuit;
A second branch line branched from a corresponding control line of the horizontal control line group and connected to the individual control circuit;
Consisting of
The individual control circuit is connected to the first branch line, the second branch line, and the second control line,
The individual control circuit switches individual on / off of the transmission / reception circuit based on a signal from the first branch line and the second branch line and a signal from the second control line. A characteristic ultrasonic probe. The ultrasonic probe according to claim 10, wherein
The individual control circuit has a memory circuit,
The individual control circuit stores the value of the first branch line or the second branch line in the storage circuit during an idle period, and outputs the value stored during the transmission / reception period as an on / off switching signal. Ultrasonic probe. The ultrasonic probe according to claim 10, wherein
The individual control circuit includes a memory circuit, an inverter circuit, a first determination circuit, and a second determination circuit,
The second determination circuit receives the second branch line and the second control line as inputs, and outputs a signal to the memory circuit,
The storage circuit receives the output of the first branch line and the second determination circuit as an input, and outputs a signal to the first determination circuit,
The inverter circuit receives the second control line and outputs a signal to the first determination circuit.
The first determination circuit receives a signal from the memory circuit and the inverter circuit, and outputs a signal to the transmission / reception circuit.
An ultrasonic probe characterized by that. The ultrasonic probe according to claim 10, wherein
The transceiver circuit is
A delay control circuit that receives the signals from the vertical control line group and the horizontal control line group and controls the output timing of the drive signal output by the transmission circuit;
A transmission circuit for outputting a drive signal of the vibrator;
A receiving circuit for inputting and amplifying a signal from the vibrator;
An ultrasonic probe comprising: The ultrasonic probe according to claim 10, wherein
An ultrasonic probe characterized in that a switch circuit connected to the ground through a resistor is provided on the output side of the transmission / reception circuit, and the switch circuit is turned on / off according to the output of the individual control circuit. The ultrasonic probe according to any one of claims 1 to 14,
An ultrasonic diagnostic apparatus comprising: a control apparatus that controls the entire ultrasonic diagnostic apparatus; an apparatus main body having an input apparatus and an output apparatus.

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