[go: up one dir, main page]

WO2016166949A1 - Plaquette de semi-conducteur et dispositif semi-conducteur - Google Patents

Plaquette de semi-conducteur et dispositif semi-conducteur Download PDF

Info

Publication number
WO2016166949A1
WO2016166949A1 PCT/JP2016/001896 JP2016001896W WO2016166949A1 WO 2016166949 A1 WO2016166949 A1 WO 2016166949A1 JP 2016001896 W JP2016001896 W JP 2016001896W WO 2016166949 A1 WO2016166949 A1 WO 2016166949A1
Authority
WO
WIPO (PCT)
Prior art keywords
buffer layer
layer
group iii
nitride semiconductor
iii nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2016/001896
Other languages
English (en)
Japanese (ja)
Inventor
紘子 井口
哲生 成田
伊藤　健治
嘉代 近藤
伸幸 大竹
真一 星
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Publication of WO2016166949A1 publication Critical patent/WO2016166949A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02516—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 

Definitions

  • the present disclosure relates to a semiconductor wafer and a semiconductor device.
  • Patent Document 1 discloses a technique for growing a multilayer buffer layer on a silicon substrate and growing a group III nitride semiconductor layer (functional layer) on the multilayer buffer layer.
  • Patent Document 1 discloses a composition modulation layer in which a first unit layer and a second unit layer having different compositions are repeatedly laminated, a termination layer grown on the composition modulation layer, and an intermediate layer (strain strengthening) grown on the termination layer.
  • a multilayer buffer layer having a unit laminated structure and having a plurality of unit laminated structures.
  • the group III nitride semiconductor When a material with a smaller coefficient of thermal expansion than the group III nitride semiconductor is used as the substrate for growing the group III nitride semiconductor layer, the group III nitride semiconductor is cooled from a high temperature (during vapor phase growth) to a low temperature (typically room temperature). When it is done, tensile strain occurs inside.
  • the multilayer buffer layer has a compressive strain.
  • an intermediate layer strain strengthening layer is provided at a portion in contact with the group III nitride semiconductor layer, thereby strengthening the compressive strain of the multilayer buffer layer and canceling the tensile strain of the group III nitride semiconductor layer.
  • the group III nitride semiconductor layer grows while maintaining the compressive strain.
  • strain-induced step bunching is likely to occur in the group III nitride semiconductor layer, and the surface of the group III nitride semiconductor layer cannot be smoothed.
  • An object of the present disclosure is to provide a semiconductor wafer and a semiconductor device in which the surface of the group III nitride semiconductor layer is smooth.
  • a semiconductor wafer in the first aspect of the present disclosure, includes a substrate and a group III nitride semiconductor layer provided on the substrate via a multilayer buffer layer.
  • the multilayer buffer layer includes at least a first buffer layer and a second buffer layer.
  • the first buffer layer is in contact with the group III nitride semiconductor layer.
  • the second buffer layer is in contact with the first buffer layer and has a composition different from that of the first buffer layer.
  • the multilayer buffer layer has an average lattice constant smaller than that of the group III nitride semiconductor layer.
  • Interfacial lattice distortion of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer is caused by the first buffer layer at the interface between the first buffer layer and the second buffer layer. Less than interfacial lattice distortion.
  • the interfacial lattice strain of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer (hereinafter referred to as the interfacial lattice strain of the group III nitride semiconductor layer) is the first buffer. It is smaller than the interface lattice strain of the first buffer layer at the interface between the layer and the second buffer layer (hereinafter referred to as the interface lattice strain of the first buffer layer). Therefore, the group III nitride semiconductor layer is suppressed from growing while having the compressive strain of the first buffer layer.
  • the interface lattice strain of the group III nitride semiconductor layer smaller than the interface lattice strain of the first buffer layer, it is possible to suppress the occurrence of strain-induced step bunching in the group III nitride semiconductor layer.
  • the semiconductor wafer described above can smooth the surface of the group III nitride semiconductor layer.
  • a semiconductor device in a second aspect of the present disclosure, includes a substrate and a group III nitride semiconductor layer provided on the substrate via a multilayer buffer layer.
  • a semiconductor element is formed on the surface side of the group III nitride semiconductor layer.
  • the multilayer buffer layer includes at least a first buffer layer and a second buffer layer.
  • the first buffer layer is in contact with the group III nitride semiconductor layer.
  • the second buffer layer is in contact with the first buffer layer and has a composition different from that of the first buffer layer.
  • the multilayer buffer layer has an average lattice constant smaller than that of the group III nitride semiconductor layer.
  • Interfacial lattice distortion of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer is caused by the first buffer layer at the interface between the first buffer layer and the second buffer layer. Less than interfacial lattice distortion.
  • the interfacial lattice strain of the group III nitride semiconductor layer (hereinafter referred to as the interfacial lattice strain of the group III nitride semiconductor layer) at the interface between the group III nitride semiconductor layer and the first buffer layer is the first buffer. It is smaller than the interface lattice strain of the first buffer layer at the interface between the layer and the second buffer layer (hereinafter referred to as the interface lattice strain of the first buffer layer). Therefore, the group III nitride semiconductor layer is suppressed from growing while having the compressive strain of the first buffer layer.
  • the interface lattice strain of the group III nitride semiconductor layer smaller than the interface lattice strain of the first buffer layer, it is possible to suppress the occurrence of strain-induced step bunching in the group III nitride semiconductor layer.
  • the semiconductor wafer described above can smooth the surface of the group III nitride semiconductor layer.
  • FIG. 1 schematically shows a cross-sectional view of the semiconductor wafer of the first embodiment
  • FIG. 2 shows the characteristics of the semiconductor wafer of the first embodiment
  • FIG. 3 schematically shows a cross-sectional view of the semiconductor wafer of the second embodiment
  • FIG. 4 shows the characteristics of the semiconductor wafer of the second embodiment
  • FIG. 5 shows the characteristics of the semiconductor wafer of the third embodiment
  • FIG. 6 shows the characteristics of the semiconductor wafer of Comparative Example 1.
  • FIG. 7 shows the characteristics of the semiconductor wafer of Comparative Example 2
  • FIG. 8 shows the results of the surface roughness of the semiconductor wafer for the examples and comparative examples.
  • a group III nitride semiconductor layer is provided on a substrate via a multilayer buffer layer.
  • the multilayer buffer layer has an average lattice constant smaller than that of the group III nitride semiconductor layer.
  • the multilayer buffer layer includes at least a first buffer layer and a second buffer layer.
  • the first buffer layer is in contact with the group III nitride semiconductor layer.
  • the second buffer layer is in contact with the first buffer layer.
  • the first buffer layer and the second buffer layer have different compositions.
  • the interfacial lattice strain of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer is the first at the interface between the first buffer layer and the second buffer layer. It is smaller than the interfacial lattice distortion of one buffer layer.
  • the interfacial lattice strain of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer (hereinafter referred to as the interfacial lattice strain of the group III nitride semiconductor layer) is the first buffer. It is smaller than the interface lattice strain of the first buffer layer at the interface between the layer and the second buffer layer (hereinafter referred to as the interface lattice strain of the first buffer layer). Therefore, the group III nitride semiconductor layer is suppressed from growing while having the compressive strain of the first buffer layer.
  • the interface lattice strain of the group III nitride semiconductor layer smaller than the interface lattice strain of the first buffer layer, it is possible to suppress the occurrence of strain-induced step bunching in the group III nitride semiconductor layer.
  • the semiconductor wafer described above can smooth the surface of the group III nitride semiconductor layer.
  • multilayer buffer layer does not mean a so-called “low temperature buffer layer” for reducing the lattice constant difference between the substrate and the semiconductor element layer, but a group III nitride semiconductor layer.
  • a group III nitride semiconductor layer In order to relieve the thermal strain generated in the group III nitride semiconductor layer when the group III nitride semiconductor layer changes from a high temperature to a low temperature after film formation.
  • strain-induced step bunching is a mechanism of step bunching occurrence discovered and proposed by Tersoff et al. And disclosed in “Physical Review Letters Volume 75 2730 (1995)”.
  • the mechanism is that when a strain is generated on a semiconductor surface formed by periodic step terraces, an attractive force between steps is proportional to the square of the strain and inversely proportional to the distance between steps.
  • the attractive force between steps forms a bundle of steps (step bunching) one after another, and a step is formed on the surface of the semiconductor wafer, so that the surface smoothness of the semiconductor wafer is lowered. Therefore, generation of step bunching can be suppressed by reducing the distortion of the semiconductor surface.
  • the strain-induced step bunching becomes more prominent in a wafer (so-called wafer having an off angle) whose main axis is slightly inclined with respect to the normal of the growth surface.
  • the c-axis is generally the main axis. Therefore, in the case of a group III nitride semiconductor, it can be said that the state where the c-axis is inclined with respect to the normal of the growth surface has an off-angle.
  • the growth surface has a periodic structure in which step terraces are regularly repeated, and the flatness of the wafer surface can be improved.
  • the strain-induced step bunching in the nitride semiconductor layer is more remarkable in the group III nitride semiconductor whose main component is gallium as the group III element.
  • Step bunching occurs in the process where group III atomic species on the terrace are diffused into the step edge. Therefore, step bunching is likely to occur in an environment that satisfies the condition of “average distance between steps ⁇ (1/2) ⁇ surface diffusion length of group III atomic species”.
  • gallium is known to have a longer surface diffusion length than aluminum and indium. Therefore, strain-induced step bunching is likely to occur in a group III nitride semiconductor mainly containing gallium, particularly gallium nitride.
  • gallium nitride includes gallium nitride containing less than 1% impurities (B, Al, In, C, Si, Ge, Mg, S, Fe, As, Sb, etc.). Is also included.
  • the multilayer buffer layer has a smaller lattice constant than the group III nitride semiconductor layer
  • the lattice constant of the multilayer buffer layer Mean lattice constant
  • the lattice constant of a portion of the multilayer buffer layer may be larger than the lattice constant of a portion of the group III nitride semiconductor layer.
  • the terms “average lattice strain” and “interface lattice strain” are used.
  • the ideal lattice constant (theoretical lattice constant) in the plane direction of the first layer (direction perpendicular to the crystal growth direction) is a 1
  • the actual lattice constant is a 1 ′
  • the ideal lattice in the plane direction of the second layer is a 2
  • the actual lattice constant is a 2 ′.
  • the rate R 1 is expressed by the following equation.
  • a group III nitride semiconductor layer is provided over a substrate via a multilayer buffer layer, and a semiconductor element is formed on the surface side of the group III nitride semiconductor layer.
  • the multilayer buffer layer includes at least a first buffer layer and a second buffer layer. The first buffer layer is in contact with the group III nitride semiconductor layer.
  • the second buffer layer is in contact with the first buffer layer.
  • the first buffer layer and the second buffer layer have different compositions.
  • the multilayer buffer layer has an average lattice constant smaller than that of the group III nitride semiconductor layer.
  • the interface lattice strain of the group III nitride semiconductor layer at the interface between the group III nitride semiconductor layer and the first buffer layer is smaller than the interface lattice strain of the first buffer layer at the interface between the first buffer layer and the second buffer layer.
  • the semiconductor wafer includes a substrate, a multilayer buffer layer provided on the substrate, and a group III nitride semiconductor layer provided on the multilayer buffer layer.
  • the substrate has a smaller coefficient of thermal expansion than the group III nitride semiconductor layer.
  • the temperature integral value of the linear expansion coefficient of 300 to 1300K is smaller than the temperature integral value of the linear expansion coefficient of 300 to 1300K in the a-axis direction of the material constituting the group III nitride semiconductor layer.
  • the material of the substrate is silicon (Si) or silicon carbide (SiC).
  • the thickness of the substrate is 0.1 to 2 mm.
  • an interface layer and an aluminum nitride (AlN) layer are provided between the substrate and the multilayer buffer layer.
  • Al 2 O 3 , AlON, or the like can be used as the material for the interface layer.
  • the interface layer can be omitted.
  • the thickness of the aluminum nitride layer is 10 to 500 nm.
  • the aluminum nitride layer preferably has a thickness of 50 to 500 nm.
  • the thickness of the aluminum nitride layer is preferably 10 to 100 nm.
  • Aluminum nitride has the smallest lattice constant among group III nitride semiconductors. Therefore, by providing the aluminum nitride layer, a necessary amount of compressive strain can be applied to the multilayer buffer layer described later. In addition, as described above, the interface layer and the aluminum nitride layer can be omitted, and the multilayer buffer layer can be formed directly on the surface of the substrate.
  • the multilayer buffer layer includes at least a first buffer layer in contact with the group III nitride semiconductor layer and a second buffer layer in contact with the first buffer layer.
  • the multilayer buffer layer may include a third buffer layer in contact with the second buffer layer, a fourth buffer layer in contact with the third buffer layer, and the like. That is, the multilayer buffer layer has a multilayer structure including two or more layers.
  • the first buffer layer is a layer located on the most surface side (group III nitride semiconductor layer side) among the layers constituting the multilayer buffer layer.
  • the first buffer layer and the second buffer layer have different compositions. Also, the first buffer layer is not coherent with respect to the second buffer layer.
  • the strain relaxation rate (R 1 ) of the first buffer layer with respect to the second buffer layer is 0.8 or more. By setting the strain relaxation rate (R 1 ) to 0.8 or more, sufficient strain relaxation occurs in the first buffer layer, and the strain of the group III nitride semiconductor layer can be effectively reduced.
  • the first buffer layer By setting the thickness of the first buffer layer to 0.05 ⁇ m or more, the first buffer layer can be prevented from growing coherently with respect to the second buffer layer. More preferably, the thickness of the first buffer layer is 0.2 ⁇ m or more. By setting the thickness of the first buffer layer to 0.2 ⁇ m or more, the first buffer layer is more reliably connected to the second buffer regardless of the size of the interfacial lattice strain of the first buffer layer and the growth conditions of the first buffer layer. It is possible to prevent coherent growth with respect to the layer.
  • the average lattice constant of the multilayer buffer layer is smaller than the average lattice constant of the group III nitride semiconductor layer. Further, when the entire multilayer buffer layer and aluminum nitride are compared, the average lattice constant of the multilayer buffer layer is larger than the lattice constant of aluminum nitride.
  • the multilayer buffer layer preferably has a compressive strain as a whole. Due to the compressive strain of the multilayer buffer layer, it occurs in the group III nitride semiconductor layer when the temperature of the group III nitride semiconductor layer changes from the growth temperature (high temperature) to room temperature (low temperature) after film formation.
  • Tensile strain can be offset. It is preferable that no tensile strain remains in the first buffer layer. In other words, in the first buffer layer, no strain remains or compressive strain remains. More preferably, the first buffer layer has a compressive strain remaining. Note that “the compressive strain remains in the first buffer layer” corresponds to the average lattice strain of the first buffer layer being a negative value.
  • the layer having the largest absolute value of the average lattice strain among the layers of the multilayer structure constituting the multilayer buffer layer is a layer other than the first buffer layer. In other words, the absolute value of the average lattice strain of the first buffer layer is not the maximum among the layers of the multilayer structure constituting the multilayer buffer layer.
  • a nitride semiconductor represented by Al x Ga 1-x N (0 ⁇ x ⁇ 1) can be used as the material of the multilayer buffer layer.
  • the first buffer layer is preferably a nitride semiconductor represented by Al x Ga 1-x N (0 ⁇ x ⁇ 0.5). More preferably, the first buffer layer is a nitride semiconductor represented by Al x Ga 1-x N (0 ⁇ x ⁇ 0.2). Since the average lattice constant of the first buffer layer is closer to GaN (nitride semiconductor) than to AlN, the difference in average lattice constant between the group III nitride semiconductor layer and the first buffer layer is reduced, and the group III nitride semiconductor layer is reduced. It is possible to reduce the interfacial lattice distortion.
  • each layer of the multilayer buffer layer may have a different “x” value.
  • the value of “x” becomes smaller toward the surface (the group III nitride semiconductor layer side). That is, the multilayer buffer layer preferably has a multilayer structure in which the Al composition becomes smaller toward the surface.
  • the multilayer buffer layer may have a structure in which different materials are repeatedly stacked.
  • the multilayer buffer layer can have a structure in which a laminated structure of AlN and GaN is repeatedly provided.
  • the multilayer buffer layer may have a structure in which a laminated structure of AlN and AlGaN is repeatedly provided.
  • the thickness of the multilayer buffer layer can be 0.5 to 10 ⁇ m.
  • the group III nitride semiconductor layer may be a single layer or multiple layers.
  • the single-layer group III nitride semiconductor layer means that the composition from the front surface to the back surface of the group III nitride semiconductor layer is the same.
  • the multiple group III nitride semiconductor layer means that the group III nitride semiconductor layer includes a plurality of layers having different compositions of group III elements.
  • the group III nitride semiconductor layer is preferably a group III nitride semiconductor mainly composed of gallium (Ga).
  • group III nitride semiconductor mainly composed of gallium typically means gallium nitride (GaN), and B, Al, In on the order of atomic percent of less than 1% with respect to GaN as impurities.
  • gallium nitride containing elements such as C, Si, Ge, Mg, S, Fe, As, and Sb is also included.
  • the group III nitride semiconductor layer preferably contains carbon. When the group III nitride semiconductor layer contains carbon, leakage current can be prevented from flowing when the semiconductor device is in the off state.
  • the group III nitride semiconductor layer can be used as a functional layer (a layer constituting a semiconductor element). A single group III nitride semiconductor layer can also be used as a functional layer.
  • a group III nitride semiconductor layer provided on the surface side of the layer in contact with the first buffer layer can also be used as a functional layer.
  • the interface lattice strain of the nitride semiconductor element (interface lattice strain of the nitride semiconductor element) at the interface between the group III nitride semiconductor layer and the first buffer layer is less than that of the first buffer layer. It is smaller than the interface lattice strain of the first buffer layer at the interface of the second buffer layer (interface lattice strain of the first buffer layer). Since the interfacial lattice strain of the nitride semiconductor element is smaller than the interfacial lattice strain of the first buffer layer, it is possible to suppress the occurrence of strain-induced step bunching in the group III nitride semiconductor layer.
  • the semiconductor wafer 1 includes a silicon substrate 2, an interface layer 4 formed on the silicon substrate 2, an AlN layer 6 formed on the interface layer 4, a multilayer buffer layer 8 formed on the AlN layer 6, A group III nitride semiconductor layer 10 formed on the multilayer buffer layer 8 and a nitride semiconductor functional layer 12 formed on the group III nitride semiconductor layer 10 are provided.
  • the thickness T2 of the silicon substrate 2 is 675 ⁇ m.
  • the material of the interface layer 4 is Al 2 O 3 .
  • the thickness T4 of the interface layer 4 is adjusted to be less than 3 nm.
  • the thickness T6 of the AlN layer 6 is adjusted to 0.3 ⁇ m.
  • the material of the multilayer buffer layer 8 is Al x Ga 1-x N.
  • the thickness T8 of the multilayer buffer layer 8 is adjusted to 2.5 ⁇ m.
  • the multilayer buffer layer 8 has a four-layer structure including a first buffer layer 8a, a second buffer layer 8b, a third buffer layer 8c, and a fourth buffer layer 8d.
  • the first buffer layer 8 a is in contact with the group III nitride semiconductor layer 10
  • the fourth buffer layer 8 d is in contact with the AlN layer 6. Note that the value of “x” of Al x Ga 1-x N increases from the first buffer layer 8a toward the fourth buffer layer 8d.
  • the thickness of the first buffer layer 8a is adjusted to 0.8 ⁇ m
  • the thickness of the second buffer layer 8b is adjusted to 0.2 ⁇ m
  • the thickness of the third buffer layer 8c is adjusted to 0.5 ⁇ m.
  • the thickness of the fourth buffer layer 8d is adjusted to 1.0 ⁇ m.
  • the interface layer 4 is formed by using an atomic layer deposition method (ALD method).
  • ALD method atomic layer deposition method
  • trimethylaluminum is used as the Al raw material
  • ozone is used as the O raw material.
  • the AlN layer 6 and the multilayer buffer layer 8 are formed using a metal organic chemical vapor deposition method (MOCVD method).
  • MOCVD method metal organic chemical vapor deposition method
  • the growth temperature is about 1000 ° C.
  • the material of the group III nitride semiconductor layer 10 is gallium nitride (GaN).
  • the thickness of group III nitride semiconductor layer 10 is adjusted to 0.6 ⁇ m, and the thickness of nitride semiconductor functional layer 12 is adjusted to 0.4 ⁇ m.
  • the group III nitride semiconductor layer 10 contains 2 ⁇ 10 18 cm ⁇ 3 of carbon.
  • the carbon introduced into the group III nitride semiconductor layer 10 prevents leakage current from flowing between the semiconductor element formed in the nitride semiconductor functional layer 12 and the silicon substrate 2.
  • the nitride semiconductor functional layer 12 is i-type that does not contain impurities (it may contain unavoidable carbon).
  • a semiconductor element can be formed using the nitride semiconductor functional layer 12.
  • FIG. 2 shows the characteristics of the AlN layer 6, the multilayer buffer layer 8, and the group III nitride semiconductor layer 10 for the semiconductor wafer 1.
  • the Al composition (x) corresponds to the value of “x” when each layer is represented by Al x Ga 1-x N.
  • the group III nitride semiconductor layer 10 is denoted by GaN
  • the first buffer layer 8a is denoted by TOP
  • the “i” th buffer layer from the first buffer layer 8a is denoted by i.
  • the average lattice constant a ′ j in the a-axis direction and the average lattice constant c ′ j in the c-axis direction were calculated from the following formulas (1) and (2) using the face spacings d 114j and d 004j .
  • Formula (2): c ′ j 4 ⁇ d 004j
  • the Al composition (x) is obtained by using the interplanar spacings d 114j and d 004j obtained by the X-ray reciprocal mapping and the results obtained by the above formulas (1) and (2), using “x” in the following formula (3). ”Was calculated.
  • a AlN is the ideal lattice constant of the a-axis of AlN
  • c AlN is the ideal lattice constant of the c-axis of AlN.
  • ⁇ 0.38 was used as the Poisson's ratio.
  • the Poisson's ratio is disclosed in “T.
  • the ideal lattice constant a j of each layer (TOP, i) of the buffer layer was calculated from the following formula (4) using the value of “x” of each layer as a variable when each layer was represented by Al x Ga 1-x N.
  • the average lattice strain and the interface lattice strain are positive strains when they are positive values, and compressive strains when they are negative values. Therefore, the magnitude relation of the lattice distortion does not compare actual numerical values but compares absolute values.
  • j GaN
  • j + 1 corresponds to TOP.
  • the semiconductor wafer 1 the interface lattice distortion of the group III nitride semiconductor layer 10 ( ⁇ If_GaN) is the interface lattice distortion ( ⁇ If_TOP) of the first buffer layer 8a smaller.
  • the average lattice strain epsilon '1 of the second buffer layer 8b is the maximum among the average lattice strain of the buffer layer 8a ⁇ 8d. That is, the average lattice strain ( ⁇ TOP ) of the first buffer layer 8 a is not the maximum among the average lattice strains ( ⁇ 1 to 3 ) of the layers constituting the multilayer buffer layer 8.
  • the semiconductor wafer 11 will be described with reference to FIG.
  • the semiconductor wafer 11 is a modification of the semiconductor wafer 1.
  • the semiconductor wafer 11 has a larger number of layers constituting the multilayer buffer layer 18 than the semiconductor wafer 1.
  • the multilayer buffer layer 18 has a five-layer structure including a first buffer layer 18a, a second buffer layer 18b, a third buffer layer 18c, a fourth buffer layer 18d, and a fifth buffer layer 18e.
  • the first buffer layer 18a is a composition gradient layer having an Al composition (x) of 0.08 to 0.03.
  • the average Al composition (x) of the first buffer layer 18a is 0.033.
  • the multilayer buffer layer 18 has a thickness T18 of 2.43 ⁇ m.
  • the thickness T18a of the first buffer layer 18a is adjusted to 0.63 ⁇ m.
  • the thicknesses T18b to T18e of the second to fifth buffer layers 18b to 18e are adjusted to 0.1, 0.2, 0.5, and 1.0 ⁇ m, respectively.
  • FIG. 4 shows the characteristics of the AlN layer 6, the multilayer buffer layer 18, and the group III nitride semiconductor layer 10 for the semiconductor wafer 11.
  • the interface lattice distortion of the group III nitride semiconductor layer 10 ⁇ If_GaN
  • interface lattice distortion of the first buffer layer 18a ⁇ If_TOP
  • the average lattice strain epsilon '1 of the second buffer layer 18b is the largest among the average lattice strain of the buffer layer 18a ⁇ 18e (absolute value).
  • the average lattice strain ( ⁇ TOP ) of the first buffer layer 18 a is not the maximum among the average lattice strains ( ⁇ 1 to 4 ) of the layers constituting the multilayer buffer layer 18.
  • the group III nitride semiconductor layer 10 has a thickness adjusted to 0.75 ⁇ m and contains 4 ⁇ 10 19 cm ⁇ 3 of carbon.
  • the nitride semiconductor functional layer 12 is adjusted to a thickness of 0.48 ⁇ m and is i-type.
  • an AlGaN barrier layer 20 nm and a GaN cap layer 5 nm are formed on the surface of the nitride semiconductor functional layer 12.
  • a field effect transistor can be manufactured by forming a gate electrode, a source electrode, and a drain electrode on the surfaces of the semiconductor wafers 1 and 11.
  • the gate electrode is opposed to the nitride semiconductor functional layer 12 through the insulating film.
  • the source electrode and the drain electrode are in ohmic contact with the nitride semiconductor functional layer 12.
  • the nitride semiconductor functional layer 12 functions as a channel layer of the field effect transistor.
  • a Schottky electrode and an ohmic electrode can be formed on the surfaces of the semiconductor wafers 1 and 11 to manufacture a Schottky diode.
  • the nitride semiconductor functional layer 12 functions as a current-carrying layer for the Schottky diode.
  • a semiconductor wafer according to a third embodiment will be described.
  • the structure of the semiconductor wafer of this embodiment is substantially the same as that of the semiconductor wafer 1 of the first embodiment.
  • the semiconductor wafer of this example has different characteristics of each layer.
  • differences from the semiconductor wafer 1 will be described with reference to FIG.
  • the average lattice strain ⁇ ′ TOP of the first buffer layer 8a is the largest among the average lattice strains (absolute values) of the buffer layers 8a to 8d. Different from wafer 1. That is, the portion of the buffer layer in contact with the group III nitride semiconductor layer 10 has the highest compressive strain. This difference can be caused by adjusting the manufacturing conditions (buffer layer growth conditions). Also in the semiconductor wafer of the present embodiment, the interface lattice distortion of the group III nitride semiconductor layer 10 ( ⁇ If_GaN) is in that the interface lattice distortion ( ⁇ If_TOP) is smaller than the first buffer layer 8a, the first embodiment The semiconductor wafer 1 has common characteristics.
  • Example 2 The surface roughness of the semiconductor wafers of Examples 1 to 3 was measured. The results are shown in FIG. The surface roughness is a root mean square roughness (RMS) of an atomic force microscope in an area of 50 ⁇ m square. In addition, the surface roughness of the semiconductor wafers of Comparative Examples 1 and 2 was also measured. First, the characteristics of the semiconductor wafers of Comparative Examples 1 and 2 will be described.
  • RMS root mean square roughness
  • the characteristics of the semiconductor wafer of Comparative Example 1 are shown in FIG.
  • the semiconductor wafer of Comparative Example 1 includes four buffer layers having different Al compositions (x).
  • the thickness of the first buffer layer is 0.5 ⁇ m.
  • the group III nitride semiconductor layer contains 4 ⁇ 10 18 cm ⁇ 3 of carbon and has a thickness of 0.4 ⁇ m.
  • an i-type nitride semiconductor functional layer is laminated on the surface of the group III nitride semiconductor layer.
  • the nitride semiconductor functional layer has a thickness of 0.6 ⁇ m.
  • the average lattice strain ⁇ ′ TOP of the first buffer layer is the largest among the average lattice strains (absolute values) of the first to fourth buffer layers. Further, the interfacial lattice strain ( ⁇ If_GaN ) of the group III nitride semiconductor layer is larger than the interfacial lattice strain ( ⁇ If_TOP ) of the first buffer layer.
  • the semiconductor wafer of Comparative Example 1 includes four buffer layers having different Al compositions (x).
  • the thickness of the first buffer layer is 0.44 ⁇ m.
  • the group III nitride semiconductor layer contains 1.5 ⁇ 10 18 cm ⁇ 3 of carbon and has a thickness of 0.66 ⁇ m.
  • an i-type nitride semiconductor functional layer is laminated on the surface of the group III nitride semiconductor layer.
  • the nitride semiconductor functional layer has a thickness of 0.33 ⁇ m.
  • an AlGaN barrier layer of 20 nm and a GaN cap layer of 5 nm are formed on the surface of the i-type nitride semiconductor functional layer.
  • the average lattice strain ⁇ ′ TOP of the first buffer layer is the largest among the average lattice strains (absolute values) of the first to fourth buffer layers. Further, the interfacial lattice strain ( ⁇ If_GaN ) of the group III nitride semiconductor layer is larger than the interfacial lattice strain ( ⁇ If_TOP ) of the first buffer layer.
  • the inclination angle of the group III nitride semiconductor layer with respect to the c-axis growth surface was measured by X-ray diffraction.
  • the c-axes of the group III nitride semiconductor layers of Examples 1 to 3 were inclined 0.22 degrees, 0.31 degrees, and 0.30 degrees in the m-axis direction with respect to the normal to the growth surface, respectively.
  • the c-axes of the group III nitride semiconductor layers of Comparative Examples 1 and 2 were inclined by 0.26 degrees and 0.33 degrees in the m-axis direction with respect to the normal to the growth surface, respectively.
  • the interface lattice distortion of the group III nitride semiconductor layer (epsilon If_GaN) is marked with ⁇ in experimental examples that satisfy the interface lattice distortion of the first buffer layer a ( ⁇ If_TOP) condition that is less than (condition 1) In the experiment example which is not satisfied, x is marked.
  • condition 1 In the experiment example which is not satisfied, x is marked.
  • Condition 2 that the average lattice strain (absolute value,
  • ⁇ is marked and not satisfied X is described in the experimental example.
  • “ ⁇ ” is marked for an experimental example having an RMS value of 5.0 or less
  • “ ⁇ ” is marked for an experimental example of 10.0 or less
  • x” is marked for an experimental example of 10.0 or more.
  • the average lattice strain (absolute value) of the group III nitride semiconductor layer is 3.97 ⁇ 10 ⁇ 4 to 1.03 ⁇ 10 ⁇ 3
  • the group III nitride semiconductor of the comparative example It is less than half of the average lattice strain (2.44 ⁇ 10 ⁇ 3 , 2.04 ⁇ 10 ⁇ 3 ) of the layer.
  • the strain relaxation rates (R TOP ) of the first buffer layer with respect to the second buffer layer are 0.974, 0.863, and 0.837, respectively (FIGS. 2 and 4). And 5). That is, the semiconductor wafers of Examples 1 to 3 have a strain relaxation rate (R TOP ) of 0.8 or more. In contrast, the semiconductor wafers of Comparative Examples 1 and 2 have strain relaxation rates (R TOP ) of 0.464 and 0.431, respectively, which are smaller than those of the semiconductor wafers of Examples 1 to 3 (see FIG. 6 and 7).
  • the average lattice strain (3.97 ⁇ 10 ⁇ 4 , 4.96 ⁇ 10 ⁇ 4 ) of the group III nitride semiconductor layers of Examples 1 and 2 satisfies both Condition 1 and Condition 2, It is one quarter or less of the average lattice strain of the Group III nitride semiconductor layer of the comparative example.
  • Examples 1 and 3 have the same structure in the upper layer than the group III nitride semiconductor layer.
  • Example 1 and 3 differ in whether condition 2 is satisfied.
  • the 004 diffraction half widths related to the helical component dislocation were 390 sec (Example 1) and 470 sec (Example 3), respectively.
  • the 114 diffraction half widths including information on the edge component dislocations were 540 sec (Example 1) and 740 sec (Example 3), respectively.
  • both conditions 1 and 2 are satisfied, the X-ray half width is narrow and the crystallinity is improved.
  • the edge dislocation density was suppressed to about 1 ⁇ 2 to 3 of Example 3 in Example 1. This is because, when both conditions 1 and 2 are satisfied, a first buffer layer having a large interface lattice strain but a small average lattice strain is formed, and a large strain relaxation occurs in the first buffer layer. This is probably because the edge dislocations having the Burgers vector of opposite polarity disappeared. It was also shown that there is an effect of reducing the dislocation density by satisfying both conditions 1 and 2. When dislocation pair annihilation having a reverse polarity Burgers vector occurs, the first buffer layer is compressive strain at the growth temperature, and the strain remaining at room temperature is either compression or no strain. That is, at least a tensile strain does not remain in the first buffer layer at room temperature.
  • the warpage of the semiconductor wafer changes according to the product of the “strain” and the “film thickness” of the group III nitride semiconductor layer. That is, when the strain of the group III nitride semiconductor layer is large, the amount of warpage of the semiconductor wafer greatly changes due to a slight change in film thickness. Therefore, when the group III nitride semiconductor layer grows with inherent strain, it becomes difficult to control the amount of warpage of the semiconductor wafer. According to the technology disclosed in this specification, the group III nitride semiconductor layer is prevented from growing with inherent strain, so even if an error occurs in the film thickness, variation in the amount of warpage between batches is suppressed. be able to.
  • the semiconductor wafer 1 can also improve the robustness of warpage control.
  • the Al composition (x) of each layer of the multilayer buffer layer was calculated using Equations 2 and 3.
  • the cathodoluminescence measurement (CL measurement) is performed on the cross section of the buffer layer, and the band edge emission peak EGap is measured. It can also be obtained optically from (eV). That is, the Al composition (x) can be obtained by measuring the band edge emission peak EGap (eV) and calculating “x” in the following formula (8).
  • the bowing parameters are disclosed in (T. Onuma et.al., J. Appl. Phys.
  • EGap (X) 3.4 ⁇ (1 ⁇ x) + 6.2 ⁇ x ⁇ b ⁇ xx ⁇ (1 ⁇ x)
  • the average composition x when a multilayer periodic structure such as AlN / GaN is used for the multilayer buffer layer can be calculated by obtaining the AlN / GaN film thickness ratio by a cross-sectional TEM (Transmission Electron Microscope) or the like.
  • AlN / AlGaN the case of a multilayer periodic structure comprising Al x Ga 1-x N / Al y Ga 1-y N, and calculates the respective layers of the Al composition (x) by CL measurement, the film thickness measurement by cross-sectional TEM By combining, it can be converted into an average Al composition (x).
  • the multilayer buffer layer may be present in at least two layers (a first buffer layer in contact with the group III nitride semiconductor layer and a second buffer layer in contact with the first buffer layer). Further, a structure having six or more multilayer buffer layers may be taken.
  • a multilayer periodic structure such as AlN / GaN
  • the layer period / film thickness ratio is different in the multilayer buffer layer
  • the i-type semiconductor functional layer is provided on the surface of the group III nitride semiconductor layer.
  • a layer containing an n-type or p-type impurity can also be provided.
  • a heterojunction is formed, a structure including a heterojunction of a mixed crystal with InN can be taken.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne une plaquette de semi-conducteur comprenant un substrat et une couche de semi-conducteur de nitrure du groupe III prévue sur le substrat avec une couche de tampon à couches multiples intercalée entre eux. La couche de tampon à couches multiples contient au moins une première couche tampon et une seconde couche tampon. La première couche tampon est en contact avec la couche de semi-conducteur de nitrure du groupe III. La seconde couche tampon est en contact avec la première couche tampon et présente une composition différente de la première couche tampon. La constante de réseau moyenne de la couche de tampon à couches multiples est inférieure à celle de la couche de semi-conducteur de nitrure du groupe III et la distorsion de réseau d'interface de la couche de semi-conducteur de nitrure du groupe III au niveau de l'interface entre la couche de semi-conducteur de nitrure du groupe III et la première couche tampon est inférieure à la distorsion de réseau d'interface de la première couche tampon au niveau de l'interface entre la première couche tampon et la seconde couche tampon.
PCT/JP2016/001896 2015-04-16 2016-04-04 Plaquette de semi-conducteur et dispositif semi-conducteur Ceased WO2016166949A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015084187A JP2016207715A (ja) 2015-04-16 2015-04-16 半導体ウエハ及び半導体装置
JP2015-084187 2015-04-16

Publications (1)

Publication Number Publication Date
WO2016166949A1 true WO2016166949A1 (fr) 2016-10-20

Family

ID=57126050

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2016/001896 Ceased WO2016166949A1 (fr) 2015-04-16 2016-04-04 Plaquette de semi-conducteur et dispositif semi-conducteur

Country Status (2)

Country Link
JP (1) JP2016207715A (fr)
WO (1) WO2016166949A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117916890A (zh) * 2022-03-15 2024-04-19 新唐科技日本株式会社 半导体装置以及半导体装置的制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007067077A (ja) * 2005-08-30 2007-03-15 Nippon Telegr & Teleph Corp <Ntt> 窒化物半導体素子およびその製造方法
JP2013021124A (ja) * 2011-07-11 2013-01-31 Dowa Electronics Materials Co Ltd Ｉｉｉ族窒化物エピタキシャル基板およびその製造方法
WO2013108733A1 (fr) * 2012-01-16 2013-07-25 シャープ株式会社 Tranche épitaxiale pour transistor à effet de champ à hétérojonction
JP2014192226A (ja) * 2013-03-26 2014-10-06 Sharp Corp 電子デバイス用エピタキシャル基板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007067077A (ja) * 2005-08-30 2007-03-15 Nippon Telegr & Teleph Corp <Ntt> 窒化物半導体素子およびその製造方法
JP2013021124A (ja) * 2011-07-11 2013-01-31 Dowa Electronics Materials Co Ltd Ｉｉｉ族窒化物エピタキシャル基板およびその製造方法
WO2013108733A1 (fr) * 2012-01-16 2013-07-25 シャープ株式会社 Tranche épitaxiale pour transistor à effet de champ à hétérojonction
JP2014192226A (ja) * 2013-03-26 2014-10-06 Sharp Corp 電子デバイス用エピタキシャル基板

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117916890A (zh) * 2022-03-15 2024-04-19 新唐科技日本株式会社 半导体装置以及半导体装置的制造方法

Also Published As

Publication number Publication date
JP2016207715A (ja) 2016-12-08

Similar Documents

Publication Publication Date Title
JP5309452B2 (ja) 半導体ウエーハ及び半導体素子及び製造方法
JP5785103B2 (ja) ヘテロ接合型電界効果トランジスタ用のエピタキシャルウエハ
US20130020581A1 (en) Epitaxial wafer including nitride-based semiconductor layers
US20120273759A1 (en) Epitaxial substrate for electronic device and method of producing the same
US11581269B2 (en) Semiconductor thin film structures and electronic devices including the same
US8823055B2 (en) REO/ALO/A1N template for III-N material growth on silicon
US8633569B1 (en) AlN inter-layers in III-N material grown on REO/silicon substrate
CN102714162A (zh) 第iii族氮化物外延层压基板
CN102859695A (zh) 外延基板以及外延基板的制造方法
JP2016515299A (ja) 希土類酸化物ゲート誘電体を備えた、シリコン基板上に成長したｉｉｉ−ｎ半導体素子
JP5159858B2 (ja) 窒化ガリウム系化合物半導体基板とその製造方法
CN103314429A (zh) 用于控制异质外延生长的iii族氮化物层的应力的层结构
CN110544716A (zh) Iii-n半导体结构及形成iii-n半导体结构的方法
JP2013014450A (ja) 窒化物半導体エピタキシャル基板及び窒化物半導体デバイス
CN103681794A (zh) 半导体晶片、半导体器件和用于制造氮化物半导体层的方法
JP2019110344A (ja) 窒化物半導体装置および窒化物半導体基板
JP2013145782A (ja) ヘテロ接合型電界効果トランジスタ用のエピタキシャルウエハ
US8872308B2 (en) AlN cap grown on GaN/REO/silicon substrate structure
JP5824814B2 (ja) 半導体ウエーハ及び半導体素子及びその製造方法
JP6173493B2 (ja) 半導体素子用のエピタキシャル基板およびその製造方法
US8823025B1 (en) III-N material grown on AIO/AIN buffer on Si substrate
JP2015103665A (ja) 窒化物半導体エピタキシャルウエハおよび窒化物半導体
JP6089122B2 (ja) 窒化物半導体積層体およびその製造方法並びに窒化物半導体装置
WO2016166949A1 (fr) Plaquette de semi-conducteur et dispositif semi-conducteur
WO2016152106A1 (fr) Tranche de semi-conducteur, dispositif à semi-conducteur et procédé de fabrication de la tranche de semi-conducteur

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16779747

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16779747

Country of ref document: EP

Kind code of ref document: A1