WO2016155623A1 - Information-push-based information system and method - Google Patents

Abstract

An information processing system and method. The method comprises: generating in advance, by an independent address generator (22), a memory address to access a memory (10); reading information from the memory (10), and pushing the same to a processor (12) for execution or processing, thus reducing the time the processor (12) waits for the information.

Description

 Information system and method based on information push Technical field

 The invention relates to the field of computers, communications and integrated circuits. In particular, it relates to an information processing system, an information processing method, and a storage system.

Background technique

The processor in the stored program computer reads instructions or data from the memory for execution by the CPU, and the results of the execution are sent back to the memory for storage. Figure 1 is a simplified block diagram of a conventional stored program computer, The processor 12 includes an execution unit and a control unit, 12 generates an address to access the memory 10 via the bus 11, 10 provides information to the 02 via the bus 13 according to the upper address of 11, and the information herein includes computer instructions and data. The execution result data of the processor 12 is also stored back to 10 via the bus 13. The dotted line above in Figure 1 is the memory and its associated logic, hereinafter referred to as the storage system; the dotted line below is the processor and its associated logic, hereinafter referred to as the processing system. Thereafter, the storage system and the processing system are collectively referred to as an information system or computer. The input and output units of the computer are omitted in FIG. 1 and other embodiments of the present disclosure for ease of explanation. With the advancement of technology, the capacity of the memory increases, the access delay increases, the channel delay of the memory access also increases, and the execution speed of the processor increases, so the memory access delay increasingly becomes a serious bottleneck for the improvement of the computer performance. The memory access delay includes the access delay inside the memory device; and the transmission channel delay between the memory and the processor, such as the transmission delay between the plurality of chips on the circuit board or the shared substrate or the TSV via, the intermediate layer chip For example, the delay of the North Bridge, the delay of the indirect connection of multiple memory chips, the delay caused by the transmission format conversion, the delay caused by the communication protocol, or even the delay on the long-distance communication channel, such as the delay of the network and wireless communication.

technical problem

Therefore, the stored program computer uses a buffer to mask the memory access latency to alleviate this bottleneck. 2 is a simplified schematic diagram of a conventional stored procedure computer using a buffer, The processor 12 includes an execution unit and a control unit, which may or may not include a high-level buffer; 14 is a label unit that stores the lowest-level buffer in the processing system, that is, a last-level buffer (Last) Level Cache, Hereinafter referred to as the label unit of LLC); 16 is the data memory RAM of the LLC. 12 generates address 11 to 14 and 16, if the tags stored in addresses 11 and 14 match, then 16 sends the corresponding data directly to 12 for execution via bus 13, thus avoiding delays in accessing memory 10; such as address 11 and If the tags stored in 14 do not match, then address 11 is sent via bus 17 to memory system access memory 10, which reads the corresponding data over bus 19 to the processing system to fill 16, the output of 16 or the bus 19 The data bypass on the 13 is sent to 12 for execution. The execution result of 12 is stored back to 16 via 13 and written back to the memory 10 of the storage system via bus 19 in accordance with the writeback rules of buffer 16. In the information system of FIG. 2, when the address 11 does not match the label in the label unit 14 in the LLC, the memory access delay is still unmaskable, and as technology advances, the delay is increasingly becoming a bottleneck for computer performance improvement. The method and system apparatus proposed by the present invention can directly address one or more of the above or other difficulties.

The stored program computer uses a buffer to try to mask the memory access latency to alleviate this bottleneck, but it still cannot be completely masked. For this reason, some stored program computers use prefetching to try to further mask memory access latency, but they also encounter difficulties. Some of these difficulties are caused by multi-level caching. Prefetch requests from a higher cache level should pass through multiple storage tiers, and layer-level delivery can reach the lowest tier of memory.

Technical solution

 It is an object of the present invention to provide an information processing system, an information processing method, and a storage system to improve system operation speed.

In the information processing system, the information processing method, and the storage system provided by the present invention, an address generator is used to generate and output more addresses according to the currently output information block, thereby causing the memory/ The register can output more information blocks according to this, which is equivalent to providing the information block that the processor (the information block requirement device) may need before it requests the information, thereby speeding up the processor (information) Block demand device) speeds up the acquisition of information blocks, which in turn increases the speed of the processor and information processing system.

 Further, the present invention proposes a memory hierarchy (Memory Hierarchy) in a processor. Method of adding an address generator and its corresponding system device, the additional address generator can work in conjunction with the processor to address one or more of the above or other difficulties . The additional address generator may generate a predicted address prior to the processor core, and read instructions and data from the lower memory level into the memory of the hierarchy for use by the processor core.

Beneficial effect

The method and system apparatus of the present invention can mask the delay caused by the processor accessing the memory via the latency channel. Other advantages and applications of the present invention will be apparent to those skilled in the art.

DRAWINGS

 1 is a block diagram showing a structure of an existing information processing system;

 2 is a block diagram showing another structure of an existing information processing system;

 3 is a block diagram showing the structure of an information processing system according to Embodiment 1 of the present invention;

 4 is a block diagram showing the structure of an information processing system according to Embodiment 2 of the present invention;

 FIG. 5 is a schematic diagram of an implementation manner of an address generator and related logic according to Embodiment 2 of the present invention; FIG.

 6 is a block diagram showing the structure of an information processing system according to Embodiment 3 of the present invention;

 FIG. 7 is a block diagram showing the structure of an information processing system according to Embodiment 4 of the present invention.

 8 is a block diagram showing a structure of a storage hierarchy system according to Embodiment 5 of the present invention;

 9 is a block diagram showing a structure of a storage hierarchy system according to Embodiment 6 of the present invention;

 10 is a block diagram showing a structure of a storage hierarchy system according to Embodiment 7 of the present invention;

 11 is a block diagram showing a structure of a storage hierarchy system according to Embodiment 8 of the present invention;

 12 is a block diagram showing the structure of a storage hierarchy system according to Embodiment 9 of the present invention;

 13 is a block diagram showing the structure of a storage hierarchy system according to Embodiment 10 of the present invention;

 14 is a schematic structural diagram of a scanner of a storage hierarchy system according to Embodiment 11 of the present invention;

 15 is a schematic diagram showing the structure of a scanner of a storage hierarchy system according to Embodiment 12 of the present invention.

Other aspects of the present invention can be understood and appreciated by those skilled in the art in light of the description of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

 The preferred embodiment of the invention is shown in Figure 3.

Embodiments of the invention

The invention will be further described in detail below with reference to the drawings and specific embodiments. Advantages and features of the present invention will be apparent from the description and appended claims. It should be noted that the drawings are in a very simplified form and all use non-precise proportions, and are only for convenience and clarity to assist the purpose of the embodiments of the present invention.

It should be noted that the various embodiments of the present invention are further described to illustrate the various embodiments of the present invention in order to clearly illustrate the present invention. Further, for the sake of brevity of explanation, the contents already mentioned in the foregoing embodiment are often omitted in the latter embodiment, and therefore, contents not mentioned in the latter embodiment can be referred to the previous embodiment accordingly.

Although the invention may be modified in various forms of modifications and substitutions, some specific embodiments of the invention are set forth in the specification and detailed. It should be understood that the inventor's point of departure is not to limit the invention to the particular embodiments set forth, but the inventor's point of departure is to protect all improvements, equivalent transformations and modifications based on the spirit or scope defined by the claims. . The same component numbers may be used in all figures to represent the same or similar parts.

 In addition, in the present specification, an architecture including a processor is taken as an example, and the technical solution of the present invention can be applied to include any suitable processor ( Processor) architecture. For example, the processor may be a general purpose processor or a central processing unit (CPU) ), Microprocessor, Core, Microcontroller (MCU), Digital Signal Processor (DSP), Image Processor (GPU) ), system on chip (SOC), application specific integrated circuit (ASIC), etc. The memory or cache may be constructed of any suitable storage device, such as a register or register file ( Register file ), static memory (SRAM), dynamic memory (DRAM), flash memory (Flash memory), hard disk (HD) ), Solid State Drive (SSD) and any suitable storage device or future new form of memory.

 The invention provides a method for adding an address generator in a storage system and a corresponding system device thereof. The additional address generator can work in conjunction with the processor to address one or more difficulties caused by the prior art . The additional address generator may take a processor to execute an instruction, or the scanner parses the information output by the memory, and the like, generating an address prior to the processor, and reading the instruction and data from the memory to the processing. The processor pushes the pushed instruction according to the program and the internal state, processes the data pushed from the memory or the data on the processor side, and writes the result of the processing back to the memory.

In the information system of the present invention, the processor may not output a memory address to the storage system at all, but the address generator in the storage system independently generates a memory address to access the memory and pushes to the processing system (push ) corresponding instructions and data. It is also possible in most cases for the memory address to be generated independently by the address generator, but in a few cases the processor in the processing system outputs control flow information to the storage system (control flow) Information ) , as branched, to simplify the address generator structure. The address generator determines a program execution path according to the control flow information, generates location information of a subsequent instruction, and pushes the device to the processor core ( Push ) the corresponding instruction or data. To further simplify the structure of the address generator, it is also possible to allow the processor to provide a memory address to an address generator in the memory system under certain conditions, and the address generator independently executes the program from the memory address provided by the processor.

 [First Embodiment] Please refer to Figure 3, which is A block diagram of an information processing system according to Embodiment 1 of the present invention. The address generator in this embodiment is a dedicated computing unit, including a plurality of registers, and some or all of the adders, shifters, and logical operators, at least part of the functions of the processor can be performed, and can be calculated Generate an instruction or data address and make a branch decision. In this way, instructions related to memory address generation can be directly executed in the storage system, and the corresponding instructions or data can be read and sent to the processor for execution according to the calculated instruction or data memory address.

 In the embodiment of FIG. 3 and the following description, the processing system below the dotted line in FIG. 3 is similar to that in the embodiment of FIG. 1, and 12 is a processor. 12 may or may not contain a buffer. In the storage system (above the dotted line) 10 is the memory, 22 is the address generator added to the storage system, and 18 is the selector. twenty two It can also contain a buffer or not. The address generator 22 generates an address via the bus 21 to access the memory 10, 10 via the bus 23 to the address generator 22 and the processor. 12 provides data and instructions. The selector 18 selects the execution result 25 of the address generator 22 or the execution result 15 of the processor 12 to write back to the memory 10 via the bus 29. Processor 12 in this embodiment The address is not sent, and the memory address is not transferred by the processing system to the memory system via the bus 11 as shown in the embodiment of FIG. The address generator 22 can execute the same set of instructions as the processor 12, namely 22 and 12 The same function; 22 and 12 can also execute a different instruction set, 22 or 12 One of them executes the complete instruction set and the other executes a restricted instruction set. Processors that execute a restricted instruction set do not execute instructions that are outside the scope of their restricted instruction set, but only set flag bits to record out-of-range events. Address generator An application that executes the same instruction set with the processor 12, or the address generator 22 executes the complete instruction set and the processor 12 executes the restricted instruction set may be the processor generated by the address generator 22. 12 required program instructions and data are pushed to the processing system; processor 12 executes the program to process data collected by the processing system or stored in the processing system, and then the processor The final result of the 12 processing is sent back to the storage system memory 10 for storage.

 The address generator 22 executes the restricted instruction set and the processor 12 executes the complete instruction set. The application may be by the address generator. 22 Push the program instructions and data required by the processor 12 to the processing system. The address generator 22 executes its instructions in the set of restricted instructions and writes back the results produced by the instructions in the set of restricted instructions to the memory 10; the processor 12 then executes all instructions in the complete instruction set, writing results other than the results that can be generated by executing the restricted instruction set back to the memory 10 of the storage system. For example, address generator 22 The restricted instruction set contains only the instructions necessary to change the flow of the program, such as loading LD, storing ST, adding ADD, subtracting SUB, shifting SHIFT, logic, comparing COMP, branch BR, jumping JUMP, etc., at this time, the main function of the address generator 22 is to generate a memory address, and the address generator 22 The program is executed, and the generated address is sent to the memory 10 for reading the information and sent to the address generator 22 and the processor 12 for execution and processing. The above-described set of restricted instructions also enables the address generator 22 to perform operations such as moving data from one area to another in the memory 10; or performing a simple operation on data in an area in the memory 10, writing it back to the The operation of a zone or another zone; or the operation of storing data of an input unit into memory 10, moving data in 10 to the output unit; reducing the bandwidth requirements of these operations for the channel between the storage system and the processing system. At the same time, the address generator twenty two The timing of executing an instruction is generally one channel delay from the storage system to the processing system earlier than the processor 12 executing the same instruction. In addition, the address generator 22 generates an address to access the memory 10 via the bus 21 for a time longer than the same address generated by the processor 12 and then passes through the processing system to the memory system's channel delay access memory 10 to the bidirectional channel between the storage system and the processing system. delay. Therefore, the information system structure of the present invention disclosed in Embodiment 1 and FIG. 3 compares the existing system structure, for example, as shown in the embodiment of FIG. 1 or FIG. 2, to mask the bidirectional channel delay between the storage system and the processing system.

 [Embodiment 2] Please refer to FIG. 4, which is a block diagram of an information processing system according to Embodiment 2 of the present invention, which is in FIG. On the basis of the embodiment, the same final level cache LLC is added to both the processing system and the storage system. In Figure 4, 10 is the memory in the storage system, 22 is the address generator, 24 For the tag unit of the storage system LLC, 26 is the data memory RAM of the LLC in the storage system, and 28 is the output of the temporary address generator 22 to be stored in the memory 10 and the LLC RAM. A first in first out (FIFO) of data of 26, 18 is a selector that selects stored data from 28 or processor 12 for storage into memory 10; a processing system under the dashed line is similar to that in the embodiment of Figure 2, 12 For the processor, 14 is the tag unit of the processing system LLC, and 16 is the data memory RAM of the processing system LLC. Address generator in storage system 22 generates address 21 to 26 and sends to 24 for screening. If the tags stored in addresses 21 and 24 match, then 26 sends the corresponding information directly to 22 for execution via bus 27; processor 12 generates the address in the processing system. Bus 11 is sent to 14 and 16, and if the address on bus 11 matches the tag stored in 14, then 16 the corresponding message is sent directly to 12 via bus 13 for execution. The bus 11 is only used inside the processing system, and in the prior art, as shown in the embodiment of FIG. 1 or FIG. 2, the processor in the processing system will be processed. The resulting address is sent to the storage system to access the memory 10 differently. If the address 21 generated by the address generator 22 in the storage system does not match the tag stored in the tag unit 24 in the storage system, the address on the bus 21 is filtered out to access the memory 10, and the read cache block is filled and stored via the bus 23. System LLC RAM 26, the output of 26 or the information on the bus 23 is bypassed via bus 27 to the address generator 22 for execution; the read information block is also sent to the processing system via bus 23, at which time the processor 12 in the processing system The generated address 11 does not match the tag stored in the LLC tag unit 14 in the processing system, so the LLC in the processing system is populated with the cache block on the bus 23. RAM 16. The output of 16 will either bypass the data on bus 23 directly to bus 12 for execution by bus 13. There is also a bus 15 for processing the system to the storage system for feeding the operation result of the processor 12 to the storage system, selecting it by the selector 18, and storing it in the memory 10 and the LLC via the bus 29. RAM 26. There is also a bus 19 that processes the system to the memory system, and the branch decision and/or branch target address of the processor 12 is sent to the address generator 22 for use by the address generator to perform branch operations independently.

The cache replacement logic of the storage system and the processing system are the same, so cache blocks of the same address in 26 and 16 are replaced by cache blocks from bus 23. The tag portion of the address 21 is also written to the entry indicated by the cache replacement logic in the storage system LLC tag unit 24; the tag portion of the same address 11 is also written to the processing system LLC tag unit 14 by the cache replacement logic. The same entry indicated. Such a storage system and processing system LLC The same data is present in the RAMs 26 and 16, and the storage system LLC tag unit 24 has the same tag content as the processing system LLC tag unit 14. The same content is first filled in the tag unit 24 and RAM of the storage system. 26, after the channel delay of the storage system to the processing system is filled in the tag unit 14 and the RAM of the storage system 16. When the address of the storage system is found to be mismatched by the comparison of the contents of the tag in the tag unit 24 with the bus 21, the access memory 10 reads the data and begins to fill the data into the storage system LLC RAM. 26, after the channel delay, fill in the processing system LLC RAM 16. Normally, the address of the processing system is compared with the contents of the tag in the tag unit 14 via the bus 11 and the timing of the mismatch is found to be later than the same address of the storage system via the bus 21 and the tag content in the tag unit 24. The channel delay of the system, as in the embodiment of Figure 2, sends the address on bus 11 to the storage system to access memory 10, which in turn passes through a channel delay of the processing system to the storage system. Thus, the architecture disclosed in the embodiment of FIG. 4 obscures the two-way between the storage system and the processing system as compared with the existing architecture in the embodiment of FIG. 1 or FIG. (Round Trip) channel delay.

 Please refer to FIG. 5 , which is a schematic diagram of an implementation manner of an address generator and related logic according to Embodiment 2 of the present invention, showing an effective chain. The concept of '(Valid Chain) and operations based on efficient chain. In Figure 5, 22 is the address generator, where 30 is the register file, 34 is the instruction decoder, and 36 is the AND gate. 38 is the execution unit, 42 is the branch judgment unit, 44, 46, 48, 50 are selectors; wherein each entry in the register file 30 has an additional valid bit 32 The branch judgment in the branch determiner 42 or each entry in the branch condition flag stored therein has a corresponding valid bit 40 . 28 outside address generator 22 is first in, first out, 18 As a selector. The 'effective chain' rule is an operation performed by a valid instruction on a valid operand, and the operation result is valid; if any one of the operands or the operation instruction used by the operation is invalid, the operation result is invalid. Here, the valid instruction refers to an instruction in the restriction instruction set, that is, an instruction that the processor executing the restriction instruction set can execute. From memory 10 or the operand of the buffer is defined as valid, so the result of the load instruction LD is valid, and the valid entry of the entry in the target register file 30 of the load instruction is 32. Medium. Thereafter, the operation of the target register is an operand. If the instruction is a valid instruction and the other operands used by the instruction are also valid, the result of the operation is valid.

 The instruction on bus 27 is decoded by instruction decoder 34. If the instruction is valid, then 34 controls the slave register file. The corresponding operand is read by the operand address in the instruction and sent to the execution unit via the bus 35 and 25. 38 is processed according to the instruction operation type, and the result is written back to the register file via the bus 39. The entry pointed to by the destination operand address in the instruction; at the same time, the valid bit of the above operand in 32 ('0' is invalid, '1' is valid) is also read out to AND gate 36, and decoded 34 The generated instruction valid signal 47 performs an AND operation, and the result 37 is written back to the valid bit in the register of the register file pointed to by the destination operand address in the instruction file 32. . If all operands and instructions are valid, the valid bit in the target entry is 'valid'; if any of the operands is invalid, the valid bit in the target entry is 'invalid'. If the instruction is invalid, the decoder 34 The instruction valid signal 47 meaning 'invalid' is sent to the AND gate 36 to make its output 37 represent 'invalid' and control the register file 30 The 'invalid' signal is written to the valid bit 32 in the destination register heap entry of the invalid instruction. Or you can control the execution unit when 37 is 'invalid'. No action is taken to save power. Such a valid signal is passed between the register entries via AND gate 36 processing, which is an active chain, and the active chain can be interrupted by an invalid instruction or an invalid operand.

 When the address generator 22 executes a store (Store) instruction on the bus 27, the decoder 34 controls the register file. 30 The base address is sent via the bus 35, and the immediate value in the store instruction selected by the control selector 50 at this time is added by the execution unit 38, and the sum is stored in the first in first out via the bus 39. The 56 field of one of the entries is used as the storage address. 34 also controls the register file 30. The bus 25 outputs the data stored in the 54 field of the same entry in the first-in, first-out, and also controls the read register file. The valid bit 32 in the data entry is stored on the bus 49 in the 52 field of the same entry in the first in first out. When the first in first out is 28, the entry reaches the head of 28, from 28 In the middle output, if the signal in the 52 field in the entry is 'valid', the signal control selector 18 selects the data in the 54 field of the entry to be sent to the memory 10 and the LLC RAM via the bus 29 26. Write to the memory location addressed by the memory address sent by the 56 field in the entry via bus 31. If the signal in the 52 field in the entry is 'invalid', the signal controls the selector 18 The data sent by the processor 12 via the bus 15 in the processing system is sent to the memory 10 and the LLC RAM 26 via the bus 29, and is also written to the bus 31. The storage location addressed by the storage address. The processor 12 executing the complete instruction set has the same valid bit and active chain, and its active chain generation and address generator 22 It's exactly the same, but its usage is just the opposite. When the processor 12 executes a store instruction, such as when the data read from the register file has a valid signal of 'invalid' (i.e., the data is an address generator that executes the restricted instruction set 22) When it cannot be correctly generated, the processor 12 sends the data to the storage system via the bus 15 and is selected by the selector 18 to be stored in the memory 10 and the LLC RAM 26 via the bus 29. . If the data read from the register file has a valid signal of 'valid', then processor 12 does not send the data to the storage system because address generator 22 has generated the same data, has it stored, or is Ready to deposit 10 and 26 .

 The valid chain can also be used for branch judgment. Figure 5 Address Generator in the Embodiment 58 Generates a Sequence Instruction Address 41 (Current instruction address plus '1') or direct branch destination address 43 (current instruction address plus branch offset in branch instruction) for selection. The instruction decoder 34 controls the selector 46 when executing the non-branch instruction The sequential address 41 is selected as the next instruction address; when the branch instruction is executed 34 causes the branch decision 45 to control the selector 46 to select the sequential address 41 or the branch target address 43 As the instruction address; the instruction address and the data address or the indirect branch destination address 39 output by the execution unit 38 are selected by the selector 48 as the memory address 21 to be sent to the memory 10, LLC Tag unit 24 and LLC RAM 26 are addressed. In this example, the branch generator 22 generates the branch judgment independently, and the branch judgment unit 42 determines the branch type and execution unit according to the branch instruction. The execution result of the execution instruction 39 is generated. When a portion of the execution result 39 is stored as a branch flag or a branch judgment, its corresponding valid chain result 37 is also stored in the register 40. 40 The output control selector 44, if the contents of 40 is valid, 44 selects the address generator branch branch of the 42 output to control the selector 46 to select the sequential address 41 or the branch target address 43 . This situation corresponds to most branch operations, such as when performing branch operations on all integers. However, some special branch operations may depend on the result of executing an instruction that is outside the scope of the restricted instruction set. For example, the branch operation is based on comparing the size of two floating point numbers. The usual practice is that the floating point unit compares the two floating point numbers, moves the comparison result from the floating point register file to the integer register file, and then the branch determiner in the integer unit. The judgment is made according to the branch type of the branch instruction. If the address generator If the restricted instruction set of 22 does not include floating-point operations, then the instruction to move data from the floating-point register file to the integer register file 30 interrupts the valid chain, causing the data to be shifted into the valid register bits in the integer register file table. Is 'invalid'. When the 'invalid' bit is considered 'invalid' after being processed by AND gate 36, it is stored in register 40 via 37, causing selector 44 to select bus 19 on processor 12. The sent branch is judged as a branch decision 45 to control the selector 46 to select the sequential address 41 or the branch target address 43. Similar to the above sending data from the processing system to the storage system, the processor 12 It is also possible to maintain a valid chain for branch judgment, and only send the processor via bus 19 when its valid chain result is 'invalid' (meaning that address generator 22 executing the restricted instruction set cannot make a correct branch decision). The branch judgment is used by the address generator 22.

 In Figure 5, when the instruction decoder 34 decodes the indirect branch instruction on the bus 27, the control register file 30 is routed via the bus 35. The base address is read, and the selector 50 is also controlled to select the branch offset in the indirect branch instruction on the bus 27, and the base address is added to the branch offset by the execution unit 38, and the sum is placed on the result bus 39. . If the valid chain result 37 corresponding to the result of the operation is 'valid', the control selector 48 selects the value on the bus 39 and places the memory address bus 21 as the branch target address pair of the indirect branch. , 24, 26 and other addressing. If the value on 37 is 'invalid', it may be that the overrange instruction is used in the process of generating the base address. At this time, the control decoder 34 controls the logic to control the selector 46. Selecting the indirect branch destination address generated by processor 12 from bus 19 also controls selector 48 to select the output of 46 to cause processor 12 The generated indirect branch destination address is placed on the memory address bus 21 to address 10, 24, 26, etc. The indirect branch destination address on bus 21 is also stored back to address generation unit 58. To generate the subsequent sequential address 41 and the next direct branch address 43 .

 Normally, the address generator 22 in the storage system executes the instructions than the processor in the processing system. The same instruction must be executed at least to store the channel delay from the system to the processing system, and the required instructions and data can be pushed to the processor 12 in advance. Waiting for the bus 19 at the above address generator 22 When the sent branch judges or indirectly branches the target address, the address generator 22 executes the post-branch instruction time ratio processor 12 The time to execute the same instruction is later to process the channel delay from the system to the storage system. However, the address generator 22 does not execute an overrange instruction, so it can catch up and lead the processor again. Execute the same instructions and push the required instructions and data to processor 12 in advance. The implementation may be to increase the read and write bandwidth of the entry valid bit 32 of the register file 30, for example 32 All of the bits can be read and written independently in parallel; the instruction decoder 34 can decode multiple instructions in parallel, and directly invalidate the corresponding valid bits of the target register file entry for the out-of-range invalid instructions. Set to 'invalid', the instruction itself does not need to be executed. For another example, the instruction decoder decodes the valid bits 32 of the operands used by the plurality of instructions in parallel according to the instruction packets, and respectively associated with the instruction valid signals. Phase 'and' (similar to the door in Figure 5 The function) draws intermediate results. The instruction decoder further performs correlation detection on the plurality of instructions. For example, if the target register file entry written by the preceding instruction in the program sequence is used as the operand by the subsequent instruction, the instruction will be in the middle of the previous instruction. The result is an AND operation with the intermediate result of the subsequent instruction as the final result of the subsequent instruction. The final result of the 'valid' instruction is executed sequentially; the final result of the 'invalid' instruction only needs to have the valid bits in its target register file table entry. 32 Set to 'invalid', the instruction itself does not need to be executed. A priority check is required when writing each valid bit. If there are multiple writes to the same location, only the valid chain result of the last instruction in the program order can be written. First detect the address generator 22 The instruction to be executed, filtering the invalid instruction or the instruction whose instruction is valid but the operand is invalid, causes the address generator 22 to execute only the instruction capable of generating a valid result, so that the address generator 22 can precede the processor 12. Execution of the same instructions enables the storage system to provide the processor 12 with the required instructions or data in advance. If the address generator 22 can also execute the complete instruction set (although the execution efficiency is not necessarily the same as the processor 12) The same can be omitted from the processor 12 to the address generator 22 or the branch destination address bus 19 .

 [Embodiment 3] Please refer to FIG. 6, which is a block diagram of an information system according to Embodiment 3 of the present invention, which is shown in FIG. The LLC RAM 26 in the storage system is omitted on the basis of the embodiment, and the rest are the same. In Figure 6, in the storage system on the dotted line, 10 is the memory and 22 is the address generator, 24 For the tag unit of the storage system LLC, 28 is the first in first out (FIFO) output of the temporary address generator 22, 18 is the selector for selecting the stored data from 28 or the processor 12; in the processing system under the dotted line 12 is the processor, 14 is the tag unit of the processing system LLC, and 16 is the data memory RAM of the processing system LLC. Address generator 22 The instruction or data input is directly from the output bus 23 of the memory 10. The address generator 22 outputs the memory address addressed by the bus 21 to the memory 10 to read the instruction or data onto the bus 23 to the address generator. 22 execution. At the same time, the memory address on bus 21 also addresses the LLC of the storage system. The tag unit 24 performs filtering. If the hit is at 24, the instruction or data on the bus 23 is only used by the address generator 22 and is not sent to the processing system; if it does not hit in 24, the memory address on the bus 21 is replaced by the rule. Deposit into LLC Label unit 24; instructions or data on bus 23 are sent to the processing system and stored in the LLC RAM 16, processor The memory address of the instruction or data that is also generated 12 is stored in the LLC tag unit 14 via the bus 11 (as with the address on the bus 21). The rest of the operation is identical to the embodiment of Figures 4 and 5.

 [Embodiment 4] Please refer to Figure 7, which is A block diagram of an information system of Embodiment 4 of the present invention. In this embodiment, the processor generates an address access memory read information in the processing system, and the address generator of the storage system does not make a branch judgment, but may generate a processor according to the address generated by the processor and the information block generated by the memory according to the address. The address of the information is sent to the memory, so that the memory advance output information is sent to the processing system for selection by the processor. As shown As shown in Figure 7, the information system includes a storage system and a processing system. The processing system includes: a processor 12 for obtaining information, which may include a buffer, responsible for generating a current address 11; and an information buffer tag unit 64, and an information buffer (Information Buffer) 66, wherein 64 and 66 are also collectively referred to as a second memory; and a selector 68. The storage system includes: a memory 10, for storing information and outputting a block of information via the bus 23 according to the received address, the address generator 60 for using the current address 11 and the bus 23 The upper information block generates an address and provides an address to the memory, as well as a selector 62. Here, the information processing system performs information processing by the following method:

 The processor 12 sends a memory address 11; an address 11 and an information buffer tag unit 64. The content is matched for comparison. If hit, the information buffer 66 outputs the information block to the processor 12; if not, the address 11 is sent to the storage system via the selector 62 to access the memory 10 The memory 10 outputs an information block via the bus 23 according to the address 11 sent by the processor 12, and the selector 68 is used by the processor 12; the address generator 60 in the storage system An address 61 is generated based on a block of information currently output by the memory 10, and an address 61 is provided to the memory 10 via selection of a selector 62; the memory 10 is based on the address generator 60 Address provided 61 The output block is stored in the message buffer 66 via bus 23.

 That is, in the present embodiment, when the processor 12 issues an address at which information needs to be obtained (i.e., a request is made / When the address is requested, the storage system memory 10 is used by the processor 12 in addition to outputting a block of information based on the address issued by the processor 12; The generated address issues another one or more blocks of information that are pre-stored in the information buffer 66 for the processor 12 Use it next. Relative to the existing processor to issue an address that needs to obtain information, the memory sends a block of information according to the address, so that the processor can only get a block of information corresponding to the address it sends out (or the block of information pointed to by the address it sends) In the information processing system provided by this embodiment, the processor 12 Issue an address that requires information, and memory 10 will output (send/send/provide) multiple blocks of information (where one block is requested by processor 12 / The address is transmitted, and the other information blocks are sent at the request/address of the address generator 60, so that the processor 12 can be requested by one / The address gets multiple blocks of information, masking the delay in obtaining the other block after the first block of instructions is fetched. It should be noted that in the terminology of the present invention, 'information block (block) ' is a unit of information, which includes an instruction block whose content is an instruction and a data block whose content is data. Here, the size of the 'information block' (ie, how many bits are specifically) is not limited, which may be different according to System requirements definition, such as a processor A multiple of the cache block size in 12.

 In the present embodiment, the address generator 60 accepts the memory address on the bus 11, the information block on the bus 23, and the bus 63. The upper signal is sent by the processor 12 to indicate that the address on the bus 11 is an instruction address or a data address; the address generator 60 outputs an address 61 which is selected by the selector 62. Select to access memory 10, which is also stored in information buffer tag unit 64. The address generator 60 scans and parses the current information block by the following process: the address generator 60 will bus The memory address on 11 is added with the block offset (ie, the address deviation of two adjacent information blocks) to obtain the address of the adjacent information block of the current information block; Determining whether the current information block is an instruction block, and if it is an instruction block, acquiring instruction type information of each instruction in the instruction block (OP ), and decode the type information of each instruction to determine whether the instruction is a direct branch instruction. If it is judged that an instruction is a direct branch instruction, the memory address on the bus 11 is Adding the branch offset contained in the instruction, obtaining the address of the instruction block where the branch target of the direct branch instruction is located; the address generator screening the generated branch target address to determine the branch target address and the current instruction block Whether the addresses are the same, if not, the generated addresses are filtered. Address generator The acquired adjacent block address or branch target information address is supplied to the memory 10 via the bus 61 and the selector 62, and the memory 10 outputs the information block according to the address of the branch instruction.

 The memory 10 outputs a block of information according to the memory address sent from the processor 12 via the bus 11 via the bus 23, and the selector 68 It is sent directly to the processor 12 for execution. The information block output from the memory 10 based on the memory address sent from the address generator 60 via the bus 61 is sent to the information buffer 66 via the bus 23. Temporary storage, while the memory address on bus 61 is also sent to the information buffer tag unit 64 for temporary storage. Replacement logic selection 64 and 66 The corresponding entry in the file is for the above temporary storage. The permutation logic can select the entry that has the longest time to exist when the buffer 66 is full, according to the existence time of the entry. Thereafter processor 12 goes through bus 11 The sent memory address is first sent to 64 matches, and if there is a match, the corresponding entry in 66 is selected by selector 68 to be sent to processor 12 for execution and stored in the buffer in 12. If 12 The buffer is included, and the above-mentioned read list in the buffer 66 and the tag unit 64 can be marked as 'replaceable' at this time. If the memory address on bus 11 is in tag unit 64 If there is no match, the memory address is sent to the memory 10 to read the information block as previously described.

 The address generator 60 of this embodiment can operate in a variety of modes. For example, when the information buffer 66 When the content is smaller than a certain capacity, the address generator 60 performs scan analysis on all the information blocks on the bus, thereby generating an address access memory 10 accordingly. When the content of the information buffer 66 is greater than a certain capacity, The address generator 60 scans only the memory address sent by the processor 12 via the bus 11 and the information block output by the memory 10 based on the address; instead of the address generator 60 via the bus 61 The sent memory address and memory 10 are scanned and parsed based on the information block output from the address. In addition, there are other modes of operation, which will not be repeated here.

 [Embodiment 5] Please refer to FIG. 8 , which is a block diagram of a storage hierarchy system according to Embodiment 5 of the present invention. Of which 110 For the buffer tag unit (Tag Unit), 120 is the buffer memory (RAM), which together constitute a memory hierarchy of the processor; 118 is an additional address generator, 114 As a selector. 113 is the Memory Access Address, from the processor core or higher memory level (Memory Hierarchi Accessing this memory hierarchy; address 113 is sent to an input of selector 114, selected by selector 114, via bus 111 and tag unit 110 The tags stored in the comparison match. If the address on bus 113 is matched in tag unit 110, the corresponding information in memory 120 is routed via bus 123. Send to a higher memory level or processor core for use. If the access address 113 is not matched in the tag unit 110, the address is sent over the bus 111 to access the lower memory level, and the obtained information is routed through the bus. 121 The memory 120 stored in the memory hierarchy, the address on the bus 111 is also stored in the corresponding entry in the tag unit 110. At this time, the access address 113 is at the tag unit 110. A match is obtained, and the corresponding information is sent to a higher memory level or processor core via bus 123 for use. It is also possible to bypass the information on the bus 121 directly to the bus while storing it in the memory 120. On. The address generator 118 adds an increment 115 to the address based on the address on the bus 111 in increments of one block size to produce a predicted address (Predicted) Address) 119 is sent to the other input of selector 114. The arbiter control selector 114 not shown in the figure, if the access address 113 is valid, the arbiter selects the access address 113 The bus 111 is placed on the tag unit 110 for matching; if the access address 113 is invalid and the predicted address 119 is valid, the arbiter selects the predicted address 119 and puts it on the bus 111. It is sent to the tag unit 110 to match.

 If the predicted address 119 does not get a match in the tag unit, then the predicted address 119 is via bus 111. The access to the lower memory level is sent, and the obtained information is stored in the memory 120 of the memory level via the bus 121, and the address on the bus 111 is also stored in the corresponding entry in the tag unit 110. Bus at this time The information on 121 does not need to be bypassed onto bus 123. The address generator 118 thus cycles by incrementing the address of the bus 111 to generate a predicted address 119; as long as the address is accessed 113 Invalid, the arbiter controls the selector 114 to select the predicted address 119 to be sent to the tag unit 110 via the bus 111; as long as the predicted address and tag unit 110 The tags in the mismatch, the predicted address on the bus 111 is sent out to access the lower memory level, and the information is stored in the memory 120; the address generator 118 increments the address of the bus 111. 115 Generate predicted address 119. When the predicted address 119 matches the tag in the tag unit 110, the address generator 118 The subsequent operation based on the predicted address is terminated. That is, the address generator 118 of the present embodiment is triggered by the access address 113 that does not obtain a match in the tag unit 110, and the predicted address 119 is continuously generated. In order to access the lower memory hierarchy, the acquisition information fills the memory 120 of the present storage hierarchy until the predicted address is matched in the tag unit 110 of the present hierarchy. That is, the address and tag unit 110 The tag match in the control controls the operation of the address generator, the unmatched access address triggers the operation of the address generator 118, and the matched predicted address terminates the operation of the address generator 118.

 The address generator 118 in the fifth embodiment generates the predicted address 119 and the tag memory 110. The labels in the match will continue to operate. In some cases, an address generator is required 118 Terminating the operation if the predicted address still matches the tag, such as at the end of the program, the following three embodiments show three different termination methods.

 [Embodiment 6] Please refer to FIG. 9, which is a block diagram of a storage hierarchy system according to Embodiment 6 of the present invention. Of which 110 For the buffer tag unit, 120 is the buffer memory, 118 is the address generator, 113 is the access address, 119 is the predicted address, and 114 is 113 or 119 for the selector. 111 is the address bus selected by the selector 114, 121 is the information bus between the lower storage level and the current level, 123 is the information bus between the level and the higher storage level or the processor core, and the figure The same in 8 . The operation is similar to that of the fifth embodiment and will not be described again. The instruction decoder 122 is added in FIG. Access address from a higher storage tier or processor core 113 There is an accompanying signal indicating that the information to be obtained is an instruction or data. This signal is sent via bus 111 to address generator 118, which generates a predicted address 119. This signal is also maintained. Thus, based on this signal accompanying the predicted address on bus 111, it can be determined that the information block from the lower memory level via bus 121 is an instruction block or a data block. Instruction decoder 122 to bus The instruction in the instruction block on 121 is decoded. If the translation block has an indirect branch instruction in the above instruction block, the address generator 118 is caused. Termination generates a predicted address. Because the compiled program ends with an indirect branch instruction, prefetching of memory locations after the end of the program is avoided.

 [Embodiment 7] Please refer to FIG. 10, which is a block diagram of a storage hierarchy system according to Embodiment 7 of the present invention. Of which 110 For the buffer tag unit, 120 is the buffer memory, 118 is the address generator, 114 is the selector, 113 is the access address, 119 is the predicted address, and 111 is the selector. 114 The selected address bus, 121 is the information bus between the lower storage hierarchy and the current level, 123 is the information bus between the upper layer and the higher storage hierarchy or processor core, and Figure 8 Same in the middle. The operation is similar to that of the fifth embodiment and will not be described again. The counter 112 is added in Figure 10. Counter 112 is paired by address generator 118 according to bus 113 The predicted address generated by the upper access address 119 is assigned an initial count value of 'N'. Each time the address generator generates a new predicted address, the count value in counter 112 is decremented by '1'. When counter When the count value in 112 reaches '0', the address generator 118 is terminated, so that the number of prefetched information blocks does not exceed a preset maximum value. This prevents pre-fetching too many processor core branches from selecting non-executable instruction segments or unused data segments. It also prevents prefetching invalid information after the end of too many programs.

 [Embodiment 8] Please refer to FIG. 11, which is a block diagram of a storage hierarchy system according to Embodiment 8 of the present invention. Of which 110 For the buffer tag unit, 120 is the buffer memory, 118 is the address generator, 114 is the selector, 113 is the access address, 119 is the predicted address, and 111 is the selector. 114 The selected address bus, 121 is the information bus between the lower storage hierarchy and the current level, 123 is the information bus between the upper layer and the higher storage hierarchy or processor core, and Figure 8 Same in the middle. The operation is similar to that of the fifth embodiment and will not be described again. Comparator 116 is added in Figure 11. Comparator 116 will be based on bus 113 by address generator 118 The predicted address generated by the upper access address is compared with the address boundary stored in 116. If the predicted address 119 crosses the address boundary stored in the comparator 116, the address generator 118 is caused Terminate the operation so that the prefetched information block does not cross the address boundary. The address boundary can be the smallest memory interval allocated to the processor, such as a page (page) or a segment (segment) . This prevents prefetching beyond the memory range allocated by this thread. It is also possible to prevent prefetching too many processor cores from selecting non-executable instruction segments or unused data segments. The address boundary may be a pre-existing comparator 116 The program is written to a register in comparator 116.

 [Embodiment 9] Please refer to FIG. 12, which is a block diagram of a storage hierarchy system according to Embodiment 9 of the present invention. Of which 110 For the buffer tag unit, 120 is the buffer memory, 118 is the address generator, 114 is the selector, 113 is the access address, 119 is the predicted address, and 111 is the selector. 114 The selected address bus, 121 is the information bus between the lower storage hierarchy and the current level, 123 is the information bus between the upper layer and the higher storage hierarchy or processor core, and Figure 8 Same in the middle. The operation is similar to that of the fifth embodiment and will not be described again. The instruction decoder 122 of Fig. 9, the counter 112 of Fig. 10, and the comparator 116 of Fig. 11 are added to Fig. 12. . Some or all of the above devices may be selected as needed to terminate the operation of address generator 118. If all of the above devices are used, no matching valid access address is obtained in the tag unit 110. The trigger address generator 118 generates a predicted address 119, and the predicted address is sent over the bus 111 to access the lower memory level, and the information is filled in the memory 120. Address Generator 118 Continue to generate new forecast addresses 119 Until the predicted address matches the tag in the tag unit, or the predicted address crosses the preset memory address boundary, or the number of generated predicted addresses reaches a preset maximum value, or the obtained instruction block has an indirect branch instruction.

 [Embodiment 10] Please refer to FIG. 13, which is a block diagram of a storage hierarchy system according to Embodiment 10 of the present invention. Of which 110 For the buffer tag unit, 120 is the buffer memory, 114 is the selector, 113 is the access address, 119 is the predicted address, and 111 is the address bus selected by the selector 114. 121 is the information bus between the lower storage tier and the tier, 123 is the information bus between the tier and the higher storage tier or processor core, the above modules and bus and Figure 8 The modules with the same number are the same. A new scanner 128 is included, which includes the functions of the address generator 118, the counter 112, the comparator 116 in the fifth to fourth embodiments, and can scan through the bus 123. The transmitted information block generates a branch target initial address according to the branch instruction. Embodiment 10 can implement all the functions of Embodiment 9. The biggest difference between Embodiment 10 and Embodiment 9 and Embodiments 5 to 4 is that the address generator operation can be operated not only by a valid access address. 113 is triggered without a match in the tag unit; and a match trigger can be obtained in tag unit 110 by a valid access address 113.

 The above valid access address 113 The process of triggering the operation of the address generator and the address generator is the same as that in the fifth embodiment, and details are not described herein again. A valid access address 113 via bus 111 at tag unit 110 When a match is obtained, the corresponding block of information is read from the memory 120 and sent to the higher storage hierarchy or processor core via the bus 123, and the valid access address on the bus 111 is also sent to the scanner 128. . The address generator in the scanner continues to generate the predicted address based on the valid access address of the tag match in the tag unit described above, and terminates the generation of the predicted address in accordance with the conditions in Embodiments 5 through 4. Scanner 128 The address generator in the medium can add the increment to the block address (the upper address of the memory address, such as the tag and the index address) in the above effective address to obtain the initial predicted address of the next block of the order. Further, the scanner 128 It is also possible to decode each instruction in the instruction block on bus 123, for branch instructions therein, 128 The address generator in the branch obtains the branch target address as the initial predicted address by the branch instruction itself plus the branch offset in the branch instruction. The address generator then generates the sequential prediction address after the initial predicted address until the termination condition causes it to terminate generating the predicted address. Some memory tiers use buffer addresses to directly address memory. In this case, the block unit can be read by the cache block address (higher bits in the cache address, such as the road number and index address). The tag in 110 is merged with the index address and sent to the scanner 128 as the memory block address.

 [Embodiment 11] Please refer to FIG. 14 , which is A schematic diagram of a scanner structure of a storage hierarchy system according to Embodiment 11 of the present invention. The eleventh embodiment can complete the operation of sequentially lowering the block address as the initial predicted address. In Figure 14, 110 is the buffer label unit, 120 For the buffer memory, 114 is the selector, 122 is the instruction address decoder, 113 is the access address, 119 is the predicted address, and 111 is the address bus selected by the selector 114. 121 is the information bus between the lower storage level and the current level. The above modules and buses are the same as the modules of the same number in Figure 12. The scanner 128 is comprised of a register 130, an adder 132 The selector 134 constitutes an address generator having a function similar to that of the address generator 118 in the fifth embodiment; including a register 136, a subtractor 138, and a selector 140. The constructed counter is similar in function to the counter 112 in the seventh embodiment; it includes an address boundary comparator 116, and also includes a lossy stack composed of the storage units 146 and 148 (Loosy). Stack ).

 When the trigger condition described in Embodiment 10 is satisfied (i.e., when the access address 113 is valid), the selector 140 selects the preset maximum prefetch number' N ' 133 is sent to the subtractor 138 minus '1', the difference is stored in register 136; at the same time selector 134 selects the address on bus 111 to be sent to adder 132 and increment 115 The sum is added to the register 130. The output of 130 is the predicted address 119. In this case, the access address 113 is invalid, and the selector 114 selects the predicted address 119 via the bus 111. It is sent to the tag unit 110 to match. If the predicted addresses 119 match the tags in 110, the further operation of the address generator is terminated. If the predicted addresses 119 and 110 do not match the label, then the bus The address on 111 is sent to the lower memory level read information to be filled in memory 120; at the same time selector 140 selects output 137 of register 136 to be sent to subtractor 138 minus '1 ', the difference is stored in register 136; selector 134 selects the predicted address on bus 119 and sends it to adder 132 to add increment 115, which is stored in register 130. . This loop operates until the output of the subtractor 138 is '0'; or the predicted address 119 matches the tag in the tag unit 110, or the predicted address 119 crosses the boundary comparator 116. The preset boundary; or the instruction decoder 122 translates the indirect branch instruction.

 If the address generator is known during operation, the access address 113 will be valid, then the selector 114 still selects the predicted address during this clock cycle. 119 Put the bus 111 to the tag unit 110 to match. At the same time, the predicted address 119 is pushed into the memory 146 in the lossy stack, and the count on the bus 137 is pushed into the memory in the lossy stack. The same line. On the next clock cycle, the selector 114 selects a valid access address 113 and puts the bus 111 on the tag unit 110 for matching. If it does not match, as described earlier, scanner 128 The middle selector 134 selects the new access address on bus 111 and sends it to adder 132 to generate a predicted address based on the new access address; at the same time selector 140 selects the maximum number of prefetch blocks 133 to the subtractor 138 counts, starting prefetching based on the new access address. When the prefetch based on the new access address is terminated for any of the above reasons, the selector 134 selects the bus 131 from the memory 146 in the lossy stack. The predicted address at the top of the stack is sent to the adder 132 and added to the increment 115; at the same time, the selector 140 selects the bus 135 from the memory 148 in the lossy stack, and sends the count value of the top of the stack to the subtractor. 138 minus '1'; thus recovering the prefetch of the old access address that was interrupted. The use of the stack prefetches the most likely information needed by the processor core (current valid access address 113 Prefetching of subsequent information requesting an access request or prefetching of more likely information (the most recent valid access address 113 The address prefetched by the subsequent information requesting the access request has priority at or near the top of the stack. The lossy stack depth is limited. When the lossy stack is filled and continues to be pushed onto the stack, the entries at the bottom of the stack are discarded. This allows for the prefetching of information that the processor core uses at a lower probability in a short period of time (whose address may be at the bottom of the stack).

 In the embodiment of Figure 14, the scanner 128 can generate an order prediction address based on the access address, which is compared with Figure 12. The modules in the module are completely equivalent, and the scanner 128 can be applied to FIG. 12 instead of the address generator 118, the counter 112 and the boundary comparator 116 of FIG. Figure 14 A slight change to the embodiment allows branch target prefetching of branch instructions passed over bus 123.

 [Embodiment 12] Please refer to FIG. 15 , which is A schematic diagram of a scanner structure of a storage hierarchy system according to Embodiment 12 of the present invention. The twelfth embodiment can complete the operation of using the lower block address as the initial predicted address and the branch target address as the initial predicted address. Figure 15 110 For the buffer tag unit, 120 is the buffer memory, 114 is the selector, 122 is the instruction address decoder, 113 is the access address, 119 is the predicted address, and 111 is the selector. 114 The selected address bus, 121 is the information bus between the lower storage hierarchy and this level. The scanner 128 includes a register 130, an adder 133, and a selector 134. The address generator is configured to include a counter composed of a register 136, a subtractor 138, and a selector 140; an address boundary comparator 116 is included, and the memory unit 146 is further included. 148 constitutes a lossy stack (Loosy Stack). The above modules and buses are the same as the modules of the same number in Figure 14. With Figure 14 In addition, the information bus 123 between the level and the higher storage level or the processor core is added, and the instruction decoder 150 and the selector 152 are also added to the scanner 128. In order to support the operation of using the branch target address as the initial predicted address.

 Scanner in the embodiment 128 Generate two initial predicted addresses, sequential initial predicted addresses, or branch target initial predicted addresses. After the initial predicted address is generated, the next predicted address (i.e., the address of the next block of information in the order of addresses) is generated by increasing the increment on the current predicted address. Regardless of the access address in the tag unit If there is a match in 110, scanner 128 will increment by the access address on bus 111. The manner of generating a sequential initial predicted address and generating a subsequent predicted address at the initial predicted address of the sequence, prefetching information from the lower storage level into the memory 120 of the hierarchy, until the termination condition causes the scanner 128 The medium address generator terminates generating the predicted address. When the sequential address is the predicted address, the command decoder 150 in Fig. 15 controls the selector 152 to select the increment 115 to be sent to the adder 132. The operation of the input terminal is the same as that of the embodiment 7 and FIG. 14 and will not be described here.

 Only when the instruction access address on bus 111 matches in tag unit 110, memory 120 passes bus 123. The scanner 128 will generate the branch target initial predicted address when the corresponding instruction block is output. At this time, the instruction decoder 150 pairs the bus 123. The instruction in the above instruction block is decoded, and the branch target address is calculated for the direct branch instruction in the instruction. At this time, the instruction decoder 150 controls the selector 152 to select the bus 123. The branch offset in the branch instruction is sent to an input of the adder 132; and the intra-block address offset of the branch instruction in the instruction block is sent over the bus 154, and the bus 111 The source address of the upper block address synthesis branch instruction is sent to the other input of the adder 132. Adder 132 The branch instruction source address (source address) is added to the branch offset to output the branch destination address. The branch target address is registered by register 130 and is output as the branch target initial address 119. Access address at this time If 113 is invalid, the branch target initial address is selected by the selector 114 and sent to the tag unit 110 via the bus 111 for matching. If the branch target initial address and tag unit 110 If the tag in the match matches, then the branch target instruction is already in the memory 120, and no prefetching is required based on the branch target initial address. Therefore, the instruction decoder 150 can process the next direct branch instruction.

 If the branch target initial address does not match the tag in the tag unit 110, the selector 134 selects the branch target initial address 119. It is supplied to an input of the adder 132, at which time the command decoder 150 controls the selector 152 to select the increment 115 to be sent to the other input of the adder 132, so the adder 132 The output is the address of the next instruction block in the order of the branch target initial address. Please note that the matching of the tag unit 110 and the pair of memories 120 Access uses only the block address, the tag portion of the address and the index address, so the intra-block address offset on the predicted address 119 has no effect on the above match and addressing; however, the adder 132 When calculating the branch target initial address, the intra-block address offset of the branch instruction needs to be sent to the adder 132 via the bus 154 and the block address on the bus 111. The input end, otherwise the resulting branch target initial address may have errors and fall on the wrong instruction block. The operation thereafter is the same as that of the seventh embodiment and FIG. 14, and will not be described again.

According to the technical solution of the present invention, the methods and systems disclosed by the present invention can also be applied to memory hierarchies of different structures. Some cache systems use a buffer address to directly access the memory hierarchy. The buffer address does not have a label in the memory address, but the label has been mapped to a road number. Therefore, the buffer block address has only the road number and the index address. scanner 128. In conjunction with such a cache system, the tag unit 110 can be addressed with a buffer block address, from which the corresponding tag is read, and the tag is combined with the index address in the buffer block address to form a memory block address via the bus 111. Send to scanner 128 Used to generate a predicted address. The rest of the operations are the same as in the above-described eighth embodiment. The disclosed method and system are applicable to any memory hierarchy, and are particularly suitable for a memory hierarchy with a large memory capacity, such as the lowest level of memory hierarchy in the processor, and the last level cache ( Last Level Cache ).

There may be any other suitable modifications in accordance with the technical solutions and concepts of the present invention. All such substitutions, modifications and improvements are intended to be within the scope of the appended claims.

Industrial applicability

The system and method proposed by the present invention can be applied to various computing, data processing, and storage system related applications, which can improve efficiency, mask memory access latency, and cache miss.

Sequence table free content

Claims (26)

An information processing method for an information system, comprising: Step A: The address generator generates an address according to the information block and sends an address to the memory, where the information block is a current information block sent by the memory or an information block stored by the address generator; Step B: The memory outputs an information block according to the address sent by the address; Step C: The processor acquires and processes the information block of the memory output. The information processing method according to claim 1, wherein said address generator is capable of processing at least part of functions of said processor, The partial function includes at least a partial branch judging function. The information processing method according to claim 2, wherein said address generator generates an address by generating method one as follows: Generation Method 1 The address generator has at least a partial address generation function of the processor, and the address generator processes the information block to generate an address. The information processing method according to claim 3, wherein said address generator includes a buffer, said address generator filters the generated address, wherein the address provided to the memory is an address through which the filter passes. The address generator filters the generated address using the following method: It is judged whether the address generated by the method 1 is matched in the cache of the address generator, and if not, the generated address is filtered. The information processing method according to claim 4, wherein the processor includes a buffer, and the buffer in the processor is in the same manner as the buffer in the address generator. The information processing method according to claim 2, wherein: said address generator and all instructions in said processor that are less capable of being executed are referred to as valid instructions; The result refers to the execution result produced by the address generator or the processor executing the instruction; the result completely generated by the execution of the valid instruction is a valid result. The information processing method according to claim 6, wherein: If the branch judgment and the branch target address generated by the address generator are valid results, the address generator independently completes the branch operation; If the branch decision and/or the branch target address generated by the address generator is not a valid result, the address generator completes the branch operation based on the branch decision and/or the branch target address provided by the processor. The information processing method according to claim 6, wherein: if the result output by said address generator is a valid result, said valid result is written into said memory; If the result of the output by the address generator is not a valid result, the result is ignored, and the processor outputs a result corresponding to the non-effective result and writes to the memory. The information processing method according to claim 6, wherein: a valid flag is added to a register of said address generator and said processor; Adding an instruction valid flag to the address generator and the instruction decoder of the processor; the address generator and the processor detecting the validity of the instruction and the validity of the register valid flag of the operand when executing the instruction ; If the valid flag of any instruction or operand is 'invalid', the execution result of the instruction is 'invalid', and the 'invalid' value is written to the valid flag of the target register; If the valid flag of all instructions or operands is 'valid', the execution result of the instruction is 'valid', and the 'valid' value is written to the valid flag of the target register; The information processing method according to claim 1, wherein said address generator generates an address by generating method 2 as follows: The method 2 is generated by the address generator parsing the current information block. If it is determined that the current information block includes a branch instruction, the target address of the branch instruction is calculated, and an address is generated. The information processing method according to claim 10, wherein the address generator filters the generated address, wherein the address provided to the memory is an address that is filtered, and the address generator uses the following method to generate the address. Filter by address: It is determined whether the information block pointed to by the address generated by the method 2 is the current information block, and if not, the generated address is filtered. The information processing method according to claim 10, wherein said address generator further generates an address by generating method three as follows: The third method generates the address of the current information block, adds an offset to the address of the current information block, and generates an address. The information processing method according to claim 12, wherein said address generator filters the generated address, wherein the address provided to the memory is an address through which the filter passes, and the address generator uses the following method to generate the address Filter by address: Step 1: The address generated by the generating method 3 is determined to be an address that is filtered; Step 2: Determine whether the information block pointed by the address generated by the generating method 2 is the current information block or the information block pointed to by the address generated by the method 3, and if not, the address generated by the method 2 is filtered. The information processing method according to claim 10, wherein a second memory is added; At least one of the information blocks and their corresponding addresses are stored in the second memory. The information processing method according to claim 14, wherein an address generated by said address generator is stored in said second memory; The corresponding information block output by the memory according to the address generated by the address generator is stored in the second memory. The information processing method according to claim 14, wherein said processor sends an address to said information buffer to match an address stored therein; If there is a match, the information buffer outputs the corresponding information block of the matching address for the processor to acquire; if not, the memory outputs the information block according to the processor output address for the processor to acquire. A storage hierarchy prefetching system, comprising: a lower storage hierarchy for storing information and providing a block of information to a memory according to the received access address or predicted address; a memory for storing information and outputting a current information block according to the received access address; The address generator is configured to add an increment to the initial address or the predicted address, continuously generate the predicted address, filter the generated address, provide a predicted address for filtering to a lower storage level, and obtain corresponding information to fill the memory; When the address fails to pass the screening, the address generator terminates the operation; A higher storage level for providing an access address to the memory and receiving the current block of information output by the memory. The storage hierarchy prefetching system according to claim 17, wherein said address generator generates said initial address by generating method 1 as follows: Method 1: The address generator adds an increment to the access address to generate the initial address. The storage hierarchy prefetching system according to claim 17, wherein said address generator generates said initial address by generating method 2 as follows: The method 2 is generated by the address generator parsing the current information block. If it is determined that the current information block includes a branch instruction, the target address of the branch instruction is calculated, and the initial address is generated. A storage hierarchy prefetching system according to claim 17, wherein said address generator includes an address filter for filtering said predicted address generated by said address generator, said address filter utilizing the following screening The method filters the predicted addresses generated by a pair: Determining whether the corresponding information of the predicted address generated by the address generator is already in the memory, and if not, the generated predicted address is filtered. A storage hierarchy prefetching system according to claim 17, wherein said address generator includes an address filter for filtering said predicted address generated by said address generator, said address filter utilizing the following screening Method 2 filters the generated predicted address: Determining whether the predicted address generated by the address generator crosses a preset address boundary, and if not, the generated predicted address is filtered. A storage hierarchy prefetching system according to claim 17, wherein said address generator includes an address filter for filtering said predicted address generated by said address generator, said address filter utilizing the following screening Method 3 filters the generated predicted addresses: Determining whether the predicted address count continuously generated by the address generator according to an access address reaches a preset maximum value; if not, the generated predicted address is filtered. A storage hierarchy prefetching system according to claim 17, wherein said address generator includes an address filter for filtering said predicted address generated by said address generator, said address filter utilizing the following screening Method 4 filters the generated predicted addresses: Determining whether the information block obtained from the lower storage level according to the predicted address generated by the address generator includes an indirect branch instruction, and if not, the predicted address that is detected at that time passes the screening. The storage hierarchy prefetching system according to claim 17, wherein said prefetching schedules a prefetch priority according to a time point at which said access address accesses said memory, and said visitor address accessed later is accessed earlier than said access address. Address priority; abandon prefetch for earlier accesses that exceed a certain limit. A storage hierarchy prefetching method, comprising: Step A: The address generator continuously generates a predicted address according to the initial address; Step B: The address generator filters the generated predicted address. Step C: The filtered predicted address is sent to a lower storage level; Step D: outputting a block of information at a lower storage level; Step E: storing the information block in a memory; Step F: The address generator is not terminated by the filtered predicted address. The storage hierarchy prefetching method according to claim 25, wherein the address generator performs screening by using the predicted address generated by a pair of screening methods as follows: Determining whether the corresponding information of the predicted address generated by the address generator is already in the memory, and if not, the generated predicted address is filtered.