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WO2016039767A1 - Attribution de taux d'erreur à une mémoire - Google Patents

Attribution de taux d'erreur à une mémoire Download PDF

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Publication number
WO2016039767A1
WO2016039767A1 PCT/US2014/055360 US2014055360W WO2016039767A1 WO 2016039767 A1 WO2016039767 A1 WO 2016039767A1 US 2014055360 W US2014055360 W US 2014055360W WO 2016039767 A1 WO2016039767 A1 WO 2016039767A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
error rate
voltage
range
error rates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2014/055360
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English (en)
Inventor
Anys Bacha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Enterprise Development LP
Original Assignee
Hewlett Packard Enterprise Development LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Enterprise Development LP filed Critical Hewlett Packard Enterprise Development LP
Priority to PCT/US2014/055360 priority Critical patent/WO2016039767A1/fr
Publication of WO2016039767A1 publication Critical patent/WO2016039767A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

Definitions

  • Computers include a wide variety of components.
  • most computing devices include a processor, volatile memory, such as dynamic random access memory (DRAM), disk drives, input / output controllers, host bus adaptors, network interface controllers, and any number of other components.
  • volatile memory such as dynamic random access memory (DRAM)
  • disk drives volatile memory
  • input / output controllers such as disk drives
  • host bus adaptors such as network interface controllers
  • network interface controllers such as Ethernet drives, and any number of other components.
  • One thing a large number of these components have in common is the need to be supplied with power to operate. Almost ail components may specify a minimum operating voltage and/or current in order to ensure error free operation of the component.
  • FIG. 1 depicts an example system that may utilize the assigning error rate to memory techniques described herein.
  • FIG. 2 depicts an example computing device that may utilize the memory error rate assignment techniques described herein.
  • FIG. 3 depicts another exampie computing device that may utilize the memory error rate assignment techniques described herein.
  • FIG. 4 depicts an exampie of a flow diagram for assigning error rates to memory according to techniques described herein.
  • P'G- 5 depicts another exampie of a flow diagram for assigning error rates to memory according to techniques described herein.
  • Power usage by computing devices is one of the larger expenses incurred by operators of computer data centers. Not only do the computers use power to operate, the operation of the computers produces heat. Because the heat may damage the computing systems, additional power may be used to operate equipment, such as liquid and air cooling systems, to dissipate the heat generated by the computers. As such, reducing the power used by a computing system may help to reduce the overall expense of running a data center;
  • the memory system of a computer is provided by dynamic random access memory ⁇ DRAM ⁇ or static random access memory (SRAM).
  • DRAM ⁇ dynamic random access memory
  • SRAM static random access memory
  • these two types of memory have different physical and operating characteristics, they both share the common feature that in order to ensure accurate storage of data, a certain voltage level should be supplied to the memory.
  • this voltage level is referred to as the nominal voltage.
  • the memory device provider may specify that so long as at least the specified nominal voltage is supplied to the memory device, the memory device will not introduce any errors based on insufficient voltage.
  • the nominal voltage to the memory device may ensure that no errors are generated by the device, it is not necessarily true that providing less than the nominal voltage to the memory device will result in the memory device introducing errors.
  • the semiconductor manufacturing process used in creating memory devices may be a variable process meaning that every memory device may have slightly different operating characteristics. For example, the operating characteristics of devices produced from different dies on the same semiconductor wafer may have slightly different nominal voltages due to natural variations in the manufacturing process. Manufacturers may specify a nominal voltage that ensures proper operation, but it is quite possible that the device would still not introduce errors at a lower voltage (although such operation would not be ensured by the device manufacturer). [00103 Although not explicitly mentioned above, an assumption is often made in the design of computing systems, and their memory systems in particular, that al!
  • social media As a more concrete example of cases wherein errors in data may be acceptable, consider one large use of large computing data centers: social media.
  • FacebookTM is the dominant social media platform. Although there may be some important information conveyed via FacebookTM, large portions of the data include trivia! items.
  • One use of social media is posting photographs on a social media site and receiving comments on those photographs.
  • An example of an especially trivial use of sociai media is a current trend wherein users order a meai at a restaurant, photograph the meal, and then post the photograph to social media sites, where other users may then comment on the photograph.
  • absoiute data integrity may not be necessary.
  • people may comment, or provide other text.
  • errors such as errors introduced due to voltage less than the nominal voltage being supplied, those errors may manifest themselves as alterations to the text.
  • the errors may appear as typographical errors.
  • the human mind is adept at understanding text, even when typographical errors are included, thus the errors may not significant!y alter the conveyance of information, in the case of a photograph, errors in the memory storing the photograph may manifest as color changes, or portions of the photograph being distorted.
  • the image depicted by the photograph may still be ascertainable by a viewer.
  • ⁇ yen when there are errors introduced by the memory storing text or a photograph, the information conveyed may still be understood. Errors introduced by memory may not be fatal, as the data can still be understood.
  • the techniques described herein provide for the ability of a computer system to reduce overall power usage by providing a mechanism to selectively provide less than the nominal voltage to portions of the memory subsystem.
  • the memory may be periodically characterized to determine the error rate introduced by the memory at voltage levels less than the nominal voltage.
  • the operating system of the computer may configure different portions of memory to operate at different voltage levels, thus effectively assigning different error rates to the different portions of memory.
  • the operating system may then store data according to the level of tolerance of errors. Data that cannot tolerate errors may be stored by memory receiving nominal voltage, while data that is more tolerant of errors may be stored in memory receiving less than nominal voltage.
  • FIG. 1 depicts an example system that may utilize the assigning error rate to memory techniques described herein.
  • System 100 may include a processor 110, a memory 120, a voltage source 130, and a non-volatiie memory 150.
  • the processor may be of any type suitable for use in a computer.
  • the processor may be a single or mu!ticore processor. The techniques described herein are not dependent on any particular type of processor.
  • the system may also include memory 120 coupled to the processor.
  • memory may include DRAM and SRAM.
  • the techniques described herein are not limited to those types of memory.
  • the memory may have a nominal voltage which may be specified by the memory manufacturer, if the memory is provided with the nominal voltage, the memory manufacturer may provide guarantees that no errors wiii be introduced due to insufficient mousseage. As mentioned above, providing less than the nominal voltage may allow the memory to function, but the manufacturer may no longer guarantee that errors due to insufficientturiage wit! not be introduced.
  • the system may also include a voltage source 130.
  • the mousseage source may be coupled to the memory 120.
  • the voltage source may be a variable voltage source that is able to supply the nominal voltage to the memory as well as a reduced voltage.
  • the reducedismeage may be referred to as a margined voltage.
  • the margineddronage may be a reduced percentage of the nominal voltage.
  • the processor 110 may be coupled to the mousseage source 130 and may determine what voltage level wiil be supplied to the memory 120.
  • the system may aiso include a non-volatile memory 150.
  • the non-volatiie memory may be used to store operating characteristics of the memory 120 when the memory is operating at different voltage ievels.
  • the non-volatile memory may store an expected error rate of the memory for a plurality of possible Kunststoffage levels, including both the nominal as well as a plurality of margined voltage ievels. The process of obtaining the operating characteristics of the memory is described in further detail below.
  • [0020] fn operation ⁇ the system 100 may be initialized
  • the processor 110 may determine that memory 120 does not need to be supplied the nominal sculpture.
  • the processor may determine that system 100 can toierate a certain error rate introduced by the memory.
  • the processor may access non-volatile memory 150 to retrieve the sculpture level that results in a memory introduced error rate that is acceptable.
  • the processor may configure the voltage source 130 to supply the memory with the voltage levei retrieved form the non-volatile memory.
  • FIG. 2 depicts an example computing device that may utilize the memory error rate assignment techniques described herein.
  • Device 200 may include a processor 210, memory 220- ⁇ a-c), a drownage source 230, non- transitory processor readable medium 240, and non-vo!atiie memory 250.
  • the processor 210, and non-volatile memory 250 are substantially the same as processor 110 and non-volatile memory 150 described above in FIG. 1. For clarity, the description of the processor and the non-volatile memory are not repeated here.
  • the memory 220 ⁇ a ⁇ c) may be provided in different forms.
  • the memory may be in the form of dual inline memory modules (DIMM)s.
  • DIMM dual inline memory modules
  • Each DIMM may contain one or more memory elements, such as memory chips.
  • the memory as a whole may be thought of as a range of physical addresses. For example, expressed in hexadecimal notation, the memory range of the device shown In FiG. 2 may be from 0x0000 to OxFFFF.
  • Each address may represent a storage location of an individuai byte of data. This range of addresses may be referred to as the physically addressable memory range.
  • a specific address range and number of memory blocks are shown, it shouid be understood that this is for purposes of description. The techniques described herein are not dependent on any particular form or layout of memory elements.
  • memory operations are performed on multiple bytes of data at a time. These multiple bytes of data may be referred to as a cache line.
  • a cache line For example, in a system operating with S byte cache lines, instead of manipulating an individual byte of data referenced by an address, an 8 byte cache fine containing the address of interest may be manipulated.
  • Devices exist with different size cache tines, and in some cases the cache line size may be 1 , which is essentially the same as manipulating individual byte sized data. The techniques described herein are not dependent on any particular size of cache line.
  • the memory 220-(a-c) may provide memory elements that make up the physicai!y addressable memory range.
  • memory 22G ⁇ a may provide the memory elements that store physically addressable memory range 0x0000 - OxOFFF
  • memory 220-b may provide the memory elements that store physically addressable memory range 0x000TM 0x3FFF
  • memory 220-c may provide the memory elements that store physically addressable memory range 0x4000 - OxFFFF.
  • a physically addressable memory range refers to a range of memory for which the error rate may be assigned by adjusting the voltage supplied to the memory elements.
  • memory 220-a provides memory elements to store physical addresses OxOOOO-OxOFFF.
  • the actual components, such as individual chips that make up the memory are unimportant What should be understood is that a range of physically addressable memory addresses is a range of addresses for which the supply voltage can be changed In order to produce the desired error rate.
  • the granularity of the memories 220 ⁇ (a-c) may be different As shown in FIG. 2, memory 220-a is 0x1000 bytes long, memory 220-b is 0x3000 byte long, while memory 220-c is OxCOQG bytes long.
  • the granularity of memory determines the ability to assign different error rates. For example, because memory 220-a encompasses the physically addressable memory range from 0x0000 to OxOFFF, ail of those addresses will have the same assigned error rate.
  • Device 200 may also include a voltage source 230.
  • Voltage source 230 may provide voltage needed for the operation of memory 220- ⁇ a-c).
  • the voltage source may provide both a nominal voltage 225 as well as a margined voltage 226.
  • the margined voltage may be a voltage that is less than the nominal voltage.
  • the rate of errors introduced may be characterized and stored, as will be described below.
  • the device 200 is shown with power supply 230 supplying the nominal sculptureage and 1 margined voltage 226.
  • the device 200 may also include a non-transitory processor readable medium 240 containing a set of instructions thereon. These instructions, which when executed by the processor, may cause the processor to implement the techniques described herein.
  • the instructions may include operating system instructions 241 to implement an operating system on device 200.
  • the instructions may also include available memory and capabilities instructions 242 to provide an interface for the device to iearn of the memory available within the device as we!i as the error rates associated with that memory.
  • the instructions may also include error rate assignment instructions 243, through which the device may assign error rates to the available memory.
  • the instructions may also include compassion setting
  • the device may begin a startup procedure.
  • the device may provide the operating system, provided by the operating system instructions 241, with an interface to determine the physically addressable memory ranges within the device, as well as the granularity of those ranges.
  • the interface may be based on the Advanced Control and Power Interface (ACPI) sandwichDSM definition.
  • ACPI Advanced Control and Power Interface
  • the operating system may receive an indication of the physically addressable memory ranges in the system, the granularity of those ranges, and the error rates that can be assigned to those systems.
  • the data used to provide this information may have been previously stored in the non-volatile memory. Storing the information in the non-voiatHe memory will be described below, but for now it may be assumed that the available memory and capacities have aiready been stored in the non-volatile memory.
  • the operating system may then determine which error rate is to be assigned to each physically addressable memory range. For example, using the error rate assignment instructions 243, the operating system may determine that 0x3000 bytes of data may need to be stored in memory that is ensured to not introduce errors, while it would be acceptable for the remainder of the memory to introduce errors. As such, the operating system may determine that memory range 0x10G0 ⁇ 0x3FFF (which is 0x3000 bytes iong), provided by memory 220-b, should be connected to the nominal voltage 225, The remainder of the memory 220 ⁇ a,c which can tolerate errors should be connected to the margined voltage 226.
  • memory range 0x10G0 ⁇ 0x3FFF which is 0x3000 bytes iong
  • the device may configure the voltage source 230 to set the margined voltage level and to provide either the margined or nominal voltage level to each memory.
  • the device may connect memory 220-b to the nominal voltage 225 to ensure no memory introduced errors.
  • the device may also determine an acceptable memory introduced error rate and the margined voltage that is associated with that rate.
  • the device may then set the voltage source to produce the determined margined voltage 226 and connect that margined voltage to memory 220-a,c.
  • FIG. 3 depicts another example computing device that may utilize the memory error rate assignment techniques described herein.
  • the processor 210, memory 220-ia-c), margined and nominal voltage 225, 226, voltage source 230, non-transitory medium 240 (including instructions 241-244), and non-voiatiie memory 250 are substantially the same as processor 310, memory 320-(a ⁇ c), margined and nominal voltage 325, 326, voltage source 330, non-transitory medium 340 (including instructions 341-344), and non- voiatiie memory 350.
  • the descriptions of those elements are not repeated here.
  • the non-transitory medium 340 may also include error rate characterization instructions 345.
  • the error rate characterization instructions may be used by the device to determine the error rates for the memory, given various operating voltages, in one exampie implementation, the error rates of memory may be determined by setting the voltage supplied to the memory, and then repeatedly running a diagnostic test on that memory. The diagnostic test may exercise the memory by repeatedly reading to and writing from the memory. The testing may determine the rate of errors introduced by the memory for each given level of supplied voltage.
  • the error rate summary / store instructions 346 may be used to summarize and store the error rate characterization information.
  • the characterization information may be stored in the non-volatile memory 350 as an error rate table 350-a.
  • the table may indicate for each possible memory range, and for each possible voltage level, an expected error rate. The expected error rate may have been determined from the error rate
  • the error rate characterization instructions may only run periodically. In the short term, it is not expected that given a specific margined voltage, that the error rate would vary widely. Thus tt may not be necessary to characterize the memory upon every system restart. For example, the characterization may be done upon every 10* 100 ,h , or 1000 th restart of the system. In other implementations, the characterization may be done oh a system restart if the time since the last characterization exceeds a threshold (e.g. last characterization was greater than ? days ago). By periodically performing the characterization, the average delay in system startup may be reduced, as the characterization is not performed on every startup.
  • a threshold e.g. last characterization was greater than ? days ago
  • the system 300 may start and it may be determined that the memory should be characterized. The system may then set the voltage level for each memory device to the nominal voltage and run through a series of diagnostic tests to ensure that no errors are introduced, in some
  • this step may be omitted, as it may be assumed that memory operating at the nominal voltage will not introduce errors.
  • all address ranges indicate 0 bits / line as the expected error rate.
  • the process of characterization may continue by setting each range of physically addressable memory to a margined distrage level (depicted here as V1 , V2, and V3) and running the diagnostic tests. For each range of memory addresses, for each tested margined voltage, an error rate may be determined. The error rate may be stored in table 35G-a r It should be noted that table 350-a depicts the error rate as bits / line (cache line). However, the techniques described herein are not dependent on any specific unit of measurement. The error rate couid be specified as a probability of error, an expected error rate per 1000 bytes, or any other suitable form. What should be understood is that the error rate may be used by the operating system to when determining which error rates to assign to which ranges of memory, and where to store those ranges of memory.
  • FiG. 4 depicts an example of a flow diagram for assigning error rates to memory according to techniques described herein.
  • the biocks described in FIG. 4 may be executed by a system such as the system depicted in FIG.. 3.
  • the medium 240 may contain instructions that when executed by the processor 210 cause the processor to implement the blocks described below.
  • an indication of physicaliy addressable memory in a system may be receivsid.
  • the indication may include avaiiable error rates and a range of granularity for assigning error rates to the ranges of physicaliy addressable memory.
  • an indication of the available memory in a system may be received by the operating system of a computer.
  • the indication may include information to notify the operating system about various ranges of memory that may be configured with different error rates. As explained above, this may be referred to as the granularity of assignment of error rates.
  • error rates may be assigned to each range of the physicaliy addressable memory.
  • the granularity of the addressable memory ranges may determine the address ranges that may be assigned different error rates.
  • error rates may be determined based on the voltage supplied to the memory elements comprising the address range.
  • each memory range may be supplied with either the nominal voltage or a margined voltage. Memory supplied with the margined voltage may introduce errors, as was described above.
  • FIG. 5 depicts another example of a flow diagram for assigning error rates to memory according to techniques described herein.
  • the blocks described in FIG. 5 may be executed by a system such as the system depicted in FIG. 3.
  • the medium 240 may contain instructions that when executed by the processor 210 cause the processor to implement the blocks described below.
  • the voltage supplied to memory elements making up the physically addressable memory may be set.
  • diagnostic tests may be run on the memory to determine the error rate of the memory elements
  • the error rate for the memory elements may be stored.
  • the dotted outline depicted as reference numeral 508 indicates that this process may be an iterative process.
  • the voltage may be set to the nominal voltage and blocks 502, 504, and 506 executed to determine the error rate of the memory.
  • the voltage may then be reduced, and the blocks re-executed to determine the error rate at the reduced voltage. This process may continue for a plurality of different voltage levels.
  • the end result may be a table, such as table 350-a which indicates the expected error rate for each range of memory addresses, given a specified voltage.
  • the table may be referred to as th£ memory characterization table.
  • the process of characterizing the memory may occur periodically. For example, the characterization process may occur on every 10 3 ⁇ 4 system restart. As another example, the characterization process may occur one the first system restart of any given month. The particular period for characterizing the memory Is unimportant. What should be understood is that the memory need not be characterized on every system restart.
  • an indication of physically addressable memory in a system may be received.
  • the indication may include available error rates and a range of granularity for assigning error rates to the ranges of physically addressable memory.
  • error rates may be assigned to each range of the physically addressable memory, wherein assigning error rates to each range of the physically addressable memory further comprises setting a voltage level supplied to memory elements providing storage for the range of physically addressable memory, wherein the buffaloage level determines the error rate for the range of physically addressable memory.
  • ranges of memory may be provided by one or more memory elements (e g. individual memory chips ⁇ . The particular arrangement of the chips may determine the memory address ranges that can be assigned different error rates, in block 515, each range of physically addressable memory may be assigned an error rate by setting the voltage supplied to the memory elements that are used to supply storage for that range of physically addressable memory.
  • a request for the error rate of a particular range of physically addressable memory may be received.
  • the system may provide an interface that allows the system to determine the current operating characteristics of a particular range of memory, in block 525, the error rate for the particular range of physically addressable memory may be provided.
  • block 525 may be the response to the request from block 520.
  • the error rate of a candidate range of memory is inappropriate for data to be stored in the candidate range of memory.
  • a range of memory may be assigned to an error rate specified by the nominal voltage (e.g. no errors introduced by insufficient voltage). This error rate may be inappropriate for trivial data, as there is no need to waste the power used by providing nominal voltage to the memory range.
  • the error rate may be greater than that provided by the nominaldronage, and as such the error rate may be
  • an acceptable error rate for a data element may be determined, in other words, it may be determined if a data element can or cannot toierate errors.
  • an appropriate error rate may be assigned to the candidate range of memory prior to storing the data element.
  • the system may be able to reassign the error rate for the range of memory. This reassignment may occur by altering the sculptureage supplied to the memory. Furthermore, the reassignment may occur dynamically while the system is stiii running.
  • the data eierriertt may be stored in the range of physically addressable memory having an appropriately assigned error rate.

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Abstract

La présente invention concerne des techniques pour attribuer des taux d'erreur à une mémoire. Selon un aspect, une indication d'une mémoire physiquement adressable dans un système est reçue. L'indication peut comprendre des taux d'erreur disponibles et une granularité de plages pour attribuer des taux d'erreur à des plages de la mémoire physiquement adressable. Des taux d'erreur peuvent être attribués à chaque plage de la mémoire physiquement adressable.
PCT/US2014/055360 2014-09-12 2014-09-12 Attribution de taux d'erreur à une mémoire Ceased WO2016039767A1 (fr)

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Application Number Priority Date Filing Date Title
PCT/US2014/055360 WO2016039767A1 (fr) 2014-09-12 2014-09-12 Attribution de taux d'erreur à une mémoire

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Application Number Priority Date Filing Date Title
PCT/US2014/055360 WO2016039767A1 (fr) 2014-09-12 2014-09-12 Attribution de taux d'erreur à une mémoire

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WO2016039767A1 true WO2016039767A1 (fr) 2016-03-17

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070022360A1 (en) * 2005-06-30 2007-01-25 Nivruti Rai Method and apparatus to lower operating voltages for memory arrays using error correcting codes
US20140026003A1 (en) * 2012-07-23 2014-01-23 Zhengang Chen Flash memory read error rate reduction
US20140043903A1 (en) * 2012-08-07 2014-02-13 Samsung Electronics Co., Ltd. Memory device having variable read voltage and related methods of operation
US20140101519A1 (en) * 2012-10-08 2014-04-10 Samsung Electronics Co., Ltd. Non-volatile memory device having adjustable read voltage, memory system comprising same, and method of operating same
US20140195733A1 (en) * 2012-08-17 2014-07-10 Andrew C. Russell Memory Using Voltage to Improve Reliability for Certain Data Types

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070022360A1 (en) * 2005-06-30 2007-01-25 Nivruti Rai Method and apparatus to lower operating voltages for memory arrays using error correcting codes
US20140026003A1 (en) * 2012-07-23 2014-01-23 Zhengang Chen Flash memory read error rate reduction
US20140043903A1 (en) * 2012-08-07 2014-02-13 Samsung Electronics Co., Ltd. Memory device having variable read voltage and related methods of operation
US20140195733A1 (en) * 2012-08-17 2014-07-10 Andrew C. Russell Memory Using Voltage to Improve Reliability for Certain Data Types
US20140101519A1 (en) * 2012-10-08 2014-04-10 Samsung Electronics Co., Ltd. Non-volatile memory device having adjustable read voltage, memory system comprising same, and method of operating same

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