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WO2016032194A1 - Light emitting diode - Google Patents

Light emitting diode Download PDF

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Publication number
WO2016032194A1
WO2016032194A1 PCT/KR2015/008841 KR2015008841W WO2016032194A1 WO 2016032194 A1 WO2016032194 A1 WO 2016032194A1 KR 2015008841 W KR2015008841 W KR 2015008841W WO 2016032194 A1 WO2016032194 A1 WO 2016032194A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
bonding pad
light emitting
semiconductor layer
emitting device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2015/008841
Other languages
French (fr)
Korean (ko)
Inventor
이소라
채종현
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seoul Viosys Co Ltd
Original Assignee
Seoul Viosys Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020140194260A external-priority patent/KR20160027875A/en
Priority to CN201580045770.0A priority Critical patent/CN106605306B/en
Priority to DE112015003963.5T priority patent/DE112015003963T5/en
Priority to JP2017510623A priority patent/JP6757313B2/en
Application filed by Seoul Viosys Co Ltd filed Critical Seoul Viosys Co Ltd
Publication of WO2016032194A1 publication Critical patent/WO2016032194A1/en
Priority to US15/140,155 priority patent/US9768367B2/en
Anticipated expiration legal-status Critical
Priority to US15/667,599 priority patent/US10069055B2/en
Priority to US15/942,510 priority patent/US10090450B2/en
Priority to US15/965,808 priority patent/US10211383B2/en
Priority to US15/995,014 priority patent/US10205077B2/en
Priority to US16/024,423 priority patent/US10276769B2/en
Ceased legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/83Electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/85Packages
    • H10H20/857Interconnections, e.g. lead-frames, bond wires or solder balls

Definitions

  • the present invention relates to a light emitting device, and more particularly, to a light emitting device having a bonding pad shape capable of minimizing voids generated during soldering in a light emitting device in which a bonding pad is soldered onto a mounting substrate.
  • the device In order to obtain a high output light emitting device, the device must be manufactured in consideration of factors such as increasing luminous efficiency, miniaturizing a package, and lowering thermal resistance. In order to satisfy the above conditions, a flip chip type light emitting device is widely used at present.
  • the flip chip method refers to a chip bonding method using solder bumps. Since the bonding length is almost smaller than that of the conventional wire bonding method, the inductance due to the bonding can be reduced to 1/10 or less, thus According to the method, the chip package can be integrated.
  • the flip chip method in the flip chip method, light is emitted toward the substrate to eliminate light loss from the electrode pad, and by depositing a reflective film on the p-layer, the extraction efficiency can be improved by changing the path of the photons traveling toward the mounting substrate in the opposite direction. have.
  • the flip-chip approach also improves current spreading, providing a low forward voltage.
  • a solder bump is melted by applying a high temperature heat source to electrically connect the bonding pads of the chip and the mounting substrate.
  • the process of melting the solder bumps is called reflow.
  • Voids are the biggest cause of weakening the heat dissipation function and deterioration of the reliability of the light emitting device due to poor bonding between the bonding pad of the chip and the mounting substrate.
  • Korean Patent Publication No. 10-2013-0030178 discloses a large area light emitting device employing a flip chip method.
  • An object of the present invention is to provide a light emitting device having a bonding pad shape in which a bonding pad is soldered on a mounting substrate, thereby minimizing void generation occurring during the soldering process.
  • Another object of the present invention is to provide a light emitting device in which defects that may occur in the soldering process are minimized.
  • a bonding pad is soldered onto a mounting substrate, and the bonding pad is electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer by a connection electrode, respectively.
  • Two or more linear bonding pads are connected to the first electrode and the second electrode and have a solder ball contact area, and at least two of the two or more linear bonding pads face each other and face each other. The non-conductive region is present between the two bonding pads.
  • the light emitting device is a bonding pad is soldered on a mounting substrate, and the bonding pad is electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer by a connecting electrode, respectively.
  • the first and second electrodes may be connected to each other, and a bonding pad may be formed in a portion of the solder ball contactable area, and a non-conductive pattern for void escape may be formed in the remaining area of the solder ball contactable area.
  • the voids generated during the soldering process are minimized because a large void is not formed or the bonding pad shape can be easily escaped without being trapped in the bonding pad. Can be improved.
  • the reliability of the light emitting device can be improved by covering the portion of the first electrode positioned on the portion where the first electrode and the first conductive semiconductor layer of the light emitting device are in contact with the bonding pad.
  • 1A is a plan view of a light emitting device having a bonding pad shape according to an embodiment of the present invention.
  • FIG. 1B is a cross-sectional view when the light emitting device of FIG. 1A is cut in the A'-A direction.
  • FIGS. 2 to 6 and 8 are plan views of a light emitting device including an electrode shape according to various embodiments of the present disclosure.
  • FIG. 7A is a cross-sectional view when the light emitting device of FIG. 3 is cut in the direction of BB '.
  • FIG. 7A is a cross-sectional view when the light emitting device of FIG. 3 is cut in the direction of BB '.
  • FIG. 7B is a cross-sectional view when the light emitting device of FIG. 3 is cut in the direction C-C '.
  • FIG. 7B is a cross-sectional view when the light emitting device of FIG. 3 is cut in the direction C-C '.
  • 9 to 14 are plan views and cross-sectional views for describing a light emitting device according to another embodiment of the present invention.
  • 15 and 16 are plan views illustrating light emitting devices according to another exemplary embodiment of the present invention.
  • FIG. 17 is an exploded perspective view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a lighting device.
  • FIG. 18 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a display device.
  • 19 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a display device.
  • FIG. 20 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a head lamp.
  • FIG. 1A is a plan view of a light emitting device having a bonding pad shape according to an embodiment of the present invention
  • FIG. 1B is a cross-sectional view when the light emitting device of FIG. 1A is cut in the A'-A direction.
  • the light emitting device including the electrode shape of the present invention may be formed on the substrate 101 such that the active layer 112 is interposed between the n-type semiconductor layer 111 and the p-type semiconductor layer 113.
  • the first conductive semiconductor layer 111, the active layer 112, and the second conductive semiconductor layer 113 are formed.
  • the substrate 101 may be selected from a known material such as Al 2 O 3 , SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, or the like.
  • Concave-convex patterns may be formed on and / or under the substrate 101, and the concave-convex pattern may be freely selected, such as a stripe shape, a lens shape, a pillar shape, or a horn shape.
  • the first conductivity type semiconductor layer 111 is a semiconductor layer doped with the first conductivity type dopant.
  • the first conductive semiconductor layer 111 may be formed of at least one of GaN, InN, AlN, InGaN, AlGaN, and InAlGaN, and the first conductive semiconductor layer 111 may be an n-type semiconductor layer.
  • the single-conducting dopant may include at least one of Si, Ge, Sn, Se, and Te, which are n-type dopants.
  • the active layer 112 may be formed in a single quantum well or multiple quantum well (MQW) structure. That is, at least one of GaN, InN, AlN, InGaN, AlGaN, and InAlGaN may be formed using a Group III-V compound semiconductor material.
  • the active layer 112 may have a structure in which InGaN well layers / GaN barrier layers are alternately formed. The active layer 112 generates light while the carrier supplied from the first conductive semiconductor layer 111 and the carrier supplied from the second conductive semiconductor layer 113 are recombined.
  • the carrier supplied from the first conductivity-type semiconductor layer 111 may be electrons, and the second conductivity-type semiconductor layer 113 may be p-type. In the case of the semiconductor layer, the carrier supplied from the second conductivity type semiconductor layer 113 may be a hole.
  • the second conductivity type semiconductor layer 113 may include a semiconductor layer doped with the second conductivity type dopant and may be formed in a single layer or multiple layers.
  • the second conductive semiconductor layer 113 may be formed of at least one of GaN, InN, AlN, InGaN, AlGaN, and InAlGaN, and when the second conductive semiconductor layer 113 is a p-type semiconductor layer, the second The conductive dopant may include one or more of p-type dopants, Mg, Zn, Ca, Sr, and Ba.
  • the light emitting device according to the present invention may include an undoped layer or other buffer layer to improve crystal quality.
  • the second conductive semiconductor layer 113 is a p-type semiconductor layer
  • various functional layers such as an electron blocking layer (not shown) formed between the active layer 112 and the second conductive semiconductor layer 113 may be used. May be included.
  • the nitride based semiconductor stack 110 may include an exposed region e partially exposing the first conductive semiconductor layer 111, and the first conductive semiconductor layer 111 may be exposed through the exposed region e.
  • the first electrode 140 may be electrically connected.
  • the current dispersion efficiency and the light emission pattern of the light emitting device may be adjusted according to the position, shape, and number of the exposed regions e.
  • the exposed area e may be formed using photo and etching techniques.
  • the exposed area e may be formed using photo and etching techniques.
  • an exposed region e may be formed by defining an etching region using a photoresist and etching the second conductive semiconductor layer 113 and the active layer 112 using dry etching such as ICP. .
  • FIG. 1B illustrates an example in which the exposed region e is formed in a hole shape penetrating through the active layer 112 and the second conductive semiconductor layer 113.
  • the first conductive semiconductor layer 111 and the first electrode 140 are electrically connected through the hole. Holes may be formed regularly as shown, but the present invention is not limited thereto.
  • the current dispersion efficiency and the light emission pattern of the light emitting device may be adjusted according to the position, shape, and number of holes.
  • the second electrode 120 is positioned on the second conductive semiconductor layer 113 and may be electrically connected to the second conductive semiconductor layer 113.
  • the second electrode 120 may include the reflective metal layer 121, and further include the barrier metal layer 122, and the barrier metal layer 122 may cover the top and side surfaces of the reflective metal layer 121.
  • the barrier metal layer 122 may be formed to cover the top and side surfaces of the reflective metal layer 121.
  • the reflective metal layer 121 may be formed by depositing and patterning an Ag, Ag alloy, Ni / Ag, NiZn / Ag, or TiO / Ag layer.
  • the barrier metal layer 122 may be formed of Ni, Cr, Ti, Pt, or a composite layer thereof to prevent the metal material of the reflective metal layer 121 from being diffused or contaminated.
  • the second electrode 120 may include indium tin oxide (ITO), zinc oxide (ZnO), or the like. Since ITO or ZnO is made of a metal oxide having a high light transmittance, light absorption by the second electrode 120 may be suppressed to improve luminous efficiency.
  • the first electrode 140 may include a first conductive semiconductor layer 111. Can be electrically connected to. The first electrode 140 may cover the nitride based semiconductor stack 110. In addition, the first electrode 140 may have an opening 140b exposing the second electrode 120.
  • the first electrode 140 may be formed on an almost entire area of the growth substrate 100 except for the opening 140b. Thus, current may be easily dispersed over the entire area of the growth substrate 100 through the first electrode 140.
  • the first electrode 140 may include a high reflective metal layer such as an Al layer, and the high reflective metal layer may be formed on an adhesive layer such as Ti, Cr, or Ni.
  • a protective layer of a single layer or a composite layer structure such as Ni, Cr, Au, or the like may be formed on the highly reflective metal layer.
  • the first electrode 140 may have, for example, a multilayer structure of Ti / Al / Ti / Ni / Au.
  • the first electrode 140 may be formed by depositing and patterning a metal material on the nitride-based semiconductor stack 110.
  • the light emitting device may further include a lower insulating layer 130.
  • the lower insulating layer 130 covers the top surface and side surfaces of the nitride-based semiconductor stack 110 and the second electrode 120, and is positioned between the nitride-based semiconductor stack 110 and the first electrode 140.
  • the first electrode 140 may be insulated from the second electrode 120.
  • the lower insulating layer 130 has openings 130a and 130b for allowing electrical connection to the first conductive semiconductor layer 111 and the second conductive semiconductor layer 113 in a specific region.
  • the lower insulating layer 130 may have an opening 130a exposing the first conductive semiconductor layer 111 and an opening 130b exposing the second electrode 120.
  • the opening 130b of the lower insulating layer 130 may have a relatively narrow area than the opening 140b of the first electrode 140.
  • the lower insulating layer 130 may be formed of an oxide film such as SiO 2, a nitride film such as SiNx, or an insulating film of MgF 2 using a technique such as chemical vapor deposition (CVD).
  • the lower insulating layer 130 may be formed of a single layer, but is not limited thereto and may be formed of multiple layers.
  • the lower insulating layer 130 may include a distributed Bragg reflector (DBR) in which the low refractive material layer and the high refractive material layer are alternately stacked.
  • DBR distributed Bragg reflector
  • an insulating reflective layer having a high reflectance can be formed by laminating layers such as SiO 2 / TiO 2 or SiO 2 / Nb 2 O 5.
  • the light emitting device may further include an upper insulating layer 150.
  • the upper insulating layer 150 may cover a portion of the first electrode 140.
  • the upper insulating layer 150 may have an opening 150a exposing the first electrode 140 and an opening 150b exposing the second electrode 120.
  • the opening 150b of the upper insulating layer 150 may have a relatively narrower area than the opening 140b of the first electrode 140 and the opening 130b of the lower insulating layer 130. Accordingly, sidewalls of the opening 130b of the lower insulating layer 130 may be covered by the upper insulating layer 150 as well as sidewalls of the opening 140b of the first electrode 140. In this case, the second electrode 120 may be more effectively protected from moisture.
  • the present disclosure is not limited thereto, and the upper insulating layer 150 may be formed by depositing and patterning an oxide insulating layer, a nitride insulating layer, or a polymer such as polyimide, teflon, and parylene on the first electrode 140. have.
  • the bonding pad of the light emitting device may include a first bonding pad 200a and a second bonding pad 200b electrically connected to the first electrode 140 and the second electrode 120, respectively.
  • the first bonding pad 200a may be connected to the first electrode 140 through a first connection electrode formed in the opening 150a of the upper insulating layer 150.
  • the 2 bonding pads 200b may be connected to the second electrode 120 through the second connection electrode formed in the opening 150b of the upper insulating layer 150.
  • the first bonding pad 200a and the second bonding pad 200b may serve to effectively connect the first electrode 140 and the second electrode 120 to the substrate.
  • the first bonding pad 200a and the second bonding pad 200b may be formed together in the same process, for example, by using a photo and etching technique or a lift off technique.
  • the first bonding pad 200a and the second bonding pad 200b may include, for example, an adhesive layer such as Ti, Cr, or Ni, and a highly conductive metal layer such as Al, Cu, Ag, or Au.
  • the light emitting device including the bonding pads 200a and 200b of the present invention may have a form in which a plurality of separated active layers share one first conductive semiconductor layer 111.
  • first bonding pad 200a and the second bonding pad 200b are designed to occupy the largest area in the solder ball contactable area 210 to facilitate bonding between the mounting substrate and the bonding pad, they may occur during the reflow process. Since the voids deteriorate the reliability of the light emitting device, it is necessary to design an electrode shape in which large voids are not formed or the voids can escape well without being trapped in the electrode.
  • the light emitting device having the electrode shape according to the present invention has the bonding pads 200a and 200b soldered onto the mounting substrate, as shown in FIGS. 1 to 6.
  • Two or more linear bonding pads 200a and 200b are electrically connected to the first conductive semiconductor layer 111 and the second conductive semiconductor layer 113 by connecting electrodes, respectively, in the solder ball contactable area 210. Is formed, and at least two of the two or more linear bonding pads 200a and 200b face each other, and a non-conductive area 220 is disposed between the two bonding pads 200a and 200b facing each other. It is characterized by the presence.
  • the solder ball contactable area 210 refers to a portion where the light emitting device may contact the solder ball located on the mounting substrate. When the solder is melted by the reflow process, the solder ball contactable area 210 is melted. It may be included in the area occupied by the solder.
  • the linear bonding pad 200a means that the length of the electrode having an area is larger than the width.
  • the non-conductive region 220 is a region where the bonding pad 200a is not formed and means a portion where the upper insulating layer 150 is exposed. That is, the space due to the step between the upper insulating layer 150 and the bonding pad 200a layer corresponds to this.
  • the bonding pads face each other as long as the bonding pads can be recognized as facing each other in parallel or even if they are not parallel.
  • the bonding pad 200a of the light emitting device of the present invention at least two of the two or more linear bonding pads 200a face each other, but the non-conductive area 220 is disposed between the two electrodes facing each other. By being present, void generation is minimized.
  • At least two of the two or more linear bonding pads 200a may be spaced apart from each other.
  • At least two of the two or more linear bonding pads 200a may be connected to each other.
  • linear bonding pads shown in FIG. 1A may be all connected at any position by the connection unit as shown in FIGS. 3 to 6.
  • all four bonding pads 200a having three linear shapes are connected to each other through three connection portions. That is, as shown in Figures 3 to 6, if the two or more linear bonding pads 200a are formed (n ⁇ 2), when at least n-1 or more connection parts are included, the linear shape
  • the bonding pads 200a may be connected to each other.
  • linear bonding pads 200a may be connected with more connections as long as the condition that the non-conductive area 220 exists between the two bonding pads facing each other.
  • the bonding pad included in the light emitting device of the present invention at least two of the two or more linear bonding pads 200a face each other, but are not electrically conductive between two bonding pads 200a facing each other.
  • the presence of the region 220 exposes the upper portion of the insulating layer 150, thereby providing a space due to the step between the insulating layer 150 and the bonding pad 200a layer, thereby creating a large void generated in the reflow process. It is designed so that it is not formed.
  • FIG. 7A and 7B show cross-sectional views of the light emitting device of FIG. 3 in the B-B 'and C-C' directions, respectively, and the above-described effects can be confirmed.
  • the second bonding pad 200b of the present invention has a non-conductive area 220 between linear bonding pads facing each other, that is, the insulating layer 150 and the bonding pad. (200b) As the space due to the step between the layers, the voids generated in the reflow process is released to the space, the reliability of the product can be improved.
  • the first bonding pad 200a of the present invention has a non-conductive area 220 between the linear bonding pads facing each other, that is, the insulating layer 150 and the bonding layer. As the space due to the step between the pads 200a, the voids generated in the reflow process are released to the space, thereby improving the reliability of the product.
  • the width t of the linear bonding pad 200a is preferably 200 ⁇ m or less. If the above range is exceeded, the distance from the void presence point generated in the solder ball contactable area 210 in the bonding pad 200a to the non-conductive area becomes too far, so that the void does not escape and is trapped in the bonding pad 200a. As a result, the reliability of the light emitting device is reduced, such as poor bonding to the mounting substrate and poor heat dissipation performance.
  • variety t of the linear bonding pad 200a is 40 micrometers or more. If it is less than the above range there is a problem that the current injection amount to the bonding pad 200a is lowered to reduce the luminous efficiency of the light emitting device.
  • the area of the linear bonding pad 200a is preferably 40% or more of the solder ball contactable area 210. If it is less than the above range there is a problem that the current injection amount to the bonding pad 200a is lowered to reduce the luminous efficiency of the light emitting device.
  • the shape of the bonding pad of the present invention is not limited to the above-described embodiments, and those skilled in the art can deform as many as possible within the scope of the present invention in terms of designing such that voids having a diameter of an electrode width or more are not generated.
  • bonding pads 200a and 200b are soldered onto the mounting substrate.
  • a bonding pad 200a is formed in a portion of the solder pad, and a non-conductive pattern 230 for void escape is formed in the remaining portion of the solder ball contactable region 210.
  • the void escape non-conductive pattern 230 corresponds to an area in which the bonding pads 200a and 200b are not formed.
  • the upper portion of the insulating layer 150 is exposed to expose the upper insulating layer 150 and the bonding pad ( 200a, 200b) because the space is provided by the step between the layers, it means a form of the space that the void generated in the reflow process can escape.
  • the bonding pads 200a and 200b of the light emitting device of the present invention are formed in some of the solder ball contactable regions 210, and the remaining bonding pads 200a and 200b are formed in the remaining solder ball contactable regions 210.
  • the void escape non-conductive pattern 230 the voids may escape through the non-conductive pattern 230, thereby minimizing the occurrence of voids.
  • the non-conductive pattern 230 may be formed in the direction of the edge of the solder ball contactable region 210 within 200 ⁇ m at an arbitrary point P in the bonding pads 200a and 200b. have. The void generated through this can be immediately exited through the non-conductive pattern 230.
  • the thickness exceeds 200 ⁇ m at any point P in the electrode, it is difficult for the voids to escape, so it is preferable to form the void-free non-conductive pattern 230 for void escape without forming the electrode so that the voids can escape. .
  • the non-conductive pattern 230 may have a tapered shape that extends toward the edge of the solder ball contactable region 210.
  • the non-conductive pattern 230 has a tapered shape that becomes wider toward the edge portion of the solder ball contactable region 210, the voids may easily escape.
  • the area of the bonding pads 200a and 200b is preferably 40% or more of the area of the solder ball contactable area 210. If it is less than the above range, there is a problem that the current injection amount to the electrode is lowered to reduce the luminous efficiency of the light emitting device.
  • FIG. 9 to 14 are plan views and cross-sectional views for describing a light emitting device according to another embodiment of the present invention.
  • FIG. 9 is a plan view illustrating a plane of the light emitting device
  • FIG. 10 is a plan view omitting bonding pads 200a and 200b for convenience of description
  • FIG. 11 is a bonding view for convenience of description.
  • the pads 200a and 200b, the upper insulating layer 150, the first electrode 140, and the lower insulating layer 130 are omitted.
  • FIG. 12 shows a cross section of a portion corresponding to line AA ′ of the top views of FIGS. 9 to 11, and
  • FIG. 13 shows a cross section of a portion corresponding to line B-B ′ of the top views of FIGS. 9 to 11.
  • 14 shows a cross section of a portion corresponding to line C-C 'of the plan views of FIGS.
  • the light emitting device according to the present embodiment has a difference in the structure of the bonding pads 200a and 200b and the structure of the nitride-based semiconductor stack 110 compared to the embodiments described with reference to FIGS. 1 to 8.
  • the light emitting device of the present embodiment will be described based on differences, and detailed descriptions of the same components will be omitted.
  • the light emitting device includes a nitride based semiconductor stack 110, a first electrode 140, a second electrode 120, a first bonding pad 200a, and a second bonding pad 200b. It includes. Further, the light emitting device may further include a lower insulating layer 130, an upper insulating layer 150, and a substrate 101. In addition, the light emitting device may have a rectangular planar shape. In the present embodiment, the light emitting device may have a generally square planar shape, and the third side surface 100c positioned opposite to the first side surface 100a, the second side surface 100b, and the first side surface 100a. And a fourth side surface 100d positioned opposite to the second side surface 100b. However, the present invention is not limited thereto.
  • the nitride based semiconductor layer 110 includes a first conductive semiconductor layer 111, an active layer 112 positioned on the first conductive semiconductor layer 111, and a second conductive semiconductor layer positioned on the active layer 112. (113).
  • the nitride-based semiconductor stack 110 may include regions 110a and 110b partially exposing the first conductivity-type semiconductor layer 111. The current dispersion efficiency and the light emission pattern of the light emitting device may be adjusted according to the position, shape, and number of the exposed areas 110a and 110b.
  • regions 110a, 110b and 110c where the first conductivity type semiconductor layer 111 is partially exposed may include holes.
  • the holes may include a first hole 110a, a second hole 110b, and a third hole 110c.
  • a plurality of first holes 110a, second holes 110b, and third holes 110c may be formed.
  • the first hole 110a may have a planar shape of a generally circular or polygonal shape.
  • the second hole 110b may have substantially the same shape as the first hole 110a.
  • the third hole 110c may be formed to extend in an arbitrary direction from the second hole 110b. In this case, the third hole 110c and the second hole 110b may be connected to each other.
  • the width of the third hole 110c may be smaller than the width of the first hole 110a and the second hole 110b.
  • the first hole 110a has a circular planar shape and may be formed in plural.
  • the third hole 110c may extend from the second hole 100b and may extend from the first side surface 100a toward the third side surface 100c and may be formed in plural. At least a portion of the third hole 110c may be formed to extend from a lower portion of the first bonding pad 200a to a lower portion of the second bonding pad 200b.
  • the second electrode 120 may be positioned on the nitride-based semiconductor stack 110 to make ohmic contact with the second conductive semiconductor layer 113.
  • the second electrode 120 may include openings exposing the first and second holes 110a and 110b, so that the second electrode 120 may be connected to the first and second holes 110a and 110b. Can be spaced apart.
  • the lower insulating layer 130 may cover the top and side surfaces of the nitride based semiconductor stack 110 and the second electrode 120.
  • the lower insulating layer 130 may have openings 130a and 130b for allowing electrical connection to the first conductive semiconductor layer 111 and the second conductive semiconductor layer 113 in a specific region.
  • the lower insulating layer 130 may have a first opening 130a exposing the first conductive semiconductor layer 111 and a second opening 130b exposing the second electrode 120.
  • the first electrode 140 may be electrically connected to the first conductive semiconductor layer 111, and in particular, the first electrode 140 may be in ohmic contact with the first conductive semiconductor layer 111.
  • the first electrode 140 may be electrically connected to the first conductivity type semiconductor layer 111 through the first and second holes 110a and 110b. Accordingly, the portion into which the current is injected into the nitride based semiconductor stack 110 through the first electrode 140 may be controlled according to the position and shape of the first and second holes 110a and 110b.
  • the first electrode 140 may have an opening 140b exposing the second electrode 120.
  • the first electrode 140 may be formed on an almost entire area of the growth substrate 100 except for the opening 140b.
  • the upper insulating layer 150 may cover a portion of the first electrode 140.
  • the upper insulating layer 150 may include a third opening 150a exposing the first electrode 140 and a fourth opening 150b exposing the second electrode 120.
  • the fourth opening 150b of the upper insulating layer 150 may have a relatively narrower area than the opening 140b of the first electrode 140 and the opening 130b of the lower insulating layer 130.
  • the upper insulating layer 150 covers a portion of the first electrode 140 positioned on the third hole 110c. Accordingly, the third opening 150a of the upper insulating layer 150 may partially expose the first electrode 140 positioned on the first hole 110a and / or the second hole 110b.
  • the first bonding pad 200a and the second bonding pad 200b may be electrically connected to the first electrode 140 and the second electrode 120, respectively. Referring to FIG. 10, the first bonding pad 200a may contact the first electrode 140 through the third openings 150a, and the second bonding pad 200b may contact the fourth openings 150b. It may be in contact with the second electrode 150 through.
  • the first and second bonding pads 200a and 200b include the non-conductive region 220 positioned in the solder ball contactable region 210, as described in the above embodiments.
  • Each of the first and second bonding pads 200a and 200b may include a portion disposed side by side on one side of the light emitting device, and at least one protrusion 240 protruding from the portion.
  • the first bonding pad 200a may include a portion generally disposed side by side on the first side surface 100a of the light emitting device and three protrusions 240 protruding from the portion.
  • the non-conductive area 220 of the first bonding pad 200a may be located between the three protrusions 240.
  • the second bonding pad 200b may include a portion generally disposed side by side on the third side surface 100c of the light emitting device and three protrusions 240 protruding from the portion.
  • the non-conductive area 220 of the second bonding pad 200b may be located between the three protrusions 240. Through the non-conductive region 220, it is possible to effectively prevent voids generated during the soldering process.
  • the width t2 and the width t1 of the protrusions disposed side by side on one side of each of the first and second bonding pads 200a and 200b may be the same as or different from each other.
  • the widths t1 and t2 may be 40 to 200 ⁇ m, as described in the above embodiments.
  • the first bonding pad 200a may contact the first conductive semiconductor layer 111 through the regions 110a, 110b and 110c where the first conductive semiconductor layer 111 is partially exposed. A portion of 140 may be at least partially covered. In particular, the first bonding pad 200a may be formed to cover a portion of the first electrode 140 positioned on the first hole 110a and the second hole 110b having a relatively large width. For example, the protrusions 240 of the first bonding pad 200a may be disposed corresponding to the positions where the first holes 110a and the second holes 110b are formed.
  • the first conductivity-type semiconductor layer 111 and the first electrode are formed through regions 110a, 110b, and 110c where the first conductivity-type semiconductor layer 111 is partially exposed. Stress and strain may be applied to the interface 140 contacts. Due to such stress and strain, a problem may occur in which the first electrode 140 is separated from the first conductive semiconductor layer 111. In this case, the forward voltage Vf of the light emitting device is increased or current dispersion is smooth. A phenomenon that cannot be achieved may occur. In this case, a decrease in reliability may occur due to a decrease in electrical and optical characteristics of the light emitting device.
  • a portion of the first electrode 140 positioned on the first hole 110a and the second hole 110b is covered by the first bonding pad 200a to thereby cover the first electrode 140.
  • the first hole 110a and the second hole 110b have a relatively larger width than the third hole 110c, the current injection efficiency through the first hole 110a and the second hole 110b. When this decreases, the deterioration of characteristics of the light emitting device may be further intensified.
  • by covering the portion of the first electrode 140 positioned on the first hole 110a and the second hole 110b with the first bonding pad 200a reliability of the light emitting device more effectively. Can improve.
  • the first bonding pad 200a and the second bonding pad 200b may be formed to be generally symmetrical.
  • the present invention is not limited thereto, and the protrusions 240 of the first and second bonding pads 200a and 200b may be variously modified.
  • the protrusions 240 of the first bonding pad 200a may be formed on the first and second holes 110a and 110b.
  • the first bonding pad 200a may include three protrusions 240 protruding in the direction toward the second bonding pad 200b, and the non-conductive area 220 may be disposed between the three protrusions 240. Is placed.
  • the second bonding pad 200b may include protrusions 240 protruding in a direction toward the non-conductive area 220 of the first bonding pad 200a.
  • the passage through which the void is discharged to the outside in the reflow process can be changed.
  • the first and second bonding pads 200a and 200b of the present exemplary embodiment are not limited thereto and may be variously changed as described in the embodiments of FIGS. 1 to 8.
  • the first and second bonding pads 200a and 200b are formed to cover the first hole 110a and the second hole 110b, thereby similarly obtaining a reliability improvement effect of the light emitting device according to the present embodiment. have.
  • FIG. 17 is an exploded perspective view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a lighting device.
  • the lighting apparatus includes a diffusion cover 1010, a light emitting device module 1020, and a body portion 1030.
  • the body portion 1030 may accommodate the light emitting device module 1020, and the diffusion cover 1010 may be disposed on the body portion 1030 to cover the upper portion of the light emitting device module 1020.
  • the body portion 1030 is not limited as long as it can receive and support the light emitting device module 1020 and supply electric power to the light emitting device module 1020.
  • the body portion 1030 may include a body case 1031, a power supply device 1033, a power case 1035, and a power connection portion 1037.
  • the power supply device 1033 is accommodated in the power case 1035 and electrically connected to the light emitting device module 1020, and may include at least one IC chip.
  • the IC chip may adjust, convert, or control the characteristics of the power supplied to the light emitting device module 1020.
  • the power case 1035 may receive and support the power supply 1033, and the power case 1035 to which the power supply 1033 is fixed may be located inside the body case 1031. .
  • the power connection unit 115 may be disposed at a lower end of the power case 1035 and may be coupled to the power case 1035. Accordingly, the power connection unit 1037 may be electrically connected to the power supply device 1033 inside the power case 1035 to serve as a path through which external power may be supplied to the power supply device 1033.
  • the light emitting device module 1020 includes a substrate 1023 and a light emitting device 1021 disposed on the substrate 1023.
  • the light emitting device module 1020 may be disposed on the body case 1031 and electrically connected to the power supply device 1033.
  • the substrate 1023 is not limited as long as it can support the light emitting device 1021.
  • the substrate 1023 may be a printed circuit board including wiring.
  • the substrate 1023 may have a shape corresponding to the fixing portion of the upper portion of the body case 1031 so as to be stably fixed to the body case 1031.
  • the light emitting device 1021 may include at least one of the light emitting devices according to the embodiments of the present invention described above.
  • the diffusion cover 1010 may be disposed on the light emitting device 1021, and may be fixed to the body case 1031 to cover the light emitting device 1021.
  • the diffusion cover 1010 may have a translucent material and may adjust the directivity of the lighting device by adjusting the shape and the light transmittance of the diffusion cover 1010. Therefore, the diffusion cover 1010 may be modified in various forms according to the purpose of use of the lighting device and the application aspect.
  • FIG. 18 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a display device.
  • the display device includes a display panel 2110, a backlight unit providing light to the display panel 2110, and a panel guide supporting a lower edge of the display panel 2110.
  • the display panel 2110 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer.
  • a gate driving PCB for supplying a driving signal to the gate line may be further located at the edge of the display panel 2110.
  • the gate driving PCB is not configured in a separate PCB, but may be formed on the thin film transistor substrate.
  • the backlight unit includes a light source module including at least one substrate and a plurality of light emitting devices 2160.
  • the backlight unit may further include a bottom cover 2180, a reflective sheet 2170, a diffusion plate 2131, and optical sheets 2130.
  • the bottom cover 2180 may be opened upward to accommodate the substrate, the light emitting device 2160, the reflective sheet 2170, the diffusion plate 2131, and the optical sheets 2130.
  • the bottom cover 2180 may be combined with the panel guide.
  • the substrate may be disposed under the reflective sheet 2170 and be surrounded by the reflective sheet 2170.
  • the present invention is not limited thereto, and when the reflective material is coated on the surface, the reflective material may be positioned on the reflective sheet 2170.
  • a plurality of substrates may be formed, and the plurality of substrates may be arranged in a side-by-side arrangement, but is not limited thereto and may be formed of a single substrate.
  • the light emitting device 2160 may include at least one of the light emitting devices according to the embodiments of the present invention described above.
  • the light emitting devices 2160 may be regularly arranged in a predetermined pattern on the substrate.
  • a lens 2210 may be disposed on each light emitting device 2160 to improve uniformity of light emitted from the plurality of light emitting devices 2160.
  • the diffusion plate 2131 and the optical sheets 2130 are positioned on the light emitting device 2160. Light emitted from the light emitting device 2160 may be supplied to the display panel 2110 in the form of a surface light source through the diffusion plate 2131 and the optical sheets 2130.
  • the light emitting device according to the embodiments of the present invention may be applied to the direct type display device as the present embodiment.
  • 19 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment is applied to a display device.
  • the display device including the backlight unit includes a display panel 3210 on which an image is displayed and a backlight unit disposed on a rear surface of the display panel 3210 to irradiate light.
  • the display apparatus includes a frame 240 that supports the display panel 3210 and accommodates the backlight unit, and covers 3240 and 3280 that surround the display panel 3210.
  • the display panel 3210 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer.
  • a gate driving PCB for supplying a driving signal to the gate line may be further located at an edge of the display panel 3210.
  • the gate driving PCB is not configured in a separate PCB, but may be formed on the thin film transistor substrate.
  • the display panel 3210 may be fixed by covers 3240 and 3280 positioned at upper and lower portions thereof, and the cover 3280 positioned at lower portions thereof may be coupled to the backlight unit.
  • the backlight unit for providing light to the display panel 3210 may include a lower cover 3270 having a portion of an upper surface thereof, a light source module disposed on one side of the lower cover 3270, and positioned in parallel with the light source module to provide point light. And a light guide plate 3250 for converting to surface light.
  • the backlight unit according to the present exemplary embodiment is disposed on the light guide plate 3250 and is disposed below the light guide plate 3250 and the optical sheets 3230 for diffusing and condensing light.
  • the display apparatus may further include a reflective sheet 3260 reflecting in the direction of the display panel 3210.
  • the light source module includes a substrate 3220 and a plurality of light emitting devices 3110 spaced apart from each other by a predetermined interval on one surface of the substrate 3220.
  • the substrate 3220 is not limited as long as it supports the light emitting device 3110 and is electrically connected to the light emitting device 3110.
  • the substrate 3220 may be a printed circuit board.
  • the light emitting device 3110 may include at least one light emitting device according to the embodiments of the present invention described above. Light emitted from the light source module is incident to the light guide plate 3250 and is supplied to the display panel 3210 through the optical sheets 3230. Through the light guide plate 3250 and the optical sheets 3230, the point light sources emitted from the light emitting devices 3110 may be transformed into surface light sources.
  • the light emitting device according to the embodiments of the present invention may be applied to the edge type display device as the present embodiment.
  • FIG. 20 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a head lamp.
  • the head lamp includes a lamp body 4070, a substrate 4020, a light emitting device 4010, and a cover lens 4050. Furthermore, the head lamp may further include a heat dissipation unit 4030, a support rack 4060, and a connection member 4040.
  • the substrate 4020 is fixed by the support rack 4060 and spaced apart from the lamp body 4070.
  • the substrate 4020 is not limited as long as it is a substrate capable of supporting the light emitting device 4010.
  • the substrate 4020 may be a substrate having a conductive pattern such as a printed circuit board.
  • the light emitting device 4010 is positioned on the substrate 4020 and may be supported and fixed by the substrate 4020.
  • the light emitting device 4010 may be electrically connected to an external power source through the conductive pattern of the substrate 4020.
  • the light emitting device 4010 may include at least one light emitting device according to the embodiments of the present invention described above.
  • the cover lens 4050 is positioned on a path along which light emitted from the light emitting element 4010 travels.
  • the cover lens 4050 may be disposed spaced apart from the light emitting element 4010 by the connecting member 4040, and may be disposed in a direction to provide light emitted from the light emitting element 4010. Can be.
  • the connection member 4040 may fix the cover lens 4050 with the substrate 4020 and may be disposed to surround the light emitting device 4010 to serve as a light guide for providing the light emitting path 4045.
  • connection member 4040 may be formed of a light reflective material or coated with a light reflective material.
  • the heat dissipation unit 4030 may include a heat dissipation fin 4031 and / or a heat dissipation fan 4033, and emits heat generated when the light emitting device 4010 is driven to the outside.
  • the light emitting device may be applied to the head lamp, in particular, a vehicle head lamp as in the present embodiment.

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Abstract

The present invention relates to a light emitting diode, and more specifically, to a light emitting diode in which a bonding pad is soldered to a mounting substrate, wherein the light emitting diode has a bonding pad shape that can minimize the occurrence of voids during soldering.

Description

발광소자Light emitting element

본 발명은 발광소자에 관한 것으로, 특히 본딩패드가 실장기판 상에 솔더링되는 발광소자에 있어서, 솔더링 과정에서 발생되는 보이드 발생 현상을 최소화 할 수 있는 본딩패드 형상을 갖는 발광소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting device, and more particularly, to a light emitting device having a bonding pad shape capable of minimizing voids generated during soldering in a light emitting device in which a bonding pad is soldered onto a mounting substrate.

고출력 발광소자를 얻기 위해서는 발광 효율을 높이거나, 패키지를 소형화시키거나, 열 저항을 낮추는 등의 요소를 고려하여 소자를 제작하여야 한다. 상기 조건을 만족시키기 위해서 현재 널리 사용되고 있는 것이 플립칩 방식의 발광소자이다.In order to obtain a high output light emitting device, the device must be manufactured in consideration of factors such as increasing luminous efficiency, miniaturizing a package, and lowering thermal resistance. In order to satisfy the above conditions, a flip chip type light emitting device is widely used at present.

플립칩 방식은 솔더 범프(solder bump)를 이용한 칩 본딩 방식을 의미하는 것으로, 기존의 와이어 본딩 방식에 비하여 본딩 길이가 거의 없기 때문에, 본딩에 의한 인덕턴스를 1/10 이하로 줄일 수 있고, 따라서 해당 방식에 의하는 경우 칩 패키지의 집적화가 가능하다.The flip chip method refers to a chip bonding method using solder bumps. Since the bonding length is almost smaller than that of the conventional wire bonding method, the inductance due to the bonding can be reduced to 1/10 or less, thus According to the method, the chip package can be integrated.

즉, 플립칩 방식에서는 기판 쪽으로 빛을 나오게 함으로써 전극패드에서의 광 손실을 없앨 수 있으며, p층에 반사막을 증착하여 실장기판 쪽으로 진행되는 광자의 경로를 반대방향으로 바꿈으로써 추출효율을 향상시킬 수 있다. 또한 플립칩 방식에 의하면 전류확산이 개선되어 낮은 순방향 전압이 제공된다.In other words, in the flip chip method, light is emitted toward the substrate to eliminate light loss from the electrode pad, and by depositing a reflective film on the p-layer, the extraction efficiency can be improved by changing the path of the photons traveling toward the mounting substrate in the opposite direction. have. The flip-chip approach also improves current spreading, providing a low forward voltage.

또한, 고출력 발광소자의 경우 주입 전류가 커질 때 많은 열이 발생하게 되는데, 열발생 영역인 활성층으로부터 방열구조까지의 거리가 가까우므로 방열이 용이하여 열저항이 크게 감소한다. 따라서 대면적 발광소자와 같은 고출력소자에서는 대부분 플립칩 방식을 채용하고 있다. In addition, in the case of a high output light emitting device, a lot of heat is generated when the injection current is increased. Since the distance from the active layer, which is a heat generating region, to the heat dissipation structure is close, heat dissipation is easy and heat resistance is greatly reduced. Therefore, in the high output device such as a large area light emitting device, the flip chip method is adopted.

한편, 플립칩 방식이 널리 사용되고 있는 대면적 발광소자는 전류 분산을 돕기 위하여 다양한 구조가 제안되고 있는데, 제1 도전형 반도체층과 제2 도전형 반도체층 사이에 개재되는 활성층이 2개 이상으로 분리되고, 상기 2개 이상의 활성층이 하나의 제1도전형 반도체층을 공유하는 형태도 알려져 있다.On the other hand, various structures have been proposed for large area light emitting devices in which a flip chip method is widely used to help current dispersing. The active layer interposed between the first conductive semiconductor layer and the second conductive semiconductor layer is separated into two or more. Also, a form in which the two or more active layers share one first conductive semiconductor layer is also known.

이러한 플립칩 방식은 고온의 열원을 가하여 솔더 범프를 용융함으로써 칩의 본딩패드와 실장기판이 전기적으로 접속하도록 하는 것인데, 솔더 범프를 용융시키는 공정을 리플로우(reflow)라고 한다.In the flip chip method, a solder bump is melted by applying a high temperature heat source to electrically connect the bonding pads of the chip and the mounting substrate. The process of melting the solder bumps is called reflow.

리플로우 공정 중에는 플럭스가 증발하여 용융 솔더가 응고할 때 기포가 그 내부에 갇히게 되어 보이드(void)가 발생될 수 있다. 보이드는 방열기능을 약화시키고, 칩의 본딩패드와 실장기판 간 접합불량을 일으켜 발광소자의 신뢰성을 떨어뜨리는 가장 큰 원인이 되고 있다. During the reflow process, when the flux evaporates and the molten solder solidifies, bubbles may be trapped inside, resulting in voids. Voids are the biggest cause of weakening the heat dissipation function and deterioration of the reliability of the light emitting device due to poor bonding between the bonding pad of the chip and the mounting substrate.

따라서, 발광소자의 신뢰성을 향상시키기 위하여, 보이드 발생 현상을 최소화하기 위한 기술이 요구되는 실정이다.Therefore, in order to improve the reliability of the light emitting device, a technique for minimizing void generation is required.

본 발명과 관련하여, 대한민국 공개특허 제10-2013-0030178호(2013.03.26 공개)에는 플립칩 방식을 채택한 대면적 발광소자가 개시되어 있다.In connection with the present invention, Korean Patent Publication No. 10-2013-0030178 (published on March 26, 2013) discloses a large area light emitting device employing a flip chip method.

본 발명의 목적은 본딩패드가 실장기판 상에 솔더링되는 발광소자에 있어서, 솔더링 과정에서 발생되는 보이드 발생 현상을 최소화할 수 있는 본딩패드 형상을 갖는 발광소자를 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to provide a light emitting device having a bonding pad shape in which a bonding pad is soldered on a mounting substrate, thereby minimizing void generation occurring during the soldering process.

본 발명이 해결하고자 하는 또 다른 과제는, 솔더링 과정에서 발생할 수 있는 불량이 최소화된 발광 소자를 제공하는 것이다.Another object of the present invention is to provide a light emitting device in which defects that may occur in the soldering process are minimized.

본 발명의 일 실시예에 의한 발광소자는 본딩패드가 실장기판 상에 솔더링되는 것으로서, 상기 본딩패드는 연결전극에 의하여 각각 제1 도전형 반도체층 및 제2 도전형 반도체층과 전기적으로 접속된 제1전극 및 제2전극과 연결되고, 솔더볼 접촉 가능 영역에 2개 이상의 선 형상의 본딩패드가 형성되어 있으며, 상기 2개 이상의 선 형상의 본딩패드 중 적어도 2개는 서로 대면하되, 서로 대면하는 2개의 본딩패드 사이에 비도전 영역이 존재하는 것을 특징으로 한다.In the light emitting device according to the embodiment of the present invention, a bonding pad is soldered onto a mounting substrate, and the bonding pad is electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer by a connection electrode, respectively. Two or more linear bonding pads are connected to the first electrode and the second electrode and have a solder ball contact area, and at least two of the two or more linear bonding pads face each other and face each other. The non-conductive region is present between the two bonding pads.

본 발명의 또 다른 실시예에 의한 발광소자는 본딩패드가 실장기판 상에 솔더링되는 것으로서, 상기 본딩패드는 연결전극에 의하여 각각 제1 도전형 반도체층 및 제2 도전형 반도체층과 전기적으로 접속된 제1전극 및 제2전극과 연결되고, 솔더볼 접촉 가능 영역 중 일부에 본딩패드가 형성되어 있고, 솔더볼 접촉 가능 영역 중 나머지에 보이드 탈출용 비도전 패턴이 형성되어 있는 것을 특징으로 한다.The light emitting device according to another embodiment of the present invention is a bonding pad is soldered on a mounting substrate, and the bonding pad is electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer by a connecting electrode, respectively. The first and second electrodes may be connected to each other, and a bonding pad may be formed in a portion of the solder ball contactable area, and a non-conductive pattern for void escape may be formed in the remaining area of the solder ball contactable area.

본 발명의 발광소자에 의하면 큰 보이드가 형성되지 않거나, 보이드가 본딩패드 내 갇히지 않고 잘 빠져나갈 수 있는 본딩패드 형상을 가짐으로써 솔더링 과정에서 발생되는 보이드 발생 현상이 최소화되는바, 발광소자의 신뢰성이 향상될 수 있다. 또한, 발광소자의 제1 전극과 제1 도전형 반도체층이 접촉하는 부분 상에 위치하는 제1 전극의 부분을 본딩패드로 덮음으로써, 발광소자의 신뢰성을 향상시킬 수 있다.According to the light emitting device of the present invention, the voids generated during the soldering process are minimized because a large void is not formed or the bonding pad shape can be easily escaped without being trapped in the bonding pad. Can be improved. In addition, the reliability of the light emitting device can be improved by covering the portion of the first electrode positioned on the portion where the first electrode and the first conductive semiconductor layer of the light emitting device are in contact with the bonding pad.

도 1a는 본 발명의 실시예에 의한 본딩패드 형상을 포함하는 발광소자의 평면도이다. 1A is a plan view of a light emitting device having a bonding pad shape according to an embodiment of the present invention.

도 1b는 도 1a의 발광소자에 대하여 A'-A 방향으로 절단한 경우의 단면도이다.FIG. 1B is a cross-sectional view when the light emitting device of FIG. 1A is cut in the A'-A direction.

도 2 내지 도 6, 및 도 8은 본 발명의 다양한 실시예에 의한 전극 형상을 포함하는 발광소자의 평면도이다.2 to 6 and 8 are plan views of a light emitting device including an electrode shape according to various embodiments of the present disclosure.

도 7a는 도 3의 발광소자에 대하여 B-B'방향으로 절단한 경우의 단면도이다.FIG. 7A is a cross-sectional view when the light emitting device of FIG. 3 is cut in the direction of BB '. FIG.

도 7b는 도 3의 발광소자에 대하여 C-C'방향으로 절단한 경우의 단면도이다.FIG. 7B is a cross-sectional view when the light emitting device of FIG. 3 is cut in the direction C-C '. FIG.

도 9 내지 도 14는 본 발명의 다른 실시예에 따른 발광소자를 설명하기 위한 평면도들 및 단면도들이다.9 to 14 are plan views and cross-sectional views for describing a light emitting device according to another embodiment of the present invention.

도 15 및 도 16은 본 발명의 다른 실시예에 따른 발광소자를 설명하기 위한 평면도들이다.15 and 16 are plan views illustrating light emitting devices according to another exemplary embodiment of the present invention.

도 17은 본 발명의 일 실시예에 따른 발광 소자를 조명 장치에 적용한 예를 설명하기 위한 분해 사시도이다.17 is an exploded perspective view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a lighting device.

도 18은 본 발명의 일 실시예에 따른 발광 소자를 디스플레이 장치에 적용한 예를 설명하기 위한 단면도이다.18 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a display device.

도 19는 본 발명의 일 실시예에 따른 발광 소자를 디스플레이 장치에 적용한 예를 설명하기 위한 단면도이다.19 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a display device.

도 20은 본 발명의 일 실시예에 따른 발광 소자를 헤드 램프에 적용한 예를 설명하기 위한 단면도이다.20 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a head lamp.

본 발명의 이점 및 특징, 그리고 그것들을 달성하는 방법은 첨부되는 도면과 함께 상세하게 후술되어 있는 실시예를 참조하면 명확해질 것이다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예는 본 발명의 개시가 완전하도록 하는 것으로, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것인바, 본 발명은 청구항의 범주에 의해 정의될 뿐이다. 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성요소를 지칭한다.Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and are commonly known in the art. It is provided to fully inform the scope of the invention to those having the present invention, the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

이하, 첨부된 도면을 참조하여 본 발명에 따른 발광소자에 관하여 상세히 설명하기로 한다.Hereinafter, a light emitting device according to the present invention will be described in detail with reference to the accompanying drawings.

도 1a는 본 발명의 실시예에 의한 본딩패드 형상을 포함하는 발광소자의 평면도, 도 1b는 도 1a의 발광소자에 대하여 A'-A 방향으로 절단한 경우의 단면도이다.FIG. 1A is a plan view of a light emitting device having a bonding pad shape according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view when the light emitting device of FIG. 1A is cut in the A'-A direction.

먼저 도 1을 참조하면, 본 발명의 전극 형상을 포함하는 발광소자는 활성층(112)이 n형 반도체층(111)과 p형 반도체층(113) 사이에 개재되도록, 기판(101) 상에 제1 도전형 반도체층(111), 활성층(112) 및 제2 도전형 반도체층(113)이 형성되어 있는 구조를 갖는다. First, referring to FIG. 1, the light emitting device including the electrode shape of the present invention may be formed on the substrate 101 such that the active layer 112 is interposed between the n-type semiconductor layer 111 and the p-type semiconductor layer 113. The first conductive semiconductor layer 111, the active layer 112, and the second conductive semiconductor layer 113 are formed.

기판(101)은 Al2O3, SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge 등과 같은 공지의 재료를 선택하여 이용할 수 있다. 상기 기판(101)의 위 및/또는 아래에는 요철 패턴이 형성될 수 있으며, 상기 요철 패턴의 형상은 스트라이프 형상, 렌즈 형상, 기둥 형상, 뿔 형상 등 자유롭게 선택 가능하다.The substrate 101 may be selected from a known material such as Al 2 O 3 , SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, or the like. Concave-convex patterns may be formed on and / or under the substrate 101, and the concave-convex pattern may be freely selected, such as a stripe shape, a lens shape, a pillar shape, or a horn shape.

제1 도전형 반도체층(111)은 제1 도전형 도펀트가 도핑된 반도체층이다. 상기 제1 도전형 반도체층(111)은 GaN, InN, AlN, InGaN, AlGaN, InAlGaN 중 적어도 하나로 형성될 수 있으며, 상기 제1 도전형 반도체층(111)이 n형 반도체층인 경우, 상기 제1 도전형 도펀트는 n형 도펀트인 Si, Ge, Sn, Se, Te 중 1종 이상을 포함할 수 있다.The first conductivity type semiconductor layer 111 is a semiconductor layer doped with the first conductivity type dopant. The first conductive semiconductor layer 111 may be formed of at least one of GaN, InN, AlN, InGaN, AlGaN, and InAlGaN, and the first conductive semiconductor layer 111 may be an n-type semiconductor layer. The single-conducting dopant may include at least one of Si, Ge, Sn, Se, and Te, which are n-type dopants.

활성층(112)은 단일 양자 우물 또는 다중 양자 우물(MQW) 구조로 형성될 수 있다. 즉, 3족-5족 화합물 반도체 재료를 이용하여 GaN, InN, AlN, InGaN, AlGaN, InAlGaN 중 적어도 하나로 형성될 수 있다. 예컨대 활성층(112)은 InGaN 우물층/GaN 장벽층이 교대로 형성된 구조를 가질 수 있다. 상기 활성층(112)은 제1 도전형 반도체층(111)에서 공급되는 캐리어와 제2 도전형 반도체층(113)에서 공급되는 캐리어가 재결합하면서 광을 발생시킨다. 상기 제1 도전형 반도체층(111)이 n형 반도체층인 경우, 상기 제1 도전형 반도체층(111)에서 공급되는 캐리어는 전자일 수 있고, 제2 도전형 반도체층(113)이 p형 반도체층인 경우, 상기 제2 도전형 반도체층(113)에서 공급되는 캐리어는 정공일 수 있다.The active layer 112 may be formed in a single quantum well or multiple quantum well (MQW) structure. That is, at least one of GaN, InN, AlN, InGaN, AlGaN, and InAlGaN may be formed using a Group III-V compound semiconductor material. For example, the active layer 112 may have a structure in which InGaN well layers / GaN barrier layers are alternately formed. The active layer 112 generates light while the carrier supplied from the first conductive semiconductor layer 111 and the carrier supplied from the second conductive semiconductor layer 113 are recombined. When the first conductivity-type semiconductor layer 111 is an n-type semiconductor layer, the carrier supplied from the first conductivity-type semiconductor layer 111 may be electrons, and the second conductivity-type semiconductor layer 113 may be p-type. In the case of the semiconductor layer, the carrier supplied from the second conductivity type semiconductor layer 113 may be a hole.

제2 도전형 반도체층(113)은 제2 도전형 도펀트가 도핑된 반도체층을 포함하며, 단층 또는 다층으로 형성될 수 있다. 상기 제2 도전형 반도체층(113)은 GaN, InN, AlN, InGaN, AlGaN, InAlGaN 중 적어도 하나로 형성될 수 있으며, 제2 도전형 반도체층(113)이 p형 반도체층인 경우, 상기 제2 도전형 도펀트는 p형 도펀트인 Mg, Zn, Ca, Sr, Ba 중 1종 이상을 포함할 수 있다.The second conductivity type semiconductor layer 113 may include a semiconductor layer doped with the second conductivity type dopant and may be formed in a single layer or multiple layers. The second conductive semiconductor layer 113 may be formed of at least one of GaN, InN, AlN, InGaN, AlGaN, and InAlGaN, and when the second conductive semiconductor layer 113 is a p-type semiconductor layer, the second The conductive dopant may include one or more of p-type dopants, Mg, Zn, Ca, Sr, and Ba.

본 발명에 따른 발광소자는 도 1에 나타낸 제1 도전형 반도체층(111), 활성층(112) 및 제2 도전형 반도체층(113) 이외에도 결정 품질 향상을 위하여 비도핑층이나 기타 버퍼층을 포함할 수 있으며, 제2 도전형 반도체층(113)이 p형 반도체층인 경우, 활성층(112)과 제2 도전형 반도체층(113) 사이에 형성되는 전자차단층(미도시)과 같이 다양한 기능층들이 포함될 수 있다. In addition to the first conductive semiconductor layer 111, the active layer 112, and the second conductive semiconductor layer 113 shown in FIG. 1, the light emitting device according to the present invention may include an undoped layer or other buffer layer to improve crystal quality. When the second conductive semiconductor layer 113 is a p-type semiconductor layer, various functional layers such as an electron blocking layer (not shown) formed between the active layer 112 and the second conductive semiconductor layer 113 may be used. May be included.

질화물계 반도체 적층(110)은 제1 도전형 반도체층(111)을 부분적으로 노출시키는 노출 영역(e)을 포함할 수 있으며, 노출 영역(e)을 통해 제1 도전형 반도체층(111)과 제1 전극(140)이 전기적으로 접속될 수 있다. 노출 영역(e)의 위치, 형태, 및 개수에 따라 전류 분산 효율 및 발광 장치의 발광 패턴이 조절될 수 있다. 노출 영역(e)은 사진 및 식각 기술을 이용하여 형성될 수 있다. 노출 영역(e)은 사진 및 식각 기술을 이용하여 형성될 수 있다. 예를 들어, 포토레지스트를 이용하여 식각 영역을 정의하고, ICP와 같은 건식 식각을 이용하여 제2 도전형 반도체층(113)과 활성층(112)을 식각함으로써 노출 영역(e)이 형성될 수 있다.The nitride based semiconductor stack 110 may include an exposed region e partially exposing the first conductive semiconductor layer 111, and the first conductive semiconductor layer 111 may be exposed through the exposed region e. The first electrode 140 may be electrically connected. The current dispersion efficiency and the light emission pattern of the light emitting device may be adjusted according to the position, shape, and number of the exposed regions e. The exposed area e may be formed using photo and etching techniques. The exposed area e may be formed using photo and etching techniques. For example, an exposed region e may be formed by defining an etching region using a photoresist and etching the second conductive semiconductor layer 113 and the active layer 112 using dry etching such as ICP. .

이에 한정되는 것은 아니지만, 도 1b는 노출 영역(e)이 활성층(112) 및 제2 도전형 반도체층(113)을 관통하는 홀 형태로 형성된 예를 보여준다. 홀을 통해 제1 도전형 반도체층(111)과 제1 전극(140)이 전기적으로 접속된다. 홀은 도시된 바와 같이 규칙적으로 형성될 수 있으나, 본 발명이 이에 한정되는 것은 아니다. 홀의 위치, 형태 및 개수에 따라 전류 분산 효율 및 발광 장치의 발광 패턴이 조절될 수 있다.Although not limited thereto, FIG. 1B illustrates an example in which the exposed region e is formed in a hole shape penetrating through the active layer 112 and the second conductive semiconductor layer 113. The first conductive semiconductor layer 111 and the first electrode 140 are electrically connected through the hole. Holes may be formed regularly as shown, but the present invention is not limited thereto. The current dispersion efficiency and the light emission pattern of the light emitting device may be adjusted according to the position, shape, and number of holes.

제2 전극(120)은 제2 도전형 반도체층(113) 상에 위치하며, 제2 도전형 반도체층(113)과 전기적으로 접속될 수 있다. 제2 전극(120)은 반사 금속층(121)을 포함하며, 나아가 장벽 금속층(122)을 포함할 수 있으며, 장벽 금속층(122)은 반사 금속층(121)의 상면 및 측면을 덮을 수 있다. 예컨대, 반사 금속층(121)의 패턴을 형성하고, 그 위에 장벽 금속층(122)을 형성함으로써, 장벽 금속층(122)이 반사 금속층(121)의 상면 및 측면을 덮도록 형성될 수 있다. 예를 들어, 반사 금속층(121)은 Ag, Ag 합금, Ni/Ag, NiZn/Ag, TiO/Ag 층을 증착 및 패터닝하여 형성될 수 있다.The second electrode 120 is positioned on the second conductive semiconductor layer 113 and may be electrically connected to the second conductive semiconductor layer 113. The second electrode 120 may include the reflective metal layer 121, and further include the barrier metal layer 122, and the barrier metal layer 122 may cover the top and side surfaces of the reflective metal layer 121. For example, by forming a pattern of the reflective metal layer 121 and forming the barrier metal layer 122 thereon, the barrier metal layer 122 may be formed to cover the top and side surfaces of the reflective metal layer 121. For example, the reflective metal layer 121 may be formed by depositing and patterning an Ag, Ag alloy, Ni / Ag, NiZn / Ag, or TiO / Ag layer.

한편, 장벽 금속층(122)은 Ni, Cr, Ti, Pt 또는 그 복합층으로 형성될 수 있으며, 반사 금속층(121)의 금속 물질이 확산되거나 오염되는 것을 방지한다. 또한, 제2 전극(120)은 ITO(Indium tin oxide), ZnO(Zinc oxide) 등을 포함할 수 있다. ITO 또는 ZnO는 광투과율이 높은 금속 산화물로 이루어져서, 제2 전극(120)에 의한 광의 흡수를 억제하여 발광 효율을 향상시킬 수 있다.제1 전극(140)은 제1 도전형 반도체층(111)에 전기적으로 접속될 수 있다. 제1 전극(140)은 질화물계 반도체 적층(110)을 덮을 수 있다. 또한, 제1 전극(140)은 제2 전극(120)을 노출시키는 개구부(140b)를 가질 수 있다. 제1 전극(140)은 개구부(140b)를 제외한 성장 기판(100)의 거의 전 영역 상부에 형성될 수 있다. 따라서, 제1 전극(140)을 통해 전류가 성장 기판(100)의 거의 전 영역 상부에 쉽게 분산될 수 있다. 제1 전극(140)은 Al층과 같은 고반사 금속층을 포함할 수 있으며, 고반사 금속층은 Ti, Cr 또는 Ni 등의 접착층 상에 형성될 수 있다. 또한, 고반사 금속층 상에 Ni, Cr, Au 등의 단층 또는 복합층 구조의 보호층이 형성될 수 있다. 제1 전극(140)은 예컨대, Ti/Al/Ti/Ni/Au 의 다층 구조를 가질 수 있다. 제1 전극(140)은 질화물계 반도체 적층(110) 상에 금속 물질을 증착하고, 이를 패터닝하여 형성될 수 있다.Meanwhile, the barrier metal layer 122 may be formed of Ni, Cr, Ti, Pt, or a composite layer thereof to prevent the metal material of the reflective metal layer 121 from being diffused or contaminated. In addition, the second electrode 120 may include indium tin oxide (ITO), zinc oxide (ZnO), or the like. Since ITO or ZnO is made of a metal oxide having a high light transmittance, light absorption by the second electrode 120 may be suppressed to improve luminous efficiency. The first electrode 140 may include a first conductive semiconductor layer 111. Can be electrically connected to. The first electrode 140 may cover the nitride based semiconductor stack 110. In addition, the first electrode 140 may have an opening 140b exposing the second electrode 120. The first electrode 140 may be formed on an almost entire area of the growth substrate 100 except for the opening 140b. Thus, current may be easily dispersed over the entire area of the growth substrate 100 through the first electrode 140. The first electrode 140 may include a high reflective metal layer such as an Al layer, and the high reflective metal layer may be formed on an adhesive layer such as Ti, Cr, or Ni. In addition, a protective layer of a single layer or a composite layer structure such as Ni, Cr, Au, or the like may be formed on the highly reflective metal layer. The first electrode 140 may have, for example, a multilayer structure of Ti / Al / Ti / Ni / Au. The first electrode 140 may be formed by depositing and patterning a metal material on the nitride-based semiconductor stack 110.

본 실시예에 따른 발광 장치는 하부 절연층(130)을 더 포함할 수 있다. 하부 절연층(130)은 질화물계 반도체 적층(110)의 상면 및 제2 전극(120)의 상면과 측면을 덮으며, 상기 질화물계 반도체 적층(110)과 상기 제1 전극(140) 사이에 위치하여 제1 전극(140)을 상기 제2 전극(120)으로부터 절연시킬 수 있다. 하부 절연층(130)은 특정 영역에서 제1 도전형 반도체층(111) 및 제2 도전형 반도체층(113)에 전기적 접속을 허용하기 위한 개구부(130a, 130b)를 갖는다. 예컨대, 하부 절연층(130)은 제1 도전형 반도체층(111)을 노출시키는 개구부(130a)와 제2 전극(120)을 노출시키는 개구부(130b)를 가질 수 있다. 하부 절연층(130)의 개구부(130b)는 제1 전극(140)의 개구부(140b)에 비해 상대적으로 좁은 면적을 가질 수 있다. 하부 절연층(130)은 화학기상증착(CVD) 등의 기술을 사용하여 SiO2 등의 산화막, SiNx 등의 질화막, MgF2의 절연막으로 형성될 수 있다. 하부 절연층(130)은 단일층으로 형성될 수 있으나, 이에 한정되는 것은 아니며 다중층으로 형성될 수도 있다. 나아가 하부 절연층(130)은 저굴절 물질층과 고굴절 물질층이 교대로 적층된 분포 브래그 반사기(DBR)를 포함할 수 있다. 예컨대, SiO2/TiO2 나 SiO2/Nb2O5 등의 층을 적층함으로써 반사율이 높은 절연 반사층을 형성할 수 있다.The light emitting device according to the present embodiment may further include a lower insulating layer 130. The lower insulating layer 130 covers the top surface and side surfaces of the nitride-based semiconductor stack 110 and the second electrode 120, and is positioned between the nitride-based semiconductor stack 110 and the first electrode 140. Thus, the first electrode 140 may be insulated from the second electrode 120. The lower insulating layer 130 has openings 130a and 130b for allowing electrical connection to the first conductive semiconductor layer 111 and the second conductive semiconductor layer 113 in a specific region. For example, the lower insulating layer 130 may have an opening 130a exposing the first conductive semiconductor layer 111 and an opening 130b exposing the second electrode 120. The opening 130b of the lower insulating layer 130 may have a relatively narrow area than the opening 140b of the first electrode 140. The lower insulating layer 130 may be formed of an oxide film such as SiO 2, a nitride film such as SiNx, or an insulating film of MgF 2 using a technique such as chemical vapor deposition (CVD). The lower insulating layer 130 may be formed of a single layer, but is not limited thereto and may be formed of multiple layers. Further, the lower insulating layer 130 may include a distributed Bragg reflector (DBR) in which the low refractive material layer and the high refractive material layer are alternately stacked. For example, an insulating reflective layer having a high reflectance can be formed by laminating layers such as SiO 2 / TiO 2 or SiO 2 / Nb 2 O 5.

본 실시예에 따른 발광 장치는 상부 절연층(150)을 더 포함할 수 있다. 상부 절연층(150)은 제1 전극(140)의 일부를 덮을 수 있다. 상부 절연층(150)은 제1 전극(140)을 노출시키는 개구부(150a) 및 제2 전극(120)을 노출시키는 개구부(150b)를 가질 수 있다. 상부 절연층(150)의 개구부(150b)는 제1 전극(140)의 개구부(140b) 및 하부 절연층(130)의 개구부(130b)에 비해 상대적으로 더 좁은 면적을 가질 수 있다. 이에 따라, 제1 전극(140)의 개구부(140b)의 측벽 뿐만 아니라 하부 절연층(130)의 개구부(130b)의 측벽들도 상부 절연층(150) 에 의해 덮일 수 있다. 이 경우, 제2 전극(120)을 습기 등으로부터 더 효과적으로 보호할 수 있다. 구체적으로, 제2 전극(120)이 장벽 금속층을 포함하지 않더라도 외부의 습기가 제2 전극(120)의 반사 금속층으로 침투하는 것을 방지할 수 있다. 그러나, 반드시 이에 한정되는 것은 아니며, 상부 절연층(150)은 제1 전극(140) 상에 산화물 절연층, 질화물 절연층 또는 폴리이미드, 테플론, 파릴렌 등의 폴리머를 증착 및 패터닝하여 형성할 수 있다.The light emitting device according to the present embodiment may further include an upper insulating layer 150. The upper insulating layer 150 may cover a portion of the first electrode 140. The upper insulating layer 150 may have an opening 150a exposing the first electrode 140 and an opening 150b exposing the second electrode 120. The opening 150b of the upper insulating layer 150 may have a relatively narrower area than the opening 140b of the first electrode 140 and the opening 130b of the lower insulating layer 130. Accordingly, sidewalls of the opening 130b of the lower insulating layer 130 may be covered by the upper insulating layer 150 as well as sidewalls of the opening 140b of the first electrode 140. In this case, the second electrode 120 may be more effectively protected from moisture. In detail, even if the second electrode 120 does not include the barrier metal layer, external moisture may be prevented from penetrating into the reflective metal layer of the second electrode 120. However, the present disclosure is not limited thereto, and the upper insulating layer 150 may be formed by depositing and patterning an oxide insulating layer, a nitride insulating layer, or a polymer such as polyimide, teflon, and parylene on the first electrode 140. have.

본 실시예에 따른 발광 소자의 본딩패드는 제1 전극(140) 및 제2 전극(120)과 각각 전기적으로 접속하는 제1 본딩패드(200a) 및 제2 본딩패드(200b)를 포함할 수 있다. 이에 한정되는 것은 아니지만, 도 1b를 참조하면, 제1 본딩패드(200a)는 상부 절연층(150)의 개구부(150a)에 형성된 제1연결전극을 통해 제1 전극(140)과 접속하고, 제2 본딩패드(200b)는 상부 절연층(150)의 개구부(150b)에 형성된 제2 연결전극을 통해 제2 전극(120)에 접속될 수 있다. 제1 본딩패드(200a) 및 제2 본딩패드(200b)는 제1 전극(140) 및 제2 전극(120)을 기판에 효과적으로 접속시키는 역할을 할 수 있다. 제1 본딩패드(200a) 및 제2 본딩패드(200b)은 동일 공정으로 함께 형성될 수 있으며, 예컨대 사진 및 식각 기술 또는 리프트 오프 기술을 사용하여 형성될 수 있다. 제1 본딩패드(200a) 및 제2 본딩패드(200b)는 예컨대 Ti, Cr, Ni 등의 접착층과 Al, Cu, Ag 또는 Au 등의 고전도 금속층을 포함할 수 있다.The bonding pad of the light emitting device according to the present exemplary embodiment may include a first bonding pad 200a and a second bonding pad 200b electrically connected to the first electrode 140 and the second electrode 120, respectively. . Although not limited thereto, referring to FIG. 1B, the first bonding pad 200a may be connected to the first electrode 140 through a first connection electrode formed in the opening 150a of the upper insulating layer 150. The 2 bonding pads 200b may be connected to the second electrode 120 through the second connection electrode formed in the opening 150b of the upper insulating layer 150. The first bonding pad 200a and the second bonding pad 200b may serve to effectively connect the first electrode 140 and the second electrode 120 to the substrate. The first bonding pad 200a and the second bonding pad 200b may be formed together in the same process, for example, by using a photo and etching technique or a lift off technique. The first bonding pad 200a and the second bonding pad 200b may include, for example, an adhesive layer such as Ti, Cr, or Ni, and a highly conductive metal layer such as Al, Cu, Ag, or Au.

한편, 본 발명의 본딩패드(200a, 200b)가 포함되는 발광소자는 다수의 분리된 활성층이 하나의 제1 도전형 반도체층(111)을 공유하는 형태일 수 있다.Meanwhile, the light emitting device including the bonding pads 200a and 200b of the present invention may have a form in which a plurality of separated active layers share one first conductive semiconductor layer 111.

실장기판과 본딩패드간의 본딩이 용이하도록 제1 본딩패드(200a)와 제2 본딩패드(200b)가 솔더볼 접촉 가능 영역(210) 내에서 최대한 넓은 면적을 차지하도록 설계하는 경우, 리플로우 공정 중에서 발생되는 보이드가 발광소자의 신뢰성을 떨어뜨리는바, 큰 보이드가 형성되지 않거나, 보이드가 전극 내 갇히지 않고 잘 빠져나갈 수 있는 전극 형상을 설계할 필요가 있게 되었다.When the first bonding pad 200a and the second bonding pad 200b are designed to occupy the largest area in the solder ball contactable area 210 to facilitate bonding between the mounting substrate and the bonding pad, they may occur during the reflow process. Since the voids deteriorate the reliability of the light emitting device, it is necessary to design an electrode shape in which large voids are not formed or the voids can escape well without being trapped in the electrode.

이러한 필요성에 의하여 본 발명에 따른 전극 형상을 갖는 발광소자는 도 1 내지 도 6에 나타난 바와 같이, 본딩패드(200a, 200b)가 실장기판 상에 솔더링되는 것으로서, 상기 본딩패드(200a, 200b)는 연결전극에 의하여 각각 제1 도전형 반도체층(111) 및 제2 도전형 반도체층(113)과 전기적으로 연결되고, 솔더볼 접촉 가능 영역(210)에 2개 이상의 선 형상의 본딩패드(200a, 200b)가 형성되어 있으며, 상기 2개 이상의 선 형상의 본딩패드(200a, 200b) 중 적어도 2개는 서로 대면하되, 서로 대면하는 2개의 본딩패드(200a, 200b) 사이에 비도전 영역(220)이 존재하는 것을 특징으로 한다.According to this necessity, the light emitting device having the electrode shape according to the present invention has the bonding pads 200a and 200b soldered onto the mounting substrate, as shown in FIGS. 1 to 6. Two or more linear bonding pads 200a and 200b are electrically connected to the first conductive semiconductor layer 111 and the second conductive semiconductor layer 113 by connecting electrodes, respectively, in the solder ball contactable area 210. Is formed, and at least two of the two or more linear bonding pads 200a and 200b face each other, and a non-conductive area 220 is disposed between the two bonding pads 200a and 200b facing each other. It is characterized by the presence.

여기에서 솔더볼 접촉 가능 영역(210)은 발광소자가 실장기판에 위치하는 솔더볼과 접촉할 수 있는 부분을 의미하는 것으로, 리플로우 공정에 의해 솔더가 용융되는 경우, 솔더볼 접촉 가능 영역(210)은 용융 솔더가 차지하게 되는 영역 내에 포함될 수 있다.Here, the solder ball contactable area 210 refers to a portion where the light emitting device may contact the solder ball located on the mounting substrate. When the solder is melted by the reflow process, the solder ball contactable area 210 is melted. It may be included in the area occupied by the solder.

제1 본딩패드(200a)에 해당되는 내용은 제2 본딩패드(200b)에도 그대로 적용되므로, 편의상 이하에서는 제1 본딩패드(200a)를 기준으로 본 발명의 본딩패드에 대하여 설명한다.Since the content corresponding to the first bonding pad 200a is also applied to the second bonding pad 200b as it is, the bonding pad of the present invention will be described below with reference to the first bonding pad 200a.

여기에서 선 형상의 본딩패드(200a)라 함은, 면적을 갖는 전극에 있어서 길이가 폭 보다 더 큰 형상인 것을 의미한다. Here, the linear bonding pad 200a means that the length of the electrode having an area is larger than the width.

여기에서 비도전 영역(220)은 본딩패드(200a)가 형성되지 않은 영역으로서, 상부 절연층(150)이 노출된 부분을 의미한다. 즉, 상부 절연층(150)과 본딩패드(200a)층 간 단차에 의한 공간이 이에 해당된다.Here, the non-conductive region 220 is a region where the bonding pad 200a is not formed and means a portion where the upper insulating layer 150 is exposed. That is, the space due to the step between the upper insulating layer 150 and the bonding pad 200a layer corresponds to this.

여기에서 본딩패드가 서로 대면한다는 의미는, 본딩패드가 서로 평행하게 마주보거나, 평행하지 않더라도 서로 마주보는 것으로 인정될 수 있는 것이라면 모두 해당된다.Herein, the bonding pads face each other as long as the bonding pads can be recognized as facing each other in parallel or even if they are not parallel.

즉, 본 발명의 발광소자에 포함되는 본딩패드(200a)는, 2개 이상의 선 형상의 본딩패드(200a) 중 적어도 2개는 서로 대면하되, 서로 대면하는 2개의 전극 사이에 비도전 영역(220)이 존재하게 됨으로써, 보이드 발생이 최소화된다.That is, in the bonding pad 200a of the light emitting device of the present invention, at least two of the two or more linear bonding pads 200a face each other, but the non-conductive area 220 is disposed between the two electrodes facing each other. By being present, void generation is minimized.

구체적으로, 도 1a에 나타난 바와 같이, 상기 2개 이상의 선 형상의 본딩패드(200a) 중 적어도 2개는 서로 이격될 수 있다. Specifically, as shown in FIG. 1A, at least two of the two or more linear bonding pads 200a may be spaced apart from each other.

또한, 도 2에 나타낸 바와 같이, 상기 2개 이상의 선 형상의 본딩패드(200a) 중 적어도 2개는 서로 연결될 수 있다. In addition, as shown in FIG. 2, at least two of the two or more linear bonding pads 200a may be connected to each other.

또한, 도 1a에 나타난 선 형상의 본딩패드는 도 3 내지 도 6에 나타난 바와 같이 연결부에 의해 어느 위치에서든 모두 연결될 수 있다. In addition, the linear bonding pads shown in FIG. 1A may be all connected at any position by the connection unit as shown in FIGS. 3 to 6.

도 3을 예로 들면, 3개의 연결부를 통해 4개의 선 형상의 본딩패드(200a)가 모두 연결된다. 즉, 도 3 내지 도 6에 나타난 바와 같이, 상기 2개 이상의 선 형상의 본딩패드(200a)가 n개(n≥2) 형성되어 있다면, 적어도 n-1개 이상의 연결부가 포함될 경우, 선 형상의 본딩패드(200a)가 모두 서로 연결될 수 있게 된다. 3, for example, all four bonding pads 200a having three linear shapes are connected to each other through three connection portions. That is, as shown in Figures 3 to 6, if the two or more linear bonding pads 200a are formed (n≥2), when at least n-1 or more connection parts are included, the linear shape The bonding pads 200a may be connected to each other.

도 3 내지 도 6에 나타난 형상 이외에도 선 형상의 본딩패드(200a)는 서로 대면하는 2개의 본딩패드 사이에 비도전 영역(220)이 존재한다는 조건만 만족하면 더 많은 연결부를 갖고 연결될 수도 있다.In addition to the shapes shown in FIGS. 3 to 6, the linear bonding pads 200a may be connected with more connections as long as the condition that the non-conductive area 220 exists between the two bonding pads facing each other.

즉, 본 발명의 발광소자에 포함되는 본딩패드는 기본적으로, 2개 이상의 선 형상의 본딩패드(200a) 중 적어도 2개는 서로 대면하되, 서로 대면하는 2개의 본딩패드(200a) 사이에 비도전 영역(220)이 존재하게 됨으로써, 절연층(150)의 상부가 노출되고, 이로써 절연층(150)과 본딩패드(200a)층 간 단차에 의한 공간이 마련되므로, 리플로우 공정에서 발생된 큰 보이드가 형성되지 않도록 설계된다.That is, in the bonding pad included in the light emitting device of the present invention, at least two of the two or more linear bonding pads 200a face each other, but are not electrically conductive between two bonding pads 200a facing each other. The presence of the region 220 exposes the upper portion of the insulating layer 150, thereby providing a space due to the step between the insulating layer 150 and the bonding pad 200a layer, thereby creating a large void generated in the reflow process. It is designed so that it is not formed.

도 7a, 7b에 도 3의 발광소자에 대하여 B-B', C-C' 방향으로 절단한 경우의 단면도를 각각 나타내었는바, 상기한 효과에 대하여 확인할 수 있다.7A and 7B show cross-sectional views of the light emitting device of FIG. 3 in the B-B 'and C-C' directions, respectively, and the above-described effects can be confirmed.

먼저 도 7a에서 확인할 수 있는 바와 같이, 본 발명의 제2 본딩패드(200b)는 서로 대면하는 선 형상의 본딩패드 사이에 비도전 영역(220)이 있고, 이는 즉 절연층(150)과 본딩패드(200b)층 간 단차에 의한 공간으로서, 해당 공간으로 리플로우 공정에서 발생된 보이드가 빠져나가게 되므로 제품의 신뢰성이 향상될 수 있게 된다. As shown in FIG. 7A, the second bonding pad 200b of the present invention has a non-conductive area 220 between linear bonding pads facing each other, that is, the insulating layer 150 and the bonding pad. (200b) As the space due to the step between the layers, the voids generated in the reflow process is released to the space, the reliability of the product can be improved.

마찬가지로, 도 7b에서 확인할 수 있는 바와 같이, 본 발명의 제1 본딩패드(200a)는 서로 대면하는 선 형상의 본딩패드 사이에 비도전 영역(220)이 있고, 이는 즉 절연층(150)과 본딩패드(200a)층 간 단차에 의한 공간으로서, 해당 공간으로 리플로우 공정에서 발생된 보이드가 빠져나가게 되므로 제품의 신뢰성이 향상될 수 있게 된다.Similarly, as can be seen in FIG. 7B, the first bonding pad 200a of the present invention has a non-conductive area 220 between the linear bonding pads facing each other, that is, the insulating layer 150 and the bonding layer. As the space due to the step between the pads 200a, the voids generated in the reflow process are released to the space, thereby improving the reliability of the product.

선 형상의 본딩패드(200a)의 폭(t)은 200um이하인 것이 바람직하다. 상기 범위를 초과하는 경우에는 본딩패드(200a) 내 솔더볼 접촉 가능 영역(210)에서 발생된 보이드 존재 지점으로부터 비도전 영역까지의 거리가 너무 멀어지므로, 보이드가 빠져나가지 못하고 본딩패드(200a) 내에 갇히게 되어, 실장기판과의 접합이 불량해지고 방열성능이 떨어지는 등, 발광소자의 신뢰도가 저하된다.The width t of the linear bonding pad 200a is preferably 200 μm or less. If the above range is exceeded, the distance from the void presence point generated in the solder ball contactable area 210 in the bonding pad 200a to the non-conductive area becomes too far, so that the void does not escape and is trapped in the bonding pad 200a. As a result, the reliability of the light emitting device is reduced, such as poor bonding to the mounting substrate and poor heat dissipation performance.

또한, 선 형상의 본딩패드(200a)의 폭(t)은 40㎛ 이상인 것이 바람직하다. 상기 범위 미만인 경우에는 본딩패드(200a)로의 전류주입량이 저하되어 발광소자의 발광효율이 감소되는 문제가 있다.Moreover, it is preferable that the width | variety t of the linear bonding pad 200a is 40 micrometers or more. If it is less than the above range there is a problem that the current injection amount to the bonding pad 200a is lowered to reduce the luminous efficiency of the light emitting device.

또한, 선 형상의 본딩패드(200a)의 면적은 솔더볼 접촉 가능 영역 면적(210)의 40% 이상인 것이 바람직하다. 상기 범위 미만인 경우에는 본딩패드(200a)로의 전류주입량이 저하되어 발광소자의 발광효율이 감소되는 문제가 있다. In addition, the area of the linear bonding pad 200a is preferably 40% or more of the solder ball contactable area 210. If it is less than the above range there is a problem that the current injection amount to the bonding pad 200a is lowered to reduce the luminous efficiency of the light emitting device.

본 발명의 본딩패드의 형상은 상술한 구체예에 한정되지 않고, 전극 폭 이상의 지름을 갖는 보이드는 발생하지 않도록 설계한다는 측면에서 당업자가 본 발명의 범위 내에서 얼마든지 변형이 가능하다.The shape of the bonding pad of the present invention is not limited to the above-described embodiments, and those skilled in the art can deform as many as possible within the scope of the present invention in terms of designing such that voids having a diameter of an electrode width or more are not generated.

이에 따라, 본 발명의 또 다른 실시예에 따른 전극 형상을 갖는 발광소자는, 도 8에 나타난 바와 같이, 본딩패드(200a, 200b)가 실장기판 상에 솔더링되는 것으로서, 상기 본딩패드(200a, 200b)는 연결전극에 의하여 각각 제1 도전형 반도체층 및 제2 도전형 반도체층과 전기적으로 접속된 제1 전극(140) 및 제2 전극(120)과 연결되고, 솔더볼 접촉 가능 영역(210) 중 일부에 본딩패드(200a)가 형성되어 있고, 솔더볼 접촉 가능 영역(210) 중 나머지에 보이드 탈출용 비도전 패턴(230)이 형성되어 있는 것을 특징으로 한다.Accordingly, in the light emitting device having the electrode shape according to another exemplary embodiment of the present invention, as shown in FIG. 8, bonding pads 200a and 200b are soldered onto the mounting substrate. ) Is connected to the first electrode 140 and the second electrode 120 electrically connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively, by the connecting electrode, and among the solder ball contactable areas 210. A bonding pad 200a is formed in a portion of the solder pad, and a non-conductive pattern 230 for void escape is formed in the remaining portion of the solder ball contactable region 210.

여기에서 보이드 탈출용 비도전 패턴(230)이란, 본딩패드(200a, 200b)가 형성되지 않은 영역에 대응되는 것으로서, 절연층(150)의 상부가 노출됨으로써 상부 절연층(150)과 본딩패드(200a, 200b)층 간 단차에 의한 공간이 마련되므로, 리플로우 공정에서 발생된 보이드가 빠져나갈 수 있는 공간의 형태를 의미한다.Here, the void escape non-conductive pattern 230 corresponds to an area in which the bonding pads 200a and 200b are not formed. The upper portion of the insulating layer 150 is exposed to expose the upper insulating layer 150 and the bonding pad ( 200a, 200b) because the space is provided by the step between the layers, it means a form of the space that the void generated in the reflow process can escape.

즉, 본 발명의 발광소자에 포함되는 본딩패드(200a, 200b)는 솔더볼 접촉 가능 영역(210) 중 일부에 본딩패드(200a, 200b)가 형성되어 있고, 솔더볼 접촉 가능 영역(210) 중 나머지에 보이드 탈출용 비도전 패턴(230)이 형성됨으로써, 비도전 패턴(230)을 통해 보이드가 빠져나갈 수 있으므로 보이드 발생이 최소화된다.That is, in the bonding pads 200a and 200b of the light emitting device of the present invention, the bonding pads 200a and 200b are formed in some of the solder ball contactable regions 210, and the remaining bonding pads 200a and 200b are formed in the remaining solder ball contactable regions 210. By forming the void escape non-conductive pattern 230, the voids may escape through the non-conductive pattern 230, thereby minimizing the occurrence of voids.

구체적으로, 도 8에 나타난 바와 같이, 비도전 패턴(230)은 본딩패드(200a, 200b) 내 임의의 점(P)에서 200㎛ 이내에 솔더볼 접촉 가능 영역(210)의 테두리부 방향으로 형성될 수 있다. 이를 통해 발생되는 보이드가 비도전 패턴(230)을 통해 바로 빠져나갈 수 있게 된다.Specifically, as shown in FIG. 8, the non-conductive pattern 230 may be formed in the direction of the edge of the solder ball contactable region 210 within 200 μm at an arbitrary point P in the bonding pads 200a and 200b. have. The void generated through this can be immediately exited through the non-conductive pattern 230.

즉, 전극 내 임의의 점(P)에서 200㎛가 초과해버리면 보이드가 빠져나가기 어려우므로 보이드가 빠져나갈 수 있도록 전극을 형성하지 않고 보이드 탈출용 비도전 패턴(230)을 형성하여 주는 것이 바람직하다.That is, if the thickness exceeds 200 μm at any point P in the electrode, it is difficult for the voids to escape, so it is preferable to form the void-free non-conductive pattern 230 for void escape without forming the electrode so that the voids can escape. .

상기 비도전 패턴(230)은 솔더볼 접촉 가능 영역(210)의 테두리부 방향으로 갈수록 넓어지는 테이퍼 형상일 수도 있다.The non-conductive pattern 230 may have a tapered shape that extends toward the edge of the solder ball contactable region 210.

비도전 패턴(230)이 솔더볼 접촉 가능 영역(210)의 테두리부 방향으로 갈수록 넓어지는 테이퍼 형상을 갖게 되는 경우, 보이드가 용이하게 빠져나갈 수 있게 된다.When the non-conductive pattern 230 has a tapered shape that becomes wider toward the edge portion of the solder ball contactable region 210, the voids may easily escape.

또한, 본딩패드(200a, 200b)의 면적은 솔더볼 접촉 가능 영역(210) 면적의 40% 이상인 것이 바람직하다. 상기 범위 미만인 경우에는 전극으로의 전류주입량이 저하되어 발광소자의 발광효율이 감소되는 문제가 있다.In addition, the area of the bonding pads 200a and 200b is preferably 40% or more of the area of the solder ball contactable area 210. If it is less than the above range, there is a problem that the current injection amount to the electrode is lowered to reduce the luminous efficiency of the light emitting device.

도 9 내지 도 14는 본 발명의 다른 실시예에 따른 발광소자를 설명하기 위한 평면도들 및 단면도들이다. 구체적으로, 도 9는 상기 발광소자의 평면을 도시하는 평면도이고, 도 10은 설명의 편의를 위하여 본딩패드들(200a, 200b)을 생략하여 도시한 평면도이며, 도 11은 설명의 편의를 위하여 본딩패드들(200a, 200b), 상부 절연층(150), 제1 전극(140) 및 하부 절연층(130)을 생략하여 도시한 평면도이다. 도 12는 도 9 내지 도 11의 평면도들의 A-A'선에 대응하는 부분의 단면을 도시하고, 도 13은 도 9 내지 도 11의 평면도들의 B-B'선에 대응하는 부분의 단면을 도시하며, 도 14는 도 9 내지 도 11의 평면도들의 C-C'선에 대응하는 부분의 단면을 도시한다.9 to 14 are plan views and cross-sectional views for describing a light emitting device according to another embodiment of the present invention. Specifically, FIG. 9 is a plan view illustrating a plane of the light emitting device, and FIG. 10 is a plan view omitting bonding pads 200a and 200b for convenience of description, and FIG. 11 is a bonding view for convenience of description. The pads 200a and 200b, the upper insulating layer 150, the first electrode 140, and the lower insulating layer 130 are omitted. FIG. 12 shows a cross section of a portion corresponding to line AA ′ of the top views of FIGS. 9 to 11, and FIG. 13 shows a cross section of a portion corresponding to line B-B ′ of the top views of FIGS. 9 to 11. 14 shows a cross section of a portion corresponding to line C-C 'of the plan views of FIGS.

본 실시예의 발광소자는 도 1 내지 도 8을 참조하여 설명한 실시예들과 비교하여, 본딩패드들(200a, 200b)의 구조 및 질화물계 반도체 적층(110)의 구조 등에서 차이가 있다. 이하 차이점을 중심으로 본 실시예의 발광소자에 관하여 설명하며, 동일한 구성에 대한 상세한 설명은 생략한다.The light emitting device according to the present embodiment has a difference in the structure of the bonding pads 200a and 200b and the structure of the nitride-based semiconductor stack 110 compared to the embodiments described with reference to FIGS. 1 to 8. Hereinafter, the light emitting device of the present embodiment will be described based on differences, and detailed descriptions of the same components will be omitted.

도 9 내지 도 14를 참조하면, 상기 발광소자는 질화물계 반도체 적층(110), 제1 전극(140), 제2 전극(120), 제1 본딩패드(200a) 및 제2 본딩패드(200b)를 포함한다. 나아가, 상기 발광소자는 하부 절연층(130), 상부 절연층(150) 및 기판(101)을 더 포함할 수 있다. 또한, 상기 발광소자는 사각형의 평면 형상을 가질 수 있다. 본 실시예에서, 상기 발광소자는 대체로 정방형의 평면 형상을 가질 수 있으며, 제1 측면(100a), 제2 측면(100b), 제1 측면(100a)에 반대하여 위치하는 제3 측면(100c), 및 제2 측면(100b)에 반대하여 위치하는 제4 측면(100d)을 포함할 수 있다. 다만 본 발명이 이에 한정되는 것은 아니다.9 to 14, the light emitting device includes a nitride based semiconductor stack 110, a first electrode 140, a second electrode 120, a first bonding pad 200a, and a second bonding pad 200b. It includes. Further, the light emitting device may further include a lower insulating layer 130, an upper insulating layer 150, and a substrate 101. In addition, the light emitting device may have a rectangular planar shape. In the present embodiment, the light emitting device may have a generally square planar shape, and the third side surface 100c positioned opposite to the first side surface 100a, the second side surface 100b, and the first side surface 100a. And a fourth side surface 100d positioned opposite to the second side surface 100b. However, the present invention is not limited thereto.

질화물계 반도체 적층(110)은 제1 도전형 반도체층(111), 제1 도전형 반도체층(111) 상에 위치하는 활성층(112), 활성층(112) 상에 위치하는 제2 도전형 반도체층(113)을 포함한다. 또한, 질화물계 반도체 적층(110)은 제1 도전형 반도체층(111)을 부분적으로 노출시키는 영역(110a, 110b)을 포함할 수 있다. 노출 영역(110a, 110b)의 위치, 형태, 및 개수에 따라 전류 분산 효율 및 발광 장치의 발광 패턴이 조절될 수 있다.The nitride based semiconductor layer 110 includes a first conductive semiconductor layer 111, an active layer 112 positioned on the first conductive semiconductor layer 111, and a second conductive semiconductor layer positioned on the active layer 112. (113). In addition, the nitride-based semiconductor stack 110 may include regions 110a and 110b partially exposing the first conductivity-type semiconductor layer 111. The current dispersion efficiency and the light emission pattern of the light emitting device may be adjusted according to the position, shape, and number of the exposed areas 110a and 110b.

도 11을 참조하면, 제1 도전형 반도체층(111)이 부분적으로 노출되는 영역(110a, 110b, 110c)은 홀들을 포함할 수 있다. 상기 홀들은 제1 홀(110a), 제2 홀(110b) 및 제3 홀(110c)을 포함할 수 있다. 제1 홀(110a), 제2 홀(110b) 및 제3 홀(110c)은 각각 복수로 형성될 수 있다. 제1 홀(110a)은 대체로 원형 또는 다각형의 평면 형상을 가질 수 있다. 제2 홀(110b)은 제1 홀(110a)과 대체로 동일한 형상을 가질 수 있다. 제3 홀(110c)은 제2 홀(110b)로부터 임의의 방향으로 연장되는 형태로 형성될 수 있다. 이때, 제3 홀(110c)과 제2 홀(110b)은 서로 연결될 수 있다. 또한, 제3 홀(110c)의 폭은 제1 홀(110a) 및 제2 홀(110b)의 폭보다 좁을 수 있다. Referring to FIG. 11, regions 110a, 110b and 110c where the first conductivity type semiconductor layer 111 is partially exposed may include holes. The holes may include a first hole 110a, a second hole 110b, and a third hole 110c. A plurality of first holes 110a, second holes 110b, and third holes 110c may be formed. The first hole 110a may have a planar shape of a generally circular or polygonal shape. The second hole 110b may have substantially the same shape as the first hole 110a. The third hole 110c may be formed to extend in an arbitrary direction from the second hole 110b. In this case, the third hole 110c and the second hole 110b may be connected to each other. In addition, the width of the third hole 110c may be smaller than the width of the first hole 110a and the second hole 110b.

예컨대, 도시된 바와 같이, 제1 홀(110a)은 원형의 평면 형상을 가지며, 복수로 형성될 수 있다. 제3 홀(110c)은 제2 홀(100b)로부터 연장되되, 제1 측면(100a)으로부터 제3 측면(100c)을 향해 연장되는 형태로 형성될 수 있으며, 복수로 형성될 수 있다. 제3 홀(110c)의 적어도 일부는 제1 본딩패드(200a)의 하부로부터 제2 본딩패드(200b)의 하부까지 연장되는 형태로 형성될 수 있다.For example, as shown, the first hole 110a has a circular planar shape and may be formed in plural. The third hole 110c may extend from the second hole 100b and may extend from the first side surface 100a toward the third side surface 100c and may be formed in plural. At least a portion of the third hole 110c may be formed to extend from a lower portion of the first bonding pad 200a to a lower portion of the second bonding pad 200b.

제2 전극(120)은 질화물계 반도체 적층(110) 상에 위치하여, 제2 도전형 반도체층(113)과 오믹 컨택할 수 있다. 제2 전극(120)은 제1 및 제2 홀(110a, 110b)을 노출시키는 개구부들을 포함할 수 있으며, 이에 따라, 제2 전극(120)은 제1 및 제2 홀(110a, 110b)과 이격될 수 있다.The second electrode 120 may be positioned on the nitride-based semiconductor stack 110 to make ohmic contact with the second conductive semiconductor layer 113. The second electrode 120 may include openings exposing the first and second holes 110a and 110b, so that the second electrode 120 may be connected to the first and second holes 110a and 110b. Can be spaced apart.

하부 절연층(130)은 질화물계 반도체 적층(110) 및 제2 전극(120)의 상면과 측면을 덮을 수 있다. 이때, 하부 절연층(130)은 특정 영역에서 제1 도전형 반도체층(111) 및 제2 도전형 반도체층(113)에 전기적 접속을 허용하기 위한 개구부들(130a, 130b)을 가질 수 있다. 예컨대, 하부 절연층(130)은 제1 도전형 반도체층(111)을 노출시키는 제1 개구부(130a)와 제2 전극(120)을 노출시키는 제2 개구부(130b)를 가질 수 있다.The lower insulating layer 130 may cover the top and side surfaces of the nitride based semiconductor stack 110 and the second electrode 120. In this case, the lower insulating layer 130 may have openings 130a and 130b for allowing electrical connection to the first conductive semiconductor layer 111 and the second conductive semiconductor layer 113 in a specific region. For example, the lower insulating layer 130 may have a first opening 130a exposing the first conductive semiconductor layer 111 and a second opening 130b exposing the second electrode 120.

제1 전극(140)은 제1 도전형 반도체층(111)에 전기적으로 접속될 수 있으며, 특히, 제1 도전형 반도체층(111)에 오믹 컨택할 수 있다. 제1 전극(140)은 제1 및 제2 홀(110a, 110b)을 통해서 제1 도전형 반도체층(111)과 전기적으로 접속될 수 있다. 이에 따라, 제1 전극(140)을 통해 질화물계 반도체 적층(110)으로 전류가 주입되는 부분은 제1 및 제2 홀(110a, 110b)의 위치 및 형태 등에 따라 제어될 수 있다. 또한, 제1 전극(140)은 제2 전극(120)을 노출시키는 개구부(140b)를 가질 수 있다. 제1 전극(140)은 개구부(140b)를 제외한 성장 기판(100)의 거의 전 영역 상부에 형성될 수 있다. The first electrode 140 may be electrically connected to the first conductive semiconductor layer 111, and in particular, the first electrode 140 may be in ohmic contact with the first conductive semiconductor layer 111. The first electrode 140 may be electrically connected to the first conductivity type semiconductor layer 111 through the first and second holes 110a and 110b. Accordingly, the portion into which the current is injected into the nitride based semiconductor stack 110 through the first electrode 140 may be controlled according to the position and shape of the first and second holes 110a and 110b. In addition, the first electrode 140 may have an opening 140b exposing the second electrode 120. The first electrode 140 may be formed on an almost entire area of the growth substrate 100 except for the opening 140b.

상부 절연층(150)은 제1 전극(140)의 일부를 덮을 수 있다. 상부 절연층(150)은 제1 전극(140)을 노출시키는 제3 개구부(150a) 및 제2 전극(120)을 노출시키는 제4 개구부(150b)를 포함할 수 있다. 상부 절연층(150)의 제4 개구부(150b)는 제1 전극(140)의 개구부(140b) 및 하부 절연층(130)의 개구부(130b)에 비해 상대적으로 더 좁은 면적을 가질 수 있다. 본 실시예에 있어서, 상부 절연층(150)은 제3 홀(110c) 상에 위치하는 제1 전극(140)의 부분을 덮는다. 이에 따라, 상부 절연층(150)의 제3 개구부(150a)는 제1 홀(110a) 및/또는 제2 홀(110b) 상에 위치하는 제1 전극(140)을 부분적으로 노출시킬 수 있다.The upper insulating layer 150 may cover a portion of the first electrode 140. The upper insulating layer 150 may include a third opening 150a exposing the first electrode 140 and a fourth opening 150b exposing the second electrode 120. The fourth opening 150b of the upper insulating layer 150 may have a relatively narrower area than the opening 140b of the first electrode 140 and the opening 130b of the lower insulating layer 130. In the present embodiment, the upper insulating layer 150 covers a portion of the first electrode 140 positioned on the third hole 110c. Accordingly, the third opening 150a of the upper insulating layer 150 may partially expose the first electrode 140 positioned on the first hole 110a and / or the second hole 110b.

제1 본딩패드(200a) 및 제2 본딩패드(200b)는 각각 제1 전극(140) 및 제2 전극(120)에 전기적으로 연결될 수 있다. 도 10 등을 참조하면, 제1 본딩패드(200a)는 제3 개구부(150a)들을 통해 제1 전극(140)과 접촉될 수 있고, 제2 본딩패드(200b)는 제4 개구부(150b)들을 통해 제2 전극(150)과 접촉될 수 있다. The first bonding pad 200a and the second bonding pad 200b may be electrically connected to the first electrode 140 and the second electrode 120, respectively. Referring to FIG. 10, the first bonding pad 200a may contact the first electrode 140 through the third openings 150a, and the second bonding pad 200b may contact the fourth openings 150b. It may be in contact with the second electrode 150 through.

제1 및 제2 본딩패드(200a, 200b)는, 상술한 실시예들에서 설명한 바와 같이, 솔더볼 접촉 가능 영역(210) 내에 위치하는 비도전 영역(220)을 포함한다. 제1 및 제2 본딩패드(200a, 200b)는 각각 발광소자의 일 측면에 나란하게 배치되는 부분과, 상기 부분으로부터 돌출되는 적어도 하나의 돌출부(240)를 포함할 수 있다. 예컨대, 제1 본딩패드(200a)는 발광소자의 제1 측면(100a)에 대체로 나란하게 배치되는 부분 및 상기 부분으로부터 돌출되는 세 개의 돌출부(240)를 포함할 수 있다. 제1 본딩패드(200a)의 비도전 영역(220)은 상기 세 개의 돌출부(240)들의 사이에 위치할 수 있다. 이와 유사하게, 제2 본딩패드(200b)는 발광소자의 제3 측면(100c)에 대체로 나란하게 배치되는 부분 및 상기 부분으로부터 돌출되는 세 개의 돌출부(240)를 포함할 수 있다. 제2 본딩패드(200b)의 비도전 영역(220)은 상기 세 개의 돌출부(240)들의 사이에 위치할 수 있다. 이러한 비도전 영역(220)을 통해 솔더링 과정에서 발생하는 보이드를 효과적으로 방지할 수 있다.The first and second bonding pads 200a and 200b include the non-conductive region 220 positioned in the solder ball contactable region 210, as described in the above embodiments. Each of the first and second bonding pads 200a and 200b may include a portion disposed side by side on one side of the light emitting device, and at least one protrusion 240 protruding from the portion. For example, the first bonding pad 200a may include a portion generally disposed side by side on the first side surface 100a of the light emitting device and three protrusions 240 protruding from the portion. The non-conductive area 220 of the first bonding pad 200a may be located between the three protrusions 240. Similarly, the second bonding pad 200b may include a portion generally disposed side by side on the third side surface 100c of the light emitting device and three protrusions 240 protruding from the portion. The non-conductive area 220 of the second bonding pad 200b may be located between the three protrusions 240. Through the non-conductive region 220, it is possible to effectively prevent voids generated during the soldering process.

제1 및 제2 본딩패드(200a, 200b) 각각의 발광소자의 일 측면에 나란하게 배치되는 부분의 폭(t2) 및 돌출부의 폭(t1)은 서로 동일할 수도 있고 다를 수도 있다. 다만, 상기 폭 t1 및 t2는, 상술한 실시예들에서 설명한 바와 같이, 40 내지 200㎛일 수 있다.The width t2 and the width t1 of the protrusions disposed side by side on one side of each of the first and second bonding pads 200a and 200b may be the same as or different from each other. However, the widths t1 and t2 may be 40 to 200 μm, as described in the above embodiments.

한편, 제1 본딩패드(200a)는 제1 도전형 반도체층(111)이 부분적으로 노출되는 영역(110a, 110b, 110c)을 통해 제1 도전형 반도체층(111)과 접촉되는 제1 전극(140)의 부분을 적어도 부분적으로 덮을 수 있다. 특히, 제1 본딩패드(200a)는 상대적으로 큰 폭을 갖는 제1 홀(110a) 및 제2 홀(110b) 상에 위치하는 제1 전극(140)의 부분을 덮도록 형성될 수 있다. 예컨대, 제1 본딩패드(200a)의 돌출부(240)들은 제1 홀(110a) 및 제2 홀(110b)이 형성된 위치에 대응하여 배치될 수 있다.The first bonding pad 200a may contact the first conductive semiconductor layer 111 through the regions 110a, 110b and 110c where the first conductive semiconductor layer 111 is partially exposed. A portion of 140 may be at least partially covered. In particular, the first bonding pad 200a may be formed to cover a portion of the first electrode 140 positioned on the first hole 110a and the second hole 110b having a relatively large width. For example, the protrusions 240 of the first bonding pad 200a may be disposed corresponding to the positions where the first holes 110a and the second holes 110b are formed.

솔더링하는 과정에서 발생하는 열, 스트레스 등으로 인하여, 제1 도전형 반도체층(111)이 부분적으로 노출되는 영역(110a, 110b, 110c)을 통해 제1 도전형 반도체층(111)과 제1 전극(140)이 접촉되는 계면에 스트레스 및 스트레인이 인가될 수 있다. 이러한 스트레스 및 스트레인으로 인하여 제1 전극(140)이 제1 도전형 반도체층(111)으로부터 박리되는 문제가 발생할 수 있는데, 이 경우, 발광 소자의 순방향 전압(Vf)이 상승하거나, 전류 분산이 원활하게 이루지지 못하는 현상이 발생할 수 있다. 이러한 경우 발광소자의 전기적 특성 및 광학적 특성의 저하로 인한 신뢰성 저하가 발생할 수 있다.Due to heat, stress, etc. generated during the soldering process, the first conductivity-type semiconductor layer 111 and the first electrode are formed through regions 110a, 110b, and 110c where the first conductivity-type semiconductor layer 111 is partially exposed. Stress and strain may be applied to the interface 140 contacts. Due to such stress and strain, a problem may occur in which the first electrode 140 is separated from the first conductive semiconductor layer 111. In this case, the forward voltage Vf of the light emitting device is increased or current dispersion is smooth. A phenomenon that cannot be achieved may occur. In this case, a decrease in reliability may occur due to a decrease in electrical and optical characteristics of the light emitting device.

본 실시예에 따르면, 제1 홀(110a) 및 제2 홀(110b) 상에 위치하는 제1 전극(140)의 부분이 제1 본딩패드(200a)에 의해 덮이도록 함으로써, 제1 전극(140)을 더욱 확실하게 고정할 수 있다. 이에 따라, 솔더링 과정에서 제1 전극(140)이 제1 도전형 반도체층(111)으로부터 박리되는 것을 효과적으로 방지할 수 있다. 또한, 제1 홀(110a) 및 제2 홀(110b)은 제3 홀(110c)에 비해 상대적으로 큰 폭을 가지므로, 제1 홀(110a) 및 제2 홀(110b)을 통한 전류 주입 효율이 저하되면 발광소자의 특성 저하가 더욱 심화될 수 있다. 본 실시예에 따르면, 이러한 제1 홀(110a) 및 제2 홀(110b) 상에 위치하는 제1 전극(140)의 부분을 제1 본딩패드(200a)로 덮음으로써, 더욱 효과적으로 발광소자의 신뢰성을 향상시킬 수 있다.According to the present exemplary embodiment, a portion of the first electrode 140 positioned on the first hole 110a and the second hole 110b is covered by the first bonding pad 200a to thereby cover the first electrode 140. ) Can be fixed more securely. Accordingly, it is possible to effectively prevent the first electrode 140 from being peeled from the first conductivity type semiconductor layer 111 in the soldering process. In addition, since the first hole 110a and the second hole 110b have a relatively larger width than the third hole 110c, the current injection efficiency through the first hole 110a and the second hole 110b. When this decreases, the deterioration of characteristics of the light emitting device may be further intensified. According to the present embodiment, by covering the portion of the first electrode 140 positioned on the first hole 110a and the second hole 110b with the first bonding pad 200a, reliability of the light emitting device more effectively. Can improve.

다시 도 9 내지 도 14를 참조하면, 제1 본딩패드(200a)와 제2 본딩패드(200b)는 대체로 대칭되는 형태로 형성될 수 있다. 다만, 본 발명이 이에 한정되는 것은 아니며, 제1 및 제2 본딩패드(200a, 200b)의 돌출부들(240)은 다양하게 변형될 수 있다. 예컨대, 도 15 및 도 16을 참조하면, 제1 본딩패드(200a)의 돌출부들(240)은 제1 및 제2 홀(110a, 110b) 상에 위치하도록 형성될 수 있다. 따라서 제1 본딩패드(200a)는 제2 본딩패드(200b)를 향하는 방향으로 돌출되는 세 개의 돌출부(240)를 포함할 수 있으며, 비도전 영역(220)은 세 개의 돌출부(240)들의 사이에 배치된다. 이에 대응하여, 제2 본딩패드(200b)는 제1 본딩패드(200a)의 비도전 영역(220)을 향하는 방향으로 돌출되는 돌출부(240)들을 포함할 수 있다. 본 실시예의 경우, 돌출부(240)들의 배치를 변경함으로써, 리플로우 공정에서 보이드가 외부로 배출되는 통로가 변경될 수 있다.9 to 14, the first bonding pad 200a and the second bonding pad 200b may be formed to be generally symmetrical. However, the present invention is not limited thereto, and the protrusions 240 of the first and second bonding pads 200a and 200b may be variously modified. For example, referring to FIGS. 15 and 16, the protrusions 240 of the first bonding pad 200a may be formed on the first and second holes 110a and 110b. Accordingly, the first bonding pad 200a may include three protrusions 240 protruding in the direction toward the second bonding pad 200b, and the non-conductive area 220 may be disposed between the three protrusions 240. Is placed. In response, the second bonding pad 200b may include protrusions 240 protruding in a direction toward the non-conductive area 220 of the first bonding pad 200a. In the present embodiment, by changing the arrangement of the protrusions 240, the passage through which the void is discharged to the outside in the reflow process can be changed.

본 실시예의 제1 및 제2 본딩패드(200a, 200b)는 이에 한정되지 않으며, 도 1 내지 도 8의 실시예들에서 설명한 바와 같이 다양하게 변경될 수 있다. 이때, 제1 및 제2 본딩패드(200a, 200b)는 제1 홀(110a) 및 제2 홀(110b)을 덮도록 형성함으로써, 본 실시예에 따른 발광소자의 신뢰성 향상 효과를 유사하게 얻을 수 있다.The first and second bonding pads 200a and 200b of the present exemplary embodiment are not limited thereto and may be variously changed as described in the embodiments of FIGS. 1 to 8. In this case, the first and second bonding pads 200a and 200b are formed to cover the first hole 110a and the second hole 110b, thereby similarly obtaining a reliability improvement effect of the light emitting device according to the present embodiment. have.

도 17은 본 발명의 일 실시예에 따른 발광 소자를 조명 장치에 적용한 예를 설명하기 위한 분해 사시도이다.17 is an exploded perspective view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a lighting device.

도 17을 참조하면, 본 실시예에 따른 조명 장치는, 확산 커버(1010), 발광 소자 모듈(1020) 및 바디부(1030)를 포함한다. 바디부(1030)는 발광 소자 모듈(1020)을 수용할 수 있고, 확산 커버(1010)는 발광 소자 모듈(1020)의 상부를 커버할 수 있도록 바디부(1030) 상에 배치될 수 있다.Referring to FIG. 17, the lighting apparatus according to the present embodiment includes a diffusion cover 1010, a light emitting device module 1020, and a body portion 1030. The body portion 1030 may accommodate the light emitting device module 1020, and the diffusion cover 1010 may be disposed on the body portion 1030 to cover the upper portion of the light emitting device module 1020.

바디부(1030)는 발광 소자 모듈(1020)을 수용 및 지지하여, 발광 소자 모듈(1020)에 전기적 전원을 공급할 수 있는 형태이면 제한되지 않는다. 예를 들어, 도시된 바와 같이, 바디부(1030)는 바디 케이스(1031), 전원 공급 장치(1033), 전원 케이스(1035), 및 전원 접속부(1037)를 포함할 수 있다. The body portion 1030 is not limited as long as it can receive and support the light emitting device module 1020 and supply electric power to the light emitting device module 1020. For example, as shown, the body portion 1030 may include a body case 1031, a power supply device 1033, a power case 1035, and a power connection portion 1037.

전원 공급 장치(1033)는 전원 케이스(1035) 내에 수용되어 발광 소자 모듈(1020)과 전기적으로 연결되며, 적어도 하나의 IC칩을 포함할 수 있다. 상기 IC칩은 발광 소자 모듈(1020)로 공급되는 전원의 특성을 조절, 변환 또는 제어할 수 있다. 전원 케이스(1035)는 전원 공급 장치(1033)를 수용하여 지지할 수 있고, 전원 공급 장치(1033)가 그 내부에 고정된 전원 케이스(1035)는 바디 케이스(1031)의 내부에 위치할 수 있다. 전원 접속부(115)는 전원 케이스(1035)의 하단에 배치되어, 전원 케이스(1035)와 결속될 수 있다. 이에 따라, 전원 접속부(1037)는 전원 케이스(1035) 내부의 전원 공급 장치(1033)와 전기적으로 연결되어, 외부 전원이 전원 공급 장치(1033)에 공급될 수 있는 통로 역할을 할 수 있다.The power supply device 1033 is accommodated in the power case 1035 and electrically connected to the light emitting device module 1020, and may include at least one IC chip. The IC chip may adjust, convert, or control the characteristics of the power supplied to the light emitting device module 1020. The power case 1035 may receive and support the power supply 1033, and the power case 1035 to which the power supply 1033 is fixed may be located inside the body case 1031. . The power connection unit 115 may be disposed at a lower end of the power case 1035 and may be coupled to the power case 1035. Accordingly, the power connection unit 1037 may be electrically connected to the power supply device 1033 inside the power case 1035 to serve as a path through which external power may be supplied to the power supply device 1033.

발광 소자 모듈(1020)은 기판(1023) 및 기판(1023) 상에 배치된 발광 소자(1021)를 포함한다. 발광 소자 모듈(1020)은 바디 케이스(1031) 상부에 마련되어 전원 공급 장치(1033)에 전기적으로 연결될 수 있다.The light emitting device module 1020 includes a substrate 1023 and a light emitting device 1021 disposed on the substrate 1023. The light emitting device module 1020 may be disposed on the body case 1031 and electrically connected to the power supply device 1033.

기판(1023)은 발광 소자(1021)를 지지할 수 있는 기판이면 제한되지 않으며, 예를 들어, 배선을 포함하는 인쇄회로기판일 수 있다. 기판(1023)은 바디 케이스(1031)에 안정적으로 고정될 수 있도록, 바디 케이스(1031) 상부의 고정부에 대응하는 형태를 가질 수 있다. 발광 소자(1021)는 상술한 본 발명의 실시예들에 따른 발광 소자들 중 적어도 하나를 포함할 수 있다. The substrate 1023 is not limited as long as it can support the light emitting device 1021. For example, the substrate 1023 may be a printed circuit board including wiring. The substrate 1023 may have a shape corresponding to the fixing portion of the upper portion of the body case 1031 so as to be stably fixed to the body case 1031. The light emitting device 1021 may include at least one of the light emitting devices according to the embodiments of the present invention described above.

확산 커버(1010)는 발광 소자(1021) 상에 배치되되, 바디 케이스(1031)에 고정되어 발광 소자(1021)를 커버할 수 있다. 확산 커버(1010)는 투광성 재질을 가질 수 있으며, 확산 커버(1010)의 형태 및 광 투과성을 조절하여 조명 장치의 지향 특성을 조절할 수 있다. 따라서 확산 커버(1010)는 조명 장치의 이용 목적 및 적용 태양에 따라 다양한 형태로 변형될 수 있다.The diffusion cover 1010 may be disposed on the light emitting device 1021, and may be fixed to the body case 1031 to cover the light emitting device 1021. The diffusion cover 1010 may have a translucent material and may adjust the directivity of the lighting device by adjusting the shape and the light transmittance of the diffusion cover 1010. Therefore, the diffusion cover 1010 may be modified in various forms according to the purpose of use of the lighting device and the application aspect.

도 18은 본 발명의 일 실시예에 따른 발광 소자를 디스플레이 장치에 적용한 예를 설명하기 위한 단면도이다. 18 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a display device.

본 실시예의 디스플레이 장치는 표시패널(2110), 표시패널(2110)에 광을 제공하는 백라이트 유닛 및, 상기 표시패널(2110)의 하부 가장자리를 지지하는 패널 가이드를 포함한다.The display device according to the present exemplary embodiment includes a display panel 2110, a backlight unit providing light to the display panel 2110, and a panel guide supporting a lower edge of the display panel 2110.

표시패널(2110)은 특별히 한정되지 않고, 예컨대, 액정층을 포함하는 액정표시패널일 수 있다. 표시패널(2110)의 가장자리에는 상기 게이트 라인으로 구동신호를 공급하는 게이트 구동 PCB가 더 위치할 수 있다. 여기서, 게이트 구동 PCB는 별도의 PCB에 구성되지 않고, 박막 트랜지스터 기판상에 형성될 수도 있다.The display panel 2110 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer. A gate driving PCB for supplying a driving signal to the gate line may be further located at the edge of the display panel 2110. Here, the gate driving PCB is not configured in a separate PCB, but may be formed on the thin film transistor substrate.

백라이트 유닛은 적어도 하나의 기판 및 복수의 발광 소자(2160)를 포함하는 광원 모듈을 포함한다. 나아가, 백라이트 유닛은 바텀커버(2180), 반사 시트(2170), 확산 플레이트(2131) 및 광학 시트들(2130)을 더 포함할 수 있다.The backlight unit includes a light source module including at least one substrate and a plurality of light emitting devices 2160. In addition, the backlight unit may further include a bottom cover 2180, a reflective sheet 2170, a diffusion plate 2131, and optical sheets 2130.

바텀커버(2180)는 상부로 개구되어, 기판, 발광 소자(2160), 반사 시트(2170), 확산 플레이트(2131) 및 광학 시트들(2130)을 수납할 수 있다. 또한, 바텀커버(2180)는 패널 가이드와 결합될 수 있다. 기판은 반사 시트(2170)의 하부에 위치하여, 반사 시트(2170)에 둘러싸인 형태로 배치될 수 있다. 다만, 이에 한정되지 않고, 반사 물질이 표면에 코팅된 경우에는 반사 시트(2170) 상에 위치할 수도 있다. 또한, 기판은 복수로 형성되어, 복수의 기판들이 나란히 배치된 형태로 배치될 수 있으나, 이에 한정되지 않고, 단일의 기판으로 형성될 수도 있다.The bottom cover 2180 may be opened upward to accommodate the substrate, the light emitting device 2160, the reflective sheet 2170, the diffusion plate 2131, and the optical sheets 2130. In addition, the bottom cover 2180 may be combined with the panel guide. The substrate may be disposed under the reflective sheet 2170 and be surrounded by the reflective sheet 2170. However, the present invention is not limited thereto, and when the reflective material is coated on the surface, the reflective material may be positioned on the reflective sheet 2170. In addition, a plurality of substrates may be formed, and the plurality of substrates may be arranged in a side-by-side arrangement, but is not limited thereto and may be formed of a single substrate.

발광 소자(2160)는 상술한 본 발명의 실시예들에 따른 발광 소자들 중 적어도 하나를 포함할 수 있다. 발광 소자(2160)들은 기판 상에 일정한 패턴으로 규칙적으로 배열될 수 있다. 또한, 각각의 발광 소자(2160) 상에는 렌즈(2210)가 배치되어, 복수의 발광 소자(2160)들로부터 방출되는 광을 균일성을 향상시킬 수 있다.The light emitting device 2160 may include at least one of the light emitting devices according to the embodiments of the present invention described above. The light emitting devices 2160 may be regularly arranged in a predetermined pattern on the substrate. In addition, a lens 2210 may be disposed on each light emitting device 2160 to improve uniformity of light emitted from the plurality of light emitting devices 2160.

확산 플레이트(2131) 및 광학 시트들(2130)은 발광 소자(2160) 상에 위치한다. 발광 소자(2160)로부터 방출된 광은 확산 플레이트(2131) 및 광학 시트들(2130)을 거쳐 면 광원 형태로 표시패널(2110)로 공급될 수 있다. The diffusion plate 2131 and the optical sheets 2130 are positioned on the light emitting device 2160. Light emitted from the light emitting device 2160 may be supplied to the display panel 2110 in the form of a surface light source through the diffusion plate 2131 and the optical sheets 2130.

이와 같이, 본 발명의 실시예들에 따른 발광 소자는 본 실시예와 같은 직하형 디스플레이 장치에 적용될 수 있다.As such, the light emitting device according to the embodiments of the present invention may be applied to the direct type display device as the present embodiment.

도 19는 일 실시예에 따른 발광 소자를 디스플레이 장치에 적용한 예를 설명하기 위한 단면도이다. 19 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment is applied to a display device.

본 실시예에 따른 백라이트 유닛이 구비된 디스플레이 장치는 영상이 디스플레이되는 표시패널(3210), 표시패널(3210)의 배면에 배치되어 광을 조사하는 백라이트 유닛을 포함한다. 나아가, 상기 디스플레이 장치는, 표시패널(3210)을 지지하고 백라이트 유닛이 수납되는 프레임(240) 및 상기 표시패널(3210)을 감싸는 커버(3240, 3280)를 포함한다.The display device including the backlight unit according to the present exemplary embodiment includes a display panel 3210 on which an image is displayed and a backlight unit disposed on a rear surface of the display panel 3210 to irradiate light. In addition, the display apparatus includes a frame 240 that supports the display panel 3210 and accommodates the backlight unit, and covers 3240 and 3280 that surround the display panel 3210.

표시패널(3210)은 특별히 한정되지 않고, 예컨대, 액정층을 포함하는 액정표시패널일 수 있다. 표시패널(3210)의 가장자리에는 상기 게이트 라인으로 구동신호를 공급하는 게이트 구동 PCB가 더 위치할 수 있다. 여기서, 게이트 구동 PCB는 별도의 PCB에 구성되지 않고, 박막 트랜지스터 기판상에 형성될 수도 있다. 표시패널(3210)은 그 상하부에 위치하는 커버(3240, 3280)에 의해 고정되며, 하부에 위치하는 커버(3280)는 백라이트 유닛과 결속될 수 있다.The display panel 3210 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer. A gate driving PCB for supplying a driving signal to the gate line may be further located at an edge of the display panel 3210. Here, the gate driving PCB is not configured in a separate PCB, but may be formed on the thin film transistor substrate. The display panel 3210 may be fixed by covers 3240 and 3280 positioned at upper and lower portions thereof, and the cover 3280 positioned at lower portions thereof may be coupled to the backlight unit.

표시패널(3210)에 광을 제공하는 백라이트 유닛은 상면의 일부가 개구된 하부 커버(3270), 하부 커버(3270)의 내부 일 측에 배치된 광원 모듈 및 상기 광원 모듈과 나란하게 위치되어 점광을 면광으로 변환하는 도광판(3250)을 포함한다. 또한, 본 실시예의 백라이트 유닛은 도광판(3250) 상에 위치되어 광을 확산 및 집광시키는 광학 시트들(3230), 도광판(3250)의 하부에 배치되어 도광판(3250)의 하부방향으로 진행하는 광을 표시패널(3210) 방향으로 반사시키는 반사시트(3260)를 더 포함할 수 있다.The backlight unit for providing light to the display panel 3210 may include a lower cover 3270 having a portion of an upper surface thereof, a light source module disposed on one side of the lower cover 3270, and positioned in parallel with the light source module to provide point light. And a light guide plate 3250 for converting to surface light. In addition, the backlight unit according to the present exemplary embodiment is disposed on the light guide plate 3250 and is disposed below the light guide plate 3250 and the optical sheets 3230 for diffusing and condensing light. The display apparatus may further include a reflective sheet 3260 reflecting in the direction of the display panel 3210.

광원 모듈은 기판(3220) 및 상기 기판(3220)의 일면에 일정 간격으로 이격되어 배치된 복수의 발광 소자(3110)를 포함한다. 기판(3220)은 발광 소자(3110)를 지지하고 발광 소자(3110)에 전기적으로 연결된 것이면 제한되지 않으며, 예컨대, 인쇄회로기판일 수 있다. 발광 소자(3110)는 상술한 본 발명의 실시예들에 따른 발광 소자를 적어도 하나 포함할 수 있다. 광원 모듈로부터 방출된 광은 도광판(3250)으로 입사되어 광학 시트들(3230)을 통해 표시패널(3210)로 공급된다. 도광판(3250) 및 광학 시트들(3230)을 통해, 발광 소자(3110)들로부터 방출된 점 광원이 면 광원으로 변형될 수 있다.The light source module includes a substrate 3220 and a plurality of light emitting devices 3110 spaced apart from each other by a predetermined interval on one surface of the substrate 3220. The substrate 3220 is not limited as long as it supports the light emitting device 3110 and is electrically connected to the light emitting device 3110. For example, the substrate 3220 may be a printed circuit board. The light emitting device 3110 may include at least one light emitting device according to the embodiments of the present invention described above. Light emitted from the light source module is incident to the light guide plate 3250 and is supplied to the display panel 3210 through the optical sheets 3230. Through the light guide plate 3250 and the optical sheets 3230, the point light sources emitted from the light emitting devices 3110 may be transformed into surface light sources.

이와 같이, 본 발명의 실시예들에 따른 발광 소자는 본 실시예와 같은 에지형 디스플레이 장치에 적용될 수 있다.As such, the light emitting device according to the embodiments of the present invention may be applied to the edge type display device as the present embodiment.

도 20은 본 발명의 일 실시예에 따른 발광 소자를 헤드 램프에 적용한 예를 설명하기 위한 단면도이다.20 is a cross-sectional view illustrating an example in which a light emitting device according to an embodiment of the present invention is applied to a head lamp.

도 20을 참조하면, 상기 헤드 램프는, 램프 바디(4070), 기판(4020), 발광 소자(4010) 및 커버 렌즈(4050)를 포함한다. 나아가, 상기 헤드 램프는, 방열부(4030), 지지랙(4060) 및 연결 부재(4040)를 더 포함할 수 있다.Referring to FIG. 20, the head lamp includes a lamp body 4070, a substrate 4020, a light emitting device 4010, and a cover lens 4050. Furthermore, the head lamp may further include a heat dissipation unit 4030, a support rack 4060, and a connection member 4040.

기판(4020)은 지지랙(4060)에 의해 고정되어 램프 바디(4070) 상에 이격 배치된다. 기판(4020)은 발광 소자(4010)를 지지할 수 있는 기판이면 제한되지 않으며, 예컨대, 인쇄회로기판과 같은 도전 패턴을 갖는 기판일 수 있다. 발광 소자(4010)는 기판(4020) 상에 위치하며, 기판(4020)에 의해 지지 및 고정될 수 있다. 또한, 기판(4020)의 도전 패턴을 통해 발광 소자(4010)는 외부의 전원과 전기적으로 연결될 수 있다. 또한, 발광 소자(4010)는 상술한 본 발명의 실시예들에 따른 발광 소자를 적어도 하나 포함할 수 있다. The substrate 4020 is fixed by the support rack 4060 and spaced apart from the lamp body 4070. The substrate 4020 is not limited as long as it is a substrate capable of supporting the light emitting device 4010. For example, the substrate 4020 may be a substrate having a conductive pattern such as a printed circuit board. The light emitting device 4010 is positioned on the substrate 4020 and may be supported and fixed by the substrate 4020. In addition, the light emitting device 4010 may be electrically connected to an external power source through the conductive pattern of the substrate 4020. In addition, the light emitting device 4010 may include at least one light emitting device according to the embodiments of the present invention described above.

커버 렌즈(4050)는 발광 소자(4010)로부터 방출되는 광이 이동하는 경로 상에 위치한다. 예컨대, 도시된 바와 같이, 커버 렌즈(4050)는 연결 부재(4040)에 의해 발광 소자(4010)로부터 이격되어 배치될 수 있고, 발광 소자(4010)로부터 방출된 광을 제공하고자하는 방향에 배치될 수 있다. 커버 렌즈(4050)에 의해 헤드 램프로부터 외부로 방출되는 광의 지향각 및/또는 색상이 조절될 수 있다. 한편, 연결 부재(4040)는 커버 렌즈(4050)를 기판(4020)과 고정시킴과 아울러, 발광 소자(4010)를 둘러싸도록 배치되어 발광 경로(4045)를 제공하는 광 가이드 역할을 할 수도 있다. 이때, 연결 부재(4040)는 광 반사성 물질로 형성되거나, 광 반사성 물질로 코팅될 수 있다. 한편, 방열부(4030)는 방열핀(4031) 및/또는 방열팬(4033)을 포함할 수 있고, 발광 소자(4010) 구동 시 발생하는 열을 외부로 방출시킨다.The cover lens 4050 is positioned on a path along which light emitted from the light emitting element 4010 travels. For example, as shown, the cover lens 4050 may be disposed spaced apart from the light emitting element 4010 by the connecting member 4040, and may be disposed in a direction to provide light emitted from the light emitting element 4010. Can be. By the cover lens 4050, the direction angle and / or color of the light emitted from the head lamp to the outside may be adjusted. Meanwhile, the connection member 4040 may fix the cover lens 4050 with the substrate 4020 and may be disposed to surround the light emitting device 4010 to serve as a light guide for providing the light emitting path 4045. In this case, the connection member 4040 may be formed of a light reflective material or coated with a light reflective material. Meanwhile, the heat dissipation unit 4030 may include a heat dissipation fin 4031 and / or a heat dissipation fan 4033, and emits heat generated when the light emitting device 4010 is driven to the outside.

이와 같이, 본 발명의 실시예들에 따른 발광 소자는 본 실시예와 같은 헤드 램프, 특히, 차량용 헤드 램프에 적용될 수 있다.As such, the light emitting device according to the embodiments of the present invention may be applied to the head lamp, in particular, a vehicle head lamp as in the present embodiment.

이상에서는 본 발명의 실시예를 중심으로 설명하였지만, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 기술자의 수준에서 다양한 변경이나 변형을 가할 수 있다. 이러한 변경과 변형은 본 발명이 제공하는 기술 사상의 범위를 벗어나지 않는 한 본 발명에 속한다고 할 수 있다. 따라서 본 발명의 권리범위는 이하에 기재되는 청구범위에 의해 판단되어야 할 것이다.Although the above has been described with reference to the embodiments of the present invention, various changes and modifications can be made at the level of those skilled in the art. Such changes and modifications can be said to belong to the present invention without departing from the scope of the technical idea provided by the present invention. Therefore, the scope of the present invention will be determined by the claims described below.

Claims (23)

본딩패드가 실장기판 상에 솔더링되는 발광소자에 있어서,In the light emitting device in which the bonding pad is soldered on the mounting substrate, 상기 본딩패드는 연결전극에 의하여 각각 제1 도전형 반도체층 및 제2 도전형 반도체층과 전기적으로 접속된 제1 전극 및 제2 전극과 연결되고,The bonding pad is connected to the first electrode and the second electrode electrically connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer by connecting electrodes, respectively. 솔더볼 접촉 가능 영역에 2개 이상의 선 형상의 본딩패드가 형성되어 있으며,Two or more linear bonding pads are formed in the solder ball contact area. 상기 2개 이상의 선 형상의 본딩패드 중 적어도 2개는 서로 대면하되, 서로 대면하는 2개의 본딩패드 사이에 비도전 영역이 존재하는 것을 특징으로 하는 발광소자.At least two of the two or more linear bonding pads face each other, and a non-conductive area is present between the two bonding pads facing each other. 제1항에 있어서,The method of claim 1, 상기 2개 이상의 선 형상의 본딩패드 중 적어도 2개는 서로 이격되어 있는 것을 특징으로 하는 발광소자.At least two of the two or more linear bonding pads are spaced apart from each other. 제1항에 있어서,The method of claim 1, 상기 2개 이상의 선 형상의 본딩패드 중 적어도 2개는 서로 연결되어 있는 것을 특징으로 하는 발광소자.At least two of the two or more linear bonding pads are connected to each other. 제1항에 있어서,The method of claim 1, 상기 2개 이상의 선 형상의 본딩패드는 n개(n≥2) 형성되어 있고, 적어도 n-1개 이상의 연결부를 포함하여 서로 연결되어 있는 것을 특징으로 하는 발광소자.The two or more linear bonding pads are formed n (n≥2), and the light emitting device, characterized in that connected to each other, including at least n-1 or more. 제1항에 있어서,The method of claim 1, 상기 선 형상의 본딩패드의 폭은 200㎛ 이하인 것을 특징으로 하는 발광소자.The linear bonding pad has a width of 200 μm or less. 제1항에 있어서,The method of claim 1, 상기 선 형상의 본딩패드의 폭은 40㎛ 이상인 것을 특징으로 하는 발광소자.The linear bonding pad has a width of 40 μm or more. 제1항에 있어서,The method of claim 1, 상기 선 형상의 본딩패드의 면적은 솔더볼 접촉 가능 영역 면적의 40% 이상인 것을 특징으로 하는 발광소자.And the area of the linear bonding pad is 40% or more of the solder ball contactable area. 제 1항에 있어서,The method of claim 1, 상기 연결전극은 본딩패드와 제1 전극을 전기적으로 연결하는 제1 연결전극 및 본딩패드와 제2 전극을 전기적으로 연결하는 제2 연결전극을 포함하는 것을 특징으로 하는 발광소자.The connection electrode includes a first connection electrode electrically connecting the bonding pad and the first electrode and a second connection electrode electrically connecting the bonding pad and the second electrode. 제 8항에 있어서,The method of claim 8, 상기 제1 연결전극은 제1 전극상에 위치하는 상부 절연층의 개구부에 형성된 것을 특징으로 하는 발광소자.The first connecting electrode is formed in the opening of the upper insulating layer positioned on the first electrode. 제 8항에 있어서,The method of claim 8, 상기 제2 연결전극은 제2 전극상에 위치하는 하부 절연층 및 제1 전극상에 위치하는 상부 절연층의 개구부에 형성되는 것을 특징으로 하는 발광소자.And the second connection electrode is formed in an opening of a lower insulating layer on the second electrode and an upper insulating layer on the first electrode. 제 1항에 있어서,The method of claim 1, 상기 본딩패드는 서로 이격된 제1 본딩패드 및 제2 본딩패드를 포함하고,The bonding pad includes a first bonding pad and a second bonding pad spaced apart from each other, 상기 발광소자는 상기 제1 본딩패드에 전기적으로 연결되는 제1 도전형 반도체층과, 상기 제2 본딩패드에 전기적으로 연결되는 제2 도전형 반도체층과, 상기 제1 도전형 반도체층과 상기 제2 도전형 반도체층 사이에 개재되는 활성층을 포함하되, The light emitting device includes a first conductive semiconductor layer electrically connected to the first bonding pad, a second conductive semiconductor layer electrically connected to the second bonding pad, the first conductive semiconductor layer and the first conductive layer. 2 includes an active layer interposed between the conductive semiconductor layer, 상기 활성층이 2개 이상으로 분리된 것을 특징으로 하는 발광소자.Light emitting device, characterized in that the active layer is separated into two or more. 본딩패드가 실장기판 상에 솔더링되는 발광소자에 있어서,In the light emitting device in which the bonding pad is soldered on the mounting substrate, 상기 본딩패드는 연결전극에 의하여 각각 제1 도전형 반도체층 및 제2 도전형 반도체층과 전기적으로 접속된 제1 전극 및 제2 전극과 연결되고,The bonding pad is connected to the first electrode and the second electrode electrically connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer by connecting electrodes, respectively. 솔더볼 접촉 가능 영역 중 일부에 본딩패드가 형성되어 있고, 솔더볼 접촉 가능 영역 중 나머지에 보이드 탈출용 비도전 패턴이 형성되어 있는 것을 특징으로 하는 발광소자.A bonding pad is formed in a part of the solder ball contactable area, and a non-conductive pattern for void escape is formed in the rest of the solder ball contactable area. 제12항에 있어서,The method of claim 12, 상기 비도전 패턴은 본딩패드 전극 내 임의의 점에서 200㎛ 이내에 솔더볼 접촉 가능 영역의 테두리부 방향으로 형성되는 것을 특징으로 하는 발광소자.And the non-conductive pattern is formed in the direction of the edge of the solder ball contactable region within 200 μm at any point in the bonding pad electrode. 제13항에 있어서,The method of claim 13, 상기 비도전 패턴은 상기 솔더볼 접촉 가능 영역의 테두리부 방향으로 갈수록 넓어지는 테이퍼 형상인 것을 특징으로 하는 발광소자.The non-conductive pattern is a light emitting device, characterized in that the tapered shape that increases toward the edge portion of the solder ball contactable region. 제12항에 있어서,The method of claim 12, 상기 본딩패드의 면적은 솔더볼 접촉 가능 영역 면적의 40% 이상인 것을 특징으로 하는 발광소자.The area of the bonding pad is light emitting device, characterized in that more than 40% of the solder ball contact area. 제 12항에 있어서,The method of claim 12, 상기 연결전극은 본딩패드와 제1 전극을 전기적으로 연결하는 제1 연결전극 및 본딩패드와 제2 전극을 전기적으로 연결하는 제2 연결전극을 포함하는 것을 특징으로 하는 발광소자.The connection electrode includes a first connection electrode electrically connecting the bonding pad and the first electrode and a second connection electrode electrically connecting the bonding pad and the second electrode. 제 16항에 있어서,The method of claim 16, 상기 제1 연결전극은 제1 전극상에 위치하는 상부 절연층의 개구부에 형성된 것을 특징으로 하는 발광소자.The first connecting electrode is formed in the opening of the upper insulating layer positioned on the first electrode. 제 16항에 있어서,The method of claim 16, 상기 제2 연결전극은 제2 전극상에 위치하는 하부 절연층 및 제1 전극상에 위치하는 상부 절연층의 개구부에 형성되는 것을 특징으로 하는 발광소자.And the second connection electrode is formed in an opening of a lower insulating layer on the second electrode and an upper insulating layer on the first electrode. 제12항에 있어서,The method of claim 12, 상기 본딩패드는 서로 이격된 제1 본딩패드 및 제2 본딩패드를 포함하고,The bonding pad includes a first bonding pad and a second bonding pad spaced apart from each other, 상기 발광소자는 상기 제1 본딩패드와 전기적으로 연결되는 제1 도전형 반도체층과, 상기 제2 본딩패드와 전기적으로 연결되는 제2 도전형 반도체층과, 상기 제1 도전형 반도체층과 상기 제2 도전형 반도체층사이에 개재되는 활성층을 포함하되, The light emitting device includes a first conductive semiconductor layer electrically connected to the first bonding pad, a second conductive semiconductor layer electrically connected to the second bonding pad, the first conductive semiconductor layer and the first conductive layer. An active layer interposed between the two conductive semiconductor layers, 상기 활성층이 2개 이상으로 분리된 것을 특징으로 하는 발광소자.Light emitting device, characterized in that the active layer is separated into two or more. 제1항에 있어서,The method of claim 1, 상기 제1 도전형 반도체층, 상기 제2 도전형 반도체층 및 상기 제1 및 제2 도전형 반도체층의 사이에 위치하는 활성층을 포함하며, 상기 제2 도전형 반도체층 및 활성층을 관통하여 상기 제1 도전형 반도체층을 노출시키는 영역을 포함하는 질화물계 반도체 적층을 더 포함하고,An active layer disposed between the first conductive semiconductor layer, the second conductive semiconductor layer, and the first and second conductive semiconductor layers, and penetrating through the second conductive semiconductor layer and the active layer; The semiconductor device may further include a nitride based semiconductor laminate including a region exposing the first conductive semiconductor layer. 상기 제1 도전형 반도체층을 노출시키는 영역은 홀들을 포함하며,The region exposing the first conductivity type semiconductor layer includes holes, 상기 제1 전극은 상기 홀들을 통해 상기 제1 도전형 반도체층과 접촉하고,The first electrode is in contact with the first conductivity type semiconductor layer through the holes, 상기 홀들 중 적어도 일부의 홀 상에 위치하는 제1 전극의 부분은 상기 본딩패드에 의해 덮이는 발광소자.A portion of the first electrode positioned on at least some of the holes is covered by the bonding pads. 제20항에 있어서,The method of claim 20, 상기 홀들은,The holes, 제1 홀;A first hole; 상기 제1 홀과 이격된 제2 홀; 및A second hole spaced apart from the first hole; And 상기 제2 홀과 연결되며, 상기 제2 홀로부터 연장된 제3 홀을 포함하고,A third hole connected to the second hole and extending from the second hole, 상기 제3 홀의 폭은 상기 제1 홀 및 제2 홀의 폭보다 작은 발광소자.The width of the third hole is smaller than the width of the first hole and the second hole. 제21항에 있어서,The method of claim 21, 상기 본딩패드는 상기 제1 전극과 연결된 제1 본딩패드, 및 상기 제2 전극과 연결된 제2 본딩패드를 포함하고,The bonding pad includes a first bonding pad connected to the first electrode, and a second bonding pad connected to the second electrode. 상기 제1 본딩패드는 상기 제1 홀 및 제2 홀 상에 위치하는 제1 전극의 부분을 덮는 발광소자.The first bonding pad covers a portion of the first electrode positioned on the first hole and the second hole. 제22항에 있어서,The method of claim 22, 상기 제3 홀은 상기 제2 홀로부터 상기 제2 본딩패드를 향하는 방향으로 연장되고,The third hole extends in a direction from the second hole toward the second bonding pad, 상기 제3 홀의 적어도 일부는 상기 제1 및 제2 본딩패드의 사이의 하부에 위치하는 발광소자.At least a portion of the third hole is a light emitting device positioned below the first and second bonding pads.
PCT/KR2015/008841 2014-08-28 2015-08-24 Light emitting diode Ceased WO2016032194A1 (en)

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US15/942,510 US10090450B2 (en) 2014-08-28 2018-03-31 Light emitting device
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US15/995,014 US10205077B2 (en) 2014-08-28 2018-05-31 Light emitting device
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