WO2016019606A1 - Array substrate and manufacturing method therefor - Google Patents
Array substrate and manufacturing method therefor Download PDFInfo
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- WO2016019606A1 WO2016019606A1 PCT/CN2014/084942 CN2014084942W WO2016019606A1 WO 2016019606 A1 WO2016019606 A1 WO 2016019606A1 CN 2014084942 W CN2014084942 W CN 2014084942W WO 2016019606 A1 WO2016019606 A1 WO 2016019606A1
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- insulating layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
Definitions
- the present invention relates to the field of displays, and in particular to an array substrate and a method of fabricating the same.
- Liquid crystal display devices have been widely used in people's work and life. With the development of liquid crystal display technology, people have higher and higher requirements on the image quality of displays, such as resolution, brightness, viewing angle, color saturation and screen response speed. Wait.
- a conventional liquid crystal display device fabricates a color filter substrate and an array substrate on different substrates, wherein the color filter substrate includes a common electrode, RGB (red, green, blue) color film (color film photoresist), and black matrix (BM, Black).
- the array substrate includes a thin film transistor, a peripheral line, and a pixel electrode; and then the color filter substrate and the array substrate are subjected to a box operation to form a liquid crystal display panel.
- the manufacturing process of the conventional liquid crystal display panel is simple, when the color film substrate and the array substrate are subjected to the box operation, the light leakage due to the alignment error and the technical problem of the aperture ratio are easily reduced.
- the manufacturer of the liquid crystal display device has developed a COA (Color Film On). Array) Array substrate, COA array substrate, the color film substrate and the array substrate are disposed on the same glass substrate, so that no alignment error occurs during the operation of the box, and the aperture ratio of the liquid crystal display panel is improved.
- COA Color Film On
- the existing COA array substrate needs to adhere the color film photoresist (organic material) to the insulating material (inorganic material) of the array substrate, and it is easy to cause peeling phenomenon of the color film photoresist.
- An object of the present invention is to provide an array substrate in which the color film resist is not easily detached from the array substrate and a manufacturing method thereof, and to solve the technical problem that the color film photoresist in the existing array substrate is easily detached from the array substrate.
- An embodiment of the present invention provides an array substrate, including:
- a glass substrate on which a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a color film photoresist layer, a third insulating layer, and a transparent electrode layer are sequentially disposed;
- a thin film transistor configured to transmit the data signal to the pixel electrode according to the scan signal
- the first insulating layer is used for insulating the first metal layer and the second metal layer;
- the third insulating layer is used for performing the color film photoresist layer and the transparent electrode layer Insulating treatment;
- the second insulating layer is for insulating treatment of the second metal layer and the color film photoresist layer;
- the second insulating layer comprises a silicon nitride insulating layer and disposed on the silicon nitride a silicon dioxide insulating layer on the insulating layer;
- the second metal layer includes a data line for transmitting a data signal
- the first metal layer includes a scan line for transmitting a scan signal
- the transparent electrode layer includes a pixel electrode for displaying the data signal
- the color film photoresist layer comprises a color film photoresist.
- the silicon nitride insulating layer of the second insulating layer has a thickness of 50 nm to 100 nm; and the thickness of the silicon oxide insulating layer of the second insulating layer is 50 Nano to 100 nanometers.
- the third insulating layer is a silicon nitride insulating layer or a silicon dioxide insulating layer, and the third insulating layer has a thickness of 100 nm to 200 nm.
- the first insulating layer is a silicon nitride insulating layer, and the first insulating layer has a thickness of 100 nm to 300 nm.
- the color film photoresist layer has a thickness of 500 nm to 2000 nm.
- the transparent electrode layer is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer, and the transparent electrode layer has a thickness of 10 nm to 100 nm.
- An embodiment of the present invention provides an array substrate, including:
- a glass substrate on which a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a color film photoresist layer, a third insulating layer, and a transparent electrode layer are sequentially disposed;
- the first insulating layer is used for insulating the first metal layer and the second metal layer; the third insulating layer is used for performing the color film photoresist layer and the transparent electrode layer Insulating treatment; the second insulating layer is for insulating treatment of the second metal layer and the color film photoresist layer; the second insulating layer comprises a silicon nitride insulating layer and disposed on the silicon nitride A silicon dioxide insulating layer on the insulating layer.
- the second metal layer includes a data line for transmitting a data signal;
- the first metal layer includes a scan line for transmitting a scan signal; and
- the transparent electrode layer includes a display for display a pixel electrode of the data signal;
- the color film photoresist layer comprises a color film photoresist.
- the array substrate further includes:
- a thin film transistor for transmitting the data signal to the pixel electrode according to the scan signal.
- the silicon nitride insulating layer of the second insulating layer has a thickness of 50 nm to 100 nm; and the thickness of the silicon oxide insulating layer of the second insulating layer is 50 Nano to 100 nanometers.
- the third insulating layer is a silicon nitride insulating layer or a silicon dioxide insulating layer, and the third insulating layer has a thickness of 100 nm to 200 nm.
- the first insulating layer is a silicon nitride insulating layer, and the first insulating layer has a thickness of 100 nm to 300 nm.
- the color film photoresist layer has a thickness of 500 nm to 2000 nm.
- the transparent electrode layer is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer, and the transparent electrode layer has a thickness of 10 nm to 100 nm.
- the embodiment of the invention further provides a method for fabricating an array substrate, which comprises:
- the second insulating layer includes a silicon nitride insulating layer and a silicon dioxide insulating layer disposed on the silicon nitride insulating layer.
- the silicon nitride insulating layer of the second insulating layer has a thickness of 50 nm to 100 nm; and the silicon dioxide insulating layer of the second insulating layer The thickness is from 50 nanometers to 100 nanometers.
- the color film photoresist layer has a thickness of 500 nm to 2000 nm.
- the third insulating layer is a silicon nitride insulating layer or a silicon dioxide insulating layer, and the third insulating layer has a thickness of 100 nm to 200 nm.
- the first insulating layer is a silicon nitride insulating layer, and the first insulating layer has a thickness of 100 nm to 300 nm.
- the transparent electrode layer is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer, and the transparent electrode layer has a thickness of 10 nm to 100 nm.
- the array substrate of the present invention and the manufacturing method thereof are provided by providing a second insulating layer having a silicon nitride insulating layer and a silicon dioxide insulating layer, and setting the color film photoresist On the silicon dioxide insulating layer of the second insulating layer, the photoresist of the color film is not easily detached from the second insulating layer; the technical problem that the color film resist of the existing array substrate is easily detached from the array substrate is solved.
- FIG. 1 is a schematic structural view of a preferred embodiment of an array substrate of the present invention
- FIG. 2 is a flow chart of a preferred embodiment of a method of fabricating an array substrate of the present invention
- 3A-3F are schematic views showing the fabrication of a preferred embodiment of the method of fabricating the array substrate of the present invention.
- FIG. 1 is a schematic structural view of a preferred embodiment of an array substrate of the present invention.
- the array substrate 10 of the preferred embodiment includes a glass substrate 11, a data line, a scan line, a pixel electrode, a thin film transistor, and a color film photoresist 15.
- the first metal layer, the first insulating layer 13, the semiconductor layer, the second metal layer, the second insulating layer, the color film photoresist layer, the third insulating layer 16, and the transparent electrode layer are sequentially disposed on the glass substrate 11.
- the scan line is disposed on the first metal layer for transmitting the scan signal;
- the data line is disposed on the second metal layer for transmitting the data signal;
- the pixel electrode 17 is disposed on the transparent electrode layer for displaying the data signal;
- the thin film transistor The source 122, the drain 123, the gate 121, and the channel 124 are disposed, wherein the gate 121 of the thin film transistor is disposed on the first metal layer and connected to the scan line; and the source 122 of the thin film transistor is disposed on the second metal layer Upper, connected to the data line;
- the drain electrode 123 of the thin film transistor is disposed on the second metal layer and connected to the pixel electrode 17; and
- the channel 124 of the thin film transistor is disposed on the semiconductor layer.
- the first insulating layer 13 is used for insulating the data line and the scan line
- the third insulating layer 16 is used for insulating the color film photoresist 15 and the pixel electrode 17
- the second insulating layer is used for the data line and the color
- the film photoresist 15 is insulated.
- the second insulating layer includes a silicon nitride insulating layer 141 in contact with the data line, and a silicon dioxide insulating layer 142 in contact with the color film photoresist 15, that is, the silicon dioxide insulating layer 142 is disposed in the nitrogen On the silicon insulating layer 141.
- the material of the first metal layer may be chromium, molybdenum, aluminum or copper, and the first metal layer has a thickness of 100 nm to 600 nm.
- the first insulating layer 13 is a silicon nitride insulating layer, and the first insulating layer 13 has a thickness of 100 nm to 300 nm.
- the material of the second metal layer may be chromium, molybdenum, aluminum or copper, and the second metal layer has a thickness of 100 nm to 600 nm.
- the thickness of the silicon nitride insulating layer 141 of the second insulating layer is 50 nm to 100 nm; and the thickness of the silicon oxide insulating layer 142 of the second insulating layer is 50 nm to 100 nm.
- the color film photoresist layer has a thickness of 500 nm to 2000 nm.
- the third insulating layer 16 is a silicon nitride insulating layer or a silicon dioxide insulating layer, and the third insulating layer 16 has a thickness of 100 nm to 200 nm.
- the transparent electrode layer is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer, and the transparent electrode layer has a thickness of 10 nm to 100 nm.
- the silicon nitride insulating layer 141 is used as a channel 124 for protecting the thin film transistor. Since the material of the silicon nitride insulating layer 141 is relatively dense, the channel 124 of the thin film transistor can be preferably insulated.
- the array substrate 10 is provided with a silicon dioxide insulating layer 142 on the silicon nitride insulating layer 141, and the color film photoresist 15 is directly disposed on the silicon dioxide insulating layer 142, since the material of the silicon dioxide insulating layer 142 is lower than that of the nitrogen.
- the material of the silicon insulating layer 141 is more loose, and the surface roughness of the silicon dioxide insulating layer 142 is much higher than that of the silicon nitride insulating layer, so that the color photoresist 15 can adhere well to the silicon dioxide insulating layer.
- the silicon dioxide insulating layer 142 and the silicon nitride insulating layer 141 are both inorganic materials, the silicon dioxide insulating layer 142 and the silicon nitride insulating layer 141 can also be firmly adhered together. Therefore, the problem that the color film resist 15 is detached from the second insulating layer is avoided.
- the surface of the silicon dioxide insulating layer 142 may be bombarded with plasma before the color film photoresist 15 is adhered to further The surface roughness of the silicon dioxide insulating layer 142 is increased.
- the array substrate of the present invention is provided with a second insulating layer having a silicon nitride insulating layer and a silicon dioxide insulating layer, and the color film photoresist is disposed on the silicon dioxide insulating layer of the second insulating layer, so that the color film photoresist It is not easy to fall off from the second insulating layer; the problem that the color film photoresist is detached from the array substrate is avoided.
- FIG. 2 is a flow chart of a preferred embodiment of the method for fabricating the array substrate of the present invention.
- the method for fabricating the array substrate of the preferred embodiment includes:
- Step S201 depositing a first metal layer on the glass substrate, and patterning the first metal layer to form a scan line and a gate of the thin film transistor;
- Step S202 depositing a first insulating layer and a semiconductor layer on the glass substrate, and patterning the first insulating layer and the semiconductor layer to form a channel of the thin film transistor;
- Step S203 depositing a second metal layer on the glass substrate, and patterning the second metal layer to form a data line, and a drain and a source of the thin film transistor;
- Step S204 depositing a second insulating layer on the glass substrate, and patterning the second insulating layer;
- Step S205 depositing a color film photoresist layer on the patterned second insulating layer to form a color film photoresist
- Step S206 depositing a third insulating layer on the glass substrate, and patterning the third insulating layer to form a via hole on the third insulating layer;
- Step S207 depositing a transparent electrode layer on the glass substrate, and patterning the transparent electrode layer to form a pixel electrode;
- step S207 The method of fabricating the array substrate of the preferred embodiment ends in step S207.
- FIG. 3A - FIG. 3F are schematic diagrams showing the fabrication of a preferred embodiment of the method for fabricating the array substrate of the present invention.
- a first metal layer is deposited on the glass substrate 11.
- the material of the first metal layer may be chromium, molybdenum, aluminum or copper, and the first metal layer has a thickness of 100 nm to 600 nm.
- the first metal layer is then patterned using a photomask (the photoresist is stripped after wet etching) to form a scan line (not shown) and a gate 121 of the thin film transistor (with corresponding scan) Line connection), as shown in FIG. 3A, then proceeds to step S202.
- a first insulating layer 13 and a semiconductor layer are deposited on the glass substrate 11, wherein the first insulating layer is a silicon nitride insulating layer, the first insulating layer has a thickness of 100 nm to 300 nm; and the semiconductor layer is amorphous. Silicon layer. Then, the first insulating layer and the semiconductor layer are patterned using a photomask (the photoresist is stripped after dry etching) to form a trench 124 of the thin film transistor, as shown in FIG. 3B, and then transferred to Step S203.
- a photomask the photoresist is stripped after dry etching
- a second metal layer is deposited on the glass substrate 11.
- the material of the second metal layer may be chromium, molybdenum, aluminum or copper, and the second metal layer has a thickness of 100 nm to 600 nm.
- the second metal layer is patterned using a photomask (the photoresist is stripped after dry etching) to form a data line (not shown), and the drain electrode 123 and the source 122 of the thin film transistor. (Connected to the corresponding data line), as shown in FIG. 3C, then proceeds to step S204.
- a second insulating layer is deposited on the glass substrate 11, and the second insulating layer includes a silicon nitride insulating layer 141 and a silicon oxide insulating layer 142 disposed on the silicon nitride insulating layer 141.
- the thickness of the silicon nitride insulating layer 141 of the second insulating layer is 50 nm to 100 nm; and the thickness of the silicon oxide insulating layer 142 of the second insulating layer is 50 nm to 100 nm.
- the second insulating layer is then patterned using a photomask (the photoresist is stripped after dry etching), as shown in FIG. 3D, and then proceeds to step S205.
- step S205 a color film photoresist layer is deposited on the patterned second insulating layer, the color film photoresist layer has a thickness of 500 nm to 2000 nm, and then a color film photoresist 15 is formed by an exposure and development process. As shown in FIG. 3E, the process proceeds to step S206.
- a third insulating layer 16 is deposited on the glass substrate.
- the third insulating layer 16 is a silicon nitride insulating layer or a silicon dioxide insulating layer, and the third insulating layer 16 has a thickness of 100 nm to 200 nm.
- the third insulating layer 16 is patterned using a photomask (the photoresist is stripped after dry etching) to form a via hole 161 on the third insulating layer; as shown in FIG. 3F, then the process proceeds to the step. S207.
- a transparent electrode layer is deposited on the glass substrate 11.
- the transparent electrode layer is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer, and the transparent electrode layer has a thickness of 10 nm to 100 nm.
- the transparent electrode layer is patterned by using a photomask (the photoresist is peeled off after the wet etching) to form the pixel electrode 17; the pixel electrode 17 is connected to the drain 123 of the thin film transistor through the via 161, such as Figure 1 shows.
- a silicon nitride insulating layer is used as a channel for protecting the thin film transistor. Since the material of the silicon nitride insulating layer is relatively dense, the channel of the thin film transistor can be preferably insulated.
- the array substrate is provided with a silicon dioxide insulating layer on the silicon nitride insulating layer, and the color film photoresist is directly disposed on the silicon dioxide insulating layer, because the material texture of the silicon dioxide insulating layer is lower than that of the silicon nitride insulating layer.
- the texture is more loose, the surface roughness of the silicon dioxide insulating layer is much higher than that of the silicon nitride insulating layer, so the color film photoresist can adhere well to the surface of the silicon dioxide insulating layer, and at the same time Since the insulating layer and the silicon nitride insulating layer are both inorganic materials, the silicon dioxide insulating layer and the silicon nitride insulating layer can also be firmly adhered together, thereby preventing the color film photoresist from falling off from the second insulating layer. The problem arises.
- the method for fabricating the array substrate of the present invention comprises: providing a second insulating layer having a silicon nitride insulating layer and a silicon dioxide insulating layer, and disposing the color film photoresist on the silicon dioxide insulating layer of the second insulating layer; The film photoresist is not easily detached from the second insulating layer; the problem that the color film photoresist is detached from the array substrate is avoided.
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Abstract
Description
本发明涉及显示器领域，特别是涉及一种阵列基板及其制作方法。The present invention relates to the field of displays, and in particular to an array substrate and a method of fabricating the same.
液晶显示装置已广泛的应用于人们的工作和生活中，随着液晶显示技术的发展，人们对显示器的画质要求越来越高，如分辨率、亮度、视角、色彩饱和度以及画面响应速度等。Liquid crystal display devices have been widely used in people's work and life. With the development of liquid crystal display technology, people have higher and higher requirements on the image quality of displays, such as resolution, brightness, viewing angle, color saturation and screen response speed. Wait.
传统的液晶显示装置将彩膜基板和阵列基板分别在不同的基板上进行制作，其中彩膜基板包括公共电极、RGB(红绿蓝)彩膜（彩膜光阻）以及黑色矩阵（BM，Black Matrix）；阵列基板包括薄膜晶体管、外围线路以及像素电极；然后将彩膜基板和阵列基板进行对盒操作，以形成液晶显示面板。传统的液晶显示面板的制作过程虽然简单，但是彩膜基板和阵列基板进行对盒操作时，容易由于对位误差产生漏光以及开口率降低的技术问题。A conventional liquid crystal display device fabricates a color filter substrate and an array substrate on different substrates, wherein the color filter substrate includes a common electrode, RGB (red, green, blue) color film (color film photoresist), and black matrix (BM, Black). The array substrate includes a thin film transistor, a peripheral line, and a pixel electrode; and then the color filter substrate and the array substrate are subjected to a box operation to form a liquid crystal display panel. Although the manufacturing process of the conventional liquid crystal display panel is simple, when the color film substrate and the array substrate are subjected to the box operation, the light leakage due to the alignment error and the technical problem of the aperture ratio are easily reduced.
因此为了避免上述的技术问题，液晶显示装置的制作商开发了一种COA（Color Film On Array）阵列基板，COA阵列基板将彩膜基板和阵列基板设置在同一玻璃基板上，这样在对盒操作时不会产生对位误差，提高了液晶显示面板的开口率。Therefore, in order to avoid the above technical problems, the manufacturer of the liquid crystal display device has developed a COA (Color Film On). Array) Array substrate, COA array substrate, the color film substrate and the array substrate are disposed on the same glass substrate, so that no alignment error occurs during the operation of the box, and the aperture ratio of the liquid crystal display panel is improved.
但是现有的COA阵列基板需要将彩膜光阻（有机材料）粘附在阵列基板的绝缘材料（无机材料）上，容易产生彩膜光阻的脱落（peeling）现象。However, the existing COA array substrate needs to adhere the color film photoresist (organic material) to the insulating material (inorganic material) of the array substrate, and it is easy to cause peeling phenomenon of the color film photoresist.
故，有必要提供一种阵列基板及其制作方法，以解决现有技术所存在的问题。Therefore, it is necessary to provide an array substrate and a manufacturing method thereof to solve the problems existing in the prior art.
本发明的目的在于提供一种彩膜光阻不易从阵列基板上脱落的阵列基板及其制作方法；以解决现有的阵列基板中彩膜光阻易从阵列基板上脱落的技术问题。An object of the present invention is to provide an array substrate in which the color film resist is not easily detached from the array substrate and a manufacturing method thereof, and to solve the technical problem that the color film photoresist in the existing array substrate is easily detached from the array substrate.
本发明实施例提供一种阵列基板，其包括：An embodiment of the present invention provides an array substrate, including:
玻璃基板，其上依次设置有第一金属层、第一绝缘层、第二金属层、第二绝缘层、彩膜光阻层、第三绝缘层以及透明电极层；以及a glass substrate on which a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a color film photoresist layer, a third insulating layer, and a transparent electrode layer are sequentially disposed;
薄膜晶体管，用于根据所述扫描信号，将所述数据信号传输至所述像素电极上；a thin film transistor, configured to transmit the data signal to the pixel electrode according to the scan signal;
其中所述第一绝缘层用于对所述第一金属层与所述第二金属层进行绝缘处理；所述第三绝缘层用于对所述彩膜光阻层和所述透明电极层进行绝缘处理；所述第二绝缘层用于对所述第二金属层与所述彩膜光阻层进行绝缘处理；所述第二绝缘层包括氮化硅绝缘层以及设置在所述氮化硅绝缘层上的二氧化硅绝缘层；The first insulating layer is used for insulating the first metal layer and the second metal layer; the third insulating layer is used for performing the color film photoresist layer and the transparent electrode layer Insulating treatment; the second insulating layer is for insulating treatment of the second metal layer and the color film photoresist layer; the second insulating layer comprises a silicon nitride insulating layer and disposed on the silicon nitride a silicon dioxide insulating layer on the insulating layer;
其中所述第二金属层包括用于传输数据信号的数据线；所述第一金属层包括用于传输扫描信号的扫描线；所述透明电极层包括用于显示所述数据信号的像素电极；所述彩膜光阻层包括彩膜光阻。Wherein the second metal layer includes a data line for transmitting a data signal; the first metal layer includes a scan line for transmitting a scan signal; and the transparent electrode layer includes a pixel electrode for displaying the data signal; The color film photoresist layer comprises a color film photoresist.
在本发明所述阵列基板中，所述第二绝缘层的所述氮化硅绝缘层的厚度为50纳米至100纳米；所述第二绝缘层的所述二氧化硅绝缘层的厚度为50纳米至100纳米。In the array substrate of the present invention, the silicon nitride insulating layer of the second insulating layer has a thickness of 50 nm to 100 nm; and the thickness of the silicon oxide insulating layer of the second insulating layer is 50 Nano to 100 nanometers.
在本发明所述阵列基板中，所述第三绝缘层为氮化硅绝缘层或二氧化硅绝缘层，所述第三绝缘层的厚度为100纳米至200纳米。In the array substrate of the present invention, the third insulating layer is a silicon nitride insulating layer or a silicon dioxide insulating layer, and the third insulating layer has a thickness of 100 nm to 200 nm.
在本发明所述阵列基板中，所述第一绝缘层为氮化硅绝缘层，所述第一绝缘层的厚度为100纳米至300纳米。In the array substrate of the present invention, the first insulating layer is a silicon nitride insulating layer, and the first insulating layer has a thickness of 100 nm to 300 nm.
在本发明所述阵列基板中，所述彩膜光阻层的厚度为500纳米至2000纳米。In the array substrate of the present invention, the color film photoresist layer has a thickness of 500 nm to 2000 nm.
在本发明所述阵列基板中，所述透明电极层为氧化铟锡透明电极层或氧化铟锌透明电极层，所述透明电极层的厚度为10纳米至100纳米。In the array substrate of the present invention, the transparent electrode layer is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer, and the transparent electrode layer has a thickness of 10 nm to 100 nm.
本发明实施例提供一种阵列基板，其包括：An embodiment of the present invention provides an array substrate, including:
玻璃基板，其上依次设置有第一金属层、第一绝缘层、第二金属层、第二绝缘层、彩膜光阻层、第三绝缘层以及透明电极层；a glass substrate on which a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a color film photoresist layer, a third insulating layer, and a transparent electrode layer are sequentially disposed;
其中所述第一绝缘层用于对所述第一金属层与所述第二金属层进行绝缘处理；所述第三绝缘层用于对所述彩膜光阻层和所述透明电极层进行绝缘处理；所述第二绝缘层用于对所述第二金属层与所述彩膜光阻层进行绝缘处理；所述第二绝缘层包括氮化硅绝缘层以及设置在所述氮化硅绝缘层上的二氧化硅绝缘层。The first insulating layer is used for insulating the first metal layer and the second metal layer; the third insulating layer is used for performing the color film photoresist layer and the transparent electrode layer Insulating treatment; the second insulating layer is for insulating treatment of the second metal layer and the color film photoresist layer; the second insulating layer comprises a silicon nitride insulating layer and disposed on the silicon nitride A silicon dioxide insulating layer on the insulating layer.
在本发明所述阵列基板中，所述第二金属层包括用于传输数据信号的数据线；所述第一金属层包括用于传输扫描信号的扫描线；所述透明电极层包括用于显示所述数据信号的像素电极；所述彩膜光阻层包括彩膜光阻。In the array substrate of the present invention, the second metal layer includes a data line for transmitting a data signal; the first metal layer includes a scan line for transmitting a scan signal; and the transparent electrode layer includes a display for display a pixel electrode of the data signal; the color film photoresist layer comprises a color film photoresist.
在本发明所述阵列基板中，所述阵列基板还包括：In the array substrate of the present invention, the array substrate further includes:
薄膜晶体管，用于根据所述扫描信号，将所述数据信号传输至所述像素电极上。And a thin film transistor for transmitting the data signal to the pixel electrode according to the scan signal.
在本发明所述阵列基板中，所述第二绝缘层的所述氮化硅绝缘层的厚度为50纳米至100纳米；所述第二绝缘层的所述二氧化硅绝缘层的厚度为50纳米至100纳米。In the array substrate of the present invention, the silicon nitride insulating layer of the second insulating layer has a thickness of 50 nm to 100 nm; and the thickness of the silicon oxide insulating layer of the second insulating layer is 50 Nano to 100 nanometers.
在本发明所述阵列基板中，所述第三绝缘层为氮化硅绝缘层或二氧化硅绝缘层，所述第三绝缘层的厚度为100纳米至200纳米。In the array substrate of the present invention, the third insulating layer is a silicon nitride insulating layer or a silicon dioxide insulating layer, and the third insulating layer has a thickness of 100 nm to 200 nm.
在本发明所述阵列基板中，所述第一绝缘层为氮化硅绝缘层，所述第一绝缘层的厚度为100纳米至300纳米。In the array substrate of the present invention, the first insulating layer is a silicon nitride insulating layer, and the first insulating layer has a thickness of 100 nm to 300 nm.
在本发明所述阵列基板中，所述彩膜光阻层的厚度为500纳米至2000纳米。In the array substrate of the present invention, the color film photoresist layer has a thickness of 500 nm to 2000 nm.
在本发明所述阵列基板中，所述透明电极层为氧化铟锡透明电极层或氧化铟锌透明电极层，所述透明电极层的厚度为10纳米至100纳米。In the array substrate of the present invention, the transparent electrode layer is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer, and the transparent electrode layer has a thickness of 10 nm to 100 nm.
本发明实施例还提供一种阵列基板的制作方法，其包括：The embodiment of the invention further provides a method for fabricating an array substrate, which comprises:
在玻璃基板上沉积第一金属层，并对所述第一金属层进行图形化处理，以形成扫描线以及薄膜晶体管的栅极；Depositing a first metal layer on the glass substrate, and patterning the first metal layer to form a scan line and a gate of the thin film transistor;
在所述玻璃基板上沉积第一绝缘层以及半导体层，并对所述第一绝缘层以及所述半导体层进行图形化处理，以形成所述薄膜晶体管的沟道；Depositing a first insulating layer and a semiconductor layer on the glass substrate, and patterning the first insulating layer and the semiconductor layer to form a channel of the thin film transistor;
在所述玻璃基板上沉积第二金属层，并对所述第二金属层进行图形化处理，以形成数据线以及所述薄膜晶体管的漏极以及源极；Depositing a second metal layer on the glass substrate, and patterning the second metal layer to form a data line and a drain and a source of the thin film transistor;
在所述玻璃基板上沉积第二绝缘层，并对所述第二绝缘层进行图形化处理；Depositing a second insulating layer on the glass substrate, and patterning the second insulating layer;
在所述图形化处理后的所述第二绝缘层上沉积彩膜光阻层，以形成所述彩膜光阻；Depositing a color film photoresist layer on the patterned second insulating layer to form the color film photoresist;
在所述玻璃基板上沉积第三绝缘层，并对所述第三绝缘层进行图形化处理，以在所述第三绝缘层上形成通孔；以及Depositing a third insulating layer on the glass substrate, and patterning the third insulating layer to form a via hole on the third insulating layer;
在所述玻璃基板上沉积透明电极层，并对所述透明电极层进行图形化处理，以形成像素电极；Depositing a transparent electrode layer on the glass substrate, and patterning the transparent electrode layer to form a pixel electrode;
其中所述第二绝缘层包括氮化硅绝缘层以及设置在所述氮化硅绝缘层上的二氧化硅绝缘层。The second insulating layer includes a silicon nitride insulating layer and a silicon dioxide insulating layer disposed on the silicon nitride insulating layer.
在本发明所述的阵列基板的制作方法中，所述第二绝缘层的所述氮化硅绝缘层的厚度为50纳米至100纳米；所述第二绝缘层的所述二氧化硅绝缘层的厚度为50纳米至100纳米。In the method of fabricating the array substrate of the present invention, the silicon nitride insulating layer of the second insulating layer has a thickness of 50 nm to 100 nm; and the silicon dioxide insulating layer of the second insulating layer The thickness is from 50 nanometers to 100 nanometers.
在本发明所述的阵列基板的制作方法中，所述彩膜光阻层的厚度为500纳米至2000纳米。In the method for fabricating the array substrate of the present invention, the color film photoresist layer has a thickness of 500 nm to 2000 nm.
在本发明所述的阵列基板的制作方法中，所述第三绝缘层为氮化硅绝缘层或二氧化硅绝缘层，所述第三绝缘层的厚度为100纳米至200纳米。In the method of fabricating the array substrate of the present invention, the third insulating layer is a silicon nitride insulating layer or a silicon dioxide insulating layer, and the third insulating layer has a thickness of 100 nm to 200 nm.
在本发明所述的阵列基板的制作方法中，所述第一绝缘层为氮化硅绝缘层，所述第一绝缘层的厚度为100纳米至300纳米。In the method of fabricating the array substrate of the present invention, the first insulating layer is a silicon nitride insulating layer, and the first insulating layer has a thickness of 100 nm to 300 nm.
在本发明所述的阵列基板的制作方法中，所述透明电极层为氧化铟锡透明电极层或氧化铟锌透明电极层，所述透明电极层的厚度为10纳米至100纳米。In the method for fabricating the array substrate of the present invention, the transparent electrode layer is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer, and the transparent electrode layer has a thickness of 10 nm to 100 nm.
相较于现有的阵列基板及其制作方法，本发明的阵列基板及其制作方法通过设置具有氮化硅绝缘层以及二氧化硅绝缘层的第二绝缘层，并将彩膜光阻设置在第二绝缘层的二氧化硅绝缘层上，使得彩膜光阻不易从第二绝缘层上脱落；解决了现有的阵列基板中彩膜光阻易从阵列基板上脱落的技术问题。Compared with the prior art array substrate and the manufacturing method thereof, the array substrate of the present invention and the manufacturing method thereof are provided by providing a second insulating layer having a silicon nitride insulating layer and a silicon dioxide insulating layer, and setting the color film photoresist On the silicon dioxide insulating layer of the second insulating layer, the photoresist of the color film is not easily detached from the second insulating layer; the technical problem that the color film resist of the existing array substrate is easily detached from the array substrate is solved.
图1为本发明的阵列基板的优选实施例的结构示意图；1 is a schematic structural view of a preferred embodiment of an array substrate of the present invention;
图2为本发明的阵列基板的制作方法的优选实施例的流程图；2 is a flow chart of a preferred embodiment of a method of fabricating an array substrate of the present invention;
图3A-图3F为本发明的阵列基板的制作方法的优选实施例的制作示意图。3A-3F are schematic views showing the fabrication of a preferred embodiment of the method of fabricating the array substrate of the present invention.
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。The following description of the various embodiments is provided to illustrate the specific embodiments of the invention. The directional terms mentioned in the present invention, such as "upper", "lower", "before", "after", "left", "right", "inside", "outside", "side", etc., are merely references. Attach the direction of the drawing. Therefore, the directional terminology used is for the purpose of illustration and understanding of the invention.
在图中，结构相似的单元是以相同标号表示。In the figures, structurally similar elements are denoted by the same reference numerals.
请参照图1，图1为本发明的阵列基板的优选实施例的结构示意图。本优选实施例的阵列基板10包括玻璃基板11、数据线、扫描线、像素电极、薄膜晶体管以及彩膜光阻15。Please refer to FIG. 1. FIG. 1 is a schematic structural view of a preferred embodiment of an array substrate of the present invention. The array substrate 10 of the preferred embodiment includes a glass substrate 11, a data line, a scan line, a pixel electrode, a thin film transistor, and a color film photoresist 15.
其中在玻璃基板11上依次设置有第一金属层、第一绝缘层13、半导体层、第二金属层、第二绝缘层、彩膜光阻层、第三绝缘层16以及透明电极层。扫描线设置在第一金属层上，用于传输扫描信号；数据线设置在第二金属层上，用于传输数据信号；像素电极17设置在透明电极层上，用于显示数据信号；薄膜晶体管包括源极122、漏极123、栅极121以及沟道124，其中薄膜晶体管的栅极121设置在第一金属层上，与扫描线连接；薄膜晶体管的源极122上设置在第二金属层上，与数据线连接；薄膜晶体管的漏极123设置在第二金属层上，与像素电极17连接；薄膜晶体管的沟道124设置在半导体层。彩膜光阻15设置在彩膜光阻层上，用于形成RGB像素。The first metal layer, the first insulating layer 13, the semiconductor layer, the second metal layer, the second insulating layer, the color film photoresist layer, the third insulating layer 16, and the transparent electrode layer are sequentially disposed on the glass substrate 11. The scan line is disposed on the first metal layer for transmitting the scan signal; the data line is disposed on the second metal layer for transmitting the data signal; the pixel electrode 17 is disposed on the transparent electrode layer for displaying the data signal; the thin film transistor The source 122, the drain 123, the gate 121, and the channel 124 are disposed, wherein the gate 121 of the thin film transistor is disposed on the first metal layer and connected to the scan line; and the source 122 of the thin film transistor is disposed on the second metal layer Upper, connected to the data line; the drain electrode 123 of the thin film transistor is disposed on the second metal layer and connected to the pixel electrode 17; and the channel 124 of the thin film transistor is disposed on the semiconductor layer. A color film photoresist 15 is disposed on the color film photoresist layer for forming RGB pixels.
其中第一绝缘层13用于对数据线与扫描线进行绝缘处理，第三绝缘层16用于对彩膜光阻15和像素电极17进行绝缘处理，第二绝缘层用于对数据线和彩膜光阻15进行绝缘处理。The first insulating layer 13 is used for insulating the data line and the scan line, the third insulating layer 16 is used for insulating the color film photoresist 15 and the pixel electrode 17, and the second insulating layer is used for the data line and the color The film photoresist 15 is insulated.
在本优选实施例中，第二绝缘层包括与数据线接触的氮化硅绝缘层141、以及与彩膜光阻15接触的二氧化硅绝缘层142，即二氧化硅绝缘层142设置在氮化硅绝缘层141上。In the preferred embodiment, the second insulating layer includes a silicon nitride insulating layer 141 in contact with the data line, and a silicon dioxide insulating layer 142 in contact with the color film photoresist 15, that is, the silicon dioxide insulating layer 142 is disposed in the nitrogen On the silicon insulating layer 141.
其中第一金属层的材料可为铬、钼、铝或铜等，该第一金属层的厚度为100纳米至600纳米。第一绝缘层13为氮化硅绝缘层，第一绝缘层13的厚度为100纳米至300纳米。第二金属层的材料可为铬、钼、铝或铜等，该第二金属层的厚度为100纳米至600纳米。第二绝缘层的氮化硅绝缘层141的厚度为50纳米至100纳米；第二绝缘层的二氧化硅绝缘层142的厚度为50纳米至100纳米。彩膜光阻层的厚度为500纳米至2000纳米。第三绝缘层16为氮化硅绝缘层或二氧化硅绝缘层，第三绝缘层16的厚度为100纳米至200纳米。透明电极层为氧化铟锡透明电极层或氧化铟锌透明电极层，透明电极层的厚度为10纳米至100纳米。The material of the first metal layer may be chromium, molybdenum, aluminum or copper, and the first metal layer has a thickness of 100 nm to 600 nm. The first insulating layer 13 is a silicon nitride insulating layer, and the first insulating layer 13 has a thickness of 100 nm to 300 nm. The material of the second metal layer may be chromium, molybdenum, aluminum or copper, and the second metal layer has a thickness of 100 nm to 600 nm. The thickness of the silicon nitride insulating layer 141 of the second insulating layer is 50 nm to 100 nm; and the thickness of the silicon oxide insulating layer 142 of the second insulating layer is 50 nm to 100 nm. The color film photoresist layer has a thickness of 500 nm to 2000 nm. The third insulating layer 16 is a silicon nitride insulating layer or a silicon dioxide insulating layer, and the third insulating layer 16 has a thickness of 100 nm to 200 nm. The transparent electrode layer is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer, and the transparent electrode layer has a thickness of 10 nm to 100 nm.
本优选实施例的阵列基板10制作时，采用氮化硅绝缘层141作为来保护薄膜晶体管的沟道124。由于氮化硅绝缘层141的材料质地较为致密，因此可对薄膜晶体管的沟道124进行较好的绝缘保护。When the array substrate 10 of the preferred embodiment is fabricated, the silicon nitride insulating layer 141 is used as a channel 124 for protecting the thin film transistor. Since the material of the silicon nitride insulating layer 141 is relatively dense, the channel 124 of the thin film transistor can be preferably insulated.
同时该阵列基板10在氮化硅绝缘层141上设置有二氧化硅绝缘层142，彩膜光阻15直接设置在二氧化硅绝缘层142上，由于二氧化硅绝缘层142的材料质地较氮化硅绝缘层141的材料质地更为松散，二氧化硅绝缘层142的表面粗糙度远远高于氮化硅绝缘层，因此彩膜光阻15可以很好的粘附在二氧化硅绝缘层142的表面上，同时由于二氧化硅绝缘层142与氮化硅绝缘层141由于均为无机材料，二氧化硅绝缘层142与氮化硅绝缘层141之间也能牢固的粘附在一起，因此避免了彩膜光阻15从第二绝缘层上脱落问题的产生。At the same time, the array substrate 10 is provided with a silicon dioxide insulating layer 142 on the silicon nitride insulating layer 141, and the color film photoresist 15 is directly disposed on the silicon dioxide insulating layer 142, since the material of the silicon dioxide insulating layer 142 is lower than that of the nitrogen. The material of the silicon insulating layer 141 is more loose, and the surface roughness of the silicon dioxide insulating layer 142 is much higher than that of the silicon nitride insulating layer, so that the color photoresist 15 can adhere well to the silicon dioxide insulating layer. On the surface of 142, at the same time, since the silicon dioxide insulating layer 142 and the silicon nitride insulating layer 141 are both inorganic materials, the silicon dioxide insulating layer 142 and the silicon nitride insulating layer 141 can also be firmly adhered together. Therefore, the problem that the color film resist 15 is detached from the second insulating layer is avoided.
当然为了进一步二氧化硅绝缘层142与彩膜光阻15之间的粘附力，可以在粘附彩膜光阻15之前，使用等离子体对二氧化硅绝缘层142的表面进行轰击，以进一步提高二氧化硅绝缘层142的表面粗糙度。Of course, in order to further adhere the adhesion between the silicon dioxide insulating layer 142 and the color film photoresist 15, the surface of the silicon dioxide insulating layer 142 may be bombarded with plasma before the color film photoresist 15 is adhered to further The surface roughness of the silicon dioxide insulating layer 142 is increased.
本发明的阵列基板通过设置具有氮化硅绝缘层以及二氧化硅绝缘层的第二绝缘层，并将彩膜光阻设置在第二绝缘层的二氧化硅绝缘层上，使得彩膜光阻不易从第二绝缘层上脱落；避免了彩膜光阻从阵列基板上脱落的问题的产生。The array substrate of the present invention is provided with a second insulating layer having a silicon nitride insulating layer and a silicon dioxide insulating layer, and the color film photoresist is disposed on the silicon dioxide insulating layer of the second insulating layer, so that the color film photoresist It is not easy to fall off from the second insulating layer; the problem that the color film photoresist is detached from the array substrate is avoided.
本发明还提供一种阵列基板的制作方法，请参照图2，图2为本发明的阵列基板的制作方法的优选实施例的流程图。本优选实施例的阵列基板的制作方法包括：The present invention also provides a method for fabricating an array substrate. Please refer to FIG. 2. FIG. 2 is a flow chart of a preferred embodiment of the method for fabricating the array substrate of the present invention. The method for fabricating the array substrate of the preferred embodiment includes:
步骤S201，在玻璃基板上沉积第一金属层，并对第一金属层进行图形化处理，以形成扫描线以及薄膜晶体管的栅极；Step S201, depositing a first metal layer on the glass substrate, and patterning the first metal layer to form a scan line and a gate of the thin film transistor;
步骤S202，在玻璃基板上沉积第一绝缘层以及半导体层，并对第一绝缘层以及半导体层进行图形化处理，以形成薄膜晶体管的沟道；Step S202, depositing a first insulating layer and a semiconductor layer on the glass substrate, and patterning the first insulating layer and the semiconductor layer to form a channel of the thin film transistor;
步骤S203，在玻璃基板上沉积第二金属层，并对第二金属层进行图形化处理，以形成数据线、以及薄膜晶体管的漏极以及源极；Step S203, depositing a second metal layer on the glass substrate, and patterning the second metal layer to form a data line, and a drain and a source of the thin film transistor;
步骤S204，在玻璃基板上沉积第二绝缘层，并对第二绝缘层进行图形化处理；Step S204, depositing a second insulating layer on the glass substrate, and patterning the second insulating layer;
步骤S205，在图形化处理后的第二绝缘层上沉积彩膜光阻层，以形成彩膜光阻；Step S205, depositing a color film photoresist layer on the patterned second insulating layer to form a color film photoresist;
步骤S206，在玻璃基板上沉积第三绝缘层，并对第三绝缘层进行图形化处理，以在第三绝缘层上形成通孔；Step S206, depositing a third insulating layer on the glass substrate, and patterning the third insulating layer to form a via hole on the third insulating layer;
步骤S207，在玻璃基板上沉积透明电极层，并对透明电极层进行图形化处理，以形成像素电极；Step S207, depositing a transparent electrode layer on the glass substrate, and patterning the transparent electrode layer to form a pixel electrode;
本优选实施例的阵列基板的制作方法结束于步骤S207。The method of fabricating the array substrate of the preferred embodiment ends in step S207.
下面详细说明本优选实施例的阵列基板的制作方法的各步骤的流程。请参照图3A-图3F，图3A-图3F为本发明的阵列基板的制作方法的优选实施例的制作示意图。The flow of each step of the method of fabricating the array substrate of the preferred embodiment will be described in detail below. Please refer to FIG. 3A - FIG. 3F. FIG. 3A - FIG. 3F are schematic diagrams showing the fabrication of a preferred embodiment of the method for fabricating the array substrate of the present invention.
在步骤S201中，在玻璃基板11上沉积第一金属层，第一金属层的材料可为铬、钼、铝或铜等，第一金属层的厚度为100纳米至600纳米。然后使用光罩对第一金属层进行图形化处理（湿法刻蚀之后对光刻胶进行剥离），以形成扫描线（图中未示出）以及薄膜晶体管的栅极121（与相应的扫描线连接），如图3A所示，随后转到步骤S202。In step S201, a first metal layer is deposited on the glass substrate 11. The material of the first metal layer may be chromium, molybdenum, aluminum or copper, and the first metal layer has a thickness of 100 nm to 600 nm. The first metal layer is then patterned using a photomask (the photoresist is stripped after wet etching) to form a scan line (not shown) and a gate 121 of the thin film transistor (with corresponding scan) Line connection), as shown in FIG. 3A, then proceeds to step S202.
在步骤S202中，在玻璃基板11上沉积第一绝缘层13以及半导体层，其中第一绝缘层为氮化硅绝缘层，第一绝缘层的厚度为100纳米至300纳米；半导体层为非晶硅层。然后使用光罩对第一绝缘层以及所述半导体层进行图形化处理（干法刻蚀之后对光刻胶进行剥离），以形成薄膜晶体管的沟道124，如图3B所示，随后转到步骤S203。In step S202, a first insulating layer 13 and a semiconductor layer are deposited on the glass substrate 11, wherein the first insulating layer is a silicon nitride insulating layer, the first insulating layer has a thickness of 100 nm to 300 nm; and the semiconductor layer is amorphous. Silicon layer. Then, the first insulating layer and the semiconductor layer are patterned using a photomask (the photoresist is stripped after dry etching) to form a trench 124 of the thin film transistor, as shown in FIG. 3B, and then transferred to Step S203.
在步骤S203中，在玻璃基板11上沉积第二金属层，第二金属层的材料可为铬、钼、铝或铜等，第二金属层的厚度为100纳米至600纳米。然后使用光罩对第二金属层进行图形化处理（干法刻蚀之后对光刻胶进行剥离），以形成数据线（图中未示出）、以及薄膜晶体管的漏极123以及源极122（与相应的数据线连接），如图3C所示，随后转到步骤S204。In step S203, a second metal layer is deposited on the glass substrate 11. The material of the second metal layer may be chromium, molybdenum, aluminum or copper, and the second metal layer has a thickness of 100 nm to 600 nm. Then, the second metal layer is patterned using a photomask (the photoresist is stripped after dry etching) to form a data line (not shown), and the drain electrode 123 and the source 122 of the thin film transistor. (Connected to the corresponding data line), as shown in FIG. 3C, then proceeds to step S204.
在步骤S204中，在玻璃基板11上沉积第二绝缘层，第二绝缘层包括氮化硅绝缘层141以及设置在氮化硅绝缘层141上的二氧化硅绝缘层142。第二绝缘层的氮化硅绝缘层141的厚度为50纳米至100纳米；第二绝缘层的二氧化硅绝缘层142的厚度为50纳米至100纳米。然后使用光罩对第二绝缘层进行图形化处理（干法刻蚀之后对光刻胶进行剥离），如图3D所示，随后转到步骤S205。In step S204, a second insulating layer is deposited on the glass substrate 11, and the second insulating layer includes a silicon nitride insulating layer 141 and a silicon oxide insulating layer 142 disposed on the silicon nitride insulating layer 141. The thickness of the silicon nitride insulating layer 141 of the second insulating layer is 50 nm to 100 nm; and the thickness of the silicon oxide insulating layer 142 of the second insulating layer is 50 nm to 100 nm. The second insulating layer is then patterned using a photomask (the photoresist is stripped after dry etching), as shown in FIG. 3D, and then proceeds to step S205.
在步骤S205中，在图形化处理后的第二绝缘层上沉积彩膜光阻层，该彩膜光阻层的厚度为500纳米至2000纳米，然后通过曝光显影工艺形成彩膜光阻15，如图3E所示，随后转到步骤S206。In step S205, a color film photoresist layer is deposited on the patterned second insulating layer, the color film photoresist layer has a thickness of 500 nm to 2000 nm, and then a color film photoresist 15 is formed by an exposure and development process. As shown in FIG. 3E, the process proceeds to step S206.
在步骤S206中，在玻璃基板上沉积第三绝缘层16，第三绝缘层16为氮化硅绝缘层或二氧化硅绝缘层，第三绝缘层16的厚度为100纳米至200纳米。然后使用光罩对第三绝缘层16进行图形化处理（干法刻蚀之后对光刻胶进行剥离），以在第三绝缘层上形成通孔161；如图3F所示，随后转到步骤S207。In step S206, a third insulating layer 16 is deposited on the glass substrate. The third insulating layer 16 is a silicon nitride insulating layer or a silicon dioxide insulating layer, and the third insulating layer 16 has a thickness of 100 nm to 200 nm. Then, the third insulating layer 16 is patterned using a photomask (the photoresist is stripped after dry etching) to form a via hole 161 on the third insulating layer; as shown in FIG. 3F, then the process proceeds to the step. S207.
在步骤S207中，在玻璃基板11上沉积透明电极层，透明电极层为氧化铟锡透明电极层或氧化铟锌透明电极层，透明电极层的厚度为10纳米至100纳米。然后使用光罩对透明电极层进行图形化处理（湿法刻蚀之后对光刻胶进行剥离），以形成像素电极17；该像素电极17通过通孔161与薄膜晶体管的漏极123连接，如图1所示。In step S207, a transparent electrode layer is deposited on the glass substrate 11. The transparent electrode layer is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer, and the transparent electrode layer has a thickness of 10 nm to 100 nm. Then, the transparent electrode layer is patterned by using a photomask (the photoresist is peeled off after the wet etching) to form the pixel electrode 17; the pixel electrode 17 is connected to the drain 123 of the thin film transistor through the via 161, such as Figure 1 shows.
这样即完成了本优选实施例的阵列基板的制作过程。Thus, the fabrication process of the array substrate of the preferred embodiment is completed.
本优选实施例的阵列基板制作时，采用氮化硅绝缘层作为来保护薄膜晶体管的沟道。由于氮化硅绝缘层的材料质地较为致密，因此可对薄膜晶体管的沟道进行较好的绝缘保护。In the fabrication of the array substrate of the preferred embodiment, a silicon nitride insulating layer is used as a channel for protecting the thin film transistor. Since the material of the silicon nitride insulating layer is relatively dense, the channel of the thin film transistor can be preferably insulated.
同时该阵列基板在氮化硅绝缘层上设置有二氧化硅绝缘层，彩膜光阻直接设置在二氧化硅绝缘层上，由于二氧化硅绝缘层的材料质地较氮化硅绝缘层的材料质地更为松散，二氧化硅绝缘层的表面粗糙度远远高于氮化硅绝缘层，因此彩膜光阻可以很好的粘附在二氧化硅绝缘层的表面上，同时由于二氧化硅绝缘层与氮化硅绝缘层由于均为无机材料，二氧化硅绝缘层与氮化硅绝缘层之间也能牢固的粘附在一起，因此避免了彩膜光阻从第二绝缘层上脱落问题的产生。At the same time, the array substrate is provided with a silicon dioxide insulating layer on the silicon nitride insulating layer, and the color film photoresist is directly disposed on the silicon dioxide insulating layer, because the material texture of the silicon dioxide insulating layer is lower than that of the silicon nitride insulating layer. The texture is more loose, the surface roughness of the silicon dioxide insulating layer is much higher than that of the silicon nitride insulating layer, so the color film photoresist can adhere well to the surface of the silicon dioxide insulating layer, and at the same time Since the insulating layer and the silicon nitride insulating layer are both inorganic materials, the silicon dioxide insulating layer and the silicon nitride insulating layer can also be firmly adhered together, thereby preventing the color film photoresist from falling off from the second insulating layer. The problem arises.
本发明的阵列基板的制作方法通过设置具有氮化硅绝缘层以及二氧化硅绝缘层的第二绝缘层，并将彩膜光阻设置在第二绝缘层的二氧化硅绝缘层上，使得彩膜光阻不易从第二绝缘层上脱落；避免了彩膜光阻从阵列基板上脱落的问题的产生。The method for fabricating the array substrate of the present invention comprises: providing a second insulating layer having a silicon nitride insulating layer and a silicon dioxide insulating layer, and disposing the color film photoresist on the silicon dioxide insulating layer of the second insulating layer; The film photoresist is not easily detached from the second insulating layer; the problem that the color film photoresist is detached from the array substrate is avoided.
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。In the above, the present invention has been disclosed in the above preferred embodiments, but the preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various modifications without departing from the spirit and scope of the invention. The invention is modified and retouched, and the scope of the invention is defined by the scope defined by the claims.
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| CN106647077B (en) * | 2016-12-29 | 2020-02-28 | 惠科股份有限公司 | Display panel and display device |
| CN110660839B (en) * | 2019-11-13 | 2022-04-29 | 京东方科技集团股份有限公司 | Display panel and preparation method thereof |
| CN111768693A (en) * | 2020-06-24 | 2020-10-13 | 武汉华星光电半导体显示技术有限公司 | Display panel |
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| US20020012083A1 (en) * | 2000-07-28 | 2002-01-31 | Jun Tanaka | Color liquid crystal panel and color liquid crystal display apparatus |
| CN1534362A (en) * | 2003-03-28 | 2004-10-06 | 富士通显示技术株式会社 | substrate for liquid crystal display device and liquid crystal display device using the same |
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