WO2016002473A1 - Semiconductor device - Google Patents

Abstract

The purpose of the present invention is to achieve improvements in yields during fabrication of GaN-HEMTs. The present invention is provided with an external connection terminal (126 (D)) performing the role of a drain for a semiconductor device (150) and two or more GaN-HEMTs (104). The drain pad ((D)) of each GaN-HEMT (104) is connected to the external connection terminal (126 (D)).

Description

Semiconductor device

The present invention relates to a semiconductor device in which a plurality of semiconductor devices are mounted on the same plane of a die stage.

So far, various semiconductor devices (so-called semiconductor packages) incorporating a plurality of semiconductor devices have been proposed.

Recently, among them, semiconductor devices equipped with GaN (gallium nitride) power devices have attracted attention. A semiconductor device provided with a GaN-based power device has a large band gap and can realize a high electron concentration due to a heterojunction.

Patent Document 1 discloses a structure of a semiconductor device provided with a GaN-based power device. Specifically, Patent Document 1 includes a GaN-HEMT (High Electron Mobility Transistor) and a MOS-FET (Metal-Oxide Semiconductor Semiconductor Field Effect Transistor: Metal Oxide Semiconductor Field Effect Transistor). A semiconductor device is disclosed which is fixed on the same die stage (hereinafter referred to as a die pad portion) by a die attach material and is cascode-connected to each other.

FIG. 6 is a top view and a side view of a standardized semiconductor device 50 generally called TO-220. The semiconductor device 50 is often used for power devices.

The external shape of the semiconductor device 50 includes a sealing resin portion 40 that protects the semiconductor device, three external connection terminals 26 connected to the terminals on the semiconductor device, and a round hole 29 for screwing for heat dissipation. And a fin portion 28 having a shape. The three external connection terminals 26 function as a gate (G), a source (S), and a drain (D), respectively.

FIG. 7 is a view showing the lead frame 20 used for manufacturing the semiconductor device 50 shown in FIG. The lead frame 20 includes a die pad portion 22 and an inner lead portion 24 on which silver plating 16 is applied, and the above-described external connection terminals 26 and fin portions 28.

As shown in FIG. 7, in the lead frame 20 in a multiple state, generally, a metal which is a Cu (copper) alloy or an Fe (iron) alloy is punched with a mold or chemically etched. As a result, a desired pattern is formed. Further, the desired pattern is bent as necessary to have a continuous pattern in which semiconductor devices are processed in a multiple state.

FIG. 5 is a perspective view of a conventional semiconductor device 50 in which GaN-HEMT and MOS-FET are fixed to the lead frame 20 shown in FIG. 7 using different die attach materials. In FIG. 5, the hidden lines are also shown as solid lines in consideration of the visibility of the drawing.

As shown in FIG. 5, in the conventional semiconductor device 50, the MOS-FET 2 is fixed to the silver plating part 16 on the die pad part 22 by the solder 12, and the GaN-HEMT 4 is adjacent to the die pad part by the silver paste 14. 22 is fixed to the silver plating part 16 on the upper side.

Solder 12 is a Pb (lead) -Ag (silver) -Cu high melting point solder. The silver paste 14 is an epoxy resin containing a silver filler and is conductive. The MOS-FET 2 and the GaN-HEMT 4 are bonded to the silver plating 16 on the die pad portion 22 using a die bonder. Note that the solder 12 has a higher melting point, and when the solder 12 is used, it is necessary to heat the die pad portion 22 to about 350 ° C. during die bonding. For this reason, if the silver paste 14 is used before the solder 12, the epoxy resin constituting the silver paste 14 may be decomposed by high heat due to this heating. Therefore, the MOS-FET 2 is generally fixed to the silver plating portion 16 on the die pad portion 22 using the solder 12 first.

Further, according to the circuit configuration, the MOS-FET 2, the GaN-HEMT 4, and the inner lead portion 24 are wire-bonded and connected by an aluminum wire 30 and a gold wire 32 using a wire bonder. In particular, for example, an aluminum wire 30 having a diameter of 300 μm is used in a portion where a large current flows, and a gold wire 32 having a diameter of 30 μm is used in a portion where only a small current flows only by signal transmission. Connection points of the aluminum wire 30 are between the drain pad (D) of the GaN-HEMT 4 and the external connection terminal 26 (D) serving as the drain, and between the source pad (S) of the GaN-HEMT 4 and the MOS-FET 2. Between the drain pad (D). The connection point of the gold wire 32 is between the gate pad (G) of the GaN-HEMT 4 and the source pad (S) of the MOS-FET 2 and the external connection that plays the role of the gate pad (G) of the MOS-FET 2 and the gate. Between the terminal 26 (G) for use. The external connection terminal 26 (S) serving as the source is connected to the die pad portion 22. Further, the source pad (S) of the MOS-FET 2 and the back surface of the MOS-FET 2 are at the same potential inside the MOS-FET 2. For this reason, the potential of the external connection terminal 26 (S) is equal to the potential of the source pad (S) of the MOS-FET 2.

FIG. 9 shows the connection relationship according to FIG. In FIG. 9, D, G, and S indicate a drain, a gate, and a source, respectively.

Japanese Patent Publication “Japanese Patent Laid-Open No. 2013-153027 (published on August 8, 2013)”

In the semiconductor device disclosed in Patent Document 1 and the semiconductor device 50 shown in FIG. 5, one GaN-HEMT and one MOS-FET are mounted on the same die pad part.

Originally, in the field of semiconductor chips (semiconductor devices), efforts have been made to reduce the manufacturing cost per chip by increasing the degree of integration and increasing the number of chips per wafer without degrading performance. . In addition, when manufacturing semiconductor chip circuits in the wafer state, assuming that the same number and size of dust adhere to the upper surface of each wafer, the smaller the chip size, the smaller the defective area and the overall yield. It is common to improve. Furthermore, in the production of a semiconductor chip, it may be possible to reduce the production cost by separating a part of the function from the semiconductor chip into another semiconductor chip or replacing it with a discrete electronic component. In some cases, it must be done. On the other hand, by consolidating the separated functions into one semiconductor chip, the manufacturing cost may be reduced as a whole or the added value may be increased.

When a high breakdown voltage of about 600 V is required for GaN-HEMT, a small crystal defect promotes a leak between the source, drain, and gate, and this greatly increases the burden on GaN-HEMT. There is a risk of current generation. According to the specifications, when a GaN-HEMT is manufactured by the same process and design, the size of the GaN-HEMT is inevitably increased in order to cope with a large current. Assuming that crystal defects in the wafer are present at a certain rate, the larger the size of the GaN-HEMT, the higher the proportion of GaN-HEMT that cannot pass the test due to the above-mentioned leak, resulting in a worse yield. To do. This can be said to be the same reasoning as the deterioration of the yield due to dust on the upper surface of the wafer in the semiconductor chip manufacturing process described above.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of improving the yield at the time of fabricating a GaN-HEMT.

In order to solve the above problems, a semiconductor device according to one embodiment of the present invention includes a first external connection terminal serving as a drain of a semiconductor device, and two or more GaN-HEMTs, A drain pad of the GaN-HEMT is connected to the first external connection terminal.

According to one embodiment of the present invention, it is possible to improve the yield when manufacturing a GaN-HEMT.

It is the figure which saw through the semiconductor device which concerns on Embodiment 1 of this invention. It is the figure which saw through the semiconductor device which concerns on Embodiment 2 of this invention. It is the figure which saw through the semiconductor device which concerns on Embodiment 3 of this invention. It is the figure which saw through the semiconductor device which concerns on Embodiment 4 of this invention. It is the figure which saw through the conventional semiconductor device (TO-220). It is the top view and side view of the conventional semiconductor device (TO-220). FIG. 7 is a view showing a lead frame used for manufacturing the semiconductor device shown in FIG. 6. FIG. 10 is a perspective view of another conventional semiconductor device (TO-247). FIG. 6 is an electric circuit diagram showing a connection relationship according to FIG. 5. It is an electric circuit diagram which shows the connection relation which concerns on FIG. It is the figure which saw through the semiconductor device which concerns on Embodiment 5 of this invention.

It can be said that the object of the semiconductor device of the present invention is to moderately separate the function of the GaN-HEMT into a plurality of equivalent chips. As a result, the effective area of the GaN-HEMT manufactured in the wafer state can be increased and the yield can be improved without degrading the conventional performance.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the dimensions, materials, shapes, relative arrangements, and the like of the component parts described in this embodiment are merely one embodiment, and the scope of the present invention should not be construed as being limited thereto.

Embodiments of the present invention will be described below with reference to FIGS. 1 to 4, 8, 10, and 11.

[Embodiment 1]
An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a perspective view of the semiconductor device according to the present embodiment. That is, since the sealing resin portion 140 for protecting the semiconductor device is non-transparent, the inside is not actually visible to the naked eye. However, in order to explain the inside after illustrating the inside, the hidden line is also indicated by a solid line. (See through). The same applies to FIG. 2 to FIG. 4, FIG. 8, and FIG.

A semiconductor device 150 shown in FIG. 1 is for electrically connecting a die pad portion 122 (thickness: about 1.27 mm), an inner lead portion 124, and the semiconductor device 150 and a circuit outside the semiconductor device 150 to a lead frame. An external connection terminal 126 which is an outer lead portion and a fin portion 128 are provided. The die pad portion 122 and the inner lead portion 124 are subjected to silver plating (thickness: about 5 μm). The fin portion 128 is provided with a round hole 129 for screwing for heat dissipation.

One MOS-FET 102 (thickness: about 0.2 mm) and two GaN-HEMTs 104 (thickness: about 0.25 mm) are mounted on the silver plating portion on the die pad portion 122. A die bonder is used for this mounting. More specifically, the MOS-FET 102 is bonded to the silver plating portion via the solder 112, and the GaN-HEMT 104 is bonded to the silver plating portion via the silver paste 114. The solder 112 has a thermal conductivity of about 40 W / m · K and is a Pb—Ag—Cu high melting point type. On the other hand, the silver paste 114 is an epoxy resin having a thermal conductivity of about 10 W / m · K, containing a silver filler, and is conductive.

Each GaN-HEMT 104 is provided with a gate pad (G), a source pad (S), and a drain pad (D) similarly to the GaN-HEMT 4 (see FIG. 5). In addition, three external connection terminals 126 are provided, and the three external connection terminals 126 serve as a gate (G), a source (S), and a drain (D), respectively.

The electrical connection inside the sealing resin part 140 is a wire bonding connection using an aluminum wire 130 and a gold wire 132 using a wire bonder. Connection points of the aluminum wire 130 are between the drain pad (D) of each GaN-HEMT 104 and the external connection terminal (first external connection terminal) 126 (D) that plays the role of the drain, and each GaN-HEMT 104. Between the source pad (S) and the drain pad (D) of the MOS-FET 102. The connection point of the gold wire 132 plays a role of between the gate pad (G) of each GaN-HEMT 104 and each source pad (S) of the MOS-FET 102 and between the gate pad (G) of the MOS-FET 102 and the gate. This is between the external connection terminal (second external connection terminal) 126 (G). Note that the external connection terminal 126 (S) serving as the source is connected to the die pad portion 122. Further, the source pad (S) of the MOS-FET 102 and the back surface of the MOS-FET 102 are at the same potential inside the MOS-FET 102. For this reason, the potential of the external connection terminal 126 (S) is equal to the potential of the source pad (S) of the MOS-FET 102.

FIG. 10 shows the connection relationship according to FIG. 1 as an electric circuit diagram. In FIG. 10, D, G, and S indicate a drain, a gate, and a source, respectively.

The drain of each GaN-HEMT 104 constitutes the drain in the electric circuit shown in FIG. The source of each GaN-HEMT 104 is connected to the drain of the MOS-FET 102. The source of the MOS-FET 102 and the gate of each GaN-HEMT 104 constitute the source in the electric circuit. The gate of the MOS-FET 102 constitutes the gate in the same electric circuit.

The electric circuit shown in FIG. 10 can be interpreted that the MOS-FET 102 and each GaN-HEMT 104 are cascode-connected, and the GaN-HEMTs 104 are connected in parallel.

The semiconductor device 150 includes an external connection terminal 126 (D) serving as a drain and two or more (two in FIG. 1) GaN-HEMTs 104. The drain pad (D) of each GaN-HEMT 104 is connected to a common external connection terminal 126 (D), and the source pad (S) of each GaN-HEMT 104 is connected to a common part (MOS in FIG. 1). -It is connected to the drain pad (D) of the FET 102.

In addition, the semiconductor device 150 includes an external connection terminal 126 (G) that plays the role of a gate. The separation distance between the gate pad (G) of the MOS-FET 102 and the external connection terminal 126 (G) is smaller than the separation distance between the source pad (S) of the MOS-FET 102 and the external connection terminal 126 (G). In other words, in the semiconductor device 150, the MOS-FET 102 is arranged so that the gate pad (G) of the MOS-FET 102 is as close as possible to the external connection terminal 126 (G).

Furthermore, each source pad (S) of the MOS-FET 102 and the gate pad (G) of each GaN-HEMT 104 have a one-to-one correspondence.

The semiconductor device 150 is, for example, a power device having a maximum rated current of 10 A class and a drain / source maximum rated voltage of 650 V. The MOS-FET 102 is the same as the MOS-FET 2 used in the semiconductor device 50 of FIG. 5, and the size is about 1.5 mm × 5.0 mm. The GaN-HEMT 104 is equivalent to a maximum rated current of 5 A, and the size is about 2.5 mm × 2.1 mm. The size of the GaN-HEMT 104 is about 5% larger than half of the size of the GaN-HEMT 4 (equivalent to a maximum rated current of 10 A, the size is about 2.5 mm × 4.0 mm). The reason why it is not simply halved is that the number of pads for connecting the gold wire 32 is increased and the number of peripheral circuits is doubled.

For each of the above sizes, about 1600 GaN-HEMTs 4 and about 3000 GaN-HEMTs 104 can be produced on a 6-inch diameter wafer. Assuming that 200 GaN-HEMTs fail (failure) in each test due to the crystal defects described above, the actual number of pass (good) is about 1400 for GaN-HEMT4, GaN- In the HEMT 104, the number is about 2800. As a result, the number of semiconductor devices that can be manufactured from one wafer is equal to 1400 in all cases. In fact, the specification of the GaN-HEMT 104 is disadvantageous in that the number of die bonds is doubled and the cost is increased as compared with the specification of the GaN-HEMT 4, but the ratio of crystal defects is higher. When the percentage of failures in the test is higher than the above assumption (when the cost branch point that can offset the cost of die bond increase is exceeded), use GaN-HEMT104 (divide one GaN-HEMT into multiple parts ) The effect makes sense.

When the number of rejected GaN-HEMTs 104 on the wafer is the same (numerator), if the denominator (the total number of GaN-HEMTs manufactured on the wafer) increases, the ratio of rejects increases. descend. As a result, the yield during GaN-HEMT fabrication is improved.

[Embodiment 2]
Another embodiment of the present invention will be described below with reference to FIG.

FIG. 2 is a perspective view of the semiconductor device according to the present embodiment. From here, the difference between the semiconductor device 151 shown in FIG. 2 and the semiconductor device 150 shown in FIG. 1 will be mainly described, and items overlapping between the semiconductor device 151 and the semiconductor device 150 will be omitted as appropriate.

In each GaN-HEMT 104 of the semiconductor device 150 shown in FIG. 1, the drain pad (D) is arranged on the left side of the source pad (S). On the other hand, the external connection terminal 126 (D) is arranged on the right side of the external connection terminal 126 (G) that functions as a gate and the external connection terminal 126 (S) that functions as a source. In this case, in particular, the aluminum wire 130 connecting the drain pad (D) of the left GaN-HEMT 104 and the external connection terminal 126 (D) needs to be lengthened and greatly bent. The necessity becomes remarkable when each GaN-HEMT 104 must be designed to be long in the direction in which the GaN-HEMTs 104 are arranged. The aluminum wire 130 is less flexible than the gold wire 132 because of its material, and tends to be stretched, and the torsional stress on the bonded pads tends to increase.

Each GaN-HEMT 104 of the semiconductor device 151 is different from each GaN-HEMT 104 of the semiconductor device 150 in that the position of the source pad (S) and the position of the drain pad (D) are opposite.

The drain pad (D) of each GaN-HEMT 104 of the semiconductor device 151 is disposed on the side close to the external connection terminal 126 (D) to be connected. That is, the distance between the drain pad (D) of each GaN-HEMT 104 and the external connection terminal 126 (D) is the distance between the source pad (S) of each GaN-HEMT 104 and the external connection terminal 126 (D). Smaller is preferred.

Thereby, the aluminum wire 130 connected to the external connection terminal 126 (D) can be shortened and the bending angle can be reduced. As a result, an increase in torsional stress on the bonded pads can be suppressed.

The same effect can be obtained by arranging each GaN-HEMT 104 close to the external connection terminal 126 (D) as a whole. The semiconductor device 151 has a configuration that can suppress an increase in torsional stress on the bonded pads, on the assumption that each GaN-HEMT 104 is disposed at the same position as the semiconductor device 150.

FIG. 10 shows the connection relationship according to FIG. 2 as an electrical circuit diagram.

[Embodiment 3]
The following will describe still another embodiment of the present invention with reference to FIG.

FIG. 3 is a perspective view of the semiconductor device according to the present embodiment. From here, the difference between the semiconductor device 152 shown in FIG. 3 and the semiconductor device 150 shown in FIG. 1 will be mainly described, and items overlapping between the semiconductor device 152 and the semiconductor device 150 will be omitted as appropriate.

In the semiconductor device 150, each GaN-HEMT 104 is disposed on the side close to each external connection terminal 126, and the MOS-FET 102 is disposed on a side far from each external connection terminal 126. The semiconductor device 152 is obtained by rotating the GaN-HEMT 104 and the MOS-FET 102 in the semiconductor device 150 by 90 degrees counterclockwise in FIG. Strictly speaking, from the viewpoint of routing the aluminum wire 130 and the gold wire 132, the position of the MOS-FET 102 with respect to each GaN-HEMT 104 is slightly changed.

The gate pad (G) of the MOS-FET 102 and the external connection terminal 126 (G) are connected by a gold wire 132. The length of the gold wire 132 is shorter in the semiconductor device 152 than in the semiconductor device 150. . In this gold wire 132, the reactance increases due to the frequency component due to switching and energy loss occurs. Therefore, it is more efficient to make the gold wire 132 as short as possible to reduce the reactance component.

[Embodiment 4]
The following will describe still another embodiment of the present invention with reference to FIG.

FIG. 4 is a perspective view of the semiconductor device according to the present embodiment. From here, the difference between the semiconductor device 155 shown in FIG. 4 and the semiconductor device 150 shown in FIG. 1 will be mainly described, and items overlapping between the semiconductor device 155 and the semiconductor device 150 will be omitted as appropriate.

First, the semiconductor device 150 shown in FIG. 1 is based on the semiconductor device 50 (TO-220) shown in FIG. 5, but the semiconductor device 155 shown in FIG. 4 is the same as the semiconductor device 55 (TO-220) shown in FIG. 247).

The semiconductor device 55 shown in FIG. 8 will be described.

In the semiconductor device 55, the area of the die pad portion 22 on which silver plating is performed is nearly twice as large as that of the semiconductor device 50. The thickness of the die pad portion 22 of the semiconductor device 55 is about 2 mm, which is about 1.5 times the thickness of the die pad portion 22 of the semiconductor device 50 (about 1.27 mm). Therefore, the semiconductor device 55 has a larger heat capacity than the semiconductor device 50 and can accommodate a device with a large current. The GaN-HEMT 4 of the semiconductor device 55 is larger than the GaN-HEMT 4 of the semiconductor device 50 and has three drain pads (D) and three source pads (S).

Based on this, in the semiconductor device 155, one MOS-FET 102 and three GaN-HEMTs 104 are mounted on the silver plating portion on the die pad portion 122. The arrangement of the drain pad (D) and the source pad (S) of each GaN-HEMT 104 is the same as that of the semiconductor device 151.

The semiconductor device 155 is a power device having a maximum rated current of 45 A class and a drain / source maximum rated voltage of 650 V. The MOS-FET 102 is the same as the MOS-FET 2 used in the semiconductor device 55 of FIG. 8, and the size is about 2.1 mm × 7.3 mm. The GaN-HEMT 104 is equivalent to a maximum rated current of 15 A, and the size is about 4.0 mm × 2.73 mm. The size of the GaN-HEMT 104 is about 5% larger than one third of the size of the GaN-HEMT 4 (equivalent to a maximum rated current of 45 A, the size is about 4.0 mm × 7.8 mm). The reason why it is not simply one third is because the number of pads for connecting the gold wire 132 increases and the number of peripheral circuits increases three times.

For each of the above sizes, about 500 GaN-HEMTs 4 and about 1400 GaN-HEMTs 104 can be produced on a 6-inch diameter wafer. Assuming that 200 GaN-HEMTs fail (failure) in each test due to the crystal defects described above, the actual number of pass (good) is about 300 for GaN-HEMT4 and GaN- In the HEMT 104, the number is about 1200. As a result, the number of semiconductor devices that can be manufactured from one wafer is about 300 for the former and about 400 for the latter, and it is more advantageous to divide the GaN-HEMT 4 into three GaN-HEMTs 104. Actually, the specification of the GaN-HEMT 104 increases the number of die bonds three times as much as the specification of the GaN-HEMT 4 and the cost increases accordingly. It can be said that it is still advantageous to subtract that amount. In addition, when the ratio of crystal defects is higher and the ratio of failure in the test is higher than the above assumption, the effect of using the GaN-HEMT 104 (dividing one GaN-HEMT into a plurality of parts) makes more sense. It will be. Moreover, even if the ratio of crystal defects is lower and the ratio of failing the test is smaller than the assumption, it can be said that it is advantageous to the branch point.

The member with the member number 45 and the member with the member number 145 are resin molds.

[Embodiment 5]
The following will describe still another embodiment of the present invention with reference to FIG.

FIG. 11 is a perspective view of the semiconductor device according to the present embodiment, and shows a top view and a side view. From here, the difference between the semiconductor device 153 shown in FIG. 11 and the semiconductor device 150 shown in FIG. 1 will be mainly described, and items overlapping between the semiconductor device 153 and the semiconductor device 150 will be omitted as appropriate.

The semiconductor device 153 shown in FIG. 11 does not include a MOS-FET.

Further, the aluminum wire 130 is connected between the drain pad (D) of each GaN-HEMT 104 and the external connection terminal 126 (D), and on the source pad (S) of each GaN-HEMT 104 and the die pad portion 122. Between the silver-plated parts. The connection point of the gold wire 132 is between the gate pad (G) of each GaN-HEMT 104 and the external connection terminal 126 (G).

In the semiconductor device 153, each GaN-HEMT 104 has a normally-off specification. At present, the specification of each GaN-HEMT 104 is preceded by normally-on, but by separately connecting each GaN-HEMT 104 and a MOS-FET (not shown) in cascode connection, the operation is normally re-off. Will behave.

[Summary]
A semiconductor device according to one embodiment of the present invention includes a first external connection terminal that serves as a drain of the semiconductor device, and two or more GaN-HEMTs. It is connected to the first external connection terminal.

According to the above configuration, by separating the function originally possessed by one GaN-HEMT into a plurality of GaN-HEMTs, the GaN-HEMT manufactured in the wafer state can be manufactured without degrading the conventional performance. The effective area can be increased and the yield can be improved.

Further, in the semiconductor device according to another aspect of the present invention, in each GaN-HEMT, the distance between the drain pad of the GaN-HEMT and the first external connection terminal is such that the source pad of the GaN-HEMT and the first pad 1 is smaller than the distance from the external connection terminal.

According to the above configuration, the wiring (for example, aluminum wire) connected to the first external connection terminal can be shortened and the bending angle can be reduced. As a result, an increase in torsional stress on the bonded pads can be suppressed.

Further, the semiconductor device according to another aspect of the present invention further includes a MOS-FET, and each GaN-HEMT and the MOS-FET are cascode-connected.

The semiconductor device according to another aspect of the present invention further includes a second external connection terminal serving as a gate, the gate pad of the MOS-FET and the second external connection terminal. Is smaller than the separation distance between the source pad of the MOS-FET and the second external connection terminal.

The gate pad of the MOS-FET and the second external connection terminal are connected by, for example, a gold wire. In this gold wire, reactance increases due to frequency components due to switching, and energy loss occurs. It is more efficient to make the reactance component as short as possible.

Further, in the semiconductor device according to another aspect of the present invention, the MOS-FET further includes a plurality of source pads, and the source pads of the MOS-FET and the gate pads of the GaN-HEMT are in a one-to-one relationship. It corresponds.

The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention. Furthermore, a new technical feature can be formed by combining the technical means disclosed in each embodiment.

The present invention can be used for a semiconductor device in which a plurality of semiconductor devices are mounted on the same plane of a die stage. For example, the present invention is a semiconductor device that houses a GaN-HEMT power device, and can be used as a power switching element mainly used in consumer equipment and industrial equipment.

102 MOS-FET
104 GaN-HEMT
126 (D) External connection terminal (first external connection terminal)
126 (G) External connection terminal (second external connection terminal)
150 Semiconductor Device 151 Semiconductor Device 152 Semiconductor Device 153 Semiconductor Device 155 Semiconductor Device

Claims (5)

A first external connection terminal serving as a drain of the semiconductor device;
With two or more GaN-HEMTs,
A drain pad of each GaN-HEMT is connected to the first external connection terminal. In each GaN-HEMT,
2. The separation distance between a drain pad of a GaN-HEMT and the first external connection terminal is smaller than a separation distance between a source pad of the GaN-HEMT and the first external connection terminal. Semiconductor device. The semiconductor device includes a MOS-FET,
3. The semiconductor device according to claim 1, wherein each GaN-HEMT and MOS-FET are cascode-connected. The semiconductor device includes a second external connection terminal serving as a gate,
The distance between the gate pad of the MOS-FET and the second external connection terminal is smaller than the distance between the source pad of the MOS-FET and the second external connection terminal. Semiconductor device. MOS-FET has multiple source pads,
5. The semiconductor device according to claim 3, wherein each source pad of the MOS-FET and a gate pad of each GaN-HEMT have a one-to-one correspondence.

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