WO2016000296A1 - Low color washout liquid crystal array substrate and driving method therefor - Google Patents

Abstract

A liquid crystal array substrate and a corresponding driving method. The liquid crystal array substrate comprises multiple pixel structures. Each pixel structure comprises a main pixel area (31) and a subpixel area (32). A gate line (36) is provided between the main pixel area (31) and the subpixel area (32). The gate line (36) is provided with a first thin-film transistor (33) and a second thin-film transistor (34) that respectively are connected to the main pixel area (31) and the subpixel area (32). The gate line (36) and the subpixel area (32) also comprise therebetween: a common electrode line (37) and a metal component (39). The common electrode line (37) is provided with an off-state capacitance (38). The metal component (39) is provided with a shared thin-film transistor (35). Also, the shared thin-film transistor (35) is connected to the off-state capacitance (38) and is electrically connected to a data line (40) through a via (41). The pixel structures allow for an increased aperture ratio.

Description

Low color shift liquid crystal array substrate and driving method thereof Technical field

The present invention relates to a low color shift liquid crystal array substrate and a corresponding driving method thereof, and more particularly to a pixel structure in which a sub-gate line is omitted.

Background technique

With the development of the information society, people's demand for display devices has increased year by year, which has promoted the rapid development of liquid crystal panels. The size of the panel is also getting larger and larger, especially for the wide viewing angle and low power consumption. Therefore, the pixel structure design of the thin film transistor (TFT) device and the liquid crystal panel is also diversified.

A general liquid crystal electronic device has a display mode with a wide viewing angle, and in a display mode of a wide viewing angle, Due to the different orientation of the liquid crystal molecules observed at different viewing angles, the color distortion observed at a large viewing angle is caused. At present, in order to improve the color distortion of a large viewing angle, a pixel structure is divided into a main pixel region and a sub-pixel region in the pixel structure design, and the voltage of the sub-pixel region is reduced by sharing the thin film transistor and the off-state capacitance, thereby The difference in liquid crystal rotation between the main pixel region and the sub-pixel region is controlled to improve the phenomenon of color distortion at a wide viewing angle. The above design of dividing the pixel structure into a main pixel region and a sub-pixel region is generally referred to as a low color shift design. (Low Color Shift, LCS).

1 shows a schematic diagram of a pixel structure of a prior art, the pixel structure including a main pixel region 11 and a sub-pixel region 12, and a first thin film transistor connected to the main pixel region 11. 13. A second thin film transistor 14 connected to the sub-pixel region 12, a shared thin film transistor 15, a main gate line 16, and a sub gate line 17 (sub gate) Line), common electrode 18, off-state (Cdown) capacitor 19, and shared thin film transistor 15 and other key components, among which shared thin film transistors The switch of 15 is controlled by the sub-gate line 17, and the Nth sub-gate line is connected to the N+1th or N+2 or N+3 or N+4 main gate lines.

A disadvantage of the above design is that the sub-gate line 17 increases the overlap area with the data line 20, which not only affects the aperture ratio of the pixel, but also causes a short circuit between the gate line and the data line 20 (Gate-Drain) The probability of occurrence of Short, GDS) has increased, and the cost of manufacturing related products has increased significantly. Therefore, it is necessary to provide a pixel structure to solve the problems of the prior art.

technical problem

An object of the present invention is to provide a technical solution of a low color-shift liquid crystal array substrate, which can reduce the occurrence of a bad short circuit by omitting a sub-gate line, thereby improving the aperture ratio and saving cost.

Another object of the present invention is to provide a method for driving a liquid crystal array substrate by directly omitting a shared thin film transistor with a data line by omitting a sub-gate line to reduce occurrence of a defective short circuit, thereby increasing an aperture ratio and saving cost.

Technical solution

In order to achieve the foregoing object of the present invention, the present invention provides a design different from the prior art in which two gate lines are used to realize a low color-offset array substrate. The liquid crystal array substrate of the present invention includes a plurality of pixel structures, each pixel structure. a main pixel region and a sub-pixel region, wherein the main pixel region and the sub-pixel region are provided with a gate line, the gate line is respectively connected to a first thin film transistor and a second thin film transistor, and at least one data line respectively Connecting to the first thin film transistor and the second thin film transistor, wherein the gate line and the sub-pixel interval further comprise: a common electrode line, an off-state capacitor is disposed; and a metal component is provided with a shared thin film transistor and The off-state capacitors are connected and electrically connected to the data lines through a via.

In the liquid crystal array substrate of the present invention, the switch of the shared thin film transistor can be directly controlled by the data line.

In the liquid crystal array substrate of the present invention, the first thin film transistor has a first gate-source capacitance value, the second thin film transistor has a second gate-source capacitance value, and the first gate-source capacitance value is greater than the The second gate source capacitance value.

In the liquid crystal array substrate of the present invention, the metal member is a floating gate.

Another object of the present invention is to provide a method for driving a liquid crystal array substrate by directly omitting a shared thin film transistor with a data line by omitting a sub-gate line to reduce occurrence of a defective short circuit, thereby increasing an aperture ratio and saving cost.

In order to solve the above technical problem, the present invention provides a driving method of a liquid crystal array substrate, the liquid crystal array substrate includes a plurality of pixel structures, each pixel structure includes a main pixel region and a primary pixel region, and the main pixel region and the a sub-pixel section is provided with a gate line, the gate line is respectively connected to a first thin film transistor and a second thin film transistor, and at least one data line is respectively connected to the first thin film transistor and the second thin film transistor, the gate The line and the sub-pixel section further include a common electrode line, and an off-state capacitor is disposed; and a first metal portion is provided with a shared thin film transistor, wherein the gate line generates a voltage signal for controlling the first film a transistor and a switch of a second thin film transistor; the shared thin film transistor is electrically connected to the data line through a via, and the data line generates a voltage signal for controlling switching of the shared thin film transistor.

In the driving method of the present invention, the shared thin film transistor is connected to the off-state capacitor, and when the shared thin film transistor is turned on, a charge of the sub-pixel region is released to the off-state capacitor.

In the driving method of the present invention, the first thin film transistor has a first gate-source capacitance value, the second thin film transistor has a second gate-source capacitance value, and the first gate-source capacitance value is greater than the first The value of the second gate source capacitor.

In the driving method of the present invention, the metal member is a floating gate.

In the driving method of the present invention, the voltage of the data line is 0.2 volt or 14.2 volts in the case of a white screen.

In the driving method of the present invention, the voltage of the data line is 7.7 volts or 7.2 volts in a black screen.

By omitting the setting of the sub-gate lines, the switch of the shared thin film transistor is directly controlled by the data line, and by designing the gate-source capacitance of the thin film transistor in the main pixel region to be larger than the gate-source capacitance of the thin film transistor in the sub-pixel region, The voltage difference between the main pixel region and the sub-pixel region is adjusted such that the voltage between the main pixel region and the sub-pixel region is uniform.

Beneficial effect

In the design of the present invention, the sub-gate lines can be omitted, the overlap of the data lines and the metal parts can be reduced, the occurrence of the GDS failure rate can be reduced, and the display effect of low color shift can be achieved without lowering the pixel aperture ratio. That is to save energy and save costs.

DRAWINGS

FIG. 1 is a schematic diagram of a pixel structure of the prior art.

2 is a schematic view showing the structure of a pixel of the present invention.

Figure 3 is a schematic cross-sectional view taken at the symbol "50" in Figure 2.

BEST MODE FOR CARRYING OUT THE INVENTION

The following description of the various embodiments is provided to illustrate the specific embodiments of the invention. The directional terms mentioned in the present invention, such as "upper", "lower", "before", "after", "left", "right", "inside", "outside", "side", etc., are merely references. Attach the direction of the drawing. Therefore, the directional terminology used is for the purpose of illustration and understanding of the invention. In the figures, structurally similar elements are denoted by the same reference numerals.

The liquid crystal array substrate of the present invention comprises a plurality of pixel structures. FIG. 2 is a schematic diagram of each pixel structure. Each pixel structure includes a main pixel region 31 and a sub-pixel region 32, and the main pixel region 31 and the sub-pixel. A gate line 36 is disposed between the regions 32, and the gate lines 36 are electrically connected to a first thin film transistor. 33 and a gate of a second thin film transistor 34, and at least one data line is respectively connected to a source stage of the first thin film transistor 33 and the second thin film transistor 34, the first thin film transistor 33 and the second thin film transistor The drains of 34 are respectively connected to the main pixel region 31 and the sub-pixel region 32 for controlling the display of the main pixel region 31 and the sub-pixel region 32. The gate line 36 and the sub-pixel region 32 further include: a common electrode line 37 and the common electrode line 37 is provided with an off-state capacitor 38, and a metal member 39 is provided with a shared thin film transistor 35. The shared thin film transistor 35 is electrically connected to the off-state capacitor 38 and electrically connected to the data line 40 through a via 41.

In an embodiment of the invention, the gate line 36, the via hole 41, the metal member 39, and the common electrode line 37 are all a first metal layer, which can be simultaneously formed on the liquid crystal array substrate, and the data line 40 is A second metal layer is formed after the first metal layer and partially overlaps the gate line 36 and the via hole 41.

In an embodiment of the invention, the electrodes of the main pixel region and the sub-pixel region are transparent conductive electrodes, preferably indium tin oxide (ITO).

In an embodiment of the invention, the metal component 39 is a floating gate.

Referring to FIG. 3, FIG. 3 is a schematic cross-sectional view taken along the line "50" in the second embodiment of the present invention, wherein 39 is a metal member, that is, a first metal layer, which may be a floating gate; - silicon nitride layer (Gate-SiNx); 40 is the data line, that is, the second metal layer; 52 is the silicon nitride passivation layer (Passivation-SiNx). Therefore, the metal member 39 is electrically connected to the data lines 40, 40 through the through holes 41.

The voltage of the general data line is a positive and negative half cycle alternating voltage, for example, the voltage at the white screen is 0.2 volts. Or 14.2 volts, the voltage at black screen is 7.7 volts or 7.2 volts. Current vs. voltage curve based on existing amorphous silicon (I-V Curve characteristics, the above 7.2 volts, 7.7 volts, and 14.2 volts can all turn on the switch of the shared thin film transistor 35.

Therefore, unlike the prior art, the sub-gate lines are used to control the switches of the shared thin film transistors. In an embodiment of the invention, the switches of the shared thin film transistors 35 can be directly controlled by the data lines 40, that is, by using the data lines 40. The signal voltage turns on the switch of the amorphous silicon shared thin film transistor 35, so that the charge of the sub-pixel region 32 can be released to the off-state capacitor 38, achieving a low color shift display effect.

Since the voltage of the data line 40 is close to the threshold voltage (Vth) at 0.2 volts, the switch of the shared thin film transistor 35 is regarded as not being turned on, so that the degree of opening of the thin film transistor 35 is different in the positive and negative half cycles under the white screen, and the sub-pixel region is different. The charge released by 32 is also different, resulting in a decrease in the voltage of the positive half cycle of the sub-pixel region 32, and a decrease in the voltage of the negative half cycle, thereby optimally sharing the voltage (Best Vcom) also needs to be adjusted downwards.

Therefore, in order to make the optimal sharing voltage of the main pixel region 31 and the sub-pixel region 32 coincide, in an embodiment of the invention, the thin film transistor in the main pixel region 31 can be regarded as the actual situation. The gate-source capacitance (Cgs) of 33 is designed to be larger, and the optimum shared voltage of the main pixel region 31 is pulled down to the optimum shared voltage of the sub-pixel region 32 by the trip voltage (?Vp). That is, the first thin film transistor in the main pixel region 31 is made The first gate source capacitance value of 33 is greater than the second thin film transistor in the sub-pixel region 32 The second gate-source capacitance value of 34 is used to improve the optimum shared voltage offset caused by the different degrees of positive and negative half-cycle turn-on of the data line when the shared thin film transistor 35 is controlled by the data line 40 (Best Vcom) Shift) phenomenon.

Through the above pixel structure design, the present invention can omit the configuration of the sub-gate lines, directly turn on the switch of the shared thin film transistor with the signal voltage controlled by the data line, and improve the main pixel area by adjusting the gate-source capacitance of the thin film transistor in the main pixel region. The problem of voltage inconsistency with the sub-pixel area. Therefore, not only can the overlap between the data line and the gate line be reduced, the aperture ratio can be increased, and the cost of the overall process can be reduced.

The present invention also relates to a method of driving a liquid crystal array substrate, the liquid crystal array substrate comprising: The liquid crystal display panel includes a plurality of pixel structures, each of the pixel structures includes a main pixel region 31 and a primary pixel region 32. A gate line 36 is disposed between the main pixel region 31 and the sub-pixel region 32. The wires 36 are electrically connected to a first thin film transistor 33 and a second thin film transistor 34, the first thin film transistor 33 and the second thin film transistor 34 is respectively connected to the main pixel area 31 and the sub-pixel area 32 for controlling the display of the main pixel area 31 and the sub-pixel area 32. The gate line 36 and the sub-pixel area 32 further include: A common electrode line 37 is provided with an off-state capacitor 38; and a first metal portion 39 is provided with a shared thin film transistor 35.

In an embodiment of the invention, the metal component 39 is a floating gate.

In an embodiment of the invention, the electrodes of the main pixel region 31 and the sub-pixel region 32 are transparent conductive electrodes, preferably indium tin oxide (ITO).

In an embodiment of the invention, the gate line 36 is used to generate an open or closed voltage signal to the first thin film transistor. 33, for controlling the switch of the first thin film transistor 33, the drain of the first thin film transistor 33 is connected to the first pixel region 31, the first thin film transistor The source of 33 is connected to the data line 40, which inputs a data driving signal when the first thin film transistor 33 is turned on, thereby controlling the display of the main pixel region 31.

In an embodiment of the invention, the gate line 36 is used to generate an on or off voltage signal to the second thin film transistor. 34, for controlling the switch of the second thin film transistor 34, the drain of the second thin film transistor 34 is connected to the second pixel region 32, and the second thin film transistor The source of 34 is coupled to data line 40, which inputs a data drive signal when second thin film transistor 34 is turned "on", thereby controlling display of sub-pixel region 32.

Since the voltage of a general data line is a positive and negative half cycle alternating voltage, for example, a voltage of 0.2 volts or 14.2 volts in a white screen, and a voltage of 7.7 volts or 7.2 volts in a black screen. Current vs. voltage curve based on existing amorphous silicon (I-V The characteristics of Curve, the above 7.2 volts, 7.7 volts, and 14.2 volts can turn on the switches of the shared thin film transistor 35.

Therefore, in an embodiment of the present invention, the switch of the shared thin film transistor 35 can be directly controlled by the data line 40, that is, the shared thin film transistor 35 is electrically connected to the data line 40 through a through hole 41, and utilizes The voltage signal of the data line 40 turns on the switch of the amorphous silicon shared thin film transistor 35.

In an embodiment of the invention, the shared thin film transistor 35 is connected to the off-state capacitor 38. Therefore, when the shared thin film transistor 35 is turned on, the charge of the sub-pixel region 32 is released to the effect that the off-state capacitor 38 achieves a low color shift.

In an embodiment of the invention, the voltage of the data line is 0.2 volts or 14.2 volts in the case of a white screen.

In one embodiment of the invention, the voltage of the data line is 7.7 volts or 7.2 volts in the black frame.

Since the voltage of the data line 40 is close to the threshold voltage at 0.2 volts, the switch of the shared thin film transistor 35 is regarded as not turned on, so that the degree of opening of the thin film transistor 35 is different between the positive and negative half cycles under the white screen, and the sub-pixel region 32 is released. The charge is also different, causing the voltage of the positive half cycle of the sub-pixel region 32 to decrease, and the voltage of the negative half cycle to also decrease, so that the optimum shared voltage also needs to be adjusted downward.

Therefore, in order to make the optimal sharing voltage of the main pixel region 31 and the sub-pixel region 32 coincide, in an embodiment of the invention, the thin film transistor in the main pixel region 31 can be regarded as the actual situation. The gate-source capacitance of 33 is designed to be larger, and the optimum shared voltage of the main pixel region 31 is pulled down to the optimum shared voltage of the sub-pixel region 32 by the hopping voltage. That is, the first thin film transistor in the main pixel region 31 is made The first gate source capacitance value of 33 is greater than the second thin film transistor in the sub-pixel region 32 The second gate-source capacitance value of 34 is to improve the optimum shared voltage shift phenomenon caused by the difference in the degree of opening of the positive and negative half cycles of the data line when the shared thin film transistor 35 is controlled by the data line 40.

In the above, the present invention has been disclosed in the above preferred embodiments, but the preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various modifications without departing from the spirit and scope of the invention. The invention is modified and retouched, and the scope of the invention is defined by the scope defined by the claims.

Claims (11)

A liquid crystal array substrate includes a plurality of pixel structures, each pixel structure including a main pixel region and a primary pixel region. a gate line is disposed in the main pixel region and the sub-pixel region, the gate line is respectively connected to a first thin film transistor and a second thin film transistor, and at least one data line is respectively connected to the first thin film transistor and The second thin film transistor is characterized in that: the gate line and the sub-pixel interval further include: a common electrode line, and an off state capacitor is provided; a floating gate, a shared thin film transistor is disposed to be connected to the off-state capacitor, and electrically connected to the data line through a through hole; The switch of the shared thin film transistor is controlled by the data line; The first thin film transistor has a first gate-source capacitance value, the second thin film transistor has a second gate-source capacitance value, and the first gate-source capacitance value is greater than the second gate-source capacitance value. A liquid crystal array substrate includes a plurality of pixel structures, each pixel structure including a main pixel region and a primary pixel region. a gate line is disposed in the main pixel region and the sub-pixel region, the gate line is respectively connected to a first thin film transistor and a second thin film transistor, and at least one data line is respectively connected to the first thin film transistor and The second thin film transistor is characterized in that: the gate line and the sub-pixel interval further include: a common electrode line, and an off state capacitor is provided; A metal component is provided with a shared thin film transistor connected to the off-state capacitor and electrically connected to the data line through a via. The liquid crystal array substrate according to claim 2, wherein the switch of the shared thin film transistor is controlled by the data line. The liquid crystal array substrate according to claim 2, wherein the first thin film transistor has a first gate-source capacitance value, and the second thin film transistor has a second gate-source capacitance value, the first gate The source capacitance value is greater than the second gate source capacitance value. The liquid crystal array substrate according to claim 2, wherein the metal member is a floating gate. A driving method of a liquid crystal array substrate, the liquid crystal array substrate includes a plurality of pixel structures, each pixel structure includes a main pixel region and a primary pixel region, and the main pixel region and the sub-pixel region are provided with a gate line. The gate lines are respectively connected to a first thin film transistor and a second thin film transistor, and at least one data line is respectively connected to the first thin film transistor and the second thin film transistor, and the gate line and the sub-pixel interval further include A common electrode line is provided with an off-state capacitor, and a first metal portion is provided with a shared thin film transistor, characterized in that: The gate line generates a voltage signal for controlling switching of the first thin film transistor and a second thin film transistor; The shared thin film transistor is electrically connected to the data line through a via, and the data line generates a voltage signal for controlling switching of the shared thin film transistor. The driving method according to claim 6, wherein the shared thin film transistor is connected to the off-state capacitor, and when the shared thin film transistor is turned on, a charge of the sub-pixel region is released to the Off state capacitor. The driving method according to claim 6, wherein the first thin film transistor has a first gate-source capacitance value, and the second thin film transistor has a second gate-source capacitance value, the first gate source The capacitance value is greater than the second gate source capacitance value. The driving method according to claim 6, wherein said metal member is a floating gate. The driving method according to claim 6, wherein the voltage of the data line is 0.2 volt or 14.2 volts in a white screen. The driving method according to claim 6, wherein the voltage of the data line is 7.7 volts or 7.2 volts in a black screen.