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WO2016079881A1 - Module de puissance semi-conducteur, son procédé de fabrication et objet mobile - Google Patents

Module de puissance semi-conducteur, son procédé de fabrication et objet mobile Download PDF

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Publication number
WO2016079881A1
WO2016079881A1 PCT/JP2014/080978 JP2014080978W WO2016079881A1 WO 2016079881 A1 WO2016079881 A1 WO 2016079881A1 JP 2014080978 W JP2014080978 W JP 2014080978W WO 2016079881 A1 WO2016079881 A1 WO 2016079881A1
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WIPO (PCT)
Prior art keywords
semiconductor
power module
solder
solder alloy
insulating substrate
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PCT/JP2014/080978
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English (en)
Japanese (ja)
Inventor
高彰 宮崎
靖 池田
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Hitachi Ltd
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Hitachi Ltd
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Priority to JP2016559781A priority Critical patent/JP6429208B2/ja
Priority to PCT/JP2014/080978 priority patent/WO2016079881A1/fr
Publication of WO2016079881A1 publication Critical patent/WO2016079881A1/fr
Anticipated expiration legal-status Critical
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    • H10W72/30—
    • H10W72/071—
    • H10W72/073—
    • H10W72/5366—
    • H10W72/884—
    • H10W74/00—
    • H10W90/734—
    • H10W90/753—
    • H10W90/754—

Definitions

  • the present invention relates to a semiconductor power module using lead-free solder as a bonding material and a manufacturing method thereof.
  • the present invention relates to a power module that has a high joint temperature.
  • the power module has a structure in which a semiconductor element and an insulating substrate or a heat dissipation base are joined with solder or the like.
  • Solder which is a connecting member used for electrical connection of parts of electrical and electronic equipment, generally contained lead.
  • the lead regulations pointed out have begun. In Europe, the ELV Directive (End-of Life Life Vehicles Directive), which restricts the use of lead in automobiles, and the RoHS (Restriction of the use of certain Hazardous Substances in electrical) that prohibits the use of lead in electrical and electronic equipment and electronic equipment) directive was enforced.
  • solder containing lead (Pb) has been used as a connecting member (bonding material) for semiconductor devices that are required to have high heat resistance, particularly semiconductor devices used in the fields of automobiles, construction equipment, railways, and information equipment.
  • solder containing lead (Pb) has been used as a connecting member (bonding material) for semiconductor devices that are required to have high heat resistance, particularly semiconductor devices used in the fields of automobiles, construction equipment, railways, and information equipment.
  • lead-free connection members to reduce environmental burdens.
  • Si (silicon) semiconductor elements In recent years, development of wide gap semiconductors such as SiC and GaN that can operate at high temperature and can reduce the size and weight of devices has been promoted.
  • the upper limit of the operating temperature of Si (silicon) semiconductor elements is 150 to 175 ° C., whereas SiC semiconductor elements can be used at 175 ° C. or higher.
  • Patent Document 1 Japanese Patent Laid-Open No. 2010-226115.
  • This Patent Document 1 states that “as a connection method with a heat resistance of 200 ° C., an interfacial reaction is suppressed by combining a Sn-based solder containing Cu6Sn5 phase and Ni-based plating from room temperature to 200 ° C., and a heat resistance of 200 ° C. or higher.
  • Semiconductor device (see abstract) ”has been disclosed.
  • Patent Document 2 Japanese Patent Laid-Open No. 2009-255176.
  • This patent document 2 states that “the soldering portion has a composition of Sb of 10 to 40% by mass, Cu of 0.5 to 10% by mass, and a balance of Sn, depending on the solder composition.
  • the problem of the solidification range between the line temperature and the liquidus temperature is solved, and in order to improve the mechanical strength, any one or more of Co, Fe, Mo, Cr, Ag, Bi elements And adding at least one of Ce and Ca as an oxidation-inhibiting element (see summary).
  • a large current is often applied as compared with other electronic components, so that a semiconductor chip (hereinafter also referred to as a chip) generates heat, and stress is applied to the joint.
  • a semiconductor chip hereinafter also referred to as a chip
  • thermal stress is applied due to the difference in coefficient of linear expansion between the chip and the insulating substrate, and between the insulating substrate and the heat dissipation base, and a crack develops from the end part.
  • Grain boundary destruction develops at the center of the joint due to temperature non-uniformity occurring in the joint due to transient heat generation of the chip.
  • the reaction progresses at the bonding interface and the bonding reliability decreases.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2010-226115 discloses a power module and an inverter using Sn-3 to 10 wt% Cu solder at the joint.
  • the technique described in Patent Document 1 has a problem that when Sn—Cu solder is used for the joint, cracks grow quickly and reliability decreases in a high temperature environment.
  • Patent Document 2 Japanese Patent Laid-Open No. 2009-255176
  • a high-temperature lead-free solder alloy composed of Sb 10 to 40% by mass, Cu 1 to 9% by mass and the balance Sn is disclosed.
  • the structure of the joint and the joining temperature are not defined, and these are unclear.
  • An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor power module under a high temperature environment.
  • the semiconductor power module according to the present invention includes a semiconductor element and a bonding material bonded to the semiconductor element, and the semiconductor element and the insulating substrate, or the insulating substrate and the heat dissipation base are Cu1-7. Bonded by the above-mentioned bonding material comprising wt%, Sb 3 to 15 wt%, and the remaining Sn, and the bonding material is bonded at a temperature of 280 ° C. or higher.
  • another semiconductor power module includes a semiconductor element and a bonding material bonded to the semiconductor element. Further, the first Cu—Sn compound, the Sn—Cu—Sb layer, and the second Cu—Sn compound at the junction between the semiconductor element and the insulating substrate or between the insulating substrate and the heat dissipation base. Assuming that the thickness ratio of the above-mentioned joining portion obtained by adding the respective thicknesses is 100, the ratio of the thicknesses of the first Cu—Sn compound and the second Cu—Sn compound is 1 or more and 10 or less. .
  • the bonding layer between the semiconductor element and the insulating substrate or between the insulating substrate and the heat sink is formed by the first Cu—Sn compound, the Sn—Cu—Sb layer, and the first layer.
  • the thickness of the bonding layer is 100, the thicknesses of the first Cu-Sn compound and the second Cu-Sn compound are 1 or more and 10 or less.
  • the semiconductor power module is provided.
  • the method for manufacturing a semiconductor power module according to the present invention includes a semiconductor element and an insulating substrate, or the insulating substrate and a heat dissipation base, Cu 1 to 7 wt%, Sb 3 to 15 wt%, and the remaining Sn. And joining the semiconductor element and the insulating substrate, or joining the insulating substrate and the heat dissipation base.
  • the reliability of the semiconductor power module in a high temperature environment can be improved.
  • FIG. 1 is a sectional view showing an example of the structure of the main part of a semiconductor device according to an embodiment of the present invention, and FIG. It is sectional drawing.
  • a semiconductor device 9 shown in FIG. 1 is a semiconductor power module using a lead-free solder alloy.
  • a schematic configuration of a main part of the semiconductor device 9 will be described.
  • a semiconductor chip 1 as a semiconductor element is a ceramic substrate (covered member). Solder-bonded onto a bonding member (insulating substrate) 5 via a solder alloy (bonding material) 2b.
  • the solder alloy 2b is a solder that does not contain lead (Pb).
  • the ceramic substrate 5 on which the semiconductor chip 1 is mounted is soldered via a solder alloy (joining material) 2c on a heat radiating metal plate 12 which is a heat radiating member (heat radiating base).
  • the solder alloy 2c is also a solder containing no lead (Pb).
  • a wiring portion 5c is formed on the upper surface 5a of the ceramic substrate 5, and a Ni plating layer (Ni metallized layer) 3 as shown in FIG. 2, for example, is formed on the surface of the wiring portion 5c. .
  • a conductor portion 5d is formed on the lower surface 5b of the ceramic substrate 5. The conductor portion 5d is, for example, the Ni plating layer 3 described above.
  • the ceramic substrate 5 is joined to the solder alloy 2b and the solder alloy 2c through the Ni plating layer 3, respectively.
  • At least one of the solder alloy 2 b and the solder alloy 2 c, or both of the solder is Cu 1 to 7 wt (wt)%, Sb 3 to 15 wt (wt)%, It consists of the remainder Sn.
  • the thickness of the solder alloy 2c is larger than the thickness of the solder alloy 2b.
  • the thickness of the solder alloy 2b is about 0.1 mm, and the thickness of the solder alloy 2c is 0.2 to 0.4 mm.
  • solder joining by the lead-free solder alloy of the present embodiment will be described with reference to FIG.
  • a solder foil (joining material) 2a is sandwiched from above and below by a ceramic substrate 5 which is a connected material to which Ni plating 3 is applied (or ceramic substrate 5 and semiconductor). It may be sandwiched between the chip 1).
  • the solder foil (joining material) 2a has a composition composed of Cu 1 to 7 wt%, Sb 3 to 15 wt%, and the remaining Sn. That is, solder bonding is performed using a solder foil 2a having a composition including Cu 1 to 7 wt%, Sb 3 to 15 wt%, and the remaining Sn. That is, in the composition of the solder foil 2a, Sn has the highest content compared to Cu and Sb. Further, the Cu—Sn compound 6 is contained in the solder before joining.
  • the solder foil 2a is heated at a temperature of 280 ° C. or higher.
  • the Cu—Sn compound for example, Cu 6 Sn 5
  • the Cu—Sn based compound layer 4 is formed on the Ni plating layer 3.
  • Sb contained in the solder dissolves in the Sn phase.
  • a Cu—Sn-based compound layer 4 is formed on the Ni plating layer 3 applied to the ceramic substrate 5 as shown after bonding in FIG.
  • a solder alloy 2 mainly composed of Sn containing Sb contained in the solder is formed between the Cu—Sn compound layer 4 and the Cu—Sn compound layer 4.
  • the structure of the solder joint portion is a three-layer structure including the solder alloy 2 and the Cu—Sn-based compound layer 4 formed on the upper and lower layers thereof.
  • the solder alloy 2 is thicker than the Cu—Sn compound layer 4. In other words, the thickness of the solder alloy 2 serving as an intermediate layer in the three-layer structure is the thickest.
  • FIG. 3 is a cross-sectional view (cross-sectional SEM image) showing the structure of the solder joint portion according to the embodiment of the present invention
  • FIG. 4 is a cross-sectional view showing the structure of the solder joint portion of the comparative example.
  • the compound layer mainly composed of the Cu—Sn-based compound layer 4 forms the joint interface and the solder. It becomes a barrier layer with the alloy 2.
  • the Cu—Sn-based compound layer 4 is obtained by replacing a part of the Cu—Sn compound with another element, and Cu—Sn is the main constituent element.
  • the composition with the largest proportion of the composition constituting the bonding layer is called the main constituent element.
  • connection structure of the present invention Cu contained in the solder dissolves only 0.7 wt% in Sn, so that it is precipitated almost as a Cu—Sn compound at the joint interface. Therefore, the joint after soldering is composed of the first Cu—Sn compound layer, the Sn—Cu—Sb layer, and the second Cu—Sn compound layer.
  • the first Cu—Sn compound: Sn—Cu—Sb layer: second Cu—Sn compound has a thickness of 0.5 ⁇ m: 49 ⁇ m: 0. 5 ⁇ m to 5 ⁇ m: 40 ⁇ m: 5 ⁇ m.
  • the first Cu—Sn compound: Sn—Cu—Sb layer: second Cu—Sn compound is 1 ⁇ m: 98 ⁇ m: 1 ⁇ m to 10 ⁇ m: 80 ⁇ m: 10 ⁇ m.
  • the first Cu—Sn compound layer has a ratio of 1 or more and 10 or less. As described above, this varies depending on the composition ratio of the solder implemented in the present invention. That is, the thickness ratio of the Sn—Cu—Sb layer is a value obtained by subtracting the thickness ratio of the first Cu—Sn compound layer and the second Cu—Sn compound layer from 100, which is the ratio of the total thickness. It means that there is.
  • the solder bonding temperature is lower than 280 ° C., as shown in the structure of the comparative example in FIG. 4, the Cu—Sn compound 6 in the solder foil 20 is distributed in a floating island shape in the bonding layer. It does not become the structure of the junction part (after joining) shown in FIG. 2 of this Embodiment. Therefore, as shown in Comparative Examples 6 and 7 in FIG. 8 to be described later, in the joint structure divided into a floating island shape in FIG. 4, when the joint temperature is 280 ° C. or lower, the stability of the joint interface is lowered.
  • the thickness of the Sn—Cu—Sb layer at the joint is less than 50 ⁇ m, the amount of liquid phase generated at the time of joining is small and void (bubble) discharge is reduced, and a large amount of voids remain in the joint layer. Resulting in. Further, when the average thickness of the solder joint becomes thicker than 400 ⁇ m, the amount of Cu—Sn compound contained in the solder becomes excessive, and not only Cu—Sn compound is formed at the joint interface but also in the joint layer. The crack progresses faster because it remains in a floating island shape. Therefore, it is desirable that the thickness of the solder after solder joining is 50 ⁇ m or more and 400 ⁇ m or less.
  • the Cu—Sn compound layer 4 mainly composed of the Cu—Sn compound is used as a barrier between the connection interface and the solder. Since it becomes a layer, the growth of the compound layer due to the reaction at the connection interface and the accompanying formation of voids can be suppressed.
  • solder of the present application does not contain a noble metal in its composition, it is a low-cost material compared to Sn3Ag0.5Cu, which is a standard lead-free solder.
  • FIG. 5 is a plan view of the joint showing the definition of the void ratio in the embodiment of the present invention
  • FIG. 6 is a plan view of the joint showing the definition of the crack in the embodiment of the present invention
  • FIG. 7 is a comparative example. It is sectional drawing which shows the destruction condition at the time of intermittent electricity supply.
  • FIG. 5 shows the progress of the void 7, and the area ratio of the void 7 in the solder joint can be measured by ultrasonic flaw detection.
  • the void ratio is obtained by dividing the total area of the void 7 by the area in the plane direction of the bonding layer in the plane direction of the solder alloy 2 that is the bonding portion.
  • FIG. 6 shows cracks 8 generated in a solder joint due to thermal stress after performing a temperature cycle test of about 500 cycles, with 15 minutes at ⁇ 55 ° C. and 15 minutes at 200 ° C. It is.
  • the crack progress rate in the solder joint portion was measured by ultrasonic flaw detection on the semiconductor device 9 thus subjected to the temperature cycle test.
  • the crack progress rate is obtained by dividing the total area of the crack 8 by the area of the bonding layer in the plane direction in the plane direction of the solder alloy 2 that is the solder joint portion.
  • the void ratio exceeds 10%
  • the crack 8 is preferentially developed from around the void due to the temperature cycle, and the reliability is lowered at an early stage. Therefore, long-term reliability can be ensured by reducing the void ratio.
  • heat is generated by energizing the semiconductor element.
  • the crack growth rate exceeds 20%
  • the heat generated in the semiconductor element is deteriorated, the temperature of the semiconductor element is increased, and the reliability is rapidly decreased.
  • the material of the material to be joined such as the semiconductor chip 1 and the substrate
  • various metals such as Cu, Ni, Au, Ag, Pt, Pd, Ti, TiN, Fe-based alloys such as Fe—Ni and Fe—Co, etc. Alloys are applicable.
  • the material to be joined is Ni metallized.
  • the barrier layer of the Cu—Sn compound layer 4 is formed on the Ni plating layer 3 to suppress the diffusion of Ni, the bonding interface is kept stable, and the high temperature environment. This is because better reliability can be maintained below.
  • Ni when the metallization of the surface of a to-be-joined material is Ni, the oxidation of Ni itself becomes a problem and wettability may be inhibited. Therefore, Au, Ag, Pt, or Pd that is difficult to oxidize may be laminated on Ni. In other words, it is desirable that the surface of the material to be joined is subjected to metallization such as Ni, Ni / Au, Ni / Ag.
  • the semiconductor chip 1 can be bonded to any semiconductor chip 1 such as Si, SiC, GaAs, CdTe, GaN.
  • the substrate by adding the above metallization, Cu, Al, Cu—Mo, Al—SiC (a composite material of aluminum and silicon carbide), Mg—SiC (a composite material of magnesium and silicon carbide), 42 alloy, CIC (Copper Invar Copper), DBC (Direct Bond Copper), DBA (Direct Bond Aluminum) and other metal substrates bonded together, such as a ceramic substrate (insulating substrate) with high reliability Bonding can be realized.
  • the material to be joined (material to be joined) with Ni metallization is joined by the solder alloy 2 of the present embodiment is described in detail, the material to be joined / Ni / Cu—Sn system Compound / solder alloy / Cu—Sn compound / Ni / bonded material.
  • connection between the semiconductor element and the substrate has been described.
  • such a structure is formed by bonding the semiconductor and the lead, the semiconductor and the heat dissipation substrate, the semiconductor and the frame, the semiconductor and the insulating substrate, or the semiconductor and the general electrode.
  • the configuration described above is not limited to the connection between the semiconductor element and the substrate, and is generally applicable to the case where the first connected member and the second connected member are bonded by the bonding material of the present embodiment. can do.
  • the present invention can be applied to joining a metal plate and a metal plate, a metal plate and a ceramic substrate, or the like.
  • FIG. 8 is an evaluation result diagram showing the results of evaluation of each example and comparative example of the present invention.
  • the semiconductor device 9 shown in FIG. 1 is manufactured using the solder foil (lead-free solder alloy) 2a of Examples 1 to 18 shown in FIG. 8, and the void ratio, the bonding interface stability, the temperature cycle reliability, Intermittent conduction reliability was evaluated and examined.
  • a ceramic substrate 5 on which a Ni plating layer 3 as shown in FIG. 2 is formed, a solder foil 2a having the composition of Examples 1 to 18, a 10 mm square, and a thickness of 0.3 mm The ceramic substrates 5 on which the Ni plating layer 3 was formed were stacked and connected in a heat treatment furnace in a 100% H 2 atmosphere.
  • the temperature cycle reliability is determined by measuring the crack growth rate after conducting a temperature cycle test of about 500 cycles, assuming 15 minutes at -55 ° C and 15 minutes at 200 ° C.
  • the crack growth rate which is a reliability criterion, was 20% or less, and the case where the semiconductor element normally operated was evaluated as ⁇ , and the others were evaluated as ⁇ .
  • Interfacial stability was evaluated as “ ⁇ ” when Ni plating remained after holding at 200 ° C. for 1000 hours, and “X” when disappearance was confirmed even partially. This is because when Ni plating disappears, diffusion proceeds between the material to be joined and the solder alloy, an intermetallic compound is formed, voids 7 are generated due to the volume difference, and long-term reliability cannot be maintained.
  • the heat conduction fatigue reliability is general in which the semiconductor chip 1 generates heat by energization, and after reaching 175 ° C., the current is turned off and cooling to 25 ° C. is performed as one cycle, so that the cooling semiconductor device can obtain a certain reliability.
  • the thermal resistance of the semiconductor chip 1 is measured after a 5000 cycle test, which is a reference thermal fatigue test. Then, when the thermal resistance was increased by less than 20% and the semiconductor chip 1 normally operated, the evaluation was evaluated as “ ⁇ ” and the others were evaluated as “X”.
  • the overall evaluation was evaluated as ⁇ when the evaluation was good under all conditions, and ⁇ when there was one that could not meet the reliability standards, because reliability under a high temperature environment could not be secured.
  • the bonding material having a good crack growth rate in the temperature cycle test is Sn 3 wt% or more 7 wt% or less and 9 wt% or more 11 wt% or less Sb. It was confirmed that it was added.
  • the solder bonding temperature was 300 ° C. was evaluated, and it was confirmed that the same structure after bonding as in the case of 280 ° C. was obtained even at 300 ° C. That is, the structure after joining shown in FIG. 2 can be obtained by joining at a temperature of 280 ° C. or more and 300 ° C. or less using the solder (joining material) of Examples 1 to 18 shown in FIG. In consideration of the influence of heat on other members, it is desirable to join at a temperature as low as possible even at 280 ° C. or higher.
  • Cu—Sn compound is formed at the bonding interface by adding Cu at 1 wt% or more and 7 wt% or less and bonding at a bonding temperature of 280 ° C. or higher.
  • Example 1 shown in FIG. 8 the temperature cycle reliability can be maintained by adding more than 1% by weight of Sb.
  • Comparative Example 6 when 15% or more of Sb is added, the void ratio is evaluated as x, and the temperature cycle reliability is also x. This is because as the amount of Sb added increases, the amount of Sn—Sb-based compound precipitated in the solder increases, and the viscosity of the solder increases, the void ratio increases, the solder becomes harder, and the temperature cycle reliability decreases. It is.
  • FIG. 9 is a cross-sectional view showing an example of the structure of a semiconductor device (semiconductor power module) using the lead-free solder alloy (joining material) according to the embodiment of the present invention.
  • a semiconductor power module (a semiconductor device, hereinafter also referred to as a semiconductor module) 10 shown in FIG. 9 is a power module mounted on, for example, a railway vehicle or an automobile. Therefore, heat dissipation measures for the power module are required.
  • the configuration of the semiconductor module 10 will be described.
  • the semiconductor chip 1 is formed of a ceramic substrate (chip support member, insulating material) using the solder alloy (any of the solder alloys (joining materials) of Examples 1 to 18) 2b of the present embodiment. (Connected substrate, connected member) 5.
  • a metal plate for heat radiation including a concept of a heat radiation member, a heat radiation base, a heat radiation plate, a heat radiation fin, and a heat sink
  • a ceramic substrate 5 that play a role of releasing heat during operation of the semiconductor chip 1 are provided in this embodiment.
  • Solder alloy 2c (a joining material, any of the lead-free solder alloys of Examples 1 to 18), which is a lead-free solder alloy of the form, is connected.
  • the specific structure of the semiconductor module 10 shown in FIG. 9 will be described.
  • the semiconductor chip 1, and a ceramic substrate (insulating substrate, connected member) 5 which is a chip support member connected to the semiconductor chip 1 via a solder alloy 2b; And a lead (external terminal) 13 electrically connected to the semiconductor chip 1. That is, a conductor portion 5d such as a wiring pattern is formed on the upper surface 5a of the substrate body portion 5e of the ceramic substrate 5, and a solder alloy (any of the lead-free solder alloys of Examples 1 to 18) is formed on the conductor portion 5d.
  • the semiconductor chip 1 is mounted via 2b.
  • a wiring part (wiring pattern) 5c is formed on the upper surface 5a of the substrate body 5e of the ceramic substrate 5, and the leads 13 are electrically connected to the wiring part 5c.
  • the electrode pad 1c and the lead 13 formed on the main surface 1a of the semiconductor chip 1 and the electrode pad 1c and the wiring part 5c are electrically connected by a wire 11 such as a gold wire or a copper wire, respectively. ing.
  • a wiring portion 5c is formed on the lower surface 5b of the substrate body portion 5e of the ceramic substrate 5, and the wiring portion 5c is used for heat dissipation via the solder alloy 2c (any of the lead-free solder alloys of Examples 1 to 18).
  • a metal plate (heat radiating member) 12 is connected.
  • the semiconductor module 10 is manufactured by connecting the semiconductor chip 1 and the ceramic substrate 5 with the solder alloy 2b, and then connecting the ceramic substrate 5 and the heat radiating metal plate 12 with another solder alloy 2c.
  • solder alloy 2b that connects the semiconductor chip 1 and the ceramic substrate 5 is remelted by heating when connecting the ceramic substrate 5 and the heat radiating metal plate 12, the molten solder flows, Misalignment or the like occurs, leading to a failure.
  • a material having a melting point lower than that of the solder alloy 2b it is necessary to employ a material having a melting point lower than that of the solder alloy 2b.
  • the solder alloy 2 of Examples 1 to 18 which is the solder alloy 2 (2b, 2c) of the present embodiment is used, the Cu—Sn-based compound layer 4 having undulations as shown in FIG. Therefore, no solder flow occurs and the semiconductor chip 1 is not displaced.
  • any one of the solder alloys 2 of Examples 1 to 18 is applied to the solder alloy 2b of the semiconductor module 10 shown in FIG. 9, and, similarly to Examples 1 to 18, the bonding temperature is 280 ° C., the holding time is 5 min, N In a 2 + 4% H 2 atmosphere, the semiconductor chip 1 and the Ni / Cu / Si 3 N 4 / Cu / Ni ceramic substrate 5 on which the Ni plating layer 3 is formed are connected, thereby the semiconductor device 9 as a connection body.
  • solder alloy 2c of any of Examples 1 to 18 is sandwiched between the heat dissipation metal plate 12 which is an AlSiC / Ni substrate and the semiconductor device 9, and the bonding temperature is 280 ° C., the holding time is 5 min, no load, 100% H 2.
  • the semiconductor module 10 was formed by connecting in an atmosphere. Therefore, the ceramic substrate 5 and the heat radiating metal plate 12 can be connected without remelting the solder alloy 2b of the semiconductor device 9.
  • the lead 13 is connected to the semiconductor device 9 thus formed, and the electrode pad 1c on the main surface 1a of the semiconductor chip 1 is bonded to the wiring portion 5c and the lead 13 on the ceramic substrate 5 with the wire 11.
  • the semiconductor module 10 can be formed.
  • the interface between the lead-free solder alloy (solder alloy 2) and the semiconductor chip 1, the interface between the lead-free solder alloy and the ceramic substrate 5, and the lead-free solder alloy Ni plating layers 3 are respectively formed at the interfaces of the connecting portions with the heat radiating metal plate 12.
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • the solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • connection reliability in each connection part of the lead-free solder alloy (solder alloy 2) can be improved.
  • FIG. 10 is a cross-sectional view showing an example of the structure of a semiconductor device (semiconductor power module) using the lead-free solder alloy according to the embodiment of the present invention.
  • a semiconductor module (semiconductor power module) 19 shown in FIG. 10 has a bonding material such as solder alloy 2b or solder alloy 2b bonded to the front and back surfaces of the semiconductor chip 1, and lead frames 28 are bonded to the bonding materials on both surfaces of the semiconductor chip 1. Further, the heat radiating metal plate 12 is bonded to the lead frame 28 via the insulating heat radiating grease 27.
  • the structure of the solder joint portion of the present embodiment is also applicable to a power module (semiconductor module 19) having a structure in which heat is radiated from the front and back both sides of the semiconductor chip 1 by the heat radiating metal plate 12.
  • the structure of the solder joint portion of the present embodiment can be applied to, for example, a miniaturized semiconductor module 34 that is not mounted with a diode chip as shown in FIG. Since the current density generally increases by downsizing the power module (semiconductor module 34), the temperature of the solder joint also increases. However, this can be realized by using the present invention.
  • FIG. 11 is a partial side view showing an example of a railway vehicle on which the semiconductor module 10 using the lead-free solder alloy of the present embodiment is mounted
  • FIG. 12 shows an example of the internal structure of the inverter installed in the vehicle of FIG. FIG.
  • FIG. 11 shows a railway vehicle 21 provided with a pantograph 22 that is a current collector, and an inverter 23 is provided below the vehicle 21.
  • a plurality of semiconductor modules 10 are mounted on a printed circuit board 25, and a cooling device 24 that cools these semiconductor modules 10 is further mounted.
  • the cooling device 24 is attached so that the plurality of semiconductor modules 10 can be cooled to cool the inside of the inverter 23.
  • the inverter 23 equipped with the plurality of semiconductor modules 10 using the lead-free solder alloy (solder alloy 2) of the present embodiment is provided in the railway vehicle 21, so that the temperature inside the inverter 23 is high. Even when it becomes an environment, the reliability of the inverter 23 and the vehicle 21 provided with the inverter 23 can be improved.
  • the semiconductor device shown in FIG. 13 is, for example, a semiconductor module (semiconductor power module) 18 for an on-vehicle AC generator.
  • FIG. 14 is a perspective view showing an example of an automobile on which the semiconductor power module shown in FIG. 13 is mounted.
  • the configuration of the semiconductor module 18 shown in FIG. 13 will be described.
  • the connection portion connected to the semiconductor chip (diode) 1 and the back surface 1b of the semiconductor chip 1 via the solder alloy (lead-free solder alloy) 2c of the present embodiment.
  • a cylindrical cap (lead electrode body) 15 having Ni plating applied thereto.
  • the semiconductor module 18 is for thermal expansion coefficient difference buffering in which Ni-based plating is applied to a connection portion connected to the main surface 1a of the semiconductor chip 1 via the solder alloy (lead-free solder alloy) 2b of the present embodiment.
  • Buffer material 17, and Cu lead (external terminal) 14 having Ni-based plating applied to the connecting portion connected to the other surface of the buffer material 17 via the solder alloy (lead-free solder alloy) 2 c of the present embodiment.
  • Buffer material 17, and Cu lead (external terminal) 14 having Ni-based plating applied to the connecting portion connected to the other surface of the buffer material 17 via the solder alloy (le
  • the cylindrical cap 15 is filled with a sealing resin 16 that seals part of the semiconductor chip 1, the buffer material 17, the solder alloys 2 b and 2 c, and the Cu lead 14.
  • the buffer material 17 is preferably 30 to 500 ⁇ m. This is because when the thickness of the buffer material 17 is less than 30 ⁇ m, the stress cannot be sufficiently buffered, and cracks may occur in the semiconductor chip 1 and the intermetallic compound. Further, when the thickness of the buffer material 17 exceeds 500 ⁇ m, Al, Mg, Ag, and Zn have a larger coefficient of thermal expansion than the Cu lead 14, and therefore the connection reliability is reduced due to the influence of the difference in coefficient of thermal expansion. There is.
  • the buffer material 17 it is preferable to use any one of Cu / Invar alloy / Cu composite material, Cu / Cu composite material Cu—Mo alloy, Ti, Mo, and W.
  • the buffer material 17 it is possible to buffer the stress generated in the connection portion during the temperature cycle and the cooling after the connection resulting from the difference in thermal expansion coefficient between the semiconductor chip 1 and the Cu lead 14.
  • the stress applied to the semiconductor chip 1 can be reduced, and the formation of cracks in the semiconductor chip 1 can be reduced. Furthermore, in the semiconductor module 18, the connection reliability of the solder connection can be improved.
  • the automobile 32 shown in FIG. 14 is mounted with the semiconductor module 18 shown in FIG. 13, and is a vehicle body 31, a tire 29, the semiconductor module 18, and a mounting member that supports the semiconductor module 18. And a mounting unit 30.
  • the semiconductor module 18 is mounted on the mounting unit 30.
  • the mounting unit 30 is, for example, an engine control unit, and in this case, the mounting unit 30 is disposed in the vicinity of the engine. In this case, the mounting unit 30 is used in a high temperature environment, and the semiconductor module 18 is also in a high temperature state.
  • the solder alloy 2 of the present embodiment (the lead-free solder alloys of Examples 1 to 18 ( By applying any one of the solder alloy 2 and the bonding material), the Cu—Sn based compound layer (see FIG. 2) 4 can be formed thick at each interface at each connection portion of the lead-free solder alloy. . As a result, the interface stability at each solder connection portion can be improved.
  • connection reliability in each connection part of the lead-free solder alloy (solder alloy 2) can be improved. That is, the reliability of the semiconductor module 18 can be increased.
  • FIG. 15 is a cross-sectional view showing the structure of a semiconductor power module of a first modification of the embodiment of the present invention.
  • a semiconductor module (semiconductor power module) 33 shown in FIG. 15 is a power module in which a plurality of semiconductor chips 33 a and a plurality of semiconductor chips 33 b are mounted on the ceramic substrate 5.
  • the semiconductor chip 33a is, for example, a MOS (Metal Oxide Semiconductor) made of SiC
  • the semiconductor chip 33b is, for example, a diode made of SiC.
  • the semiconductor module 33 is also called a full SiC module or the like, and each mounted semiconductor chip is made of SiC.
  • solder alloy (joining material, lead-free solder alloy) 2b is applied to each lower surface side of the semiconductor chip 33a and the semiconductor chip 33b, and a solder is interposed between the ceramic substrate 5 and the heat radiating metal plate 12. Alloy 2c (joining material, lead-free solder alloy) is applied.
  • the lead 13 is electrically connected to the wiring part 5 c of the ceramic substrate 5, and the electrode pads of the semiconductor chips 33 a and 33 b and the wiring part 5 c on the ceramic substrate 5 are connected to the wire 11. It is bonded by.
  • solder alloy 2 of this embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of this embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of this embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of this embodiment solder alloy 2, bonding material
  • connection reliability in each connection part of the lead-free solder alloy (solder alloy 2) can be improved. That is, the reliability of the semiconductor module 33 can be increased.
  • FIG. 16 is a cross-sectional view showing the structure of a semiconductor power module of a second modification of the embodiment of the present invention.
  • the semiconductor module 34 shown in FIG. 16 is a power module in which a plurality of semiconductor chips 34 a are mounted on the ceramic substrate 5.
  • the semiconductor chip 34a is, for example, a MOS MOS, and further includes a diode.
  • the diode is incorporated in the semiconductor chip 34a, and the semiconductor module 34 in this case is also called a full SiC module or the like.
  • solder alloy jointing material, lead-free solder alloy
  • solder alloy 2c jointing material, lead-free solder alloy
  • the lead 13 is electrically connected to the wiring portion 5 c of the ceramic substrate 5, and the electrode pad of the semiconductor chip 30 a and the wiring portion 5 c on the ceramic substrate 5 are bonded by the wire 11. ing.
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • solder alloy 2 of the present embodiment any of the lead-free solder alloys of Examples 1 to 18 (solder alloy 2, bonding material)
  • connection reliability in each connection part of the lead-free solder alloy (solder alloy 2) can be improved. That is, the reliability of the semiconductor module 34 can be increased.
  • the number of chips to be mounted can be reduced by incorporating diodes in the chip.
  • the cost of the semiconductor module 34 can be reduced compared to the semiconductor module 33.
  • the heat radiating metal plate 12 described in the above embodiment may be a plate-shaped heat radiating plate, or a heat radiating member provided with a plurality of fins.
  • the joining structure or joining method of the present invention is not limited to automobiles and railway vehicles, but also solar power generators, power conditioners, wind power generators, construction machines, elevators, air conditioners, machine tools, motors, compressors, and other industrial equipment.
  • the present invention can also be applied to an inverter that operates. It can also be applied to IGBT modules, alternators, AC motors, and the like.

Landscapes

  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention concerne un dispositif semi-conducteur (un module de puissance semi-conducteur) (9) qui comprend : une puce semi-conductrice (1) ; un substrat (5) de céramique qui est connecté à la puce semi-conductrice (1), un alliage de brasure (un alliage de brasure sans plomb) (2b) étant intercalé entre eux ; une borne externe qui est électriquement connectée à la puce semi-conductrice (1) ; une plaque de métal pour la dissipation thermique (12) qui est connectée au substrat (5) de céramique, un alliage de brasure (un alliage de brasure sans plomb) (2c) étant intercalé entre eux. Les alliages de brasure (2b, 2c) dans le dispositif semi-conducteur (9) sont des matériaux liants, chacun étant composé de 1 à 7 % en poids de Cu et de 3 à 15 % en poids de Sb, l'équilibre étant constitué de Sn, et étant lié à une température supérieure ou égale à 280 °C.
PCT/JP2014/080978 2014-11-21 2014-11-21 Module de puissance semi-conducteur, son procédé de fabrication et objet mobile Ceased WO2016079881A1 (fr)

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JP2016559781A JP6429208B2 (ja) 2014-11-21 2014-11-21 半導体装置および移動体
PCT/JP2014/080978 WO2016079881A1 (fr) 2014-11-21 2014-11-21 Module de puissance semi-conducteur, son procédé de fabrication et objet mobile

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CN113039636A (zh) * 2018-11-21 2021-06-25 日立汽车系统株式会社 功率半导体装置
JPWO2022230697A1 (fr) * 2021-04-28 2022-11-03
WO2022244395A1 (fr) * 2021-05-18 2022-11-24 富士電機株式会社 Dispositif à semi-conducteur
WO2022259633A1 (fr) * 2021-06-09 2022-12-15 日立Astemo株式会社 Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur
CN115552576A (zh) * 2020-05-26 2022-12-30 株式会社日立功率半导体 半导体装置
CN115989579A (zh) * 2020-10-07 2023-04-18 株式会社东芝 接合体、陶瓷电路基板及半导体装置
WO2024038665A1 (fr) * 2022-08-16 2024-02-22 日立Astemo株式会社 Dispositif électronique et procédé de fabrication de dispositif électronique
TWI835016B (zh) * 2020-12-23 2024-03-11 日商日立功率半導體股份有限公司 半導體裝置及其製造方法

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CN113039636A (zh) * 2018-11-21 2021-06-25 日立汽车系统株式会社 功率半导体装置
CN115552576A (zh) * 2020-05-26 2022-12-30 株式会社日立功率半导体 半导体装置
CN115989579A (zh) * 2020-10-07 2023-04-18 株式会社东芝 接合体、陶瓷电路基板及半导体装置
TWI835016B (zh) * 2020-12-23 2024-03-11 日商日立功率半導體股份有限公司 半導體裝置及其製造方法
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WO2022259633A1 (fr) * 2021-06-09 2022-12-15 日立Astemo株式会社 Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur
JP7610471B2 (ja) 2021-06-09 2025-01-08 日立Astemo株式会社 半導体装置および半導体装置の製造方法
WO2024038665A1 (fr) * 2022-08-16 2024-02-22 日立Astemo株式会社 Dispositif électronique et procédé de fabrication de dispositif électronique

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