WO2015130114A1 - Non-volatile resistive random access memory element and method for producing same - Google Patents

Abstract

The present invention relates to a non-volatile resistive random access memory element and a method for producing same. More specifically, the non-volatile resistive random access memory element, which is includes an insulating layer between conductive layers, comprises: a first electrode; a first metal oxide insulating layer adjacent to the first electrode; a metal nanoparticle layer adjacent to the first metal oxide insulating layer; a second metal oxide insulating layer adjacent to the metal nanoparticle layer; and a second electrode adjacent to the second metal oxide layer.

Description

Nonvolatile resistance change memory device and manufacturing method thereof

The present invention relates to a nonvolatile resistance change memory device and a method of manufacturing the same. More specifically, a nonvolatile resistance change memory device comprising a non-conductor layer formed between conductor layers, comprising: a first electrode; An insulator layer made of a first metal oxide formed adjacent to the first electrode; A metal nanoparticle layer formed adjacent to the first metal oxide insulator layer; An insulator layer made of a second metal oxide formed adjacent to the metal nanoparticle layer; And a second electrode formed adjacent to the second metal oxide layer, and a nonvolatile resistance change memory device and a method of manufacturing the same.

Conventional storage techniques (flash memory with floating gates, and DRAM containing capacitors and transistors together) are based on the storage of charge on inorganic silicon based materials. These techniques for storing charges will reach scale limits in the near future. Therefore, research on other methods for storing information is increasing.

Examples of semiconductor memory devices widely used in recent years include dynamic random access memory (DRAM), static RAM (SRAM), and flash memory. Such semiconductor memory devices may be classified into volatile memory devices and non-volatile memory devices. The nonvolatile memory device is a memory device that retains data stored in a memory cell even when power supply is interrupted. Flash memory or the like belongs to the nonvolatile memory device.

Resistive Random Access Memory (RRAM) devices, which have been studied since the 1960s, are memory devices that exhibit a characteristic that the resistance state changes to a high or low resistance state depending on the voltage. It is a memory element that maintains a resistance value even if the value changes and the power supply after the change is cut off.

The resistance change memory device has a high density, fast information entry and exit speed, and a nonvolatile resistance change memory device based on a resistance switching phenomenon in which resistance changes with voltage.

Different types of resistive change memories operating through conductive path breakdown and formation are based on the principle of storing one or more bits of data per memory cell using a change in the resistance value of the metal oxide that occurs under voltage.

Using a thin film showing the electrical resistance as a storage element, a voltage is applied to flow a current to change the resistance value. In general, data is stored by setting the reset state with high resistance to 0 and the set state with low resistance to 1.

The basic structure of the memory cell of the resistance change memory is the same as that of the flash memory. Memory cells may be formed of one memory device to implement a high density nonvolatile memory having a memory capacity of flash memory level. Resistive memory cells can theoretically reduce volumes by 3-4 nm ³ , which is much smaller than all memory devices based on conventional charge scale.

In general, an RRAM device is a metal-insulator-meta (MIM) structure using a metal oxide, and when a suitable electrical signal is applied, a low resistance can be conducted in an OFF state. The memory characteristic changes to state. According to the electrical method for implementing the ON / OFF memory characteristics, it can be classified into a current controlled negative differential resistance (CCNR) or a voltage controlled negative differential resistance (VCNR). In the case of VCNR, as the voltage increases, the current changes from a large state to a small state. An on / off memory characteristic can be realized by using a large difference in resistance. The switching mechanism that causes this ON / OFF behavior is not yet clearly identified.

Republic of Korea Patent Application No. 10-2011-0146243, the first electrode; Second electrode; A variable resistance layer interposed between the first electrode and the second electrode; And a nanoparticle positioned in the variable resistance layer, the nanoparticle having a lower dielectric constant than the variable resistance layer, and a method of manufacturing the same.

The invention of the Republic of Korea Patent Application No. 10-2011-0146243, the nanoparticles are included in the variable resistance layer, the first variable resistance layer and the second variable resistance layer is in physical contact, the nanoparticles do not form a layer In that respect, there is a difference from the present invention.

Republic of Korea Patent Application No. 10-2009-0035389, the first electrode; Conductive nanoparticles positioned on the first electrode; A resistance change material layer on the conductive nanoparticles; And a second electrode on the resistance change material layer, and a method of manufacturing the same.

The invention of Korean Patent Application No. 10-2009-0035389 has a difference from the present invention in that the nanoparticles do not have a layered structure and the nanoparticles are included in the metal oxide film while contacting the first electrode. .

Republic of Korea Patent No. 10-0817752, Non-volatile memory cell, a first conductive electrode region; A second conductive electrode region; And is arranged between the first conductive electrode region and the second conductive electrode region, and contains one or more metal oxide nanoparticles, wherein the metal oxide nanoparticles are via the contact positions and the first conductive electrode region and the second conductive electrode region. Contacting and electrically connected to a second conductive electrode region, the metal oxide nanoparticles exhibit bistable resistance when an external voltage is applied, the metal oxide nanoparticles are NiO _1-x nanoparticles, and x is 0.5 Disclosed is a nonvolatile memory cell including a memory region in the range of 0.9 to 0.95 and a method of manufacturing the same.

The invention of the Republic of Korea Patent No. 10-0817752 is that the nanoparticles are metal oxides, not metals, the nanoparticles are in contact with the upper electrode and the lower electrode, the nanoparticles are included in the insulating layer does not form a layer. In the difference between the present invention exists.

Republic of Korea Patent No. 10-1295888, The first electrode on the substrate; An electron channel layer on the first electrode; And a second electrode on the electron channel layer, wherein an upper surface of the electron channel layer protrudes toward the second electrode under the second electrode, and a method of manufacturing the same. .

The invention of the Republic of Korea Patent No. 10-1295888 is different from the method of the present invention in that the organic thin film layer is used, the nanochannel is included in the organic thin film layer is formed an electron channel layer, the nanoparticles do not form a layer. This exists.

The present inventors have completed the present invention in view of the fact that the driving current of the resistance variable memory device can be significantly reduced by forming a metal nanoparticle layer between the metal oxide insulator layers.

In particular, the metal nanoparticle layer can be formed by Langmuir-Blodgett assembly, layer-by-layer assembly or spin-coating assembly. In addition, the technical characteristics of the present invention is that as the number of the metal nanoparticle layers is increased by one, the driving current of the resistance variable memory device can be reduced by an order of magnitude.

SUMMARY OF THE INVENTION A basic object of the present invention is a nonvolatile resistance change memory device comprising a non-conductor layer formed between conductor layers, comprising: a first electrode; An insulator layer made of a first metal oxide formed adjacent to the first electrode; A metal nanoparticle layer formed adjacent to the first metal oxide insulator layer; An insulator layer made of a second metal oxide formed adjacent to the metal nanoparticle layer; And a second electrode formed adjacent to the second metal oxide layer.

Yet another object of the present invention is to provide a method for forming a substrate comprising: (i) forming a first electrode on a substrate; (ii) forming an insulator layer made of a first metal oxide adjacent to the first electrode; (iii) forming a metal nanoparticle layer adjacent the first metal oxide insulator layer; (iv) forming an insulator layer made of a second metal oxide adjacent to the metal nanoparticle layer; and (v) forming a second electrode adjacent to the second metal oxide insulator layer.

The above-described basic object of the present invention is a nonvolatile resistance change memory device comprising a non-conductor layer formed between a conductor layer, comprising: a first electrode; An insulator layer made of a first metal oxide formed adjacent to the first electrode; A metal nanoparticle layer formed adjacent to the first metal oxide insulator layer; An insulator layer made of a second metal oxide formed adjacent to the metal nanoparticle layer; And a second electrode formed adjacent to the second metal oxide layer.

The first electrode included in the nonvolatile resistance change memory device of the present invention may be selected from Al, Cu, Ag, Au, Pt, TiN, indium tin oxide (ITO), TaN, W, Mg, Zn or Fe. .

The first metal oxide included in the nonvolatile resistance change memory device of the present invention is selected from titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide, or hafnium oxide. Can be selected. In addition, the thickness of the first metal oxide insulator layer may be 5 nm to 200 nm.

The metal nanoparticles constituting the metal nanoparticle layer are nanoparticles of a metal selected from Au, Pt or Ag. In addition, the size of the metal nanoparticles may be 2 nm to 40 nm.

Furthermore, the metal nanoparticle layer can be formed by Langmuir-blojet assembly, layer-by-layer assembly or spin coating assembly of the metal nanoparticles. The number of metal oxide nanoparticle layers is, for example, determined by the number of Langmuir-blojet assembly processes, and the number of nanoparticle layers can be selected according to the range of acceptable operating currents in the system. For example, the number of the nanoparticle layers is preferably 1 layer to 10 layers, more preferably 3 layers.

As used herein, "langmuir-blojet assembly" refers to a two-dimensional layer of nanoparticles by dipping a solid substrate into a liquid and then removing and transferring one or more nanoparticle monolayers from the subphase of the liquid onto the solid substrate. It means to form.

As used herein, "self-assembly" refers to the process by which a disordered system of components forms an organized structure or pattern as a result of certain local interactions between the components.

The second metal oxide of the memory device of the present invention may be selected from titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide or hafnium oxide. In addition, the thickness of the second metal oxide insulator layer may be 5 nm to 200 nm.

The second electrode of the memory device of the present invention may be selected from Al, Cu, Ag, Au, Pt, TiN, ITO, TaN, W, Mg, Zn or Fe.

Still another object of the present invention described above is the steps of (i) forming a first electrode on a substrate; (ii) forming an insulator layer made of a first metal oxide adjacent to the first electrode; (iii) forming a metal nanoparticle layer adjacent the first metal oxide insulator layer; (iv) forming an insulator layer made of a second metal oxide adjacent to the metal nanoparticle layer; and (v) forming a second electrode adjacent to the second metal oxide insulator layer.

* The step (i) of the method of the present invention may be performed by thermal evaporation, electron bean evaporation or magnetron sputtering. In addition, the first electrode may be selected from Al, Cu, Ag, Au, Pt, TiN, ITO, TaN, W, Mg, Zn or Fe.

The step (ii) of the method of the present invention may be performed by magnetron sputtering or atomic layer deposition. In addition, the first metal oxide may be selected from titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide, or hafnium oxide. Furthermore, the thickness of the first metal oxide insulator layer may be 5 nm to 200 nm.

* The step (iii) of the method of the present invention can be carried out by Langmuir-blojet assembly, layer-by-layer assembly or spin coating assembly of the metal nanoparticles. In addition, the metal nanoparticles may be selected from Au, Pt or Ag. Furthermore, the number of metal oxide nanoparticle layers is, for example, determined by the number of Langmuir-blojet assembly processes, and the number of nanoparticle layers can be selected according to the range of allowable operating currents in the system. For example, the number of the nanoparticle layers is preferably 1 layer to 10 layers, more preferably 3 layers.

Step (iv) of the method of the present invention may be performed by magnetron sputtering or atomic layer deposition. In addition, the second metal oxide may be selected from titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide, or hafnium oxide. Furthermore, the thickness of the second metal oxide insulator layer may be 5 nm to 200 nm.

Step (v) of the method of the present invention may be performed by thermal deposition, electron beam deposition or magnetron sputtering. In addition, the second electrode may be selected from Cu, Ag, Au, Pt, TiN, ITO, TaN, W, Mg, Zn or Fe.

The resistive variable memory device of the present invention consumes less power than the conventional resistive variable memory device. In particular, as the number of metal nanoparticle layers increases by one, the set current and reset current decrease by an order of magnitude, thereby increasing the number of the metal nanoparticle layers to further increase power consumption of a memory device. You can save more.

1A is a diagram illustrating Langmuir-Blozet (LB) assembly and stearic acid (SAM) functionalization; 1B are photographs (top) for the LB assembly process and planar TEM photographs (bottom) for one layer gold nanoparticles and three layer gold nanoparticles; 1C is cross-sectional TEM photographs of fabricated memory cells; 1D is an EDS profile showing the thickness of three layer gold nanoparticles in MINIM (Metal-Insulator-Nanoparticle-Insulator-Metal).

FIG. 2A shows the I-V characteristics of bipolar resistive switching of MIM (Metal-Insulator-Metal), MISIM (Metal-Insulator-Self-Assembled Monolayer (SAM) -Insulator-Metal) and MINIM structures; 2B is a diagram illustrating low current resistive switching due to Au nanoparticle-induced traps; 2C is an I-V curve at MIM and MINIM; 2D shows I-V characteristics at compliance currents up to about 100 μA in MIM and MINIM; FIG. 2E is the reliability test (durability (left) and retention (right)) results of MINIM (resistance measurement at -0.5 V); 2F is the cumulative probability in MIM and MINIM; 2G shows MLC (multilayer cell) operation in MIM (left) and MINIM (right).

Hereinafter, the present invention will be described in more detail with reference to the following examples or drawings. However, the following description of the embodiments or drawings is only intended to specifically describe the specific embodiments of the present invention, it is not intended to limit or limit the scope of the present invention to the contents described therein.

Example 1 Synthesis of Gold Nanoparticles

0.4 g of HAuCl ₄ .3H ₂ O (99.9%, Strem, USA), oleylamine (90%, Acros, USA) and 30 mL of 1-octadecene (90%, Sigma Aldrich, USA) at room temperature 50 Mix in mL glass vials. The vial was placed in an oil bath and heated to 90 ° C. The solution was heated for 2 hours, after which nanoparticles were precipitated and washed twice with ethanol and then centrifuged. The precipitated nanoparticles were redispersed in 5 mL of chloroform.

Example 2 Fabrication of Nonvolatile Resistance Change Memory Device

Poly (methyl methacrylate) (PMMA) (A11, Microchem, USA; spincoated at about 1 μm for 30 seconds at 3000 rpm) and polyimide (PI) (polyamic acid, Sigma Aldrich, USA; about 1.2 μm, 4000 Thin layers of precursor solution of 60 seconds spincoated at rpm were spincoated onto a Si handle wafer (test grade, 4science, Korea). After the PMMA and PI were cured at 200 ° C. for 2 hours, aluminum used as the first electrode was deposited by thermal evaporation (350 nm thick), patterned by photolithography and wet etching was performed. Thereafter, first TiO ₂ nanomembrane (thickness 66 nm) was subjected to RF magnetron sputtering (base pressure 5 × 10 ⁻⁶ Torr, room temperature, deposition pressure 5 mTorr, 20 sccm, RF Power 150 W) (first metal oxide insulator layer).

As follows, gold nanoparticles synthesized in Example 1 were assembled on the first TiO ₂ nanomembrane through a Langmuir-Bloze assembly process (FIG. 1A). First, gold nanoparticles capped with oleylamine were dispersed in chloroform (50 mg / mL). The dispersion was added dropwise onto a water sub-phase of an LB trough (LB trough; IUD 1000, KSV instrument, Finland). After evaporating the solvent, the surface layer was compressed using a mobile barrier (5 mm / min). After the surface pressure reached 30 mN / m, the gold nanoparticle layer was assembled on the substrate by lifting the substrate and soaking at a rate of 1 mm / min.

1B shows photographs of the LB assembly process (top) and planar TEM photographs (bottom) of one layer of gold nanoparticles and three layers of gold nanoparticles. The number of assembly layers can be controlled by the number of dipping / pulling cycles. Instead of a gold nanoparticle layer, the first TiO ₂ nanomembrane was coated with a self-assembled monolayer (stearic acid) to confirm the ligand effect on memory performance (FIG. 1A). i) a metal-insulator-self-assembled monolayer (SAM) -insulator-metal (MISIM), ii) a metal-insulator-nanoparticle (NP) -insulator- comprising a layer of gold nanoparticles (about 12 nm) Metal (MINIM), iii) MINIM comprising three layers of closely-packed gold nanoparticles (about 26 nm) is shown in FIG. 1C. The thickness of the gold nanoparticle layer of the three layers was confirmed through an energy dispersive X-ray specroscopy profile for the cross section (FIG. 1D). In the LB assembly method, closely-packed monolayer assembly plays an important role in device uniformity as well as accurate thickness control of several monolayers.

Then, using the same method as the deposition of the TiO ₂ nano-membrane of claim 1, it was deposited to a second TiO ₂ nano-membrane (second non-conductive metal oxide layer) on the gold nanoparticle layer (66 nm thick). An aluminum second electrode was deposited adjacent to the second TiO ₂ nanomembrane by thermal deposition.

Example 3 Characterization of Nonvolatile Resistance Change Memory Device

To evaluate electrical performance, bipolar I-V curves for MIM, MISIM and MINIM structures were obtained (FIG. 2A). 2A shows the bias order. The initial state is a high-resistance state (HRS), and transitions to a low-resistance state (LRS) by applying a negative voltage (“set”). The structures are then switched to HRS by a positive voltage ("reset"). The I-V characteristics of MIM and MISIM were nearly identical; Forming one gold nanoparticle layer in the TiO 2 layer reduced the set and reset currents by an order of magnitude compared to the MIM structure. The level of the current was further reduced by an order of three in MIMIN comprising three gold nanoparticle layers. These results indicate that the assembly of uniform gold nanoparticles in the active layer plays an important role in the reduction of power consumption, and the stearic acid ligand has little effect on the current reduction. These low power consumption characteristics play an important role in long-term use of the memory device.

2B is a diagram showing low current switching due to gold nanoparticle-induced traps. 2C is a log-log I-V curve highlighting the negative voltage region. The conduction mechanism in MINIM is similar to the conduction mechanism of MIM and follows the theory of trap-controlled space-charge-limited-current (SCLC). Figure 2d shows the I-V curves at different compliance currents for MIM (left) and MINIM (right). At compliance currents below 100 μA, MINIM showed better on / off ratios than MIM and MISIM. The reliability (endurance and retention) of MINIM, MIM and MISIM are shown in FIG. 2E, respectively. In the continuous sweep over 100 cycles, durability showed little degradation (Figure 2E left) and good retention of up to 1,000 seconds at room temperature was confirmed (Figure 2E right). Multi-level cell (MLC) operation means that multiple data storage is possible in a single cell with discrete compliance currents that have discrete resistance values (FIG. 2D). Such different resistance values can store multiple information in a single cell (FIG. 2G). MLC with current values below -100 μA was performed in MINIM, and data was preserved in more than 100 read operations.

Claims (27)

A nonvolatile resistance change memory device comprising a nonconductor layer formed between conductor layers, A first electrode; An insulator layer made of a first metal oxide formed adjacent to the first electrode; A metal nanoparticle layer formed adjacent to the first metal oxide insulator layer; An insulator layer made of a second metal oxide formed adjacent to the metal nanoparticle layer; And A second electrode formed adjacent to the second metal oxide layer; Nonvolatile Resistance Change Memory Device. The memory device of claim 1, wherein the first electrode is selected from the group consisting of Al, Cu, Ag, Au, Pt, TiN, ITO, TaN, W, Mg, Zn, and Fe. . The method of claim 1, wherein the first metal oxide is selected from the group consisting of titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide and hafnium oxide. A nonvolatile resistance change memory device characterized by the above-mentioned. The nonvolatile resistance change memory device of claim 1, wherein the first metal oxide insulator layer has a thickness of about 5 nm to about 200 nm. The memory device of claim 1, wherein the metal nanoparticles are nanoparticles of a metal selected from the group consisting of Au, Pt, and Ag. The memory device of claim 1, wherein the metal nanoparticles have a size of 2 nm to 40 nm. The non-volatile metal oxide nanoparticle of claim 1, wherein the metal oxide nanoparticle layer is formed by a process selected from the group consisting of Langmuir-blojet assembly, layer-by-layer assembly, and spin coating assembly of nanoparticles. Resistance change memory device. The nonvolatile resistive memory device of claim 1, wherein the number of the metal oxide nanoparticle layers is in a range of 1 to 10 layers. The nonvolatile resistance memory device of claim 8, wherein the number of the metal oxide nanoparticle layers is three. The method of claim 1, wherein the second metal oxide is selected from the group consisting of titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide and hafnium oxide. A nonvolatile resistance change memory device characterized by the above-mentioned. The memory device of claim 1, wherein the second metal oxide insulator layer has a thickness of about 5 nm to about 200 nm. The nonvolatile resistance change memory device of claim 1, wherein the second electrode is selected from the group consisting of Al, Cu, Ag, Au, Pt, TiN, ITO, TaN, W, Mg, Zn, and Fe. . (i) forming a first electrode on the substrate; (ii) forming an insulator layer made of a first metal oxide adjacent to the first electrode; (iii) forming a metal nanoparticle layer adjacent the first metal oxide insulator layer; (iv) forming an insulator layer made of a second metal oxide adjacent to the metal nanoparticle layer; And (v) forming a second electrode adjacent to the second metal oxide insulator layer, A nonvolatile resistance change memory device manufacturing method. The method of claim 13, wherein the step (i) is performed by a process selected from the group consisting of thermal deposition, electron beam deposition, and magnetron sputtering. The memory device of claim 13, wherein the first electrode is selected from the group consisting of Al, Cu, Ag, Au, Pt, TiN, ITO, TaN, W, Mg, Zn, and Fe. Manufacturing method. The method of claim 13, wherein step (ii) is performed by magnetron sputtering or atomic layer deposition. The method of claim 13, wherein the first metal oxide is selected from the group consisting of titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide and hafnium oxide. A nonvolatile resistance change memory device manufacturing method characterized by the above-mentioned. 15. The method of claim 13, wherein the thickness of the first metal oxide insulator layer is 5 nm to 200 nm. 15. The nonvolatile resistance change memory device according to claim 13, wherein step (iii) is performed by a process selected from the group consisting of Langmuir-Bjetjet assembly, layer-by-layer assembly, and spin coating assembly. Manufacturing method. The method of claim 13, wherein the metal nanoparticles are nanoparticles of a metal selected from the group consisting of Au, Pt, and Ag. The method of claim 13, wherein the number of metal oxide nanoparticle layers is in a range of 1 to 10 layers. 22. The method of claim 21, wherein the number of metal oxide nanoparticle layers is three. The method of claim 13, wherein step (iv) is performed by magnetron sputtering or atomic layer deposition. The method of claim 13, wherein the second metal oxide is selected from the group consisting of titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide and hafnium oxide. A nonvolatile resistance change memory device manufacturing method characterized by the above-mentioned. 15. The method of claim 13, wherein the thickness of the second metal oxide insulator layer is 5 nm to 200 nm. The method of claim 13, wherein step (v) is performed by a process selected from the group consisting of thermal deposition, electron beam deposition, and magnetron sputtering. The memory device of claim 13, wherein the second electrode is selected from the group consisting of Al, Cu, Ag, Au, Pt, TiN, ITO, TaN, W, Mg, Zn, and Fe. Manufacturing method.

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