WO2015122299A1 - Solid-state imaging device, electronic apparatus, and solid-state imaging device manufacturing method - Google Patents

Abstract

The present disclosure relates to a solid-state imaging device which enables downsizing of a package, an electronic apparatus, and a solid-state imaging device manufacturing method. A pattern group is formed on a glass substrate of a solid-state imaging device. In the pattern group, outer patterns each formed to correspond to a wiring pattern on a package are disposed on the outer side of the glass substrate, and inner patterns each formed to correspond to an image sensor are disposed on the inner side of the glass substrate. The same number of outer patterns and inner patterns are formed so as to be paired, and the patterns to be paired from among the outer patterns and the inner patterns are connected by the wiring pattern. The present disclosure is applicable, for example, to a CMOS solid-state imaging device used as an imaging device.

Description

Solid-state imaging device, electronic apparatus, and manufacturing method of solid-state imaging device

The present disclosure relates to a solid-state imaging device, an electronic device, and a manufacturing method of the solid-state imaging device, and more particularly, to a solid-state imaging device, an electronic device, and a manufacturing method of the solid-state imaging device that can be downsized.

The most common package for image sensors is a hollow package. In this structure, it is necessary to provide a sufficient clearance in order to prevent a collision between the image sensor and the package in a die bonding process during assembly. Also in the wire bonding step, sufficient clearance is required to prevent contact between the wire bonding tool (capillary) and the package. Furthermore, as a measure for ensuring the confidentiality of the product and preventing the glass from peeling off, it is necessary to secure an adhesive sheet for the sealing glass, resulting in an increase in package dimensions.

There is also a hollow package that uses an interposer and a side wall as separate parts, and the side wall is attached after wire bonding. In the case of this hollow package, there is no contact between the image sensor and the package at the time of die bonding and contact between the capillary and the package at the time of wire bonding, and a minimum clearance is required. Is possible. However, since the seal glass adhesive white is necessary in the same manner as the former hollow package, there is a limit to downsizing.

The COG (Chip On Glass) structure allows the substrate to be removed by making the glass also have the function of a substrate, and can be made thinner. However, the signal needs to be taken out from the side by the flexible substrate instead of the back side of the sensor, and the dimension in the planar direction becomes large.

Although it is possible to reduce the size by the TAB structure described in Patent Document 1, an insulation process is required between the chip and the lead.

JP 7-297226 A

As described above, the image sensor package is required to be further downsized.

The present disclosure has been made in view of such a situation, and can reduce the size of the package.

A solid-state imaging device according to one aspect of the present technology includes a glass in which a first pattern corresponding to a sensor pad, a second pattern corresponding to a wiring pattern of a package, and a wiring that connects a pair of patterns to each other are formed. A substrate, a sensor mounted on the glass substrate face down, and the package.

The wiring pattern of the package is a lead frame in which a front surface pattern and a back surface pattern are formed in a U-shape.

The package is formed of a thermoplastic resin or a thermosetting resin.

The package is formed of ceramic.

The package is formed of an organic substrate.

The first pattern is formed on the inner side of the second pattern on the glass substrate.

The electrical joint in mounting is flip chip joining.

NCP (Non-Conductive-Paste) is used for the flip chip bonding.

ACP (Anisotropic Conductive Paste) is used for the flip chip bonding.

An electronic device according to one aspect of the present invention is a glass substrate on which a first pattern corresponding to a sensor pad, a second pattern corresponding to a wiring pattern of a package, and a wiring connecting the paired patterns are formed. A solid-state imaging device having a sensor and the package mounted face-down on the glass substrate, a signal processing circuit for processing an output signal output from the solid-state imaging device, and incident light to the solid-state imaging device And an incident optical system.

The wiring pattern of the package is a lead frame in which a front surface pattern and a back surface pattern are formed in a U-shape.

The package is formed of a thermoplastic resin or a thermosetting resin.

The package is formed of ceramic.

The package is formed of an organic substrate.

The first pattern is formed on the inner side of the second pattern on the glass substrate.

The electrical joint in mounting is flip chip joining.

NCP (Non-Conductive-Paste) is used for the flip chip bonding.

ACP (Anisotropic Conductive Paste) is used for the flip chip bonding.

In the method for manufacturing a solid-state imaging device according to one aspect of the present technology, the manufacturing device pairs a glass substrate with a first pattern corresponding to the sensor pad and a second pattern corresponding to the wiring pattern of the package. Wiring for connecting the patterns is formed, and the sensor and the package are mounted face-down on the glass substrate.

In one aspect of the present technology, a first pattern corresponding to the sensor pad, a second pattern corresponding to the wiring pattern of the package, and a wiring connecting the paired patterns are formed on the glass substrate. . The sensor and the package are mounted face down on the glass substrate.

According to this technology, a package can be manufactured. Moreover, according to this technique, a package can be reduced in size.

Note that the effects described in the present specification are merely examples, and the effects of the present technology are not limited to the effects described in the present specification, and may have additional effects.

It is a block diagram which shows the schematic structural example of the solid-state imaging device to which this technique is applied. It is sectional drawing which shows the structural example of the solid-state imaging device of embodiment of this technique. It is a figure which shows the example of a pattern in the glass substrate of a solid-state imaging device. It is a flowchart explaining the manufacturing process of a solid-state imaging device. It is a figure which shows the manufacturing process of a solid-state imaging device. It is a figure which shows the manufacturing process of a solid-state imaging device. It is a block diagram which shows the structural example of the electronic device to which this technique is applied.

Hereinafter, modes for carrying out the present disclosure (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
0. Schematic configuration example of solid-state imaging device 1st Embodiment (example of solid-state imaging device of this technique)
2. Second embodiment (an example of an electronic device)

<0. Schematic configuration example of solid-state imaging device>
<Schematic configuration example of solid-state imaging device>
FIG. 1 illustrates a schematic configuration example of an example of a complementary metal oxide semiconductor (CMOS) solid-state imaging device applied to each embodiment of the present technology.

As shown in FIG. 1, a solid-state imaging device (element chip) 1 includes a pixel region (a pixel region in which pixels 2 including a plurality of photoelectric conversion elements are regularly arranged two-dimensionally on a semiconductor substrate 11 (for example, a silicon substrate). A so-called imaging region) 3 and a peripheral circuit section.

The pixel 2 includes a photoelectric conversion element (for example, a photodiode) and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be constituted by three transistors, for example, a transfer transistor, a reset transistor, and an amplifying transistor, and can further be constituted by four transistors by adding a selection transistor. Since the equivalent circuit of each pixel 2 (unit pixel) is the same as a general one, detailed description thereof is omitted here.

Also, the pixel 2 can have a shared pixel structure. The pixel sharing structure includes a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion, and one other pixel transistor that is shared.

The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.

The control circuit 8 receives data for instructing an input clock, an operation mode, and the like, and outputs data such as internal information of the solid-state imaging device 1. Specifically, the control circuit 8 is based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock, and the clock signal or the reference signal for the operations of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6 Generate a control signal. The control circuit 8 inputs these signals to the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6.

The vertical drive circuit 4 is composed of, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel 2 to the selected pixel drive wiring, and drives the pixels 2 in units of rows. Specifically, the vertical drive circuit 4 selectively scans each pixel 2 in the pixel region 3 sequentially in the vertical direction in units of rows, and generates the signal according to the amount of light received by the photoelectric conversion element of each pixel 2 through the vertical signal line 9. A pixel signal based on the signal charge is supplied to the column signal processing circuit 5.

The column signal processing circuit 5 is disposed, for example, for each column of the pixels 2 and performs signal processing such as noise removal on the signal output from the pixels 2 for one row for each pixel column. Specifically, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to the pixel 2, signal amplification, A / D (Analog / Digital) conversion, and the like. . At the output stage of the column signal processing circuit 5, a horizontal selection switch (not shown) is provided connected to the horizontal signal line 10.

The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.

The output circuit 7 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10 and outputs the signals. For example, the output circuit 7 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, and the like.

The input / output terminal 12 is provided for exchanging signals with the outside.

<1. First Example>
<Configuration example of solid-state imaging device of the present technology>
FIG. 2 is a cross-sectional view illustrating an example of a solid-state imaging device to which the present technology is applied.

2, an image sensor 62 and a package 63 are mounted face down on a glass substrate 61.

Specifically, a pattern group 71 is formed on the glass substrate 61 of the solid-state imaging device 51. In the pattern group 71, as shown in FIG. 3, an outer pattern 71-1 is arranged outside the glass substrate 61, and an inner pattern 71-2 is arranged inside the glass substrate 61. The same number of outer patterns 71-1 and inner patterns 71-2 are formed so as to be paired, and a pair of patterns from the outer pattern 71-1 and inner pattern 71-2 is a wiring pattern 71-. 3 connected.

The inner pattern 71-2 is formed corresponding to the 1st pad 81 of the image sensor 62. The outer pattern 71-1 is formed corresponding to the wiring pattern 91 on the package 63. The pattern group 71 is a conductive material (for example, aluminum, gold, copper, silver, or a material containing them), and is formed by vapor deposition or coating.

As described above, the image sensor 62 and the package 63 are electrically joined to the glass substrate 61.

A light receiving surface 82 is formed on the image sensor 62. On the image sensor 62, the 1st pad 81 is formed around the light receiving surface 82. The image sensor 62 and the package 63 are joined by an insulating adhesive 101 inside the package 63.

The package 63 may be made of any material made of ceramic, organic substrate, or plastic. In the case of being made of plastic, the package 63 can be manufactured by integrally molding a lead frame having a U-shaped shape of a katakana as the wiring pattern 91 by molding with a thermosetting resin or a thermoplastic resin.

The mounting portion (that is, the electrical joint portion) of the image sensor 62, the package 63, and the glass substrate 61 is electrically connected by the bumps 72 and sealed by the sealing resin 73. The material of the bump 72 may be Au, Cu, Ag, or solder, but the height is about 60 μm in order to fill the height difference between the 1st pad 81 on the image sensor 62 and the wiring pattern 91 of the package 63. Is desirable.

The sealing resin 73 can be sealed at the same time as improving the reliability of connectivity by using an anisotropic conductive resin (ACP: Anisotropic Conductive Paste). Further, if sufficient connection reliability can be obtained with only the bumps 72, NCP (Non Conductive Paste) without conductive particles may be used. NCP is a cheaper material than ACP.

<Manufacturing process of solid-state imaging device>
Next, processing for manufacturing the solid-state imaging device of FIG. 2 will be described with reference to the flowchart of FIG. 4 and the process diagrams of FIGS. 5 and 6. This process is a process performed by a manufacturing apparatus that manufactures a solid-state imaging device.

First, in step S11, the manufacturing apparatus performs a die bond resin coating process. That is, the manufacturing apparatus applies the insulating adhesive 101 with the dispense 111 inside the package 63 as shown in FIG.

In step S12, the manufacturing apparatus performs die bonding processing. That is, as shown in FIG. 5B, the manufacturing apparatus bonds the image sensor 62 to the package 63 in which the insulating adhesive material 101 is applied on the inside. Thereafter, the insulating adhesive 101 is cured by heating for a predetermined time.

In step S13, the manufacturing apparatus performs stud bump processing. That is, the manufacturing apparatus forms bumps 72 corresponding to the outer patterns 71-1 and 71-2 on the glass substrate 61 as shown in FIG. 5C. The processing in this step can be performed after the glass substrate 61 is singulated, or can be performed in a large format before the singulation.

In step S14, the manufacturing apparatus performs a sealing resin coating process. That is, the manufacturing apparatus applies the sealing resin (ACP or NCP) 73 so as to cover the outer patterns 71-1 and 71-2 of the glass substrate 61 subjected to the stud bump process, as shown in FIG. 6A. To do.

In step S15, the manufacturing apparatus performs a flip chip bonding process. That is, as shown in FIG. 6B, the manufacturing apparatus performs a face-down process on a semi-finished product in which the image sensor 62 and the package 63 are integrated on the glass substrate 61 coated with the bumps 72 and the sealing resin 73. Implement. At that time, sealing and electrical joining are completed by applying a predetermined load and thermal conditions. Then, in step S16, as shown in FIG. 6C, they are inverted by the manufacturing apparatus, and the solid-state imaging device 51 is manufactured.

As described above, the solid-state imaging device 51 of the present technology has a COG (Chip On Glass) structure that also has a substrate function on glass, but easily arranges output terminals on the back surface of the package (the surface opposite to the light receiving surface). can do. As a result, the package can be made thinner / smaller.

Also, in the present technology, the wire bond is not required by conducting the image sensor and the wiring pattern (lead frame) of the package through the flip chip bonding process through the pattern provided on the glass substrate. Therefore, since it is not necessary to consider contact with the wire bond tool, the package can be reduced in size.

Since the solid-state imaging device 51 of the present technology hits a bump instead of a wire, the amount of wire material used can be reduced and the cost can be reduced.

Also, when plastic is used as the package, it is difficult to route the lead frame from the front surface to the back surface. However, in this technology, since a U-shaped lead frame is used, an inexpensive plastic package can be used.

According to the present technology, the lead frame of the package is exposed to the outer periphery of the package, so that it can be mounted on either the back surface or the side surface, and the degree of freedom of mounting is increased.

Furthermore, in the present technology, since the image sensor is used as a part of the structure, it is advantageous in strength that the image sensor is thick. As a result, the back grinding process is omitted or simplified. be able to.

In the above, the configuration in which the present technology is applied to the CMOS solid-state imaging device has been described. However, the present technology may be applied to a solid-state imaging device such as a CCD (Charge Coupled Device) solid-state imaging device.

Also, the solid-state imaging device may be a backside illumination type or a frontside illumination type.

In addition, this technique is not restricted to application to a solid-state imaging device, It can apply also to an imaging device. Here, the imaging apparatus refers to a camera system such as a digital still camera or a digital video camera, or an electronic apparatus having an imaging function such as a mobile phone. In some cases, a module-like form mounted on an electronic device, that is, a camera module is used as an imaging device.

<2. Second Embodiment>
<Configuration example of electronic equipment>
Here, with reference to FIG. 7, the structural example of the electronic device of the 2nd Embodiment of this technique is demonstrated.

7 is provided with a solid-state imaging device (element chip) 301, an optical lens 302, a shutter device 303, a drive circuit 304, and a signal processing circuit 305. As the solid-state imaging device 301, the solid-state imaging device 51 according to the first embodiment of the present technology described above is provided. Thereby, the electronic device 300 can be reduced in size. In addition, the electronic device 300 can be provided at low cost.

The optical lens 302 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 301. As a result, signal charges are accumulated in the solid-state imaging device 301 for a certain period. The shutter device 303 controls the light irradiation period and the light shielding period for the solid-state imaging device 301.

The drive circuit 304 supplies a drive signal for controlling the signal transfer operation of the solid-state imaging device 301 and the shutter operation of the shutter device 303. The solid-state imaging device 301 performs signal transfer by a drive signal (timing signal) supplied from the drive circuit 304. The signal processing circuit 305 performs various signal processing on the signal output from the solid-state imaging device 301. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

In the present specification, the steps describing the series of processes described above are not limited to the processes performed in time series according to the described order, but are not necessarily performed in time series, either in parallel or individually. The process to be executed is also included.

Further, the embodiments in the present disclosure are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present disclosure.

Further, each step described in the above flowchart can be executed by one device or can be shared by a plurality of devices.

Further, when a plurality of processes are included in one step, the plurality of processes included in the one step can be executed by being shared by a plurality of apparatuses in addition to being executed by one apparatus.

Also, in the above, the configuration described as one device (or processing unit) may be divided and configured as a plurality of devices (or processing units). Conversely, the configurations described above as a plurality of devices (or processing units) may be combined into a single device (or processing unit). Of course, a configuration other than that described above may be added to the configuration of each device (or each processing unit). Furthermore, if the configuration and operation of the entire system are substantially the same, a part of the configuration of a certain device (or processing unit) may be included in the configuration of another device (or other processing unit). . That is, the present technology is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present technology.

The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, but the disclosure is not limited to such examples. It is obvious that various changes and modifications can be conceived within the scope of the technical idea described in the claims if the person has ordinary knowledge in the technical field to which the present disclosure belongs. Of course, it is understood that it belongs to the technical scope of the present disclosure.

In addition, this technique can also take the following structures.
(1) a glass substrate on which a first pattern corresponding to a sensor pad, a second pattern corresponding to a wiring pattern of a package, and a wiring connecting each pair of patterns are formed;
A solid-state imaging device comprising: a sensor mounted face-down on the glass substrate; and the package.
(2) The solid-state imaging device according to (1), wherein the wiring pattern of the package is a lead frame in which a front surface pattern and a back surface pattern are formed in a U-shape.
(3) The solid-state imaging device according to (1) or (2), wherein the package is formed of a thermoplastic resin or a thermosetting resin.
(4) The solid-state imaging device according to (1) or (2), wherein the package is formed of ceramic.
(5) The solid-state imaging device according to (1) or (2), wherein the package is formed of an organic substrate.
(6) The solid-state imaging device according to any one of (1) to (5), wherein the first pattern is formed on the inner side of the second pattern on the glass substrate.
(7) The solid-state imaging device according to any one of (1) to (6), wherein the electrical joint in mounting is flip-chip joint.
(8) NCP (Non Conductive Paste) is used for the flip-chip bonding. The solid-state imaging device according to (7).
(9) The solid-state imaging device according to (7), wherein an ACP (Anisotropic Conductive Paste) is used for the flip chip bonding.
(10) a glass substrate on which a first pattern corresponding to a sensor pad, a second pattern corresponding to a wiring pattern of a package, and a wiring connecting each pair of patterns are formed;
A solid-state imaging device having the sensor and the package mounted face-down on the glass substrate;
A signal processing circuit for processing an output signal output from the solid-state imaging device;
And an optical system that makes incident light incident on the solid-state imaging device.
(11) The electronic device according to (10), wherein the wiring pattern of the package is a lead frame in which a front surface pattern and a back surface pattern are formed in a U-shape.
(12) The electronic device according to (10) or (11), wherein the package is formed of a thermoplastic resin or a thermosetting resin.
(13) The electronic device according to (10) or (11), wherein the package is formed of ceramic.
(14) The electronic device according to (10) or (11), wherein the package is formed of an organic substrate.
(15) The electronic device according to any one of (10) to (14), wherein the first pattern is formed inside the second pattern on the glass substrate.
(16) The electronic device according to any one of (10) to (15), wherein the electrical joint portion in mounting is flip-chip joint.
(17) The electronic device according to (16), wherein NCP (Non Conductive Paste) is used for the flip chip bonding.
(18) The electronic device according to (16), wherein an ACP (Anisotropic Conductive Paste) is used for the flip chip bonding.
(19) The manufacturing equipment is
On the glass substrate, a first pattern corresponding to the sensor pad, a second pattern corresponding to the wiring pattern of the package, and a wiring connecting the paired patterns are formed.
A method of manufacturing a solid-state imaging device, wherein the sensor and the package are mounted face-down on the glass substrate.

1 solid-state imaging device, 2 pixels, 3 pixel area, 11 semiconductor substrate, 51 solid-state imaging device, 61 glass substrate, 62 image sensor, 63 package, 71 pattern group, 71-1 outer pattern, 71-2 inner pattern, 71- 3 Wiring pattern, 72 bumps, 73 sealing resin, 81 1st pad, 82 light receiving surface, 91 wiring pattern, 300 electronic equipment, 301 solid-state imaging device, 302 optical lens, 303 shutter device, 304 drive circuit, 305 signal processing circuit

Claims (19)

A glass substrate on which a first pattern corresponding to the sensor pad, a second pattern corresponding to the wiring pattern of the package, and a wiring connecting the paired patterns are formed;
A solid-state imaging device comprising: a sensor mounted face-down on the glass substrate; and the package. The solid-state imaging device according to claim 1, wherein the wiring pattern of the package is a lead frame in which a front surface pattern and a back surface pattern are formed in a U-shape. The solid-state imaging device according to claim 2, wherein the package is formed of a thermoplastic resin or a thermosetting resin. The solid-state imaging device according to claim 2, wherein the package is formed of ceramic. The solid-state imaging device according to claim 2, wherein the package is formed of an organic substrate. The solid-state imaging device according to claim 2, wherein the first pattern is formed on the inner side of the second pattern on the glass substrate. The solid-state imaging device according to claim 1, wherein the electrical joint portion in mounting is flip-chip joint. The solid-state imaging device according to claim 7, wherein NCP (Non Conductive Paste) is used for the flip chip bonding. The solid-state imaging device according to claim 7, wherein an ACP (Anisotropic Conductive Paste) is used for the flip chip bonding. A glass substrate on which a first pattern corresponding to the sensor pad, a second pattern corresponding to the wiring pattern of the package, and a wiring connecting the paired patterns are formed;
A solid-state imaging device having the sensor and the package mounted face-down on the glass substrate;
A signal processing circuit for processing an output signal output from the solid-state imaging device;
And an optical system that makes incident light incident on the solid-state imaging device. The electronic device according to claim 10, wherein the wiring pattern of the package is a lead frame in which a front surface pattern and a back surface pattern are formed in a U-shape. The electronic device according to claim 11, wherein the package is formed of a thermoplastic resin or a thermosetting resin. The electronic device according to claim 11, wherein the package is formed of ceramic. The electronic device according to claim 11, wherein the package is formed of an organic substrate. The electronic device according to claim 11, wherein the first pattern is formed on the inner side of the second pattern on the glass substrate. The electronic device according to claim 10, wherein the electrical joint portion in mounting is flip chip joining. The electronic device according to claim 16, wherein NCP (Non Conductive Paste) is used for the flip chip bonding. The electronic device according to claim 16, wherein an ACP (Anisotropic Conductive Paste) is used for the flip chip bonding. Manufacturing equipment
On the glass substrate, a first pattern corresponding to the sensor pad, a second pattern corresponding to the wiring pattern of the package, and a wiring connecting the paired patterns are formed.
A method of manufacturing a solid-state imaging device, wherein the sensor and the package are mounted face-down on the glass substrate.

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