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WO2015111370A1 - Dispositif de prise de vues à semi-conducteur, et dispositif de prise de vues à semi-conducteur - Google Patents

Dispositif de prise de vues à semi-conducteur, et dispositif de prise de vues à semi-conducteur Download PDF

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Publication number
WO2015111370A1
WO2015111370A1 PCT/JP2015/000023 JP2015000023W WO2015111370A1 WO 2015111370 A1 WO2015111370 A1 WO 2015111370A1 JP 2015000023 W JP2015000023 W JP 2015000023W WO 2015111370 A1 WO2015111370 A1 WO 2015111370A1
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Prior art keywords
circuit
transistor
signal
imaging device
solid
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PCT/JP2015/000023
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English (en)
Japanese (ja)
Inventor
阿部　豊
西村　佳壽子
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present disclosure relates to a solid-state imaging device and an imaging device.
  • MOS Metal Oxide Semiconductor
  • AD Analog-Digital
  • the MOS type image sensor can be manufactured by a general-purpose CMOS (Complementary MOS) process and has a merit that peripheral circuits can be mixed in the same chip.
  • CMOS Complementary MOS
  • high-speed AD conversion can be realized by simultaneously AD-converting pixel signals for each column, and an output with less noise can be obtained by reducing analog processing blocks. This is because there is a merit that it is possible.
  • Patent Document 1 discloses a MOS type image sensor including a conventional AD conversion circuit.
  • the AD conversion circuit disclosed in Patent Document 1 is a single slope AD conversion circuit.
  • the single slope AD converter circuit compares a reference signal whose voltage value increases or decreases with time with an analog signal, and counts the time until the magnitude relationship is reversed by a digital counter, thereby converting the analog signal into a digital signal. It is an AD conversion circuit configured to convert.
  • a solid-state imaging device is provided in each of a plurality of unit cells that are two-dimensionally arranged and generate a pixel signal corresponding to the amount of received light, and for each column of the plurality of unit cells.
  • Each of the plurality of comparison circuits a differential amplifier circuit that outputs a signal according to a difference amount between the reference signal and the pixel signal, a switch for removing the offset of the differential amplifier circuit, And a buffer circuit connected to the control terminal of the switch.
  • the buffer circuit can buffer the control signal input to the control terminal of the switch, the characteristic difference between columns can be reduced. Therefore, degradation of image quality such as shading can be suppressed.
  • the buffer circuit may be an inverter circuit.
  • the inverter circuit allows the inverter circuit to amplify the control signal input to the control terminal of the switch, thereby suppressing the rounding of the waveform of the control signal. Therefore, the difference in the waveform of the control signal can be made difficult to occur for each column, and deterioration of image quality such as shading can be suppressed.
  • the inverter circuit includes a PMOS (Positive Metal Oxide Semiconductor) transistor and an NMOS (Negative Metal Oxide Semiconductor) transistor, and the PMOS transistor and the NMOS transistor May be controlled by different control signals.
  • PMOS Positive Metal Oxide Semiconductor
  • NMOS Negative Metal Oxide Semiconductor
  • the power supply line and the ground line of the buffer circuit may be separated from the power supply line and the ground line of the differential amplifier circuit.
  • the potential difference between the power supply line and the ground line of the buffer circuit may be smaller than the potential difference between the power supply line and the ground line of the differential amplifier circuit.
  • the differential amplifier circuit forms a differential pair, the reference signal is input to one gate, and the pixel signal is input to the other gate.
  • the switch removes the offset by conducting the gate and drain or source of each of the two transistors before the reference signal and the pixel signal are input. May be.
  • each of the plurality of unit cells may include a reset transistor, a transfer transistor, a read transistor, and a selection transistor.
  • each of the plurality of unit cells may not include the selection transistor.
  • the photodiode region and the aperture ratio can be enlarged, and the sensitivity can be increased.
  • each of the plurality of unit cells includes a plurality of light receiving elements, and a reset transistor, a read transistor, and a selection transistor that are shared by the plurality of light receiving elements. You may have at least one.
  • the number of transistors included in the unit cell can be substantially reduced.
  • the solid-state imaging device and the imaging device according to the present disclosure can capture a high-quality image.
  • FIG. 1 is a diagram illustrating an example of a configuration of a solid-state imaging device according to an embodiment.
  • FIG. 2 is a timing chart illustrating an example of the operation of the solid-state imaging device according to the embodiment.
  • FIG. 3 is a diagram illustrating a circuit configuration of the comparison circuit according to the embodiment.
  • FIG. 4 is a diagram illustrating a circuit configuration of a comparison circuit included in a general solid-state imaging device.
  • FIG. 5 is a diagram illustrating a waveform of the reset control signal according to the embodiment.
  • FIG. 6 is a diagram illustrating a circuit configuration of a comparison circuit according to a modification of the embodiment.
  • FIG. 7 is a timing chart illustrating an example of the operation of the comparison circuit according to the modification of the embodiment.
  • FIG. 1 is a diagram illustrating an example of a configuration of a solid-state imaging device according to an embodiment.
  • FIG. 2 is a timing chart illustrating an example of the operation of the solid-state imaging device according to the embodiment.
  • FIG. 8 is a diagram illustrating a configuration of a comparison circuit according to another modification of the embodiment.
  • FIG. 9 is a diagram illustrating an example of a circuit configuration of a unit cell according to a modification of the embodiment.
  • FIG. 10 is a diagram illustrating an example of a circuit configuration of a unit cell according to a modification of the embodiment.
  • FIG. 11 is a block diagram illustrating an example of a configuration of an imaging apparatus (camera system) including the solid-state imaging apparatus according to the embodiment.
  • the present disclosure has been made in view of the above problems, and provides a solid-state imaging device and an imaging device that can capture a high-quality image.
  • FIG. 1 is a diagram illustrating a configuration of a solid-state imaging device 10 according to the embodiment.
  • the solid-state imaging device 10 includes a plurality of unit cells 100, a plurality of vertical signal lines 110, a reference signal generation circuit 120, a reference signal line 121, a plurality of column AD conversion circuits 130, An output circuit 140, a vertical selection circuit 150, a horizontal selection circuit 160, and a timing control circuit 170 are provided.
  • the plurality of unit cells 100 are arranged two-dimensionally.
  • the plurality of unit cells 100 are arranged in a predetermined imaging region in an array of n in the vertical direction and m in the horizontal direction, that is, in a matrix of n rows ⁇ m columns.
  • the values of n and m are tens to thousands of values.
  • Each of the plurality of unit cells 100 includes at least one light receiving element (pixel), and generates a pixel signal corresponding to the amount of received light.
  • the unit cell 100 is connected to one of the plurality of vertical signal lines 110.
  • the pixel signal generated by the unit cell 100 is transferred through the connected vertical signal line 110.
  • the unit cell 100 includes a photodiode 101, a transfer transistor 102, a reset transistor 103, a read transistor 104, a selection transistor 105, and a floating diffusion unit 106.
  • the transfer transistor 102, the reset transistor 103, the read transistor 104, and the selection transistor 105 are control transistors of the unit cell 100.
  • the photodiode 101 is a light receiving element (photoelectric conversion element) that converts light from a subject into a charge amount, and is a basic component of a pixel (light receiving unit).
  • the anode of the photodiode 101 is set to the ground potential, and the cathode is connected to the source of the transfer transistor 102.
  • the transfer transistor 102 is a transistor that is provided between the photodiode 101 and the floating diffusion portion 106 and transfers charges generated by the photodiode 101 to the floating diffusion portion 106.
  • the drain of the transfer transistor 102 is connected to the floating diffusion portion 106, and the gate is connected to the transfer signal line ( ⁇ TX).
  • the reset transistor 103 is a transistor for resetting (initializing) the potential of the floating diffusion unit 106.
  • the source of the reset transistor 103 is connected to the floating diffusion portion 106, the drain is connected to the power supply line, and the gate is connected to the reset signal line ( ⁇ RS).
  • the read transistor 104 (amplification transistor) is a transistor for reading a voltage signal (pixel signal) corresponding to the potential of the floating diffusion portion 106. Specifically, the reading transistor 104 outputs a pixel signal corresponding to the potential of the floating diffusion portion 106 to the vertical signal line 110 via the selection transistor 105.
  • the source of the read transistor 104 is connected to the drain of the selection transistor 105, the drain is connected to the power supply line, and the gate is connected to the floating diffusion unit 106.
  • the selection transistor 105 is provided between the readout transistor 104 and the vertical signal line 110, and is a transistor for outputting a pixel signal to the vertical signal line 110.
  • the source of the selection transistor 105 is connected to the vertical signal line 110, and the gate is connected to the selection signal line ( ⁇ SEL).
  • the floating diffusion unit 106 transfers the signal charge (electrons) generated by the photodiode 101 and temporarily holds the transferred signal charge. That is, the floating diffusion unit 106 generates a signal potential corresponding to the charge generated by the photodiode 101.
  • the potential of the floating diffusion unit 106 is reset by turning on the reset transistor 103.
  • the charge generated by the photodiode 101 is transferred to the floating diffusion portion 106 by turning on the transfer transistor 102.
  • the selection transistor 105 is turned on, a pixel signal corresponding to the signal potential of the floating diffusion portion 106 is output to the vertical signal line 110 via the readout transistor 104 and the selection transistor 105.
  • the transistors are turned on and off by the vertical selection circuit 150 applying predetermined signals to the transfer signal line ( ⁇ TX), the reset signal line ( ⁇ RS), and the selection signal line ( ⁇ SEL).
  • the solid-state imaging device 10 includes a reading current source unit that supplies an operation current (reading current) for reading a pixel signal to the unit cell 100 in the imaging region.
  • a reading current source unit that supplies an operation current (reading current) for reading a pixel signal to the unit cell 100 in the imaging region.
  • a plurality of vertical signal lines 110 are provided for each column of the plurality of unit cells 100. Specifically, the plurality of vertical signal lines 110 are commonly connected to the plurality of unit cells 100 arranged in a line in the vertical direction. The vertical signal line 110 transfers the pixel signal generated by the connected unit cell 100 to the comparison circuit 131.
  • the reference signal generation circuit 120 is an example of a reference signal supply circuit that supplies a common reference signal to the plurality of comparison circuits 131 included in the plurality of column AD conversion circuits 130.
  • the reference signal generation circuit 120 includes a DA conversion circuit.
  • the reference signal generation circuit 120 generates a reference signal (RAMP waveform signal) whose level changes stepwise in synchronization with the clock signal supplied from the timing control circuit 170, and generates a plurality of the generated reference signals.
  • RAMP waveform signal a reference signal
  • the reference signal is supplied to each of the plurality of comparison circuits 131 via a common reference signal line 121 that connects the reference signal generation circuit 120 and the plurality of comparison circuits 131.
  • the plurality of column AD conversion circuits 130 convert pixel signals (analog signals) transferred via the vertical signal lines 110 into digital signals.
  • the column AD conversion circuit 130 receives the pixel signal (analog signal) and converts it into, for example, a 10-bit digital signal.
  • AD conversion processing in the present embodiment a method is adopted in which analog signals held in parallel in units of rows are AD converted in parallel for each row using a column AD conversion circuit 130 provided for each column.
  • a single slope integrator (or ramp signal comparison type) AD conversion technique is used.
  • the single slope integration type AD conversion processing an analog pixel signal is converted into a digital signal based on the time from the start of conversion until the potential of the reference signal matches the potential of the pixel signal to be processed.
  • the plurality of column AD conversion circuits 130 include a comparison circuit 131, a counter circuit 132, and a memory circuit 133 for each column. That is, the plurality of comparison circuits 131, the counter circuits 132, and the memory circuits 133 are provided corresponding to the plurality of vertical signal lines 110, respectively.
  • the comparison circuit 131 outputs an output signal corresponding to the difference amount between the pixel signal and the reference signal. Specifically, the comparison circuit 131 compares the reference signal generated by the reference signal generation circuit 120 with an analog pixel signal input from the unit cell 100 via the vertical signal line 110. For example, the comparison circuit 131 compares the pixel signal with the reference signal, and the output is inverted when the magnitude relationship is switched.
  • the comparison circuit 131 has two input terminals IN1 and IN2, an output terminal OUT, and a reset control terminal RST. Specifically, a reference signal line 121 is connected to the input terminal IN1, and a reference signal is input. The vertical signal line 110 of the corresponding column is connected to the input terminal IN2, and a pixel signal is input. A counter circuit 132 is connected to the output terminal OUT, and an output signal (comparison result) is output to the counter circuit 132. A timing control circuit 170 is connected to the reset control terminal RST, and a reset control signal ⁇ CRST is input.
  • the detailed configuration of the comparison circuit 131 will be described later with reference to FIGS.
  • the reset control signal ⁇ CRST will be described later with reference to FIG.
  • the counter circuit 132 generates a count value corresponding to the output signal output from the corresponding comparison circuit 131. For example, the counter circuit 132 counts the time until the comparison circuit 131 completes the comparison process, and holds the result (count value).
  • the clock signal ⁇ CK from the timing control circuit 170 is input to the clock terminal of the counter circuit 132 in common with the clock terminals of the other counter circuits 132.
  • the counter circuit 132 receives the clock signal ⁇ CK synchronized with the clock signal that controls the reference signal generation circuit 120 from the timing control circuit 170, and counts the time from the start of comparison until the output of the comparison circuit 131 is inverted. , Generate a count value.
  • the count value is data obtained by digitally converting an analog pixel signal.
  • control pulse ⁇ FEED is input to the counter circuit 132 from the timing control circuit 170 through the control line.
  • the counter circuit 132 has a latch function for holding the count value, and holds the counter value until an instruction is given by the control pulse ⁇ FEED via the control line.
  • the counter circuit 132 includes a data transfer switch that controls transfer of the count value.
  • the data transfer switch is turned on by the control pulse ⁇ FEED, the count value is transferred from the counter circuit 132, and stored in the memory circuit 133.
  • the memory circuit 133 holds the count value generated by the corresponding counter circuit 132, that is, the digitally converted data (digital signal).
  • a control pulse is input to the memory circuit 133 from the horizontal selection circuit 160 via a control line.
  • the memory circuit 133 holds the counter value fetched from the counter circuit 132 until an instruction by a control pulse is received from the horizontal selection circuit 160 via the control line.
  • the output of the memory circuit 133 is connected to a horizontal signal line.
  • the horizontal signal line has a signal line corresponding to the n-bit width which is the bit width of the column AD conversion circuit 130, and the output circuit 140 passes through n sense circuits (not shown) corresponding to the respective output lines. It is connected to the.
  • the output circuit 140 includes, for example, an amplifier circuit and a signal processing circuit, and performs predetermined processing such as amplification processing on the digitally converted data and outputs the data.
  • the vertical selection circuit (row selection circuit) 150 controls pixel signal readout (transfer) timing from the plurality of unit cells 100. For example, the vertical selection circuit 150 controls the row address and row scanning. For example, the vertical selection circuit 150 controls the transistors of the unit cell 100 so as to drive the pixels in the row specified by the timing control circuit 170.
  • the horizontal selection circuit (horizontal scanning circuit) 160 controls the plurality of memory circuits 133.
  • the horizontal selection circuit 160 controls column addresses and column scanning.
  • the horizontal selection circuit 160 causes the output circuit 140 to output the data stored in the memory circuit 133 in the column designated by the timing control circuit 170.
  • the horizontal selection circuit 160 has a function of a reading scanning unit that reads the count value held by the memory circuit 133 in parallel with the comparison circuit 131 and the counter circuit 132 performing the processing that they are in charge of.
  • the timing control circuit 170 has a function of generating an internal clock. The operation timing of the reference signal generation circuit 120, the column AD conversion circuit 130, the vertical selection circuit 150, and the horizontal selection circuit 160 is controlled.
  • the timing control circuit 170, the vertical selection circuit 150, the horizontal selection circuit 160, and the like are examples of drive control units provided outside the imaging area. Note that the drive control unit has a control circuit function for sequentially reading signals in the imaging region.
  • the column AD conversion circuit 130 performs a count operation in a pixel signal readout period corresponding to a horizontal blanking period, and outputs a count value at a predetermined timing. That is, first, the comparison circuit 131 compares the potential of the reference signal from the reference signal generation circuit 120 with the potential of the pixel signal input via the vertical signal line 110, and when both potentials are the same. The output of the comparison circuit 131 is inverted.
  • the counter circuit 132 starts a count operation in synchronization with the reference signal output from the reference signal generation circuit 120.
  • the counter circuit 132 When the counter circuit 132 is notified of information obtained by inverting the output of the comparison circuit 131, the counter circuit 132 performs the count operation. And the AD conversion is completed by latching the count value at that time as pixel data.
  • the memory circuit 133 sequentially outputs the latched pixel data based on the shift operation by the horizontal selection signal input from the horizontal selection circuit 160 via the control line at a predetermined timing.
  • FIG. 2 is a timing chart showing the operation of the solid-state imaging device 10 according to the present embodiment.
  • the horizontal axis represents time, and the vertical axis represents the potential of each signal.
  • the reset pulse ⁇ RS is a signal applied to the reset signal line, and represents a pulse signal for commonly controlling the reset transistors 103 in a predetermined row.
  • the transfer pulse ⁇ TX is a signal applied to the transfer signal line and represents a pulse signal for commonly controlling the transfer transistors 102 in a predetermined row.
  • the selection pulse ⁇ SEL is a signal applied to the selection signal line and represents a pulse signal for commonly controlling the selection transistors 105 in a predetermined row.
  • the potential Vin represents the potential of the vertical signal line 110 connected to the predetermined unit cell 100.
  • the potentials Vrst and Vsig are the potentials of the vertical signal lines when the power supply potential of the pixel is reset and when charges generated in the photodiode 101 are transferred, respectively. That is, Vsig corresponds to the potential of the pixel signal.
  • the reset control signal ⁇ CRST is a signal for controlling the reset operation unit (offset removal circuit) of the comparison circuit 131. Specifically, the reset control signal ⁇ CRST is a signal for controlling a switch for removing an offset.
  • the clock signal ⁇ CK represents a clock signal input to the reference signal generation circuit 120 and the counter circuit 132.
  • the count value CT represents the count value of the counter circuit 132.
  • the control pulse ⁇ FEED represents a pulse signal for controlling the timing at which the count value is transferred from the counter circuit 132 to the memory circuit 133. Note that the count value is transferred to the memory circuit 133 when the control pulse ⁇ FEED is at the “H” level (high level).
  • the potential Vref represents the output potential of the reference signal generation circuit 120, that is, the potential of the reference signal line 121.
  • the potential Vco represents the output potential of the comparison circuit 131.
  • the selection pulse ⁇ SEL, the reset pulse ⁇ RS, and the reset control signal ⁇ CRST of the comparison circuit 131 are set to the “H” level.
  • the selection pulse ⁇ SEL becomes “H” level, all the selection transistors 105 connected to the selection signal line are turned on.
  • the transfer pulse ⁇ TX is set to “H” level at time t5.
  • all the transfer transistors 102 connected to the transfer pulse ⁇ TX are turned on, and charges generated in the photodiodes 101 in the corresponding row are transferred to the floating diffusion unit 106.
  • the potential of the floating diffusion portion 106 is (Vdd ⁇ qN) / C. . Therefore, the potential Vin of the vertical signal line 110 outputs the potential Vsig corresponding to the potential of the floating diffusion unit 106.
  • the reset control signal ⁇ CRST that controls the reset operation unit of the comparison circuit 131 becomes “H” level, and the comparison circuit 131 is reset.
  • the reset pulse ⁇ RS is set to low level at time t2. Further, for example, after the reset control signal ⁇ CRST is set to the “L” level after time t2, the clock signal ⁇ CK having a predetermined cycle is input to the reference signal generation circuit 120 and the counter circuit 132 at time t3.
  • the potential of the reference signal potential Vref changes from the initial potential Vstart to a low potential in synchronization with the clock signal ⁇ CK.
  • the count value CT decreases from the initial value CTini in synchronization with the clock signal ⁇ CK.
  • the magnitude relationship between the potential Vin of the pixel signal and the potential Vref of the reference signal is inverted at a predetermined timing after time t3 during the transition of the potential Vref to a low potential.
  • the output potential Vco of the comparison circuit 131 changes from the “H” level to the “L” level, and the counting operation of the counter circuit 132 stops.
  • the clock signal ⁇ CK stops and the comparison operation also stops.
  • the count value CT is held at CTdown which is a value at the time when the magnitude relationship between Vin and Vref is inverted.
  • the clock signal ⁇ CK having a predetermined cycle is input to the reference signal generation circuit 120 and the counter circuit 132 again.
  • Vref changes from Vstart to a low potential.
  • the count value CT increases from the value CTdown held during the downcount period.
  • the magnitude relationship between the potential Vin of the pixel signal and the potential Vref of the reference signal is inverted at a predetermined timing after time t6 during the transition of the potential Vref to the low potential.
  • the output potential Vco of the comparison circuit 131 changes from the “H” level to the “L” level, and the counting operation of the counter circuit 132 stops.
  • CTup corresponds to the difference between the digital conversion value of Vrst and the digital conversion value of Vsig, it can be said that the difference between Vrst and Vsig is a digital conversion value of qN / C. That is, the amount of charge accumulated in the photodiode 101 is digitally converted and output.
  • the control pulse ⁇ FEED is applied to the control line so that the data transfer switch included in the counter circuit 132 is turned on at a predetermined timing after time t7 after the completion of the upcount.
  • the count value CTup held in the counter circuit 132 is transferred to the memory circuit 133, and CTup is held in the memory circuit 133.
  • the horizontal selection circuit 160 controls the plurality of memory circuits 133 so that the data held in the memory circuit 133 is sequentially read.
  • a pixel signal generated by photoelectric conversion by the photodiode 101 (pixel) of the unit cell 100 is read as digital data.
  • ⁇ RS, ⁇ SEL, and ⁇ CRST are simultaneously started up (set to the “H” level) at time t1. Any one of ⁇ RS, ⁇ SEL, and ⁇ CRST may be started first.
  • the reset control signal ⁇ CRST is set to “L” level after the reset pulse ⁇ RS is lowered (set to “L” level) at time t2, but at the same time at time t2, the reset pulse ⁇ RS and The reset control signal ⁇ CRST may be set to “L” level.
  • the reset control signal ⁇ CRST falls later.
  • start of the clock signal ⁇ CK and the start of the transition of the reference signal potential Vref are performed at time t3, either one may be performed first.
  • end of the clock signal ⁇ CK and the end of the transition of the reference signal potential Vref do not have to be performed simultaneously.
  • the transfer pulse ⁇ TX rises at the time t5 at the same time as the end of the clock signal ⁇ CK
  • the rise of the transfer pulse ⁇ TX may be after the timing when the clock signal ⁇ CK ends.
  • the time at which the potential Vref of the reference signal is returned to the initial potential Vstart may be before, after, or simultaneously with the rise of ⁇ TX.
  • start of the clock signal ⁇ CK and the start of the transition of the reference signal potential Vref are performed at time t6, either one may be performed first.
  • FIG. 3 is a diagram showing a circuit configuration of the comparison circuit 131 according to the present embodiment.
  • the comparison circuit 131 includes a differential amplifier circuit 200 and an offset removal circuit 210.
  • the differential amplifier circuit 200 outputs a signal corresponding to the difference amount between the reference signal and the pixel signal.
  • the differential amplifier circuit 200 forms a differential pair, and includes transistors 201 and 202 in which a reference signal is input to one gate and a pixel signal is input to the other gate.
  • the differential amplifier circuit 200 includes transistors 203 and 204 constituting a current mirror circuit and a transistor 205 constituting a constant current source.
  • the transistors 201 and 202 are connected to each other to form a differential transistor pair.
  • the transistors 201 and 202 are, for example, NMOS transistors.
  • a reference signal is supplied to the gate of the transistor 201 via the capacitor 213. That is, the gate of the transistor 201 corresponds to the input terminal IN1 of the comparison circuit 131.
  • a pixel signal (analog signal) is supplied to the gate of the transistor 202 via the capacitor 214. That is, the gate of the transistor 202 corresponds to the input terminal IN2 of the comparison circuit 131. Note that the drain of the transistor 202 corresponds to the output terminal OUT of the comparison circuit 131.
  • the output terminal OUT of the differential transistor pair is connected to an amplifier (not shown).
  • the output signal from the output terminal OUT is further amplified through a buffer (not shown) and then output to the counter circuit 132.
  • Transistors 203 and 204 are a load transistor pair that is arranged on the power supply side and serves as an output load of the differential transistor pair, and constitutes a current mirror circuit.
  • the transistors 203 and 204 are, for example, PMOS transistors.
  • the gate and drain of the transistor 203 are connected to each other and further connected to the gate of the transistor 204.
  • the drain of the transistor 201 is connected to the drain of the transistor 203. Note that the source of the transistor 203 is connected to a power supply line.
  • the drain of the transistor 204 is connected to the drain of the transistor 202. That is, a node where the drain of the transistor 202 and the drain of the transistor 204 are connected corresponds to the output terminal OUT. Note that the source of the transistor 204 is connected to a power supply line.
  • the transistor 205 is a transistor arranged on the ground side for supplying a constant operating current to the differential transistor pair and the load transistor pair.
  • the transistor 205 is, for example, an NMOS transistor.
  • the drain of the transistor 205 is connected to the source of the transistor 201 and the source of the transistor 202 which are connected to each other.
  • a predetermined bias voltage is applied to the gate of the transistor 205, and the source of the transistor 205 is set to the ground potential. Note that the transistor 205 does not have to have the configuration described in this configuration example as long as the transistor 205 has a configuration operating as a constant current source, such as a cascode configuration.
  • the offset removal circuit 210 is a circuit that removes the offset of the differential amplifier circuit 200. That is, the offset removal circuit 210 is a circuit that resets the operating point of the comparison circuit 131. That is, the comparison circuit 131 is configured as a voltage comparator with an offset removal function.
  • the offset removal circuit 210 includes switching transistors 211 and 212, signal coupling capacitors 213 and 214, and an inverter circuit 215.
  • Switching transistors 211 and 212 are switching elements for removing the offset of the differential amplifier circuit 200.
  • the switching transistors 211 and 212 remove the offset by conducting the respective gates and drains or sources of the transistors 201 and 202 before the reference signal and the pixel signal are input.
  • the gates of the switching transistors 211 and 212 are connected to each other and to the output terminal of the inverter circuit 215. Note that the gates of the switching transistors 211 and 212 are an example of a control terminal to which a control signal for switching the switching transistors 211 and 212 on and off is input.
  • the switching transistor 211 is a transistor for removing the offset of the transistor 201, that is, for resetting (initializing) the transistor 201.
  • the switching transistor 211 is inserted between the gate and drain of the transistor 201. That is, the drain and source of the switching transistor 211 are connected to the gate and drain of the transistor 201.
  • the switching transistor 212 is a transistor for removing the offset of the transistor 202, that is, for resetting (initializing) the transistor 202.
  • the switching transistor 212 is inserted between the gate and drain of the transistor 202. That is, the drain and source of the switching transistor 212 are connected to the gate and drain of the transistor 202.
  • the switching transistors 211 and 212 are, for example, PMOS transistors.
  • the capacitor element 213 is provided between the input terminal IN1 of the comparison circuit 131 and the gate of the transistor 201. Specifically, one of the electrodes of the capacitor 213 is connected to the input terminal IN1, and a reference signal is input thereto. The other electrode of the capacitor 213 is connected to the gate of the transistor 201.
  • the capacitor 214 is provided between the input terminal IN2 of the comparison circuit 131 and the gate of the transistor 202. Specifically, one of the electrodes of the capacitor 214 is connected to the input terminal IN2, and a pixel signal is input thereto. The other electrode of the capacitor 214 is connected to the gate of the transistor 202.
  • the inverter circuit 215 is an example of a buffer circuit connected to the gates of the switching transistors 211 and 212.
  • the inverter circuit 215 buffers a control signal that controls on and off of the switching transistors 211 and 212.
  • the offset removal circuit 210 is activated by activating the reset control signal ⁇ CRST (comparator reset pulse) immediately before the comparison between the pixel signal and the reference signal is started.
  • the operating point of the differential transistor pair is reset to the drain voltage.
  • the pixel signal is input to the transistor 202 through the capacitor 214, and the reference signal is input to the transistor 201 through the capacitor 213, so that the comparison circuit 131 makes the pixel signal and the reference signal have the same potential. Compare until When the pixel signal and the reference signal have the same potential, the output of the comparison circuit 131 is inverted.
  • the operating point of the comparison circuit 131 can be set before the start of the comparison operation, it is less likely to be affected by variations in the reset component ⁇ V.
  • FIG. 4 is a diagram illustrating a circuit configuration of a comparison circuit 131a included in a general solid-state imaging device.
  • the same elements as those of the comparison circuit 131 shown in FIG. 4 the same elements as those of the comparison circuit 131 shown in FIG. 4
  • the comparison circuit 131 shown in FIG. 3 is different from the comparison circuit 131 shown in FIG. 3 in that an offset removal circuit 210a is provided instead of the offset removal circuit 210.
  • the comparison circuit 131a shown in FIG. Specifically, the offset removal circuit 210a differs from the offset removal circuit 210 in that the inverter circuit 215 is not provided.
  • the operating point of the comparison circuit 131a can be set, so that it is difficult to be affected by variations in the reset component ⁇ V.
  • the comparison circuit 131a includes the offset removal circuit 210a (operation reset unit), when the switching transistors 211 and 212 are turned off, charge redistribution (charge injection) in the channels of the transistors 203 and 204, or the clock Feedthrough occurs.
  • the effect of charge injection or clock feedthrough depends on the slope of the control signal input to the gates of the switching transistors 211 and 212.
  • a control signal buffered by a buffer circuit outside the column AD conversion circuit 130 is input to each column.
  • the switching time of the column far from the outer buffer circuit is longer by the wiring resistance than the column closer to the outer buffer circuit. For example, when the time until the control signal reaches about 95% of the actual amplitude is the switching time, when the wiring resistance of the control signal is R and the total capacitive load attached to the control signal is C, the switching time is 3RC. It becomes. That is, the slope of the control signal is 1/3 RC.
  • the comparison circuit 131 provided for each column has a buffer circuit.
  • each of the plurality of comparison circuits 131 includes an inverter circuit 215 that is an example of a buffer circuit.
  • the inverter circuit 215 buffers a reset control signal for controlling on and off of the switching transistors 211 and 212 and inputs the reset control signal to the switching transistors 211 and 212. Thereby, generation
  • FIG. 5 is a diagram showing a waveform of the reset control signal according to the present embodiment.
  • ⁇ CRST is the same as ⁇ CRST shown in FIG. 2, and is a reset control signal for controlling the offset removal circuit 210 of the comparison circuit 131. More specifically, the reset control signal ⁇ CRST is a signal when output from the timing control circuit 170.
  • CRST_n represents a reset control signal input to a column close to the timing control circuit 170 (outer buffer circuit). Specifically, CRST_n is an input signal to the inverter circuit 215 included in the comparison circuit 131 in the column close to the timing control circuit 170.
  • CRST_f represents a reset control signal input to a column far from the timing control circuit 170.
  • CRST_f is an input signal to the inverter circuit 215 included in the comparison circuit 131 in the column far from the timing control circuit 170.
  • CRSTIN_n is a signal input to the switching transistors 211 and 212 included in the comparison circuit 131 in the column close to the timing control circuit 170.
  • CRSTIN_n is an output signal from the inverter circuit 215 included in the comparison circuit 131 in the column close to the timing control circuit 170.
  • CRSTIN_f is a signal input to the switching transistors 211 and 212 included in the comparison circuit 131 in the column far from the timing control circuit 170.
  • CRSTIN_f is an output signal from the inverter circuit 215 included in the comparison circuit 131 in the column far from the timing control circuit 170.
  • the inclination of the reset control signal input to each column varies depending on the position of the column.
  • a reset control signal input to a column far from the timing control circuit 170 has a small slope as indicated by CRST_f. That is, the waveform of the reset control signal input to the column far from the timing control circuit 170 has a shape in which the rise and fall are rounded.
  • the slope of the signal input to the switching transistors 211 and 212 of each column increases due to the amplification action in the inverter circuit 215. That is, the waveform of the signal input to the switching transistors 211 and 212 of each column is a waveform close to the signal ⁇ CRST output from the timing control circuit 170.
  • the solid-state imaging device 10 is two-dimensionally arranged and generates a plurality of unit cells 100 that generate pixel signals according to the amount of received light, and for each column of the plurality of unit cells 100.
  • a plurality of vertical signal lines 110 that are provided and transfer pixel signals, a plurality of comparison circuits 131 provided corresponding to each of the plurality of vertical signal lines 110, and a common reference signal are supplied to the plurality of comparison circuits 131.
  • Each of the plurality of comparison circuits 131 outputs a signal corresponding to a difference amount between the reference signal and the pixel signal, and an offset of the differential amplifier circuit 200.
  • Switching transistors 211 and 212 for removal, and a buffer circuit connected to the control terminals of the switching transistors 211 and 212 are included.
  • the buffer circuit is an inverter circuit 215.
  • the inverter circuit 215 amplifies the reset control signal input to the control terminals of the switching transistors 211 and 212, thereby suppressing the rounding of the waveform of the reset control signal. Therefore, the difference in the waveform of the control signal can be made difficult to occur for each column, and deterioration of image quality such as shading can be suppressed.
  • the inverter circuit 215 has a gain that can sufficiently reduce the variation between the columns even with a small number of elements, and further has no steady current consumption. For this reason, it is advantageous in terms of cost and power consumption that the solid-state imaging device 10 includes the inverter circuit 215 as a buffer circuit.
  • the differential amplifier circuit 200 constitutes a differential pair, and a reference signal is input to one gate and a pixel signal is input to the other gate.
  • the transistors 201 and 202 are provided, and the switching transistors 211 and 212 make the offset by conducting the respective gates and drains or sources of the two transistors 201 and 202 before the reference signal and the pixel signal are input. Remove.
  • the operating point of the comparison circuit 131 can be set before the start of the comparison operation, it is less likely to be affected by variations in the reset component ⁇ V.
  • each of the plurality of unit cells 100 includes a reset transistor 103, a transfer transistor 102, a read transistor 104, and a selection transistor 105.
  • the reading of the pixel signal from the unit cell 100 can be appropriately controlled.
  • FIG. 6 is a diagram illustrating a circuit configuration of the comparison circuit 331 according to the present modification.
  • FIG. 7 is a timing chart showing an example of the operation of the comparison circuit 331 according to this modification.
  • the buffer circuit may be another circuit such as a common-source amplifier circuit, and the effects of the solid-state imaging device 10 of the present disclosure described above can be obtained in the same manner.
  • an inverter circuit 315 shown in FIG. 6 can be considered.
  • FIG. 6 the same components as those in FIG. 4 are given the same reference numerals.
  • the offset removal circuit 310 is different from the offset removal circuit 210 in that it includes an inverter circuit 315 including a PMOS transistor 315p and an NMOS transistor 315n instead of the inverter circuit 215.
  • the PMOS transistor 315p and the NMOS transistor 315n are controlled by different control signals. Specifically, the PMOS transistor 315p is controlled by the control signal RST1, and the NMOS transistor 315n is controlled by the control signal RST2.
  • the reset operation of the comparison circuit 331 according to the present modification will be described with reference to FIG.
  • the NMOS transistor 315n is turned on by setting the control signal RST2 to the “H” level at time t11. At this time, the control signal RST1 is at the “H” level, and the PMOS transistor 315p is in the off state.
  • the potential input to the switching transistors 211 and 212 can be set to the GND level, and the switching transistors 211 and 212 are turned on.
  • control signal RST2 is set to the “L” level to turn off the NMOS transistor 315n.
  • control signal RST1 is set to the “L” level to turn on the PMOS transistor 315p, so that the potential input to the switching transistors 211 and 212 is set to the VDD level.
  • time t11 which is the rise of the control signal RST2 (timing to set to “H” level), is the same as the start of ⁇ CRST in the timing chart of FIG. 2, that is, the time t1. Therefore, time t11 may be simultaneously with the fall of ⁇ SEL or ⁇ RS (timing to set to “L” level), or one of them may be first.
  • time t12 when the control signal RST2 falls may be before the time t13 when the control signal RST1 falls.
  • time t13 when the control signal RST1 falls is the same time as the fall of ⁇ CRST in the timing chart of FIG. Therefore, time t13 may be simultaneous with the fall of ⁇ RS (time t2), or one of them may be first.
  • time t14 that is the rise of the control signal RST1 may be after the end of ⁇ CK and Vref (time t7) in the timing chart of FIG.
  • the power source and ground of the buffer circuit may be separated from other power sources and grounds of the comparison circuit.
  • the power supply line and the ground line of the buffer circuit may be separated from the power supply line and the ground line of the differential amplifier circuit.
  • FIG. 8 is a diagram showing a circuit configuration of a comparison circuit 331a according to another modification.
  • the comparison circuit 331a shown in FIG. 8 has the same circuit configuration as the comparison circuit 331 shown in FIG.
  • the differential amplifier circuit 200 is connected to the power supply line VDD1 and the ground line GND1.
  • the inverter circuit 315 is connected to the power supply line VDD2 and the ground line GND2.
  • the power supply line VDD1 and the power supply line VDD2 are different from each other, and the ground line GND1 and the ground line GND2 are different from each other.
  • the potential difference between the power supply line VDD2 and the ground line GND2 of the buffer circuit may be smaller than the potential difference between the power supply line VDD1 and the ground line GND1 of the differential amplifier circuit.
  • the switching transistors 211 and 212 for reset are controlled by the power supply (power supply line VDD2) and ground (ground line GND2) of the inverter circuit 315. ing.
  • the ground potential (GND2) of the inverter circuit 315 is changed to another ground (for example, the ground potential (GND1) of the differential amplifier circuit). ) May be set at a higher bias potential. Thereby, the voltage for turning on the switching transistors 211 and 212 can be set to a level higher than the ground.
  • a potential difference is provided by making the ground potential of the differential amplifier circuit 200 different from the ground potential of the inverter circuit 315, but the power supply potential of the differential amplifier circuit 200 and the power supply potential of the inverter circuit 315 are made different. Also good.
  • the present disclosure is not limited to the above-described embodiments.
  • the technology in the present disclosure includes various embodiments realized by combining arbitrary components in each embodiment, and various types conceived by those skilled in the art without departing from the spirit of the present disclosure with respect to each embodiment.
  • the present invention can be applied to modified examples obtained by performing modifications, various devices that incorporate the solid-state imaging device according to the present disclosure, and various systems.
  • each of the plurality of unit cells included in the solid-state imaging device may share a unit cell control transistor with a plurality of adjacent light receiving units (pixels). That is, each of the plurality of unit cells may include a plurality of light receiving elements (photodiodes) and at least one of a reset transistor, a read transistor, and a selection transistor shared by the plurality of light receiving elements.
  • FIG. 9 is a diagram illustrating an example (unit cell 100a) of the circuit configuration of the unit cell 100 according to a modification of the embodiment.
  • the unit cell 100a includes photodiodes 101a and 101b, transfer transistors 102a and 102b, a reset transistor 103, a read transistor 104, a selection transistor 105, and a floating diffusion unit 106.
  • the photodiodes 101a and 101b share the reset transistor 103, the read transistor 104, the selection transistor 105, and the floating diffusion portion 106.
  • the charge when reading the charge from the photodiode 101a, the charge is transferred to the floating diffusion section 106 by turning on the transfer transistor 102a by setting the first transfer signal line ( ⁇ TXa) to the high level. Further, when reading charge from the photodiode 101b, the charge is transferred to the floating diffusion section 106 by turning on the transfer transistor 102b by setting the second transfer signal line ( ⁇ TXb) to a high level.
  • the unit cell 100 has a structure including a photodiode (pixel), a transfer transistor, a floating diffusion portion, a reset transistor, an amplification transistor (read transistor), and a selection transistor, so-called one pixel 1 A cell structure may be used.
  • a multi-pixel 1-cell structure may be used.
  • the reset transistor, the readout transistor, and the selection transistor are shared by a plurality of adjacent light receiving elements, so that the number of transistors per unit cell can be substantially reduced.
  • each of the plurality of unit cells included in the solid-state imaging device according to the present disclosure may not include a selection transistor as illustrated in FIG. 10, for example.
  • FIG. 10 is a diagram illustrating another example (unit cell 100b) of the circuit configuration of the unit cell 100 according to a modification of the embodiment.
  • the unit cell 100b shown in FIG. 10 is different from the unit cell 100 shown in FIG. In other words, among the transfer transistor 102, the reset transistor 103, the read transistor 104, and the selection transistor 105 included in the unit cell 100 as a control transistor, the unit cell 100b includes the transfer transistor 102, the reset transistor 103, and the read transistor. Only the transistor 104 is included.
  • the photodiode region and the aperture ratio can be enlarged. Therefore, the unit cell 100b can receive more light, and can increase sensitivity, for example.
  • the solid-state imaging device includes the unit cell 100 and the column AD conversion circuit 130.
  • An amplifier circuit may be provided between the two.
  • the transistors 201 and 202 constituting the differential pair are NMOS transistors.
  • the transistors 201 and 202 may be PMOS transistors. In this case, for example, the same effect can be obtained by replacing the PMOS transistor and the NMOS transistor for other transistors.
  • the solid-state imaging device may have a structure in which the pixels are formed on the surface of the semiconductor substrate, that is, on the same surface side as the surface on which the gate terminal and the wiring of the transistor are formed.
  • a so-called back-illuminated image sensor back surface in which pixels are formed on the back surface side of the semiconductor substrate, that is, on the back surface side with respect to the surface on which the gate terminal and wiring of the transistor are formed
  • back surface back-illuminated image sensor
  • the structure of an irradiation type solid-state imaging device may be used.
  • the solid-state imaging device is used as an imaging device (image input device) in an imaging device such as a video camera, a digital still camera, and a camera module for mobile devices such as a mobile phone. Is preferred.
  • FIG. 11 is a block diagram illustrating an example of a configuration of an imaging apparatus (camera system) including the solid-state imaging apparatus according to the embodiment.
  • the imaging apparatus 400 includes a lens 401, a solid-state imaging apparatus 402, a camera signal processing circuit 403, and a system controller 404.
  • the lens 401 is an optical element for guiding incident light to the imaging region of the solid-state imaging device 402.
  • the solid-state imaging device 402 is a solid-state imaging device according to the embodiment.
  • the solid-state imaging device 402 outputs an image signal obtained by converting image light imaged on the imaging surface by the lens 401 into an electrical signal in units of pixels.
  • the camera signal processing circuit 403 is a circuit that performs various processes on the output signal of the solid-state imaging device 402.
  • the system controller 404 is a control unit that drives the solid-state imaging device 402 and the camera signal processing circuit 403.
  • the image signal processed by the camera signal processing circuit 403 is recorded as a still image or a moving image on a recording medium such as a memory. Alternatively, it is projected as a moving image on a monitor including a liquid crystal display.
  • the image pickup apparatus has a built-in solid-state image pickup apparatus that can suppress deterioration in image quality such as shading, and therefore can provide a high-quality image as a camera system.
  • the solid-state imaging device can be used in various camera systems such as a CMOS solid-state imaging device, a digital still camera, a movie camera, a camera-equipped mobile phone, a surveillance camera, an in-vehicle camera, and a medical camera.
  • Solid-state imaging device 100,100a, 100b Unit cell 101,101a, 101b Photodiode 102,102a, 102b Transfer transistor 103 Reset transistor 104 Read transistor 105 Selection transistor 106 Floating diffusion part 110 Vertical signal line 120 Reference signal generation circuit 121 Reference signal Line 130 Column AD conversion circuits 131, 131a, 331, 331a Comparison circuit 132 Counter circuit 133 Memory circuit 140 Output circuit 150 Vertical selection circuit 160 Horizontal selection circuit 170 Timing control circuit 200 Differential amplification circuits 201, 202, 203, 204, 205 Transistors 210, 210 a, 310 Offset removal circuits 211, 212 Switching transistors 213, 214 Capacitor element 215 315 inverter circuit 315n NMOS transistor 315p PMOS transistor 400 imaging device 401 lens 402 solid-state imaging device 403 camera signal processing circuit 404 system controller

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

La présente invention concerne un dispositif de prise de vues à semi-conducteur pouvant capturer des images de grande qualité. Ledit dispositif de prise de vues à semi-conducteur comprend : une pluralité de cellules unitaires agencées en deux dimensions et générant des signaux de pixels qui dépendent de quantités de réception de lumière; une pluralité de lignes de signal verticales qui sont fournies pour chaque colonne de cellule unitaire et transfère les signaux de pixels; une pluralité de circuits de comparaison prévus de sorte à correspondre aux lignes de signal verticales respectives; et un circuit de génération de signal de référence qui fournit un signal de référence partagé aux circuits de comparaison. Chaque circuit de comparaison comprend : un circuit d'amplificateur différentiel (200) transmettant un signal qui dépend de la différence entre le signal de référence et un signal de pixel; des transistors de commutation (211 et 212) pour éliminer le décalage du circuit d'amplificateur différentiel (200); et un circuit d'onduleur (215) connecté aux bornes de commande des transistors de commutation (211 et 212).
PCT/JP2015/000023 2014-01-21 2015-01-07 Dispositif de prise de vues à semi-conducteur, et dispositif de prise de vues à semi-conducteur Ceased WO2015111370A1 (fr)

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WO2024224954A1 (fr) * 2023-04-28 2024-10-31 パナソニックＩｐマネジメント株式会社 Dispositif d'imagerie

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JP2007019682A (ja) * 2005-07-06 2007-01-25 Sony Corp Ａｄ変換装置並びに半導体装置
JP2009200931A (ja) * 2008-02-22 2009-09-03 Panasonic Corp 固体撮像装置、半導体集積回路装置、および信号処理方法
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