WO2015188511A1 - Nand flash operation processing method and apparatus, and logic device - Google Patents

Abstract

An NAND flash operation processing method and apparatus, and a logic device. The method comprises: establishing an address protection table for protecting an NAND flash protection region; judging whether an address at which the NAND flash is operated exists in the address protection table; and in the case where a judgement result is yes, shielding an operation conducted on the NAND flash. The present invention solves the problem in the related art that the NAND flash is incorrectly erased and written in, thereby achieving the effect that not only can an important storage region be effectively prevented from being damaged, but the reliability of an NAND flash for storing data is also effectively improved.

Description

NAND Flash operation processing method, device and logic device Technical field

The present invention relates to the field of communications, and in particular to a NAND Flash operation processing method, apparatus, and logic device.

Background technique

At present, the more common non-volatile memories include NOR Flash (NOR Flash) and NAND Flash (NAND Flash). Compared to NOR Flash, NAND Flash memory has a much faster write speed than NOR Flash memory and has a faster erase speed. It is faster than NOR Flash memory, has a large single-chip capacity, and has low cost per unit storage capacity. It is suitable for storing large amounts of data. Due to technical development needs and cost reasons, NAND Flash has been widely used in various electronic products.

In various occasions where NAND Flash is selected, improper operation from software may cause NAND Flash to be erased by mistake, which may cause serious consequences, especially when the boot and system running versions used for system booting are erroneously erased. It may even cause the system to fail to start.

Therefore, in the related art, NAND Flash has an unreliable problem caused by erroneous erasure and writing.

Summary of the invention

The invention provides a NAND Flash operation processing method, device and logic device to solve the problem that the NAND Flash in the related art is unreliable due to error erasure and writing.

According to an aspect of the present invention, a NAND Flash operation processing method is provided, including: establishing an address protection table for protecting a NAND Flash protection area; and determining whether an address for operating the NAND Flash exists in the address protection table In the case where the judgment result is YES, the operation on the NAND Flash is masked.

Preferably, the address protection table for protecting the NAND flash protection area includes: an importance degree division level for protecting different areas of the NAND Flash protection area; corresponding to the different areas according to the division level Address, establish an address protection table.

Preferably, after the establishing the address protection table for protecting the NAND Flash protection area, the method further includes: updating the address protection table.

Preferably, determining whether an address for operating the NAND Flash exists in the address protection table comprises: parsing a signal command from the central processing unit CPU to operate the NAND flash; comparing the signal command Whether the address of the NAND Flash matches the address in the address protection table; in the case of matching, it is determined whether an address operating on the NAND Flash exists in the address protection table.

Preferably, masking the operation of the NAND Flash comprises: determining whether an operation type of the operation of the NAND Flash is a modification operation; and if the determination result is YES, masking the operation of the NAND Flash.

According to another aspect of the present invention, a NAND Flash operation processing apparatus includes: an establishment module configured to establish an address protection table for protecting a NAND Flash protection area; and a determination module configured to determine to perform the NAND Flash Whether the address of the operation exists in the address protection table; and the masking module is configured to mask the operation of the NAND Flash if the determination result of the determination module is YES.

Preferably, the establishing module includes: a dividing unit, configured to divide a level of importance of protecting different areas of the NAND Flash protection area; and establishing a unit, which is set to an address corresponding to the different area after the dividing level, Create an address protection table.

Preferably, the apparatus further comprises: an update module configured to update the address protection table.

Preferably, the determining module comprises: a parsing unit configured to parse a signal command from the central processing unit CPU to operate the NAND flash; and a comparing unit configured to compare the NAND flash for the signal command Whether the address matches the address in the address protection table; the determining unit is configured to determine, in the case of matching, whether an address operating on the NAND Flash exists in the address protection table.

Preferably, the masking module includes: a determining unit configured to determine whether an operation type of the operation of the NAND Flash is a modification operation; and a shielding unit configured to block the determination result of the determining unit as yes The operation of the NAND Flash.

According to still another aspect of the present invention, there is provided a logic device comprising the apparatus of any of the above.

According to the present invention, an address protection table for protecting a NAND flash protection area is established; whether an address for operating the NAND Flash exists in the address protection table is determined; and if the determination result is yes, the shielding is performed. The operation of NAND Flash solves the problem that NAND Flash exists in related technologies. The problem of unreliable storage caused by erasing and writing achieves the effect of not only effectively preventing the important storage area from being damaged, but also effectively improving the reliability of the NAND Flash stored data.

DRAWINGS

The drawings described herein are intended to provide a further understanding of the invention, and are intended to be a part of the invention. In the drawing:

1 is a flowchart of a NAND Flash operation processing method according to an embodiment of the present invention;

2 is a block diagram showing the structure of a NAND Flash operation processing apparatus according to an embodiment of the present invention;

3 is a structural block diagram of a setup module 22 in a NAND Flash operation processing apparatus according to an embodiment of the present invention;

4 is a block diagram showing a preferred structure of a NAND Flash operation processing apparatus according to an embodiment of the present invention;

FIG. 5 is a structural block diagram of a determining module 24 in a NAND Flash operation processing apparatus according to an embodiment of the present invention;

6 is a structural block diagram of a masking module 26 in a NAND Flash operation processing apparatus according to an embodiment of the present invention;

7 is a structural block diagram of a logic device in accordance with an embodiment of the present invention;

FIG. 8 is a schematic diagram of an architecture for preventing NAND Flash from being erased and erroneously written according to an embodiment of the present invention; FIG.

9 is a functional explanatory diagram of an implementation method for preventing NAND Flash from being erroneously erased and erroneously written according to an embodiment of the present invention;

10 is a flowchart of an implementation method for preventing NAND FLASH from being erroneously erased and erroneously written according to an embodiment of the present invention;

11 is a flow diagram of adding or modifying a protected area to prevent an NAND FLASH from being erased and miswritten by an implementation in accordance with an embodiment of the present invention.

detailed description

The invention will be described in detail below with reference to the drawings in conjunction with the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict.

In this embodiment, a NAND Flash operation processing method is provided. FIG. 1 is a flowchart of a NAND Flash operation processing method according to an embodiment of the present invention. As shown in FIG. 1, the flow includes the following steps:

Step S102, establishing an address protection table for protecting the NAND Flash protection area;

Step S104, determining whether an address for operating the NAND Flash exists in the address protection table;

In step S106, if the determination result is YES, the operation on the NAND Flash is masked.

Through the above steps, the storage area of the NAND Flash is protected according to the establishment of the address protection table, which not only effectively solves the problem that the NAND Flash area is not protected in the related art, and the storage caused by the erroneous erasure and writing of the NAND Flash is unreliable. It may even cause the system to fail to boot, and effectively improve the reliability of the data stored in the NAND Flash.

When establishing an address protection table for protecting a NAND Flash protection area, a plurality of methods may be used. For example, when different protection areas need to be treated differently, the importance level of protection of different areas of the NAND Flash protection area may be divided; An address protection table is established according to addresses corresponding to different areas after the level is divided. Through such processing, the data stored in the NAND Flash area is distinguished to a significant extent. For example, the protection level can be set to be the highest for which it is particularly important that it cannot be deleted, and can be set slightly lower for the general importance.

Preferably, after the address protection table for protecting the NAND flash protection area is established, the address protection table may also be updated. For example, the importance of the NAND Flash storage area changes during different periods, and therefore, the address needs to be The protection table is updated accordingly to suit the needs of different periods.

When determining whether the address for operating the NAND Flash exists in the address protection table, the signal command for operating the NAND Flash from the CPU of the central processing unit may be parsed first; the address and address protection table of the NAND Flash for comparing the signal command may be Whether the addresses in the match match; in the case of matching, it is determined whether the address operating on the NAND Flash exists in the address protection table.

Preferably, when the operation on the NAND Flash is masked, the operation of erasing or modifying important data (protecting data stored in the corresponding area of the address) (for example, some simple read operations) is also blocked. , which may affect the user experience. Before determining whether the address for operating the NAND Flash exists in the address protection table, it is also possible to determine whether the operation type of the operation of the NAND Flash is a modification operation; if the determination result is yes, the operation on the NAND Flash is masked. .

In the embodiment, a NAND Flash operation processing device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and has not been described again. As used below, the term "module" A combination of software and/or hardware that can implement a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.

2 is a block diagram showing the structure of a NAND Flash operation processing apparatus according to an embodiment of the present invention. As shown in FIG. 2, the apparatus includes a setup module 22, a determination module 24, and a masking module 26. The apparatus will be described below.

The establishing module 22 is configured to establish an address protection table for protecting the NAND flash protection area; the determining module 24 is connected to the establishing module 22, and configured to determine whether an address for operating the NAND Flash exists in the address protection table; 26, connected to the above determining module 24, configured to mask the operation of the NAND Flash when the determination result of the determining module is YES.

3 is a structural block diagram of a setup module 22 in a NAND Flash operation processing apparatus according to an embodiment of the present invention. As shown in FIG. 3, the setup module 22 includes a division unit 32 and an establishment unit 34. The setup module 22 is described below. .

The dividing unit 32 is configured to divide the importance level of the different areas of the NAND Flash protection area; the establishing unit 34 is connected to the dividing unit 32, and is configured to establish an address protection table according to addresses corresponding to different areas after the dividing level .

4 is a block diagram of a preferred structure of a NAND Flash operation processing apparatus according to an embodiment of the present invention. As shown in FIG. 4, the apparatus includes, in addition to all the structures shown in FIG. 2, an update module 42, which is updated below. Module 42 is described.

The update module 42 is coupled to the setup module 22 and the determination module 24, and is configured to update the address protection table.

FIG. 5 is a structural block diagram of the determining module 24 in the NAND Flash operation processing apparatus according to an embodiment of the present invention. As shown in FIG. 5, the determining module 24 includes: a parsing unit 52, a comparing unit 54, and a determining unit 56. The determination module 24 is described.

The parsing unit 52 is configured to parse a signal command from the central processing unit CPU for operating the NAND flash; the comparing unit 54 is connected to the parsing unit 52, and is configured to compare the address and address protection table of the NAND flash for which the signal command is directed Whether the addresses match, the determining unit 56 is connected to the comparing unit 54 described above, and is arranged to determine, in the case of matching, whether an address operating on the NAND Flash exists in the address protection table.

FIG. 6 is a structural block diagram of a masking module 24 in a NAND Flash operation processing apparatus according to an embodiment of the present invention. As shown in FIG. 6, the masking module 26 includes: a determining unit 62 and a shielding unit 64, and the masking module 26 is performed below. Description.

The judging unit 62 is configured to determine whether the operation type of the operation of the NAND flash is a modification operation; the masking unit 64 is connected to the judging unit 62, and is configured to mask the NAND flash if the judgment result of the judging unit is YES. operating.

7 is a block diagram showing the structure of a logic device according to an embodiment of the present invention. As shown in FIG. 7, the logic device 70 includes the NAND Flash operation processing device 72 of any of the above.

In the related art, since there is no protection for a specific area of the NAND flash memory, there is a problem that the NAND flash memory is erroneously written or erased to cause storage unreliability. In the embodiment, the NAND flash is prevented from being mistaken. Erase and miswrite implementations to protect specific areas of NAND Flash, for example, using address filtering to protect specific memory areas, effectively preventing important memory areas from being erased and written by mistake, increasing The reliability of electronic products.

The implementation method of preventing NAND flash from being erased and misprogrammed (false write) is through such address filtering and masking method to prevent a specific storage area from being damaged during an erroneous operation. The following processing methods can be used to achieve:

By establishing an address protection table for the NAND Flash protection area, in the access to the NAND Flash, the interface signal is parsed, and if there is an erase or program operation on the protected interval, the corresponding operation is masked. FIG. 8 is a schematic diagram of an architecture for preventing NAND flash from being erroneously erased and erroneously written according to an embodiment of the present invention. As shown in FIG. 8 , the physical components included in the implementation method mainly include: a central processing unit (Central Processing Unit) , referred to as CPU), logic device (Field Programmable Gate Array (FPGA) or Complex Programmable Logic Device (CPLD)), NAND Flash.

In this scheme, the CPU can access the internal Flash of the logic device through the control interface while providing the Flash interface to the logic device. The interface that the CPU accesses the internal Flash of the logic device can be various types, such as interfaces in the form of IIC, LOCAL BUS, SPI, etc., which depend on the interface provided by the processor.

The logic device can be either FPGA or CPLD. The various logic devices on the market have built-in Flash. The address protection table is stored in the Flash of the logic device. The CPU can read, write, and store the address protection table.

Generally speaking, the protected area may be a boot area, a boot area, a large version area, and other storage areas for important information. The physical block addresses corresponding to these protected areas are stored in the address protection table. The logic device extracts the Row Address corresponding to these block addresses and compares it with the Row Address in the NAND Flash port. Once the same, the erase or program command is masked.

Preferably, the solution further includes establishment and update of the protection address table, signal analysis of the NAND Flash interface, masking of the error erasing and misprogramming commands, and status indication.

Compared with the related art, the protection of the flash memory generally uses the staggered address space to make the Flash cannot be accessed, and this method is limited to the application of the NOR Flash. Through the above address protection table, the protection against false erase and misprogramming of the boot area, the boot area, the large version area, and other important information storage areas on the NAND Flash is realized, and the protection method is protected by this protection method. In the access operation to NAND Flash, no additional intervention is required by the software, which reduces the complexity of the software, reduces the workload of the processor, and improves the system reliability.

The embodiments of the present invention will be described below with reference to the accompanying drawings.

9 is a functional explanatory diagram of an implementation method for preventing NAND flash from being erroneously erased and erroneously written according to an embodiment of the present invention. As shown in FIG. 9, based on the architecture shown in FIG. 1, the functional components of the scheme include: 101 processors. (CPU), 102 NAND Flash, 103 address protection table, 104 NAND Flash I/O interface parser, 105 NAND Flash I/O address filter, 106 access status indicator.

The 101 processor (CPU) can access the 103 address protection table in the internal Flash of the logic device through the control interface, and provide the Flash interface to the logic device. The CPU accesses the internal Flash interface of the logic device. It can be various types, such as IIC, LOCAL BUS, SPI, etc. The type of the specific interface depends on the CPU.

The logic device can be either FPGA or CPLD. The CPU can access (read and write) the 103 address protection table in the built-in Flash of the logic device. The 104 NAND Flash I/O interface parser in the logic device parses the signal from the CPU's Flash interface. The parsed address is compared with the 103 address protection table. The 105 NAND Flash I/O address filter determines whether to mask the wipe. In addition to or programming commands.

The 106 access status indicator indicates the current state in which erasure, programming, or normal access is prohibited.

At the head of the 103 address protection table, there is a specific flag for protection. This flag can have a check digit to distinguish it from the value when Flash was not written.

In this solution, the memory device is 102 NAND Flash, and each block on the 102 NAND Flash can be read, erased, and programmed. NAND Flash is used to store boot code, boot code, large version code, other important information, and other relatively less important information.

FIG. 10 is a flowchart of a method for preventing NAND FLASH from being erroneously erased and erroneously written according to an embodiment of the present invention. As shown in FIG. 10, the process includes the following steps:

Step A. After the system is reset or powered on, the logic device first causes the CPU to be in a reset state, waiting for the logic to read the address protection table;

Step B. The logic reads the address protection table from the built-in Flash;

Step C. If the interval that does not require protection is read from the head of the address protection table, the protection address is processed in the default manner in the logic code, for example, transparently transmitting the address and the command. Otherwise, the protection interval is extracted according to the information in the flash;

Step D. The logic determines the address to be filtered according to the extracted protection interval information, for example, the Row Address of the protected block;

Step E. Release the reset of the processor CPU to enable the CPU to start;

Step F. After the processor CPU is started, accessing the NAND Flash, the logic collects the interface information, first determines the type of the command, and if the parsed command is not Erase or Program edit, it is a read operation. (Read), the command is directly transmitted to the NAND Flash, and the normal access to the NAND Flash;

Step G. If the logic parsed command is Erase or Program, compare the Row Address of the protected block in step D. If the address does not match, the command is directly transmitted to the NAND Flash, and the NAND Flash is normally accessed.

Step H. If the logic parsed command is Erase or Program, compare the Row Address of the protected block in step D. If the address matches, the corresponding command is masked and fed back to the flag register to display an illegal Erase or Program.

11 is a flowchart of adding or modifying a protected area to prevent an NAND FLASH from being erased and miswritten by an implementation method according to an embodiment of the present invention. As shown in FIG. 11, if a guard interval needs to be changed, the flow includes the following step:

Step A. The system background starts the version update in the NAND Flash;

Step B. The system notifies the logic to release the logical address protection, and transparently transmits all the commands of the originally set NAND FLASH protected interval;

Step C. The system starts downloading and updating the content in the NAND Flash;

Step D. If the system downloads the update NAND Flash fails, the download update is terminated, and the update failure flag is set, and the logical address protection is restored.

Step E. If the system downloads and updates the NAND Flash successfully, the address protection table is updated, and the update success flag is set at the same time;

Step F. Update the protection flag of the address protection table to indicate that there is an address range that needs to be protected;

Step G. The logic initiates address filtering in accordance with the updated address protection table.

It will be apparent to those skilled in the art that the various modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein. The steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Industrial applicability

As described above, the above embodiments and preferred embodiments solve the problem that the NAND Flash in the related art is unreliable due to erroneous erasure and writing, thereby achieving not only the effective avoidance of the important storage area being damaged, but also The effect of the reliability of the data stored in the NAND Flash is effectively improved.

Claims (11)

A NAND Flash operation processing method includes: Establish an address protection table for protecting the NAND Flash protection area; Determining whether an address for operating the NAND Flash exists in the address protection table; In the case where the determination result is YES, the operation on the NAND Flash is masked. The method of claim 1 wherein establishing the address protection table to protect the NAND Flash protected area comprises: The importance level of protection for different areas of the NAND Flash protection zone; An address protection table is established according to addresses corresponding to the different areas after the level is divided. The method of claim 1, wherein after the establishing the address protection table for protecting the NAND Flash protection area, the method further comprises: The address protection table is updated. The method of claim 1, wherein determining whether an address operating on the NAND Flash exists in the address protection table comprises: Parsing a signal command from the central processing unit CPU to operate the NAND flash; Comparing whether an address of the NAND Flash for which the signal command is directed matches an address in the address protection table; In the case of a match, it is determined whether an address operating on the NAND Flash exists in the address protection table. The method of any of claims 1 to 4, wherein masking operations on the NAND Flash comprises: Determining whether the operation type of the operation of the NAND Flash is a modification operation; In the case where the determination result is YES, the operation on the NAND Flash is masked. A NAND Flash operation processing device includes: Establishing a module, and setting an address protection table for protecting the NAND Flash protection area; a determining module, configured to determine whether an address for operating the NAND Flash exists in the address protection table; The masking module is configured to mask the operation of the NAND Flash when the determination result of the determining module is YES. The apparatus of claim 6 wherein said establishing module comprises: a dividing unit, which is set to a level of importance for protecting different areas of the NAND Flash protected area; The establishing unit is configured to establish an address protection table according to addresses corresponding to the different areas after the division level. The apparatus of claim 6 further comprising: An update module is provided to update the address protection table. The apparatus of claim 6, wherein the determining module comprises: a parsing unit configured to parse a signal command from the central processing unit CPU to operate the NAND flash; a comparison unit configured to compare whether an address of the NAND Flash for which the signal command is directed matches an address in the address protection table; The determining unit is configured to determine, in the case of matching, whether an address operating on the NAND Flash exists in the address protection table. The apparatus according to any one of claims 6 to 9, wherein the shielding module comprises: a determining unit, configured to determine whether an operation type of the operation of the NAND Flash is a modification operation; The masking unit is configured to mask the operation of the NAND Flash when the determination result of the determining unit is YES. A logic device comprising the apparatus of any one of claims 6 to 10.

Images