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WO2015178307A1 - Élément de conversion photoélectrique - Google Patents

Élément de conversion photoélectrique Download PDF

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Publication number
WO2015178307A1
WO2015178307A1 PCT/JP2015/064017 JP2015064017W WO2015178307A1 WO 2015178307 A1 WO2015178307 A1 WO 2015178307A1 JP 2015064017 W JP2015064017 W JP 2015064017W WO 2015178307 A1 WO2015178307 A1 WO 2015178307A1
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Prior art keywords
amorphous silicon
silicon layer
type amorphous
type
photoelectric conversion
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English (en)
Japanese (ja)
Inventor
督章 國吉
敏彦 酒井
賢治 木本
親扶 岡本
利人 菅沼
神川　剛
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Sharp Corp
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Sharp Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/30—Coatings
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a photoelectric conversion element.
  • solar cells as photoelectric conversion elements have attracted attention.
  • An example of a solar cell is a back junction solar cell.
  • the back junction solar cell is formed on the back surface of the semiconductor substrate, the n-type amorphous semiconductor film formed on the back surface of the semiconductor substrate opposite to the solar irradiation surface, and the back surface. It consists of a p-type amorphous semiconductor film and electrodes formed on the n-type amorphous semiconductor film and the p-type amorphous semiconductor film.
  • Patent Document 1 describes that after forming a p-type amorphous semiconductor film and an n-type amorphous semiconductor film on the back surface of a semiconductor substrate, an antireflection film is formed on the light incident side surface.
  • Patent Document 2 an i-type amorphous semiconductor film, an n-type amorphous semiconductor film, and a protective layer having an antireflection function are formed on a light-receiving surface of a semiconductor substrate, and then an n-type region and a p-type are formed on the back surface. The formation of a region is described.
  • the formed film is a peripheral edge of the side surface of the semiconductor substrate and the opposite surface.
  • the phenomenon that wraps around the part occurs.
  • a portion of the semiconductor film on the light incident side for example, n-type semiconductor film
  • a semiconductor substrate in the semiconductor film on the back surface side for example, p-type semiconductor film.
  • Patent Documents 1 and 2 do not describe anything about the structure of the side surface portion of the semiconductor substrate of the photoelectric conversion unit. Therefore, the portion of the semiconductor film on the light incident side that wraps around the side surface and the back surface of the semiconductor substrate, and the portion of the semiconductor film on the back surface side that wraps around the side surface of the semiconductor substrate and the light incident surface In some cases, they are in contact with each other.
  • An object of the present invention is to provide a photoelectric conversion element in which a reduction in the lifetime of minority carriers in a semiconductor film is suppressed.
  • the photoelectric conversion element of the present invention that solves the above-described problems is a semiconductor substrate, a first semiconductor film that is formed in contact with a light incident side surface of the semiconductor substrate and has a first conductivity type, and the first semiconductor film.
  • the first semiconductor film, the dielectric film, and the second semiconductor film are stacked in this order.
  • the first semiconductor film and the second semiconductor film having opposite conductivity types are laminated on the side surface of the semiconductor substrate via the dielectric film without contacting each other. Therefore, the extraction of hydrogen atoms from the n-type semiconductor film to the p-type semiconductor film of the first semiconductor film and the second semiconductor film is blocked by the dielectric film. That is, the generation of dangling bonds due to the extraction of hydrogen atoms is suppressed by the dielectric film, and as a result, the reduction of the minority carrier lifetime can be suppressed.
  • the first semiconductor film, the dielectric film, and the second semiconductor film are laminated in this order at the periphery of the light incident surface of the semiconductor substrate.
  • the first semiconductor film and the second semiconductor film having the opposite conductivity types are also stacked through the dielectric film without contact with each other at the peripheral portion of the light incident side surface of the semiconductor substrate.
  • the extraction of hydrogen atoms from the n-type semiconductor film to the p-type semiconductor film of the first semiconductor film and the second semiconductor film is blocked by the dielectric film.
  • dangling bonds due to extraction of hydrogen atoms are suppressed by the dielectric film even at the periphery of the light incident surface of the semiconductor substrate, and as a result, the lifetime of minority carriers is more effectively suppressed. can do.
  • the first conductivity type is n-type and the second conductivity type is p-type.
  • the first semiconductor film (conductivity type: n-type) is formed prior to the second semiconductor film (conductivity type: p-type)
  • the number of times of receiving a thermal history increases.
  • a p-type semiconductor film is more likely to generate a dangling bond by extracting a hydrogen atom from a surrounding amorphous silicon layer by receiving a thermal history.
  • it can prevent that a p-type semiconductor film receives a thermal history as much as possible. Therefore, the occurrence of dangling bonds is suppressed, and as a result, the lifetime of minority carriers can be more effectively suppressed.
  • the photoelectric conversion element of the present invention is in contact with the surface opposite to the light incident side of the semiconductor substrate, has a second semiconductor film having a conductivity type opposite to the semiconductor substrate, and has the same conductivity type as the semiconductor substrate.
  • a third semiconductor film adjacent to the second semiconductor film in the in-plane direction of the semiconductor substrate may be provided.
  • the dielectric film preferably contains a positive fixed charge.
  • the dielectric film of the photoelectric conversion element of the present invention may be formed of SiN.
  • the first semiconductor film and the second semiconductor film having opposite conductivity types are laminated on the side surface of the semiconductor substrate via the dielectric film without contacting each other. Therefore, it is possible to block the extraction of hydrogen atoms from the n-type semiconductor film to the p-type semiconductor film of the first semiconductor film and the second semiconductor film by the dielectric film. That is, the generation of dangling bonds due to the extraction of hydrogen atoms is suppressed by the dielectric film, and as a result, the reduction of the minority carrier lifetime can be suppressed.
  • FIG. 1 is a cross-sectional view illustrating a configuration of the photoelectric conversion element according to the first embodiment.
  • FIG. 2A is a first process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 1.
  • FIG. 2B is a second process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 1.
  • FIG. 2C is a third process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 1.
  • FIG. 2D is a fourth process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 1.
  • FIG. 2E is a fifth process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 1.
  • FIG. 2F is a sixth process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 1.
  • FIG. 2A is a first process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 1.
  • FIG. 2B is a second process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG
  • FIG. 2G is a seventh process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 1.
  • FIG. 3 is a cross-sectional view illustrating a configuration of the photoelectric conversion element of the second embodiment.
  • FIG. 4A is a first process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 3.
  • FIG. 4B is a second process diagram illustrating the method of manufacturing the photoelectric conversion element illustrated in FIG. 3.
  • FIG. 4C is a third process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 3.
  • FIG. 5 is a cross-sectional view illustrating a configuration of the photoelectric conversion element of the third embodiment.
  • FIG. 6A is a first process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 5.
  • FIG. 5 is a first process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 5.
  • FIG. 5 is a first process diagram illustrating a method for manufacturing the photoelectric conversion element illustrated in FIG. 5.
  • FIG. 6B is a second process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 5.
  • FIG. 6C is a third process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 5.
  • FIG. 6D is a fourth process diagram illustrating the method of manufacturing the photoelectric conversion element illustrated in FIG. 5.
  • FIG. 6E is a fifth process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 5.
  • FIG. 6F is a sixth process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 5.
  • FIG. 6G is a seventh process diagram illustrating the method for manufacturing the photoelectric conversion element illustrated in FIG. 5.
  • FIG. 7 is a schematic diagram illustrating an example of the configuration of the photoelectric conversion module according to the fourth embodiment.
  • FIG. 7 is a schematic diagram illustrating an example of the configuration of the photoelectric conversion module according to the fourth embodiment.
  • FIG. 8 is a schematic diagram illustrating an example of the configuration of the photovoltaic power generation system according to the fifth embodiment.
  • FIG. 9 is a schematic diagram illustrating another example of the configuration of the solar power generation system according to the fifth embodiment.
  • FIG. 10 is a schematic diagram showing an example of the configuration of the photoelectric conversion module array shown in FIG.
  • FIG. 11 is a schematic diagram illustrating an example of a configuration of a photovoltaic power generation system according to the sixth embodiment.
  • FIG. 12 is a schematic diagram illustrating another example of the configuration of the solar power generation system according to the sixth embodiment.
  • amorphous phase refers to a state in which silicon (Si) atoms and the like are randomly arranged. Further, although amorphous silicon is expressed as “a-Si”, this notation actually means that hydrogen (H) atoms are included.
  • FIG. 1 is a cross-sectional view showing a configuration of a photoelectric conversion element 100 according to Embodiment 1 of the present invention.
  • the photoelectric conversion element 100 of Embodiment 1 includes an n-type single crystal silicon substrate 1, an i-type amorphous silicon layer 2, an n-type amorphous silicon layer 3, an antireflection film 4, and an i-type amorphous. Silicon layers 5a and 5b, a p-type amorphous silicon layer 6, an n-type amorphous silicon layer 7, and an electrode 8 are provided.
  • the n-type single crystal silicon substrate 1 has, for example, a (100) plane orientation and a specific resistance of 0.1 to 10 ⁇ ⁇ cm.
  • the thickness of the n-type single crystal silicon substrate 1 is, for example, 100 to 300 ⁇ m.
  • the n-type single crystal silicon substrate 1 has a textured surface on the light incident side.
  • the i-type amorphous silicon layer 2 is provided in contact with the light incident surface of the n-type single crystal silicon substrate 1.
  • the i-type amorphous silicon layer 2 is made of an amorphous phase and is made of, for example, i-type a-Si.
  • the thickness of the i-type amorphous silicon layer 2 is, for example, 2 to several tens of nm.
  • the i-type amorphous silicon layer 2t which is a part of the i-type amorphous silicon layer 2 is provided so as to cover the side surface 1t of the n-type single crystal silicon substrate 1 and the peripheral edge 1u of the back surface.
  • the i-type amorphous silicon layer 2t is provided so as to extend from the end face 1t of the n-type single crystal silicon substrate 1 to, for example, about 3 mm at the peripheral edge 1u on the back surface.
  • the n-type amorphous silicon layer 3 is formed in contact with the i-type amorphous silicon layer 2.
  • the n-type amorphous silicon layer 3 is made of an amorphous phase and is made of, for example, n-type a-Si.
  • the thickness of the n-type amorphous silicon layer 3 is, for example, 5 to several tens of nm.
  • the phosphorus (P) concentration of the n-type amorphous silicon layer 3 is, for example, 1 ⁇ 10 20 to 1 ⁇ 10 22 cm ⁇ 3 .
  • the n-type amorphous silicon layer 3t which is a part of the n-type amorphous silicon layer 3, is an i-type amorphous silicon layer also on the side surface 1t of the n-type single crystal silicon substrate 1 and the peripheral edge 1u of the back surface. It is in contact with 2t.
  • the antireflection film 4 is provided in contact with the n-type amorphous silicon layer 3.
  • the antireflection film 4 is preferably made of a material containing a positive fixed charge.
  • the antireflection film 4 is made of, for example, silicon nitride (SiN), diamond-like carbon (DLC), silicon carbide (SiC), aluminum nitride (AlN), or the like.
  • the thickness of the antireflection film 4 is preferably 100 to 200 nm, for example.
  • the antireflection film 4t which is a part of the antireflection film 4, is provided in contact with the n-type amorphous silicon layer 3t also on the side surface 1t of the n-type single crystal silicon substrate 1 and the peripheral edge 1u of the back surface. .
  • the i-type amorphous silicon layer 5a is provided in contact with the surface of the n-type single crystal silicon substrate 1 opposite to the light incident side.
  • the i-type amorphous silicon layer 5a is made of an amorphous phase, and is made of, for example, i-type a-Si.
  • the thickness of the i-type amorphous silicon layer 5a is, for example, 2 nm to several tens of nm.
  • an i-type amorphous silicon layer 5at is provided in contact with the antireflection film 4t at a portion covering the side surface 1t of the n-type single crystal silicon substrate 1 and the peripheral portion 1s on the light incident side.
  • the i-type amorphous silicon layer 5at is provided so as to extend from the end face 1t of the n-type single crystal silicon substrate 1 to, for example, about 3 mm in the peripheral portion 1s on the light incident side.
  • the i-type amorphous silicon layer 5at is formed of the same semiconductor film as the i-type amorphous silicon layer 5a.
  • the p-type amorphous silicon layer 6 is formed in contact with the i-type amorphous silicon layer 5a.
  • the p-type amorphous silicon layer 6 is made of an amorphous phase and is made of, for example, p-type a-Si.
  • the thickness of the p-type amorphous silicon layer 6 is, for example, 10 nm to several tens of nm.
  • the boron (B) concentration of the p-type amorphous silicon layer 6 is, for example, 1 ⁇ 10 20 to 1 ⁇ 10 22 cm ⁇ 3 .
  • a p-type amorphous silicon layer 6t is provided in contact with the i-type amorphous silicon layer 5at also on the side surface 1t of the n-type single crystal silicon substrate 1 and the peripheral edge 1s on the light incident side.
  • the p-type amorphous silicon layer 6 t is formed of the same semiconductor film as the p-type amorphous silicon layer 6.
  • the i-type amorphous silicon layer 5b is provided in contact with the surface of the n-type single crystal silicon substrate 1 opposite to the light incident side.
  • the i-type amorphous silicon layer 5b is provided in a portion where the i-type amorphous silicon layer 5a is not provided in a portion in contact with the surface of the n-type single crystal silicon substrate 1 opposite to the light incident side. Yes. That is, i-type amorphous silicon layer 5 a and i-type amorphous silicon layer 5 b are arranged adjacent to each other in the in-plane direction of n-type single crystal silicon substrate 1.
  • the i-type amorphous silicon layer 5b is made of an amorphous phase and is made of, for example, i-type a-Si.
  • the i-type amorphous silicon layer 5b has a thickness of 3 nm to several tens of nm, for example.
  • an i-type amorphous silicon layer 5bt is provided in contact with the p-type amorphous silicon layer 5at at a portion covering the side surface 1t of the n-type single crystal silicon substrate 1 and the peripheral portion 1s on the light incident side. ing.
  • i-type amorphous silicon layer 5bt is formed of the same semiconductor film as i-type amorphous silicon layer 5b.
  • the n-type amorphous silicon layer 7 is formed in contact with the i-type amorphous silicon layer 5b.
  • the n-type amorphous silicon layer 7 is disposed adjacent to the p-type amorphous silicon layer 6 in the in-plane direction of the n-type single crystal silicon substrate 1.
  • the n-type amorphous silicon layer 7 is made of an amorphous phase and is made of, for example, n-type a-Si.
  • the thickness of the n-type amorphous silicon layer 7 is, for example, 10 to several tens of nm.
  • the phosphorus (P) concentration of the n-type amorphous silicon layer 7 is, for example, 1 ⁇ 10 20 to 1 ⁇ 10 22 cm ⁇ 3 .
  • an n-type amorphous silicon layer 7t is also provided in contact with the i-type amorphous silicon layer 5bt on the side surface 1t of the n-type single crystal silicon substrate 1 and the peripheral edge 1s on the light incident side.
  • the n-type amorphous silicon layer 7 t is formed of the same semiconductor film as the n-type amorphous silicon layer 7.
  • the electrodes 8 are provided in contact with the p-type amorphous silicon layer 6 or the n-type amorphous silicon layer 7, respectively.
  • the electrode 8 has a configuration in which, for example, a transparent conductive film 8a and a metal film 8b are laminated.
  • the transparent conductive film 8a include ITO (indium tin oxide), Zn, SnO 2 and the like.
  • the metal film 8b silver (Ag) is mentioned, for example.
  • the thickness of the transparent conductive film 8a is, for example, 70 to 100 nm.
  • a side surface 1t (region T1 in FIG. 1) of the n-type single crystal silicon substrate 1 is formed in order from the side in contact with the n-type single crystal silicon substrate 1, i-type amorphous silicon layer 2t, n-type amorphous silicon layer 3t,
  • the antireflection film 4t, the i-type amorphous silicon layer 5at, the p-type amorphous silicon layer 6t, the i-type amorphous silicon layer 5bt, and the n-type amorphous silicon layer 7t are stacked.
  • the antireflection film 4t exists between the i-type amorphous silicon layer 2t and the n-type amorphous silicon layer 3t and the i-type amorphous silicon layer 5at and the p-type amorphous silicon layer 6t. To do.
  • peripheral edge 1s (region T2 in FIG. 1) on the light incident side surface of the n-type single crystal silicon substrate 1 has the same structure as the region T1.
  • the photoelectric conversion element 100 when sunlight is irradiated to the photoelectric conversion element 100 from the antireflection film 4 side, electrons and holes are photoexcited in the n-type single crystal silicon substrate 1.
  • the photoexcited holes and electrons diffuse into the p-type amorphous silicon layer 6 and the n-type amorphous silicon layer 7, respectively, thereby generating an electromotive force.
  • (Production method) 2A to 2G are process diagrams showing a method for manufacturing the photoelectric conversion element 100 shown in FIG.
  • an n-type single crystal silicon substrate 1 is prepared.
  • the texture structure 1a is formed on the entire light incident side surface of the n-type single crystal silicon substrate 1. It is formed.
  • an i-type amorphous silicon layer 2 is formed on the light incident side surface of the n-type single crystal silicon substrate 1 by plasma CVD.
  • the reaction gas is silane gas and hydrogen gas.
  • the temperature of the n-type single crystal silicon substrate 1 is, for example, 100 to 300 ° C.
  • the i-type amorphous silicon layer 2t which is a part of the i-type amorphous silicon layer 2, wraps around the side surface 1t of the n-type single crystal silicon substrate 1 and the peripheral edge 1u of the back surface.
  • an n-type amorphous silicon layer 3 is formed on the i-type amorphous silicon layer 2 by plasma CVD.
  • the reactive gases are silane gas, hydrogen gas, and phosphine gas.
  • the temperature of the n-type single crystal silicon substrate 1 is, for example, 100 to 300 ° C.
  • the n-type amorphous silicon layer 3t which is a part of the n-type amorphous silicon layer 3, wraps around the side surface 1t of the n-type single crystal silicon substrate 1 and the peripheral edge 1u of the back surface.
  • the antireflection film 4 is formed by the plasma CVD method.
  • the antireflection film 4t which is a part of the antireflection film 4, wraps around the side surface 1t of the n-type single crystal silicon substrate 1 and the peripheral edge 1u of the back surface.
  • the i-type amorphous silicon 2, the n-type amorphous silicon layer 3, and the antireflection film 4 are preferably formed in the same formation chamber.
  • an i-type amorphous silicon layer 5ap and a p-type amorphous silicon layer 6p are sequentially formed on the back surface of the n-type single crystal silicon substrate 1 by plasma CVD.
  • the formation conditions of the i-type amorphous silicon layer 5ap are the same as the formation conditions of the i-type amorphous silicon layer 2.
  • silane gas, hydrogen gas, and diborane gas are used as the reaction gas.
  • the temperature of the n-type single crystal silicon substrate 1 is, for example, 100 to 300 ° C.
  • the i-type amorphous silicon layer 5ap and the p-type amorphous silicon layer 6t which are parts of the i-type amorphous silicon layer 5ap and the p-type amorphous silicon layer 6p, are formed on the n-type single crystal silicon substrate. 1 side 1t and the peripheral edge 1s of the light incident side surface.
  • a coating layer 10 as a mask is formed on the p-type amorphous silicon layer 6p.
  • the covering layer 10 is obtained, for example, by patterning a silicon nitride film formed on the p-type amorphous silicon layer 6p.
  • a silicon oxide film, a silicon oxynitride film, or the like may be used instead of the silicon nitride film.
  • the patterning is performed by, for example, a photolithography method.
  • Covering layer 10 covers a portion of p-type amorphous silicon layer 6p formed on i-type amorphous silicon layer 5ap that will later become p-type amorphous silicon layer 6.
  • portions of the i-type amorphous silicon layer 5ap and the p-type amorphous silicon layer 6p that are not covered with the coating layer 10 are removed.
  • a method for removing the i-type amorphous silicon layer 5ap and the p-type amorphous silicon layer 6p is, for example, dry etching. Thereby, the i-type amorphous silicon layer 5a and the p-type amorphous silicon layer 6 are formed. At this time, the covering layer 10 is formed on the p-type amorphous silicon layer 6.
  • an i-type amorphous silicon layer 5bp and an n-type amorphous silicon layer 7p are sequentially formed by plasma CVD.
  • the formation conditions of the i-type amorphous silicon layer 5bp and the n-type amorphous silicon layer 7p are the same as the formation conditions of the i-type amorphous silicon layer 2 and the n-type amorphous silicon layer 3, respectively.
  • the i-type amorphous silicon layer 5bp and the i-type amorphous silicon layer 5bt and the n-type amorphous silicon layer 7t, which are part of the n-type amorphous silicon layer 7p, are formed on the n-type single crystal silicon substrate. 1 side 1t and the peripheral edge 1s of the light incident side surface.
  • the covering layer 10, the i-type amorphous silicon layer 5bp, and the n-type amorphous silicon layer 7p formed on the p-type amorphous silicon layer 6 are removed. Thereby, as shown in FIG. 2F, an i-type amorphous silicon layer 5b and an n-type amorphous silicon layer 7 are formed.
  • a method for removing the covering layer 10 and the like formed on the p-type amorphous silicon layer 6 is, for example, wet etching.
  • a transparent conductive film such as ITO is formed on the n-type amorphous silicon layer 7 and the p-type amorphous silicon layer 6 side, and a metal such as Ag is further deposited. Then, the metal film and the transparent conductive film are patterned by photolithography and etching so as to correspond to the p-type amorphous silicon layer 6 and the n-type amorphous silicon layer 7 to form the electrode 8. Thereby, the photoelectric conversion element 100 of Embodiment 1 is obtained.
  • the generation of dangling bonds due to the extraction of hydrogen atoms is suppressed by the antireflection film 4t, and as a result, the reduction of the minority carrier lifetime of the n-type amorphous silicon layer 3t can be suppressed.
  • the antireflection film 4t exists between the quality silicon layer 5at and the p-type amorphous silicon layer 6t. Therefore, the antireflection film 4t can block the extraction of hydrogen atoms from the n-type amorphous silicon layer 3t to the p-type amorphous silicon layer 6t.
  • the generation of dangling bonds due to the extraction of hydrogen atoms is suppressed by the antireflection film 4t, and as a result, the reduction of the minority carrier lifetime of the n-type amorphous silicon layer 3t can be suppressed.
  • the antireflection film 4 of this embodiment is formed of a SiN film having a positive fixed charge, even if minority carriers of the n-type amorphous silicon layer 3 try to diffuse into the surrounding layers, the antireflection film 4 Due to the repulsive action with the positive positive charge in the medium, a force acts to push the holes back to the n-type semiconductor film side. Therefore, the reduction of the minority carrier lifetime in the n-type amorphous silicon layer 3t can be more effectively suppressed.
  • the thickness of the antireflection film 4 of this embodiment is 100 to 200 nm, it has an effect of suppressing the diffusion of hydrogen atoms from the n-type amorphous silicon layer 3t to the p-type amorphous silicon layer 6t. You can get enough.
  • the n-type amorphous silicon layer 3 is provided on the i-type amorphous silicon layer 2 on the light incident side of the n-type single crystal silicon substrate 1.
  • a p-type amorphous silicon layer may be provided.
  • the n-type amorphous silicon layer 3 or the p-type amorphous silicon layer may be provided as a single layer between the n-type single crystal silicon substrate 1 and the antireflection film 4.
  • the texture structure 1a is provided on the light incident side surface of the n-type single crystal silicon substrate 1, but the texture structure is also provided on the opposite side of the light incident side surface. It may be.
  • the substrate used as the semiconductor substrate is not limited to the n-type single crystal silicon substrate 1, and a p-type single crystal silicon substrate may be used.
  • the substrate used as the semiconductor substrate is not limited to a single crystal silicon substrate, and an n-type or p-type polycrystalline silicon substrate may be used.
  • the texture structure on the light incident side surface can be formed by dry etching.
  • FIG. 3 is a cross-sectional view showing a configuration of a photoelectric conversion element 100A according to Embodiment 2 of the present invention.
  • the photoelectric conversion element 100A according to the second embodiment is different from the photoelectric conversion element 100 according to the first embodiment in that the i-type amorphous silicon layers 5a and 5b are changed to the i-type amorphous silicon layer 5A and the p-type amorphous silicon film 6 is used.
  • the n-type amorphous silicon film 7 is replaced with a p-type amorphous silicon film 6A
  • the electrode 8 is replaced with an electrode 8A and an electrode 9A.
  • the i-type amorphous silicon layer 5A is provided in contact with the surface of the n-type single crystal silicon substrate 1 opposite to the light incident side.
  • the i-type amorphous silicon layer 5A is made of an amorphous phase, and is made of, for example, i-type a-Si.
  • the thickness of the i-type amorphous silicon layer 5A is, for example, 2 to several tens of nm.
  • An i-type amorphous silicon layer 5At is provided in contact with the antireflection film 4t on the side surface 1t of the n-type single crystal silicon substrate 1 and the peripheral edge 1s on the light incident side.
  • the i-type amorphous silicon layer 5At is provided so as to extend from the end face 1t of the n-type single crystal silicon substrate 1 to, for example, about 3 mm in the peripheral portion 1s on the light incident side.
  • the i-type amorphous silicon layer 5At is a part of the i-type amorphous silicon layer 5A.
  • the p-type amorphous silicon layer 6A is formed in contact with the i-type amorphous silicon layer 5A so as to cover the entire surface of the i-type amorphous silicon layer 5A.
  • the p-type amorphous silicon layer 6A is made of an amorphous phase, and is made of, for example, p-type a-Si.
  • the thickness of the p-type amorphous silicon layer 6A is, for example, 3 to several tens of nm.
  • the boron (B) concentration of the p-type amorphous silicon layer 6A is, for example, 1 ⁇ 10 20 to 1 ⁇ 10 22 cm ⁇ 3 .
  • a p-type amorphous silicon layer 6At is provided in contact with the i-type amorphous silicon layer 5At also on the side surface 1t of the n-type single crystal silicon substrate 1 and the peripheral edge 1s on the light incident side.
  • the p-type amorphous silicon layer 6At is a part of the p-type amorphous silicon layer 6A.
  • the electrode 8A is provided in contact with the p-type amorphous silicon layer 6A.
  • the electrode 8A has, for example, a structure in which a transparent conductive film 8a and a metal film 8b are stacked.
  • the electrode 9A is provided in contact with the n-type amorphous silicon layer 3 on the light incident side of the n-type amorphous silicon layer 3 where the antireflection film 4 is not provided.
  • the electrode 9A is made of, for example, silver (Ag).
  • the side surface 1t (region T1 in FIG. 3) of the n-type single crystal silicon substrate 1 is formed in order from the side in contact with the n-type single crystal silicon substrate 1, i-type amorphous silicon layer 2t, n-type amorphous silicon layer 3t, An antireflection film 4t, an i-type amorphous silicon layer 5At, and a p-type amorphous silicon layer 6At are stacked. That is, the antireflection film 4t exists between the i-type amorphous silicon layer 2t and the n-type amorphous silicon layer 3t and the i-type amorphous silicon layer 5At and the p-type amorphous silicon layer 6At. To do.
  • peripheral portion 1s (region T2 in FIG. 3) on the light incident side surface of the n-type single crystal silicon substrate 1 has the same structure as the region T1.
  • (Production method) 4A to 4C are process diagrams showing a method for manufacturing the photoelectric conversion element 100A shown in FIG.
  • an n-type single crystal silicon substrate 1 is prepared as in the first embodiment, and an i-type amorphous silicon layer 2 and an n-type amorphous silicon layer are formed on the light incident side surface. 3 is formed. Further, similarly to the first embodiment, an antireflection film 4 is formed on the n-type amorphous silicon layer 3.
  • an i-type amorphous silicon layer 5A is formed on the back surface of the n-type single crystal silicon substrate 1 by a plasma CVD method.
  • the i-type amorphous silicon layer 5At which is a part of the i-type amorphous silicon layer 5A, wraps around the side surface 1t of the n-type single crystal silicon substrate 1 and the peripheral edge 1s side of the light incident surface to prevent reflection. It is laminated on the film 4t.
  • a p-type amorphous silicon layer 6A is formed on the i-type amorphous silicon layer 5A by a plasma CVD method.
  • the p-type amorphous silicon film 6pt which is a part of the p-type amorphous silicon film 6p, wraps around the side surface 1t of the n-type single crystal silicon substrate 1 and the peripheral edge 1s side of the light incident surface, thereby forming the i-type. It is laminated on the amorphous silicon layer 5At.
  • an electrode 8A is formed by forming a transparent conductive film 8a and a metal film 8b on the p-type amorphous silicon layer 6A. Further, after removing a part of the antireflection film 4, for example, an Ag paste is applied by a screen printing method and then baked to form an electrode 9A on the light incident side of the n-type single crystal silicon substrate 1. Either the electrode 8A or the electrode 9A may be formed first.
  • the i-type amorphous silicon layer 2t and the n-type amorphous silicon layer 3t on the side surface 1t of the n-type single crystal silicon substrate, the i-type amorphous silicon layer 2t and the n-type amorphous silicon layer 3t, the i-type amorphous silicon layer 5At and the p-type amorphous material are used. Since the antireflection film 4t is present between the porous silicon layer 6At and the minority carrier lifetime of the n-type amorphous silicon layer 3t can be suppressed as in the first embodiment.
  • the n-type amorphous silicon layer 3 is provided on the i-type amorphous silicon layer 2 on the light incident side of the n-type single crystal silicon substrate 1, and the i-type amorphous silicon on the opposite side to the light incident side.
  • the p-type amorphous silicon layer 6A is provided on the porous silicon layer 5A.
  • the p-type amorphous silicon layer is provided on the i-type amorphous silicon layer 2, and the opposite side of the light incident side is provided.
  • An n-type amorphous silicon layer may be provided on the i-type amorphous silicon layer 5A.
  • FIG. 5 is a cross-sectional view showing a configuration of a photoelectric conversion element 100B according to Embodiment 3 of the present invention.
  • the photoelectric conversion element 100B according to the third embodiment is similar to the photoelectric conversion element 100 according to the first embodiment except that the i-type amorphous silicon layer 5b and the n-type amorphous silicon layer 7 are provided instead of the n-type single crystal silicon substrate 1.
  • the n-type diffusion region 7B is formed on the surface.
  • n-type diffusion region 7B phosphorus or the like is doped in a portion including the surface opposite to the light irradiation side of the n-type single crystal silicon substrate 1 where the i-type amorphous silicon layer 5a is not provided. Is formed.
  • the phosphorus (P) concentration in the n-type diffusion region 7B is, for example, 5 ⁇ 10 20 cm ⁇ 3 .
  • the electrode 8 has the p-type amorphous silicon layer 6 or the n-type diffusion region 7B, respectively. It is provided in contact with.
  • the photoelectric conversion element 100B when sunlight is irradiated to the photoelectric conversion element 100B from the antireflection film 4 side, electrons and holes are photoexcited in the n-type single crystal silicon substrate 1. The photoexcited holes and electrons are diffused into the p-type amorphous silicon layer 6 and the n-type diffusion region 7B, respectively, thereby generating an electromotive force.
  • the i-type amorphous silicon layer 2t and the n-type amorphous silicon layer 3t are sequentially formed from the side in contact with the n-type single crystal silicon substrate 1.
  • the antireflection film 4t, the i-type amorphous silicon layer 5at, and the p-type amorphous silicon layer 6t are stacked. That is, the antireflection film 4t exists between the i-type amorphous silicon layer 2t and the n-type amorphous silicon layer 3t and the i-type amorphous silicon layer 5at and the p-type amorphous silicon layer 6t.
  • peripheral portion 1s (the region T2 in FIG. 5) on the light incident side surface of the n-type single crystal silicon substrate 1 has the same structure as the region T1.
  • (Production method) 6A to 6G are process diagrams showing a method for manufacturing the photoelectric conversion element 100B shown in FIG.
  • the n-type diffusion region 7B is formed by doping phosphorus on the surface opposite to the light incident side of the n-type single crystal silicon substrate 1 prepared in the same manner as in the first embodiment.
  • the method for doping phosphorus include an ion implantation method, a method of baking a dopant layer or a doping paste, and a method using thermal diffusion.
  • a protective film 30 is formed on the entire surface of the n-type single crystal silicon substrate 1 opposite to the light incident side.
  • the protective film 30 is formed of, for example, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like. Thereby, the surface of the n-type diffusion region 7B is protected.
  • the i-type amorphous silicon layer 2, the n-type amorphous silicon layer 3, and the reflection are formed on the light incident side of the n-type single crystal silicon substrate 1.
  • the prevention film 4 is sequentially formed by a plasma CVD method.
  • portions of the protective layer 30 on the side opposite to the light incident side of the n-type single crystal silicon substrate 1 other than the portion in contact with the n-type diffusion region 7B are removed by etching.
  • the i-type amorphous silicon layer 5ap and the p-type amorphous silicon layer 6p are formed on the back surface of the n-type single crystal silicon substrate 1 as in the first embodiment.
  • the protective layer 30, and the i-type amorphous silicon layer 5ap and the p-type amorphous silicon layer 6p as the upper layer are removed.
  • a method for removing the i-type amorphous silicon layer 5ap and the p-type amorphous silicon layer 6p is dry etching. Thereby, the i-type amorphous silicon layer 5a and the p-type amorphous silicon layer 6 are formed on the back surface of the n-type single crystal silicon substrate 1.
  • electrodes 8 are formed in the same manner as in the first embodiment so as to correspond to the p-type amorphous silicon layer 6 and the n-type diffusion region 7B, respectively. Thereby, the photoelectric conversion element 100B of Embodiment 3 is obtained.
  • the i-type amorphous silicon layer 2t and the n-type amorphous silicon layer 3t on the side surface 1t of the n-type single crystal silicon substrate, the i-type amorphous silicon layer 2t and the n-type amorphous silicon layer 3t, the i-type amorphous silicon layer 5at and the p-type amorphous material are used. Since the antireflection film 4t exists between the porous silicon layer 6t and the first exemplary embodiment, the minority carrier lifetime of the n-type amorphous silicon layer 3t can be prevented from being reduced, as in the first embodiment.
  • the n-type amorphous silicon layer 3 is provided on the i-type amorphous silicon layer 2 on the light incident side of the n-type single crystal silicon substrate 1. 2 may be provided, and the n-type amorphous silicon layer 3 may be provided in contact with the surface on the light incident side of the n-type single crystal silicon substrate 1.
  • the fourth embodiment is a photoelectric conversion module including at least one of the photoelectric conversion elements of the first to third embodiments and the modifications thereof.
  • FIG. 7 is a schematic diagram illustrating an example of the configuration of the photoelectric conversion module according to the present embodiment.
  • the photoelectric conversion module 1000 includes a plurality of photoelectric conversion elements 1001, a cover 1002, and output terminals 1013 and 1014.
  • a plurality of photoelectric conversion elements 1001 are arranged in an array and connected in series.
  • FIG. 7 illustrates an arrangement in which the photoelectric conversion elements 1001 are connected in series.
  • the arrangement and connection method are not limited to this, and the photoelectric conversion elements 1001 may be connected in parallel or may be combined in series and parallel. It is good also as an arrangement.
  • any one of the first to third embodiments and the photoelectric conversion elements of the modified examples is used.
  • the photoelectric conversion module 1000 is not limited to the above description as long as at least one of the plurality of photoelectric conversion elements 1001 includes any of the photoelectric conversion elements according to the first to third embodiments and modifications thereof, and may take any configuration. Shall. Further, the number of photoelectric conversion elements 1001 included in the photoelectric conversion module 1000 can be any integer of 2 or more.
  • the cover 1002 is composed of a weatherproof cover and covers the plurality of photoelectric conversion elements 1001.
  • the cover 1002 includes, for example, a transparent base material (for example, glass) provided on the light receiving surface side of the photoelectric conversion element 1001 and a back surface base material provided on the back surface side opposite to the light receiving surface side of the photoelectric conversion element 1001. (For example, glass, a resin sheet etc.) and the sealing material (for example, EVA etc.) which fills the clearance gap between the said transparent base material and the said resin base material.
  • a transparent base material for example, glass
  • a back surface base material provided on the back surface side opposite to the light receiving surface side of the photoelectric conversion element 1001.
  • the sealing material for example, EVA etc.
  • the output terminal 1013 is connected to a photoelectric conversion element 1001 arranged at one end of a plurality of photoelectric conversion elements 1001 connected in series.
  • the output terminal 1014 is connected to the photoelectric conversion element 1001 arranged at the other end of the plurality of photoelectric conversion elements 1001 connected in series.
  • the fifth embodiment is a photovoltaic power generation system including at least one of the photoelectric conversion elements of the first to third embodiments and the modifications thereof. Since the photoelectric conversion element of the present invention has high conversion efficiency, the photovoltaic power generation system of the present invention including the photoelectric conversion element can also have high conversion efficiency. Note that the solar power generation system is a device that appropriately converts the power output from the photoelectric conversion module and supplies the converted power to a commercial power system or an electric device.
  • FIG. 8 is a schematic diagram illustrating an example of the configuration of the photovoltaic power generation system according to the present embodiment.
  • the photovoltaic power generation system 2000 includes a photoelectric conversion module array 2001, a connection box 2002, a power conditioner 2003, a distribution board 2004, and a power meter 2005.
  • the photoelectric conversion module array 2001 includes a plurality of photoelectric conversion modules 1000 (Embodiment 4). Since the photoelectric conversion element of the present invention has high conversion efficiency, the photovoltaic power generation system of the present invention including the photoelectric conversion element can also have high conversion efficiency.
  • the solar power generation system 2000 is added with a function generally called “Home Energy Management System (HEMS)”, “Building Energy Management System (BEMS)”, or the like. can do. Accordingly, the energy consumption can be reduced by monitoring the power generation amount of the solar power generation system 2000, monitoring / controlling the power consumption amount of each electrical device connected to the solar power generation system 2000, and the like.
  • HEMS Home Energy Management System
  • BEMS Building Energy Management System
  • connection box 2002 is connected to the photoelectric conversion module array 2001.
  • the power conditioner 2003 is connected to the connection box 2002.
  • the distribution board 2004 is connected to the power conditioner 2003 and the electrical equipment 2011.
  • the power meter 2005 is connected to the distribution board 2004 and the commercial power system.
  • a storage battery 2100 may be connected to the power conditioner 2003 as shown in FIG. In this case, output fluctuation due to fluctuations in the amount of sunlight can be suppressed, and power stored in the storage battery 2100 can be supplied even in a time zone without sunlight.
  • the storage battery 2100 may be built in the power conditioner 2003.
  • the photoelectric conversion module array 2001 converts sunlight into electricity to generate DC power and supplies the DC power to the connection box 2002.
  • the power conditioner 2003 converts the DC power received from the connection box 2002 into AC power and supplies it to the distribution board 2004. Note that part or all of the DC power received from the connection box 2002 may be supplied to the distribution board 2004 as it is without being converted to AC power.
  • the power conditioner 2003 receives the direct current received from the connection box 2002. A part or all of the electric power can be appropriately converted into electric power and stored in the storage battery 2100.
  • the power stored in the storage battery 2100 is appropriately supplied to the power conditioner 2003 according to the amount of power generated by the photoelectric conversion module and the power consumption of the electrical equipment 2011, and is appropriately converted to the distribution board 2004. Supplied.
  • the distribution board 2004 supplies the electric equipment 2011 with at least one of the electric power received from the power conditioner 2003 and the commercial electric power received via the electric power meter 2005.
  • the distribution board 2004 supplies the AC power received from the power conditioner 2003 to the electrical equipment 2011 when the AC power received from the power conditioner 2003 is larger than the power consumption of the electrical equipment 2011. Then, surplus AC power is supplied to the commercial power system via the power meter 2005.
  • the distribution board 2004 receives the AC power received from the commercial power system and the AC power received from the power conditioner 2003 in the electrical equipment. To 2011.
  • the power meter 2005 measures the power in the direction from the commercial power system to the distribution board 2004 and measures the power in the direction from the distribution board 2004 to the commercial power system.
  • the photoelectric conversion module array 2001 will be described.
  • FIG. 10 is a schematic diagram showing an example of the configuration of the photoelectric conversion module array 2001 shown in FIG.
  • the photoelectric conversion module array 2001 includes a plurality of photoelectric conversion modules 1000 and output terminals 2013 and 2014.
  • FIG. 10 illustrates an arrangement in which the photoelectric conversion modules 1000 are connected in series.
  • the arrangement and connection method are not limited to this, and the photoelectric conversion modules 1000 may be connected in parallel or may be combined in series and parallel. It is good also as an arrangement.
  • the number of photoelectric conversion modules 1000 included in the photoelectric conversion module array 2001 can be any integer of 2 or more.
  • the output terminal 2013 is connected to the photoelectric conversion module 1000 located at one end of the plurality of photoelectric conversion modules 1000 connected in series.
  • the output terminal 2014 is connected to the photoelectric conversion module 1000 located at the other end of the plurality of photoelectric conversion modules 1000 connected in series.
  • At least one of the plurality of photoelectric conversion elements 1001 includes any of the photoelectric conversion elements of Embodiments 1 to 3 and its modifications. As long as it is not limited to the above description, any configuration can be used.
  • the sixth embodiment is a larger-scale solar power generation system than the solar power generation system described as the fifth embodiment.
  • the photovoltaic power generation system according to the sixth embodiment also includes at least one of the photoelectric conversion elements of the first to third embodiments and the modifications thereof. Since the photoelectric conversion element of the present invention has high conversion efficiency, the photovoltaic power generation system of the present invention including the photoelectric conversion element can also have high conversion efficiency.
  • FIG. 11 is a schematic diagram illustrating an example of the configuration of the photovoltaic power generation system according to the present embodiment.
  • solar power generation system 4000 includes a plurality of subsystems 4001, a plurality of power conditioners 4003, and a transformer 4004.
  • the photovoltaic power generation system 4000 is a larger scale photovoltaic power generation system than the photovoltaic power generation system 2000 shown in FIG. Since the photoelectric conversion element of the present invention has high conversion efficiency, the photovoltaic power generation system of the present invention including the photoelectric conversion element can also have high conversion efficiency.
  • the plurality of power conditioners 4003 are each connected to the subsystem 4001.
  • the number of the power conditioners 4003 and the subsystems 4001 connected thereto can be any integer of 2 or more.
  • a storage battery 4100 may be connected to the power conditioner 4003 as shown in FIG. In this case, output fluctuation due to fluctuations in the amount of sunshine can be suppressed, and power stored in the storage battery 4100 can be supplied even in a time zone without sunshine.
  • the storage battery 4100 may be built in the power conditioner 4003.
  • the transformer 4004 is connected to a plurality of power conditioners 4003 and a commercial power system.
  • Each of the plurality of subsystems 4001 includes a plurality of module systems 3000.
  • the number of module systems 3000 in the subsystem 4001 can be any integer greater than or equal to two.
  • Each of the plurality of module systems 3000 includes a plurality of photoelectric conversion module arrays 2001, a plurality of connection boxes 3002, and a current collection box 3004.
  • the number of the junction box 3002 in the module system 3000 and the photoelectric conversion module array 2001 connected to the junction box 3002 can be any integer of 2 or more.
  • the current collection box 3004 is connected to a plurality of connection boxes 3002.
  • the power conditioner 4003 is connected to a plurality of current collection boxes 3004 in the subsystem 4001.
  • the plurality of photoelectric conversion module arrays 2001 of the module system 3000 convert sunlight into electricity to generate DC power, and supply the DC power to the current collecting box 3004 via the connection box 3002.
  • a plurality of current collection boxes 3004 in the subsystem 4001 supplies DC power to the power conditioner 4003.
  • the plurality of power conditioners 4003 convert DC power into AC power and supply the AC power to the transformer 4004.
  • the power conditioner 4003 is received from the current collection box 3004. A part or all of the DC power can be appropriately converted into power and stored in the storage battery 4100.
  • the electric power stored in the storage battery 4100 is appropriately supplied to the power conditioner 4003 side according to the power generation amount of the subsystem 4001, appropriately converted into electric power, and supplied to the transformer 4004.
  • the transformer 4004 converts the voltage level of AC power received from a plurality of power conditioners 4003 and supplies it to the commercial power system.
  • the solar power generation system 4000 only needs to include at least one of the photoelectric conversion elements of the first to third embodiments and the modifications thereof, and all the photoelectric conversion elements included in the solar power generation system 4000 are the first embodiment. It is not necessary to be a photoelectric conversion element of .about.
  • all of the photoelectric conversion elements included in a certain subsystem 4001 are any of the photoelectric conversion elements of Embodiments 1 to 3 and modifications thereof, and some or all of the photoelectric conversion elements included in another subsystem 4001
  • the present invention is useful for photoelectric conversion elements.

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  • Photovoltaic Devices (AREA)

Abstract

Selon l'invention, un élément de conversion photoélectrique (100) qui convertit une lumière en énergie électrique, est équipé : d'un substrat de silicium monocristallin de type n (1) (substrat semi-conducteur) ; d'une couche de silicium amorphe de type i (2) possédant une conductivité de type n ainsi que d'une couche de silicium amorphe de type n (3) (premier film semi-conducteur) formées par contact avec une surface côté incidence de lumière du substrat de silicium monocristallin de type n (1) ; d'un film anti réflexion (4) (film diélectrique) formé par contact avec le premier film semi-conducteur ; et d'un second film semi-conducteur possédant une conductivité de type p (couche de silicium amorphe de type i (5a) et couche de silicium amorphe de type p (6)) formé côté opposé au côté incidence de lumière du substrat de silicium monocristallin de type n (1). Sur une face latérale (1t) du substrat de silicium monocristallin de type n (1), sont stratifiés dans l'ordre des premiers films semi-conducteurs (2t, 3t), un film anti réflexion (4t) et des seconds films semi-conducteurs (5at, 6t).
PCT/JP2015/064017 2014-05-23 2015-05-15 Élément de conversion photoélectrique Ceased WO2015178307A1 (fr)

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
WO2017150104A1 (fr) * 2016-03-04 2017-09-08 シャープ株式会社 Élément de conversion photoélectrique et module de conversion photoélectrique

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JPH09129904A (ja) * 1995-10-26 1997-05-16 Sanyo Electric Co Ltd 光起電力素子およびその製造方法
JP2001044461A (ja) * 1999-07-26 2001-02-16 Sanyo Electric Co Ltd 光起電力素子及びその製造方法
JP2011060971A (ja) * 2009-09-09 2011-03-24 Kaneka Corp 結晶シリコン太陽電池及びその製造方法
JP2011187904A (ja) * 2010-03-11 2011-09-22 Mitsubishi Electric Corp 太陽電池の製造方法
WO2013153950A1 (fr) * 2012-04-13 2013-10-17 ナガセケムテックス株式会社 Composition de dispersant de revêtement, procédé de fabrication de composition de dispersant de revêtement, cellule solaire et procédé de fabrication de cellule solaire
EP2682990A1 (fr) * 2012-07-02 2014-01-08 Roth & Rau AG Cellule solaire à hétérojonction avec isolation de bords et son procédé de fabrication

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Publication number Priority date Publication date Assignee Title
JPH09129904A (ja) * 1995-10-26 1997-05-16 Sanyo Electric Co Ltd 光起電力素子およびその製造方法
JP2001044461A (ja) * 1999-07-26 2001-02-16 Sanyo Electric Co Ltd 光起電力素子及びその製造方法
JP2011060971A (ja) * 2009-09-09 2011-03-24 Kaneka Corp 結晶シリコン太陽電池及びその製造方法
JP2011187904A (ja) * 2010-03-11 2011-09-22 Mitsubishi Electric Corp 太陽電池の製造方法
WO2013153950A1 (fr) * 2012-04-13 2013-10-17 ナガセケムテックス株式会社 Composition de dispersant de revêtement, procédé de fabrication de composition de dispersant de revêtement, cellule solaire et procédé de fabrication de cellule solaire
EP2682990A1 (fr) * 2012-07-02 2014-01-08 Roth & Rau AG Cellule solaire à hétérojonction avec isolation de bords et son procédé de fabrication

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Publication number Priority date Publication date Assignee Title
WO2017150104A1 (fr) * 2016-03-04 2017-09-08 シャープ株式会社 Élément de conversion photoélectrique et module de conversion photoélectrique

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