WO2015170533A1 - Solid-state image pickup device, driving method for solid-state image pickup device, and electronic apparatus - Google Patents

Abstract

A solid-state image pickup device of the disclosure of the present invention comprises: a first charge accumulating unit; a transfer gate unit having a plurality of gate electrodes which transfer the charge of the first charge accumulating unit; a second charge accumulating unit that accumulates the charge transferred by the transfer gate unit; and overflow paths formed between the first charge accumulating unit and the second charge accumulating unit. The overflow path below the gate electrode on the transfer gate unit first charge accumulating section side is formed at a depth so as to not be impacted by transfer gate unit modulation within a bulk, and the overflow path below the gate electrode on the transfer gate unit second charge accumulating section side is formed at a depth so as to be impacted by transfer gate unit modulation near a substrate interface.

Description

Solid-state imaging device, driving method of solid-state imaging device, and electronic apparatus

The present disclosure relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device.

In a solid-state image pickup device, for example, an XY address type solid-state image pickup device represented by a CMOS image sensor, as a shutter method of an electronic shutter function, exposure is performed for each pixel row with respect to pixels arranged in a two-dimensional matrix. A rolling shutter system for setting start and end has been used. However, unlike a global shutter type solid-state imaging device that exposes all pixels at the same timing, a rolling shutter type solid-state imaging device is distorted in the captured image because the exposure period is different for each pixel row. Occurs. The global shutter system is employed in a charge transfer type solid-state imaging device represented by a CCD image sensor.

In a solid-state imaging device such as a CMOS image sensor, a global shutter is realized by matching the exposure period for all pixel rows using a mechanical shutter in order to eliminate the above-described problems of the rolling shutter. . Specifically, by simultaneously resetting each pixel in all pixel rows in the open state of the mechanical shutter, signal charge accumulation is started simultaneously for all pixels. Then, the exposure is terminated by closing the mechanical shutter. Signals are read from the pixels one row after the end of exposure. According to this series of operations, since the exposure periods of all the pixel rows match, the captured image is not distorted.

However, when a global shutter is realized using a mechanical shutter, the amount of charge accumulated in each pixel after the mechanical shutter is closed until the signal of each pixel is read out in order, The number of pixels to be read decreases, that is, the saturation charge amount decreases. In the prior art, this reduction of the saturation charge amount is prevented as follows. That is, when the pixel reset transistor is switched from on to off, the potential of the FD portion (floating diffusion portion) is lowered, the potential under the transfer gate portion is made shallow by capacitive coupling at that time, and an overflow path provided under the transfer gate portion Is driven in the closing direction (see, for example, Patent Document 1).

JP 2010-177838 A

In the prior art described in Patent Document 1 described above, since the capacitive coupling when lowering the potential of the FD section is used to drive the overflow path in the closing direction, it is difficult to control the modulation of the overflow barrier. Also, when creating an overflow path under the transfer gate, an overflow path is created in the bulk with holes accumulated in the interface in order to prevent the occurrence of leakage current due to the interface state. Become. In that case, even if the potential of the transfer gate part is further lowered after the hole accumulation, it is difficult to control the potential of the overflow path in the bulk only by increasing the hole concentration in the vicinity of the interface. Therefore, the decrease in the saturation charge amount when using the mechanical shutter cannot be sufficiently suppressed.

The present disclosure provides a solid-state imaging device capable of sufficiently suppressing a decrease in saturation charge amount when using a mechanical shutter while preventing the occurrence of a leakage current due to an interface state, a driving method of the solid-state imaging device, and An object is to provide an electronic apparatus using the solid-state imaging device.

In order to achieve the above object, a solid-state imaging device of the present disclosure includes:
A first charge storage unit;
A transfer gate portion having a plurality of gate electrodes for transferring the charge of the first charge storage portion;
A second charge accumulating unit for accumulating charges transferred by the transfer gate unit;
An overflow path formed between the first charge storage unit and the second charge storage unit;
With
The overflow path under the gate electrode on the first charge storage portion side of the transfer gate portion is formed at a depth not affected by the modulation of the transfer gate portion in the bulk,
An overflow path under the gate electrode on the second charge storage portion side of the transfer gate portion is formed at a depth affected by the modulation of the transfer gate portion in the vicinity of the substrate interface.

In order to achieve the above object, a method for driving a solid-state imaging device according to the present disclosure includes
In driving the solid-state imaging device having the above configuration,
At the time of charge accumulation in the first charge accumulation unit, a gate voltage having a voltage value that closes the transfer channel is applied to the gate electrode on the first charge accumulation unit side, and an overflow path is formed on the gate electrode on the second charge accumulation unit side. Apply the gate voltage of the open voltage value,
In the period from the end of accumulation of the first charge accumulation unit to the start of transfer to the second charge accumulation unit, a gate voltage of a voltage value that closes the transfer channel is applied to the gate electrode on the first charge accumulation unit side, A gate voltage having a voltage value at which the overflow path is closed is applied to the gate electrode on the second charge storage portion side.
In addition, the electronic device of the present disclosure is
A solid-state imaging device having the above configuration;
A mechanical shutter that selectively takes incident light and guides it to the light receiving surface of the solid-state imaging device;
It comprises.

In the solid-state imaging device in which the overflow path is formed under the transfer gate portion, the overflow path under the gate electrode on the first charge storage portion side is formed to a depth that is not affected by the modulation of the transfer gate portion in the bulk. To do. Furthermore, an overflow path under the gate electrode on the second charge storage portion side is formed at a depth that is affected by the modulation of the transfer gate portion near the substrate interface. By doing so, it is possible to suppress a decrease in the saturation charge amount during the period from the accumulation of signal charges to the transfer.

According to the present disclosure, it is possible to suppress a decrease in the amount of saturation charge during a period from signal charge accumulation to transfer, and therefore, it is possible to prevent the occurrence of leakage current due to the interface state while using the mechanical shutter. A decrease in the amount of saturation charge can be sufficiently suppressed.
The effects described here are not necessarily limited, and any of the effects described in the present specification may be used. Moreover, the effect described in this specification is an illustration to the last, Comprising: It is not limited to this, There may be an additional effect.

FIG. 1 is a system configuration diagram illustrating an outline of a configuration of a CMOS image sensor to which the technology of the present disclosure is applied. FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of a unit pixel. FIG. 3 is a diagram schematically illustrating a cross section of a part of a unit pixel and a potential of the part for explaining the related art, and FIG. 3A shows a saturated state immediately after the mechanical shutter is closed, FIG. 3B shows a saturated state after the mechanical shutter is closed and before signal reading. 4A and 4B are diagrams for describing a CMOS image sensor according to an embodiment of the present disclosure. FIG. 4A illustrates a cross-sectional structure of the pixel and an overflow path, and FIG. 4B illustrates opening / closing timing of the mechanical shutter and driving timing of the pixel. Is shown. FIG. 5 is a diagram for explaining a pixel structure in which the gate electrode of the transfer gate portion is one. FIG. 5A shows a cross-sectional structure of a pixel having an overflow path in the bulk, and FIG. 5B shows an overflow path near the substrate interface. FIG. 5C shows the opening / closing timing of the mechanical shutter and the driving timing of the pixel. FIG. 6 is a cross-sectional view for explaining driving of the pixel structure according to the first embodiment. FIG. 6A shows a cross-sectional structure and a state at the time of charge accumulation, and FIG. 6B shows a cross-sectional structure and a state while waiting for transfer. FIG. 6C shows a cross-sectional structure and state at the time of charge transfer. FIG. 7 is an explanatory diagram of the pixel structure according to the second embodiment. FIG. 7A shows the opening / closing timing of the mechanical shutter and the driving timing of the pixel, and FIG. 7B shows the cross-sectional structure and state during charge accumulation. FIG. 7C shows a cross-sectional structure and state while waiting for transfer. FIG. 8 is a diagram illustrating the opening / closing timing of the mechanical shutter and the driving timing of the pixel in the pixel structure according to the third embodiment. FIG. 9 is a cross-sectional structure diagram illustrating the pixel structure according to the fourth embodiment. FIG. 9A illustrates the pixel structure 1 and the overflow path according to the fourth embodiment. FIG. 9B illustrates the pixel structure 2 according to the fourth embodiment. Indicates an overflow path. FIG. 10 is an explanatory diagram of a hole accumulation type pixel in which the P channel / N channel of FIG. 4A is inverted. FIG. 10A shows a pixel structure and an overflow path, and FIG. 10B shows opening / closing of the mechanical shutter. The timing and the drive timing of the pixel are shown. FIG. 11 is a system configuration diagram illustrating an outline of a configuration of the electronic device of the present disclosure.

Hereinafter, modes for carrying out the technology of the present disclosure (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. The technology of the present disclosure is not limited to the embodiments, and various numerical values in the embodiments are examples. In the following description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted. The description will be given in the following order.
1. 1. General description of the solid-state imaging device of the present disclosure, a driving method thereof, and an electronic apparatus Solid-state imaging device to which the technology of the present disclosure is applied (example of a CMOS image sensor)
3. 3. Description of prior art 4. Description of embodiments of the present disclosure Modification 6 Electronic device of the present disclosure (example of a digital still camera)

<Description of Solid-State Imaging Device of the Present Disclosure, Method for Driving the Same, and Electronic Device>
In the solid-state imaging device, the driving method thereof, and the electronic device of the present disclosure, the first charge accumulation unit may be a photoelectric conversion unit that converts incident light into electric charge and accumulates it. Further, the second charge accumulation unit can be an FD unit (floating diffusion unit).

In the solid-state imaging device of the present disclosure including the preferred configuration and configuration described above, the driving method thereof, and the electronic apparatus, the second charge accumulation unit side of the transfer gate unit after the charge accumulation of the first charge accumulation unit The gate voltage applied to the gate electrode can be set to a voltage value at which the overflow path is closed more than the voltage value applied during charge accumulation. In addition, the voltage value on the side where the transfer channel is closed is applied to both the gate electrode on the first charge accumulation unit side and the gate electrode on the second charge accumulation unit side during the charge accumulation in the first charge accumulation unit. It can be. At this time, it is preferable that the voltage value on the side where the overflow path of the gate voltage applied to the gate electrode on the second charge storage unit side is closed can be adjusted.

Further, in the solid-state imaging device of the present disclosure including the above-described preferable configuration and form, the driving method thereof, and the electronic device, the gate electrode on the first charge storage unit side and the gate on the second charge storage unit side The voltage value on the side where the transfer channel of the gate voltage applied to each electrode opens can be different. At this time, it is preferable that the voltage value on the side where the overflow path of the gate voltage applied to the gate electrode on the second charge storage unit side is open can be adjusted.

Alternatively, in the solid-state imaging device of the present disclosure including the above-described preferable configuration and configuration, the driving method thereof, and the electronic apparatus, the transfer gate unit including at least one gate electrode of the plurality of gate electrodes is embedded. It is possible to employ a configuration comprising the following transistors. Furthermore, the first charge storage unit can be configured to store signal charges based on light incident through the mechanical shutter.

<Solid-State Imaging Device to which Technology of Present Disclosure is Applied>
FIG. 1 is a system configuration diagram illustrating an outline of a configuration of a solid-state imaging device to which the technology of the present disclosure is applied. Here, as a solid-state imaging device, for example, a CMOS image sensor which is an example of an XY address type solid-state imaging device will be described.

As shown in FIG. 1, a CMOS image sensor 10 according to this application example includes a pixel array unit 12 formed on a semiconductor substrate (chip) 11 and a peripheral integrated on the same chip 11 as the pixel array unit 12. And a circuit portion. As the peripheral circuit unit, for example, a vertical drive unit 13, a column processing unit 14, a horizontal drive unit 15, an output circuit unit 16, and a system control unit 17 are provided.

1, unit pixels (not shown) (hereinafter sometimes simply referred to as “pixels”) are two-dimensionally arranged in a matrix in the pixel array section 12. The unit pixel includes a photoelectric conversion unit (photoelectric conversion element) that photoelectrically converts visible light incident on the light receiving surface (imaging surface) and accumulates signal charges (photocharges) having a charge amount corresponding to the amount of light. A specific configuration of the unit pixel will be described later.

The pixel array section 12 is further provided with pixel drive lines 121 for each pixel row along the horizontal direction (row direction / horizontal direction) in the figure with respect to the matrix pixel arrangement, and the vertical signal line 122 for each pixel column. Are wired in the vertical direction (column direction / vertical direction) in the figure. In FIG. 1, the pixel drive line 121 is illustrated as one wiring for each pixel row, but the number is not limited to one. One end of the pixel drive line 121 is connected to an output end corresponding to each pixel row of the vertical drive unit 13.

The vertical drive unit 13 is configured by a shift register, an address decoder, or the like, and is a pixel drive unit that drives each pixel of the pixel array unit 12 at the same time or in units of rows. Although the vertical drive unit 13 is not shown in detail with respect to its specific configuration, the vertical drive unit 13 generally has two scanning systems, a reading scanning system and a sweeping scanning system. The readout scanning system selectively scans the unit pixels of the pixel array unit 12 sequentially in units of rows in order to read out signals from the unit pixels. The sweep-out scanning system performs sweep-out scanning with respect to the readout row on which readout scanning is performed by the readout scanning system, preceding the readout scanning by a time corresponding to the shutter speed.

Unnecessary charges are swept out (reset) from the photoelectric conversion unit of the unit pixel in the swept row by the sweep scanning by the sweep scanning system. A so-called electronic shutter operation is performed by sweeping (reset) unnecessary charges by the sweep scanning system. Here, the electronic shutter operation refers to an operation of discarding the photocharge accumulated in the photoelectric conversion element and newly starting exposure (accumulation of signal charge). The signal read by the reading operation by the reading scanning system corresponds to the amount of light incident after the immediately preceding reading operation or electronic shutter operation. The period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the photocharge accumulation period (exposure period) in the unit pixel.

A signal output from each unit pixel in the pixel row selectively scanned by the vertical driving unit 13 is supplied to the column processing unit 14 through each vertical signal line 122. The column processing unit 14 performs predetermined signal processing on a signal output from each unit pixel in the selected row through the vertical signal line 122 for each pixel column of the pixel array unit 12 and outputs a pixel signal after the signal processing. Hold temporarily.

Specifically, the column processing unit 14 receives the signal of each unit pixel, and for example, removes noise by CDS (Correlated Double Sampling), signal amplification, AD (analog), etc. -Perform signal processing such as digital) conversion. By the noise removal processing, fixed pattern noise unique to the pixel such as reset noise and variation in threshold value of the amplification transistor is removed. The signal processing illustrated here is only an example, and the signal processing is not limited to these.

The horizontal drive unit 15 includes a shift register, an address decoder, and the like, and selects unit circuits corresponding to the pixel columns of the column processing unit 14 in order. By the selective scanning by the horizontal drive unit 15, the pixel signals subjected to signal processing for each unit circuit by the column processing unit 14 are sequentially output to the horizontal bus 18 and transmitted to the output circuit unit 16 by the horizontal bus 18.

The output circuit unit 16 processes and outputs a signal transmitted by the horizontal bus 18. As processing in the output circuit unit 16, there may be processing only for buffering, or various digital signal processing such as adjusting the black level before buffering or correcting variation for each pixel column. Is mentioned.

The system control unit 17 receives a clock given from the outside of the chip 11, data for instructing an operation mode, and the like, and outputs data such as internal information of the CMOS image sensor 10. The system control unit 17 further includes a timing generator that generates various timing signals, and the vertical driving unit 13, the column processing unit 14, and the horizontal driving unit 15 based on the various timing signals generated by the timing generator. The drive control of peripheral circuit units such as is performed.

In the peripheral portion of the chip 11, input / output terminal groups 19A and 19B including power supply terminals are provided. The input / output terminal groups 19A and 19B exchange power supply voltages and signals between the inside and the outside of the chip 11. The arrangement positions of the input / output terminal groups 19A and 19B are determined to be convenient positions in consideration of the direction in which signals are input and the direction in which signals are output.

(Circuit configuration of unit pixel)
FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of the unit pixel 20. As illustrated in FIG. 2, the unit pixel 20 according to this circuit example includes, for example, a photodiode 21 as a photoelectric conversion unit (photoelectric conversion element). In addition to the photodiode 21, the unit pixel 20 has a configuration including three transistors, for example, a transfer transistor 22, a reset transistor 23, and an amplification transistor 24.

Here, as the three transistors 22 to 24, for example, N-channel MOS transistors are used. However, the combination of the conductivity types of the transfer transistor 22, the reset transistor 23, and the amplification transistor 24 illustrated here is only an example, and is not limited to these combinations.

For the unit pixel 20, as the pixel drive line 121, for example, three drive lines including a transfer line _{121_1} , a reset line _{121_2} , and a selection line _{121_3} are provided in common for each pixel in the same pixel row. Yes.

From the vertical driving unit 13 to the transfer wiring 121 _{- 1} and the reset wiring 121 _{_2,} the transfer signal TRG and the reset signal RST high level is active are given respectively. In addition, the selection wiring 121 _{_3,} selection power SEL_V _dd taking two power supply voltages of the power supply voltage and V _dd to 0.8V as low voltage selectively is provided.

The photodiode 21 has an anode electrode connected to a power source (for example, ground) on the low potential side, and photoelectrically converts received light into photocharge (here, photoelectrons) having a charge amount corresponding to the light amount. The cathode electrode of the photodiode 21 is electrically connected to the gate electrode of the amplification transistor 24 through the transfer transistor 22.

Hereinafter, the node 25 electrically connected to the gate electrode of the amplification transistor 24 is referred to as an FD portion (floating diffusion portion). That is, the FD portion 25 is a node including a diffusion layer corresponding to the drain region of the transfer transistor 22, the gate electrode of the amplification transistor 24, and a wiring connecting them, and has a parasitic capacitance.

The transfer transistor 22 is connected between the cathode electrode of the photodiode 21 and the FD unit 25. The transfer transistor 22 becomes conductive when a transfer signal TRG is applied to the gate electrode via the transfer wiring _{121_1} , and the photoelectric charge photoelectrically converted by the photodiode 21 is transferred to the FD portion 25.

The reset transistor 23 has the FD portion 25 as one main electrode, and the other main electrode is connected to the selection wiring _{121_3} . In the case of this example, one main electrode becomes a source electrode, and the other main electrode becomes a drain electrode. Reset transistor 23 at its gate electrode, a conductive state by the reset signal RST is provided via the reset line 121 _{- 2,} and resets the FD portion 25 by discarding the charge of the FD portion 25 to the selection wiring 121 _{_3.} The reset of the FD unit 25 becomes the reset of the unit pixel 20.

The amplification transistor 24 has a gate electrode connected to the FD portion 25, a drain electrode connected to the power supply wiring of the power supply voltage _Vdd , and a source electrode connected to the vertical signal line 122. Then, the amplification transistor 24 outputs the potential of the FD unit 25 after being reset by the reset transistor 23 to the vertical signal line 122 as a reset signal (reset level). Further, the amplification transistor 24 outputs the potential of the FD section 25 after the transfer of the photocharge by the transfer transistor 22 to the vertical signal line 122 as a light accumulation signal (signal level).

In the pixel circuit having the above configuration, a large number of pixels 20 are connected to the vertical signal line 122, but the FD unit 25 is set to a low voltage for a pixel from which a signal is not read (non-selected). Then, by setting the FD unit 25 to a voltage sufficiently higher than that of the non-selected pixels only for the pixel from which the signal is read (selected), only the signal of the selected pixel can be output to the vertical signal line 122.

Specifically, using the selected power supply SEL_V _dd and the reset transistor 23, the FD unit 25 is set to a low voltage (for example, a low level of about 0.8 V) for the non-selected pixels, and the FD unit is used for the selected pixels. 25 is set to a high voltage (eg, V _dd level). Thereby, the selection of the pixels 20 can be performed in units of rows.

In the CMOS image sensor 10 having the general system configuration described above, a rolling shutter (also referred to as a focal plane shutter) that sets the start and end of exposure for each pixel row is performed as an electronic shutter. However, in the rolling shutter, the captured image is distorted because the exposure period is different for each pixel row.

In order to eliminate the problem of the distortion of the captured image that occurs due to the difference in the exposure period for each pixel row, the CMOS image sensor 10 having the above configuration selectively blocks light incident on the imaging surface. Used in combination with a mechanical shutter. By realizing a global shutter using a mechanical shutter, it is possible to match the exposure period for all the pixel rows, so that the captured image can be prevented from being distorted.

However, in the CMOS image sensor 10, when a global shutter is realized using a mechanical shutter, the amount of charge accumulated in each pixel is sequentially increased between the time when the mechanical shutter is closed and the signal of each pixel is read. In addition, the pixels to be read later are reduced, that is, the saturation charge amount is reduced. The reason is as follows.

When electrons overflow from the photodiode 21 to the photodiode 21 of the adjacent pixel, a false signal called blooming is generated. Therefore, each pixel is provided with an overflow path for discarding photoelectrons exceeding a predetermined saturation charge amount. However, a part of the photoelectrons accumulated in the photodiode 21 until the signal of each pixel is read out through the overflow path as a subthreshold current due to thermal excitation. Thereby, the number of electrons in the photodiode 21 decreases. The period from when the mechanical shutter is closed until the signal of each pixel is read out is short in the first row of signal readout, but becomes longer as it goes to the last row. Accordingly, the loss of photoelectrons increases near the last row, and the dynamic range is shortened.

<Description of prior art>
In the prior art, in the CMOS image sensor 10 in which the overflow path is provided below the gate electrode of the transfer transistor 22, the reset transistor of the pixel 20 is used to prevent a decrease in the saturation charge amount when the mechanical shutter is used. When 23 shifts from the on state to the off state, the potential of the FD section 25 is lowered. As the potential of the FD portion 25 changes, the potential of the overflow path under the gate electrode of the transfer transistor 22 is modulated.

Specifically, modulation is performed by capacitive coupling due to parasitic capacitance C interposed between the channel under the gate electrode of the transfer transistor 22 and the diffusion layer of the FD portion 25 (a diffusion layer corresponding to the drain region of the transfer transistor 22). In response, the potential of the channel under the gate electrode becomes shallow, and the overflow path moves in the closing direction. This alleviates the phenomenon in which some of the photoelectrons accumulated in the photodiode 21 exit through the overflow path as a subthreshold current due to thermal excitation.

As described above, according to the conventional technique, when the reset transistor 23 of the pixel 20 is switched from on to off, the potential of the FD unit 25 is lowered to prevent a decrease in the saturation charge amount when the mechanical shutter is used. It was like that. FIG. 3 is a diagram schematically illustrating a cross section of a part of a unit pixel and a potential of the part for explaining the related art, and FIG. 3A shows a saturated state immediately after the mechanical shutter is closed, FIG. 3B shows a saturated state after the mechanical shutter is closed and before signal reading.

However, in the above-described conventional technology, since the capacitive coupling for lowering the potential of the FD section 25 is used to drive the overflow path in the closing direction, it is difficult to control the modulation of the overflow barrier. Further, when an overflow path is formed under the gate electrode of the transfer transistor 22, an overflow path is formed in the bulk with holes accumulated in the interface in order to prevent generation of a leakage current due to the interface state. Will be made. In that case, even if the potential of the gate electrode of the transfer transistor 22 is further lowered after the hole accumulation, it is difficult to control the potential of the overflow path in the bulk only by increasing the hole concentration in the vicinity of the interface. Therefore, a decrease in the amount of saturated charge when using the mechanical shutter cannot be sufficiently suppressed.

Further, as the pixel 20, the circuit configuration of FIG. 2 composed of three transistors of the transfer transistor 22, the reset transistor 23, and the amplification transistor 24 is illustrated, but the circuit configuration of four transistors including the selection transistor is illustrated. Things can also be used. The selection transistor is used by being inserted in series with respect to the amplification transistor 24, for example. In the case of a circuit configuration including these four transistors, the potential of the drain electrode of the selection transistor needs to be variable in order to use the above-described conventional technique.

<Description of Embodiment of Present Disclosure>
In the embodiment of the present disclosure, in order to sufficiently suppress the decrease in the saturation charge amount when using the mechanical shutter while preventing the occurrence of the leakage current due to the interface state, the following pixel structure and its The driving method is adopted. FIG. 4A shows the cross-sectional structure and overflow path of the pixel according to this embodiment, and FIG. 4B shows the opening / closing timing of the mechanical shutter and the driving timing of the pixel.

As shown in FIG. 4A, the pixel structure according to this embodiment includes a first charge accumulation unit 31, a transfer gate unit 32 having a plurality of gate electrodes, a second charge accumulation unit 33, and an overflow path 34. It has a configuration. The first charge storage unit 31 is, for example, a photoelectric conversion unit that converts incident light into charges and stores it, more specifically, the photodiode 21 shown in FIG. The photodiode 21 is a PNP type buried photodiode composed of an N-type accumulation region and a P-type diffusion layer on the interface side thereof, and converts light incident through a mechanical shutter into a signal charge and converts it into an N-type. Accumulate in the accumulation area. The transfer gate portion 32 corresponds to the transfer transistor 22 in FIG. 2, and has, for example, two gate electrodes 32 _{_1} and 32 _{_} 2. The charge of the first charge storage portion 31 is changed to the second charge. Transfer to the storage unit 33.

The second charge accumulation unit 33 is, for example, the FD unit 25 illustrated in FIG. 2, and is configured by an N ⁺ type impurity layer, and accumulates signal charges transferred from the first charge accumulation unit 31 by the transfer gate unit 32. To do. The overflow path 34 is formed between the first charge accumulation unit 31 and the second charge accumulation unit 33, and photoelectrons exceeding a predetermined saturation charge amount are transferred from the first charge accumulation unit 31 to the second charge accumulation unit 31. It is discharged to the charge storage unit 33. In this overflow path 34, the overflow path under the gate electrode 32 _{_ 1} on the first charge storage section 31 side of the transfer gate section 32 is formed to a depth that is not affected by the modulation of the transfer gate section 32 in the bulk. . The overflow path below the gate electrode _{32_2} on the second charge storage portion 33 side of the transfer gate portion 32 is formed at a depth affected by the modulation of the transfer gate portion 32 in the vicinity of the substrate interface.

The pixel 20 having the pixel structure according to the present embodiment having the above-described configuration is driven by the vertical driving unit 13 at the driving timing of FIG. 4B under the control of the system control unit 17 illustrated in FIG. Specifically, when the charge accumulation of the mechanical shutter is open, the gate voltage TG _{- 1} for driving the gate electrode 32 _{- 1} and the low-voltage (low). That is, the transfer gate portion including the gate electrode _{32_1} is turned off, and charges are accumulated in the first charge accumulation portion 31. At this time, the overflow path under the gate electrode _{32_1} on the first charge accumulation unit 31 side of the transfer gate unit 32 is formed in the bulk, and thus is not affected by the modulation of the transfer gate unit 32.

Thereafter, the state where the gate voltage TG _{_1} and a low voltage, and at the same time closing the mechanical shutter, the gate voltage TG _{_2} for driving the gate electrode 32 _{- 2} and the low-voltage (low). Here, “simultaneous” means not only strictly simultaneous but also substantially simultaneous, and various variations that occur in design or manufacturing are allowed. At this time, the overflow path under the gate electrode _{32_2} on the second charge storage portion 33 side of the transfer gate portion 32 is formed in the vicinity of the substrate interface and is affected by the modulation of the transfer gate portion 32. The path potential is shallower.

Then, by setting both the gate voltage _{TG_1} and the gate voltage _{TG_2} to the high voltage value high, the charge accumulated in the first charge accumulation unit 31 can be transferred to the second charge accumulation unit 33 by the transfer gate unit 32. it can.

As described above, in the CMOS image sensor 10 in which the overflow path 34 is formed below the transfer gate portion 32, the transfer gate portion 32 has, for example, two gate electrodes _{32_1} and _{32_2} . Then, an overflow path under the gate electrode _{32_1} on the first charge storage unit 31 side is formed to a depth not affected by the modulation of the transfer gate unit 32 in the bulk, and on the second charge storage unit 33 side. An overflow path under the gate electrode _{32_2} is formed at a depth affected by the modulation of the transfer gate portion 32 in the vicinity of the substrate interface. As a result, a decrease in saturation charge amount can be suppressed during the period from signal charge accumulation to transfer, so that the saturation charge amount when the mechanical shutter is used while preventing the occurrence of leakage current due to the interface state. Can be sufficiently suppressed. Further, when the technique of the present disclosure is applied to a pixel having a circuit configuration including the above-described four transistors including a selection transistor, it is not necessary to change the potential of the drain electrode of the selection transistor.

(Pixel structure with one gate electrode in transfer gate)
Here, a pixel structure having one gate electrode of the transfer gate portion 32 will be described with reference to FIG. FIG. 5A shows a cross-sectional structure of a pixel having an overflow path 34 in the bulk, and FIG. 5B shows a cross-sectional structure of a pixel having an overflow path 34 near the substrate interface. Here again, consider a case where the potential of the overflow path 34 is made shallower after charge accumulation at the drive timing of FIG. 5C.

In the pixel structure of FIG. 5A, further lowered to a lower voltage value low _{_2} gate voltage TG from the voltage value low _{_1} while being accumulated holes after charge storage, attempting to shallow the potential of the overflow path 34, the overflow path 34 Is not affected by the modulation because it is not near the interface. Therefore, the overflow path 34 is not closed. On the other hand, in the pixel structure of FIG. 5B, the potential of the overflow path 34 can be shallowed after charge accumulation. However, a leak current is generated due to the interface state during charge accumulation, and dark current is reduced. It will get worse.

As described above, in the pixel structure having one gate electrode of the transfer gate portion 32, it is not possible to sufficiently suppress the decrease of the saturation charge amount when the mechanical shutter is used without deteriorating the white spot generated by the dark current noise. . On the other hand, in the pixel structure in which the transfer gate portion 32 has a plurality of gate electrodes, as described above, it is possible to suppress a decrease in the saturation charge amount during the period from signal charge accumulation to transfer. While preventing the occurrence of leakage current due to the interface state, it is possible to sufficiently suppress the decrease in the saturation charge amount when using the mechanical shutter. Hereinafter, specific examples of the pixel structure according to the embodiment of the present disclosure will be described.

[Example 1]
The pixel structure according to Example 1 is the pixel structure shown in FIG. 4A. The driving using the mechanical shutter of the pixel structure according to the first embodiment will be described with reference to FIG. 6A shows a cross-sectional structure and state during charge accumulation, FIG. 6B shows a cross-sectional structure and state during transfer waiting, and FIG. 6C shows a cross-sectional structure and state during charge transfer. Here, “state” means states such as light incidence, gate voltage, and overflow path. The same applies to the following. The driving of the pixel structure according to the first embodiment is performed at the driving timing shown in FIG. 4B. In this embodiment, the low voltage value low is a voltage value at which the overflow path 34 is closed, and the high voltage value high is a voltage value at which the overflow path 34 is opened. The same applies to the following.

-During charge accumulation When the mechanical shutter is in the open state, the gate voltage _{TG_1} of the gate electrode _{32_1 is set} to a low voltage value low (voltage value at which the transfer channel is closed), and the gate voltage _{TG_2} of the gate electrode _{32_2 is set} to high. The voltage value is high. As a result, an overflow path 34 is formed from the photodiode 21 toward the FD portion 25. At this time, in order to suppress dark current due to generation of leakage current due to the interface state, in the transfer gate portion including the gate electrode _{32_1} , as shown in FIG. 6A, the overflow path 34 is a region away from the interface, that is, The transfer gate 32 is located in a region having a depth that is not affected by the modulation.

Transfer wait state In the transfer wait period from the end of accumulation with the mechanical shutter closed to the start of transfer, both the gate voltage _{TG_1} and the gate voltage _{TG_2} are set to the low voltage value low as shown in FIG. 6B. At this time, since the potential of the overflow path 34 under the gate electrode _{32_2} becomes shallow, the transfer channel and the overflow path 34 are closed.

-During charge transfer During charge transfer, both the gate voltage _{TG_1} and the gate voltage _{TG_2} are set to the high voltage value high. At this time, the vicinity of the interface is modulated both under the gate electrode _{32_1 and} under the gate electrode _{32_2} . 6C, a signal charge transfer channel (transfer path) is formed in the vicinity of the substrate interface, so that the signal charge can be transferred from the photodiode 21 to the FD portion 25.

The operation as described above can suppress the decrease in the amount of saturation charge during the period from signal charge accumulation to transfer, so that leakage current due to interface states can be prevented while using a mechanical shutter. Can be sufficiently suppressed. In the drive timing shown in FIG. 4B, the closing timing of the mechanical shutter and the timing of transition from the high voltage to the low voltage from the gate voltage _{TG_2} are the same, but they may not be completely the same.

(Modification of Example 1)
As a modification of the first embodiment, the voltage value of the low potential side of the gate voltage TG _{_2} gate electrode 32 _{_2,} also employs a configuration in which the voltage value low _{_2} lower than the low voltage low for Example 1 it can. Low voltage low _{_2} at this time, it comes to a voltage value lower than the voltage value low on the low potential side of the gate electrode 32 _{_1.} By setting the voltage value on the low potential side of the gate voltage _{TG_2} to a lower voltage value _{low_2} , the channel below the transfer gate portion 32 can be closed even if the gate length L of the gate electrode _{32_2} is short. Further, it is possible to suppress a decrease in the saturation charge amount when using the mechanical shutter. Further, since the gate length L of the gate electrode _{32_2} can be shortened, an increase in area due to an increase in the gate electrode of the transfer gate portion 32 can be suppressed to a minimum.

[Example 2]
In Example 2, construction the gate voltage TG _{_2} gate electrode 32 _{_2} takes three values, i.e., adopts a configuration for driving the gate electrode 32 _{_2} three values. FIG. 7A shows the opening / closing timing of the mechanical shutter and the driving timing of the pixel. As shown in FIG. 7A, the gate voltage TG _{_2} gate electrode 32 _{_2} takes the first low voltage low _{_1} accumulation period of the signal charges, a first low voltage value in the transfer waiting time to transfer from the storage take lower second low voltage low _{_2} than low _{_1,} it takes a high voltage value high in the transfer period. The first low voltage value _{low_1} may be the same voltage value as the low potential side voltage value low of the gate voltage _{TG_2} , or may be a different voltage value.

For the drive of the third embodiment for driving the gate electrode 32 _{_2} 3 value will be described with reference to FIGS. 7B and 7C. FIG. 7B shows a cross-sectional structure and state during charge accumulation, and FIG. 7C shows a cross-sectional structure and state in a transfer waiting state.

Charge accumulation during mechanical shutter open timing, i.e., at storage start signal charges, as shown in FIG. 7B, switches the gate voltage TG _{_1} gate electrode 32 _{_1} from the high voltage high to the low voltage value low, the gate The gate voltage _{TG_2} of the electrode _{32_2} is also switched from the high voltage value high to the first low voltage value _{low_1} . At this time, since it is necessary to present channel as the overflow path 34 under the gate electrode 32 _{_2,} the first low-voltage low _{_1} gate voltage TG _{_2} is set below the threshold voltage of the transfer gate portion 32 Need to be.

· Transfer waiting state mechanical shutter closing timing, i.e., at the timing of the accumulation end, as shown in FIG. 7C, a lower second low gate voltage TG _{_2} gate electrode 32 _{_2} from the first low-voltage low _{_1} Switching to the voltage value _{low_2} , the overflow path 34 is set to a lower potential. As a result, the same operation and effect as in the first embodiment, that is, the overflow path 34 exists in a region having a depth that is not affected by the modulation of the transfer gate portion 32, and therefore, the leakage current caused by the interface state is reduced. Dark current due to generation can be suppressed. Further, it is possible to suppress a decrease in the saturation charge amount when using the mechanical shutter.

In addition, in the second embodiment, at the time of charge accumulation, both to the low voltage value low gate electrodes 32 _{- 1} and the gate electrode 32 _{_2,} the gate voltage TG _{_1} of low _{_1} (voltage value of the transfer channel is closed side), the TG _{_2} Apply. This makes it difficult for the short channel effect to occur as compared with the first embodiment, so that the gate length L of the gate electrode _{32_1} can be shortened. In addition, by setting the gate voltage TG lower voltage value the voltage value of the low potential side of _{_2} low _{_2,} it can be shortened gate length L of the gate electrode 32 _{_2.} Thereby, an increase in area due to an increase in the number of gate electrodes of the transfer gate portion 32 can be minimized.

Note that the low voltage applied to the gate electrode _{32_2} during charge accumulation, that is, the first low voltage value _{low_1} of the gate voltage _{TG_2} is not necessarily fixed. For example, the first low voltage value _{low_1} can be made variable, and the first low voltage value _{low_1} can be adjusted for each pixel or for each chip (each solid-state imaging device). It is possible to suppress the variation in the saturation charge amount due to the variation in the barrier.

[Example 3]
In Example 3, the gate voltage TG _{_1} gate electrode 32 _{- 1,} and adopts a configuration in which independent high potential side of the gate voltage TG _{_2} gate electrode 32 _{_2.} That is, in Examples 1 and 2 had adopted a configuration in which the high potential side of the gate voltage TG _{_1} and the gate voltage TG _{_2} the same voltage value high. On the other hand, in the third embodiment, the high voltage value high (voltage value on the side where the transfer channel is opened) is different between the gate voltage _{TG_1} and the gate voltage _{TG_2} .

FIG. 8 shows the opening / closing timing of the mechanical shutter and the driving timing of the pixel in the pixel structure according to the third embodiment. As shown in FIG. 8, a voltage value of the high potential side of the gate voltage TG _{_1} and high _{_1,} is higher high _{_2} than the voltage value of the high potential side of the gate voltage TG _{_2} high _{_1.} The transition timing of the gate voltage _{TG_1} and the gate voltage _{TG_2 from} the high voltage value high to the low voltage value low is the same as in the first embodiment.

Thus, the gate voltage TG _{_1} gate electrodes 32 _{- 1} and, also the high potential side of the gate voltage TG _{_2} gate electrode 32 _{_2} a case of independently be the same action as in Example 1, the effect be able to. In other words, the overflow path 34 is positioned in a region having a depth that is not affected by the modulation of the transfer gate portion 32, and dark current due to generation of leakage current due to the interface state can be suppressed. Further, it is possible to suppress a decrease in the saturation charge amount when using the mechanical shutter.

In addition, the voltage value _{high_2 on} the high potential side of the gate voltage _{TG_2} is made variable, and the voltage value _{high_2} can be adjusted for each pixel or chip (each solid-state imaging device), so that saturation due to variations in overflow barriers is achieved. Variations in the amount of charge can be suppressed.

[Example 4]
In the fourth embodiment, in the transfer gate portion 32 having a plurality of gate electrodes, the transfer gate portion including at least one gate electrode of the plurality of gate electrodes is composed of an embedded transistor in which the gate electrode is embedded in the semiconductor substrate. Is adopted. Specifically, in the transfer gate portion 32 according to the first to third embodiments, the transfer gate portion including at least one of the gate electrode _{32_1} and the gate electrode _{32_2} is formed of a buried transistor. 9A shows a pixel structure 1 and an overflow path according to the fourth embodiment, and FIG. 9B shows a pixel structure 2 and an overflow path according to the fourth embodiment. The embedded transistor has a structure in which a vertical gate electrode 36 is formed in a column shape in the depth direction from the surface of the semiconductor substrate under the gate electrode _{32_1} / _{32_2} on the semiconductor substrate.

In the pixel structure 1 shown in FIG. 9A, in the transfer gate portion 32, the transfer gate portion including the gate electrode _{32_1} is embedded in the N-type diffusion layer 36 formed in the P well 35 under the gate electrode _{32_1.} It consists of a type of transition. Also for the pixel structure 1, by using the same drive as in the first to third embodiments, it is possible to suppress a decrease in the saturation charge amount when using the mechanical shutter. Further, by the transistor of type buried transfer gate portion including the gate electrode 32 _{_1,} it is possible to deeply form the photodiode 21 in the substrate depth direction, to increase the saturation charge amount (number of saturated electrons) it can.

In the pixel structure 2 shown in FIG. 9B, in the transfer gate portion 32, the transfer gate portion including the gate electrode _{32_2} is embedded in the N-type diffusion layer 36 formed in the P well 35 under the gate electrode _{32_2.} It consists of a type of transition. Also for the pixel structure 2, by using the same drive as in the first to third embodiments, it is possible to suppress a decrease in the saturation charge amount when using the mechanical shutter. Further, as compared to when the transfer gate unit including a gate electrode 32 _{_2} is not transistor embedded, be improved transfer of toward the transfer gate unit including a gate electrode 32 _{_2} from the transfer gate unit including a gate electrode 32 _{_1} it can.

<Modification>
In the above embodiment, the first charge storage unit 31 is the photodiode 21, the second charge storage unit 33 is the FD unit 25, and the transfer gate unit 32 between the photodiode 21 and the FD unit 25 is connected to the transfer gate unit 32. Although the technique of the present disclosure is applied, the present invention is not limited to this. For example, a charge storage unit is provided between the photodiode 21 and the FD unit 25, a first transfer gate unit is disposed between the photodiode 21 and the charge storage unit, and the charge storage unit and the FD unit 25 There is a pixel structure having a configuration in which a second transfer gate portion is disposed between them.

In the above pixel structure, the photodiode 21 is the first charge storage unit 31, the charge storage unit is the second charge storage unit 33, and the technique of the present disclosure is applied to the first transfer gate unit. It can also be set as the structure to do. Alternatively, the charge storage unit may be the first charge storage unit 31, the FD unit 25 may be the second charge storage unit 33, and the technology of the present disclosure may be applied to the second transfer gate unit. it can.

Further, in the above embodiment, the case of the electron storage type pixel structure has been described as an example, but the same applies to the hole storage type pixel structure in which the conductivity type (P channel / N channel) is inverted. It is applicable to. As an example, FIG. 10A shows a pixel structure and an overflow path obtained by inverting the P channel / N channel of FIG. 4A, and FIG. 10B shows opening / closing timing of the mechanical shutter and driving timing of the pixel.

In the above, a CMOS image sensor in which unit pixels that detect charges corresponding to the amount of visible light as physical quantities are arranged in a matrix has been described as an example. However, the technology of the present disclosure is not limited to a CMOS image sensor. The present invention can be applied to all XY address type solid-state imaging devices.

Note that the solid-state imaging device may be formed as a single chip, or may be in a modular form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Good.

<Electronic device of the present disclosure>
Next, an electronic apparatus according to the present disclosure that uses the CMOS image sensor 10 according to the above embodiment in combination with a mechanical shutter will be described. FIG. 11 is a system configuration diagram illustrating an outline of a configuration of the electronic device of the present disclosure. Here, a digital still camera which is an example of an imaging apparatus will be described as an example of the electronic apparatus of the present disclosure.

As shown in FIG. 11, the electronic device of the present disclosure, that is, a digital still camera, includes an optical block 51, a camera signal processing unit 52, an encoder / decoder unit 53, a control unit 54, and an input unit 55 in addition to the imaging unit 50. The display unit 56 and the recording medium 57 are provided. As the imaging unit 50, the CMOS image sensor 10 according to the above-described embodiment is used.

The optical block 51 includes a lens 511 for condensing light from a subject on the imaging unit 50 (CMOS image sensor 10), an aperture 512 for adjusting the amount of light, and a mechanical for selectively capturing light. A shutter 513 and the like are included.

The optical block 51 further includes a lens driving mechanism for performing focusing and zooming by moving the lens 511, an iris mechanism for controlling the diaphragm 512, a mechanical shutter mechanism for driving the mechanical shutter 513, and the like. is doing. These mechanism units are driven based on a control signal from the control unit 54.

The CMOS image sensor 10 used as the image pickup unit 50 is an XY address type solid-state image pickup device, and under the control of a control signal from the control unit 54, the timing of pixel 20 exposure, signal readout, reset, and the like. Control is performed. The camera signal processing unit 52 performs camera signal processing such as white balance adjustment processing and color correction processing on the image signal output from the CMOS image sensor 10 under the control of the control unit 54.

The encoder / decoder unit 53 operates under the control of the control unit 54, and with respect to the image signal output from the camera signal processing unit 52, a predetermined still image data format such as JPEG (Joint-Photographic Coding-Experts Group) method is used. Then, compression encoding processing is performed. The encoder / decoder unit 53 also performs decompression decoding processing on the still image encoded data supplied from the control unit 54. Further, the encoder / decoder unit 53 may be able to execute a compression encoding / decompression decoding process of a moving image by an MPEG (Moving / Picture / Experts / Group) method or the like.

The control unit 54 is a microcontroller composed of, for example, a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like. And the control part 54 controls each part of this electronic device centrally by executing the program memorize | stored in ROM etc. FIG.

The input unit 55 includes various operation keys such as a shutter release button, a lever, a dial, and the like, and outputs various control signals corresponding to an input operation by the user to the control unit 54. The display unit 56 includes a display device such as an LCD (Liquid Crystal Display) and an interface circuit for the display device, and generates an image signal to be displayed on the display device based on an image signal supplied from the control unit 54. To do. And the display part 56 displays an image on the said display device by supplying the produced | generated image signal to a display device.

The recording medium 57 is realized as, for example, a portable semiconductor memory, an optical disk, an HDD (Hard Disk Drive), a magnetic tape, or the like, and receives an image data file encoded by the encoder / decoder unit 53 from the control unit 54. Remember. Further, the designated data is read based on the control signal from the control unit 54 and is output to the control unit 54.

In the electronic apparatus (that is, the digital still camera) of the present disclosure described above, in the CMOS image sensor 10, in the operation of the still image capturing mode, the exposure period is started by the reset operation simultaneously for all the pixel rows, and the mechanical shutter. The exposure period is ended by the closing operation 513. As described above, by using the CMOS image sensor 10 in combination with the mechanical shutter 513, the exposure periods of the respective pixels in all the pixel rows match, so that the captured image can be prevented from being distorted. In addition, since the CMOS image sensor 10 can suppress a decrease in the saturation charge amount when the mechanical shutter 513 is used, a better captured image can be obtained.

In the above, a digital still camera has been described as an example of an imaging apparatus. However, the imaging apparatus is not limited to a digital still camera, and can be applied to any imaging apparatus having a mechanical shutter that selectively takes incident light from a subject. In some cases, a module form (camera module) mounted on an electronic device having an imaging function is used as the imaging apparatus. That is, the technology of the present disclosure is applicable not only to an imaging apparatus such as a digital still camera but also to all electronic devices having an imaging function using a mechanical shutter.

In addition, this indication can also take the following structures.
[1] a first charge storage unit;
A transfer gate portion having a plurality of gate electrodes for transferring the charge of the first charge storage portion;
A second charge accumulating unit for accumulating charges transferred by the transfer gate unit;
An overflow path formed between the first charge storage unit and the second charge storage unit;
With
The overflow path under the gate electrode on the first charge storage portion side of the transfer gate portion is formed at a depth that is not affected by the modulation of the transfer gate portion in the bulk,
The overflow path under the gate electrode on the second charge storage portion side of the transfer gate portion is formed at a depth affected by the modulation of the transfer gate portion near the substrate interface.
Solid-state imaging device.
[2] The first charge storage unit is a photoelectric conversion unit that converts incident light into electric charge and stores the charge.
The solid-state imaging device according to [1] above.
[3] The second charge storage unit is a floating diffusion unit.
The solid-state imaging device according to [1] or [2].
[4] The voltage at which the overflow path is closed by applying the gate voltage applied to the gate electrode on the second charge storage unit side of the transfer gate unit after the charge storage in the first charge storage unit to the voltage value applied during the charge storage. Set to value,
The solid-state imaging device according to any one of [1] to [3].
[5] During the charge accumulation in the first charge accumulation unit, the voltage value on the side where the transfer channel is closed is applied to both the gate electrode on the first charge accumulation unit side and the gate electrode on the second charge accumulation unit side. ,
The solid-state imaging device according to [4] above.
[6] During the charge accumulation in the first charge accumulation unit, the voltage value on the side where the overflow path of the gate voltage applied to the gate electrode on the second charge accumulation unit side is closed can be adjusted.
The solid-state imaging device according to [4] or [5].
[7] The voltage value on the side where the transfer channel of the gate voltage applied to the gate electrode on the first charge storage unit side and the gate electrode on the second charge storage unit side opens is different.
The solid-state imaging device according to any one of [1] to [3].
[8] The voltage value on the open side of the overflow path of the gate voltage applied to the gate electrode on the second charge storage unit side can be adjusted.
The solid-state imaging device according to [7] above.
[9] The transfer gate portion including at least one gate electrode of the plurality of gate electrodes is composed of a buried transistor.
The solid-state imaging device according to any one of [1] to [8] above.
[10] The first charge accumulation unit accumulates signal charges based on light incident through the mechanical shutter.
The solid-state imaging device according to any one of [1] to [9].
[11] a first charge storage unit;
A transfer gate portion having a plurality of gate electrodes for transferring the charge of the first charge storage portion;
A second charge accumulating unit for accumulating charges transferred by the transfer gate unit;
An overflow path formed between the first charge storage unit and the second charge storage unit;
With
The overflow path under the gate electrode on the first charge storage portion side of the transfer gate portion is formed at a depth that is not affected by the modulation of the transfer gate portion in the bulk,
The overflow path under the gate electrode on the second charge storage portion side of the transfer gate portion is formed at a depth affected by the modulation of the transfer gate portion near the substrate interface.
In driving the solid-state imaging device,
At the time of charge accumulation in the first charge accumulation unit, a gate voltage having a voltage value that closes the transfer channel is applied to the gate electrode on the first charge accumulation unit side, and an overflow path is formed on the gate electrode on the second charge accumulation unit side. Apply the gate voltage of the open voltage value,
In the period from the end of accumulation of the first charge accumulation unit to the start of transfer to the second charge accumulation unit, a gate voltage of a voltage value that closes the transfer channel is applied to the gate electrode on the first charge accumulation unit side, Applying a gate voltage of a voltage value at which an overflow path is closed to the gate electrode on the second charge storage unit side;
A driving method of a solid-state imaging device.
[12] A solid-state imaging device in which pixels including a photoelectric conversion unit are arranged;
A mechanical shutter that selectively takes incident light and guides it to the light receiving surface of the solid-state imaging device;
Comprising
Each pixel of the solid-state imaging device
A first charge storage unit that photoelectrically converts and stores light incident through the mechanical shutter;
A transfer gate portion having a plurality of gate electrodes for transferring the charge of the first charge storage portion;
A second charge accumulating unit for accumulating charges transferred by the transfer gate unit;
An overflow path formed between the first charge storage unit and the second charge storage unit;
With
The overflow path under the transfer gate portion on the first charge storage portion side is formed at a depth not affected by the modulation of the transfer gate portion in the bulk,
The overflow path under the transfer gate portion on the second charge storage portion side is formed at a depth affected by the modulation of the transfer gate portion near the substrate interface.
Electronics.

DESCRIPTION OF SYMBOLS 10 ... CMOS image sensor, 11 ... Semiconductor substrate (chip), 12 ... Pixel array part, 13 ... Vertical drive part, 14 ... Column processing part, 15 ... Horizontal drive part, DESCRIPTION OF SYMBOLS 16 ... Output circuit part, 17 ... System control part, 20 ... Unit pixel, 21 ... Photodiode, 22 ... Transfer transistor, 23 ... Reset transistor, 24 ... Amplification transistor 25... FD section (floating diffusion section), 31... First charge storage section, 32... Transfer gate section, 32 _{_ 1} , 32 _{_2} . Charge storage unit, 34 ... overflow path, 50 ... imaging unit, 51 ... optical block, 52 ... camera signal processing unit, 53 ... encoder / decoder unit, 54 ... control unit, 55 ・..Input unit, 56... Display unit, 57... Recording medium, 511... Lens, 512 .. aperture, 513... Mechanical shutter, _{TG.sub._1} , _{TG.sub._2.}

Claims (12)

A first charge storage unit;
A transfer gate portion having a plurality of gate electrodes for transferring charges of the first charge storage portion;
A second charge accumulating unit for accumulating charges transferred by the transfer gate unit, and
An overflow path formed between the first charge storage unit and the second charge storage unit;
With
The overflow path under the gate electrode on the first charge storage portion side of the transfer gate portion is formed at a depth that is not affected by the modulation of the transfer gate portion in the bulk,
The solid-state imaging device, wherein the overflow path under the gate electrode on the second charge storage portion side of the transfer gate portion is formed at a depth affected by the modulation of the transfer gate portion near the substrate interface. 2. The solid-state imaging device according to claim 1, wherein the first charge storage unit is a photoelectric conversion unit that converts incident light into electric charge and stores the charge. 2. The solid-state imaging device according to claim 1, wherein the second charge accumulation unit is a floating diffusion unit. After the charge accumulation in the first charge accumulation unit, the gate voltage applied to the gate electrode on the second charge accumulation unit side of the transfer gate unit is set to a voltage value that closes the overflow path than the voltage value applied during the charge accumulation. The solid-state imaging device according to claim 1. 5. The voltage value on the side where the transfer channel is closed is applied to both the gate electrode on the first charge storage unit side and the gate electrode on the second charge storage unit side during charge storage in the first charge storage unit. The solid-state imaging device described in 1. 5. The solid-state imaging device according to claim 4, wherein a voltage value on a side where an overflow path of a gate voltage applied to a gate electrode on the second charge storage unit side is closed can be adjusted during charge storage of the first charge storage unit. . 2. The solid-state imaging device according to claim 1, wherein a voltage value on a side where a transfer channel of a gate voltage applied to the gate electrode on the first charge accumulation unit side and the gate electrode on the second charge accumulation unit side is different is different. The solid-state imaging device according to claim 7, wherein a voltage value on a side where an overflow path of a gate voltage applied to the gate electrode on the second charge storage unit side is open is adjustable. 2. The solid-state imaging device according to claim 1, wherein the transfer gate portion including at least one gate electrode of the plurality of gate electrodes is formed of a buried type transistor. The solid-state imaging device according to claim 1, wherein the first charge accumulation unit accumulates signal charges based on light incident through the mechanical shutter. A first charge storage unit;
A transfer gate portion having a plurality of gate electrodes for transferring charges of the first charge storage portion;
A second charge accumulating unit for accumulating charges transferred by the transfer gate unit, and
An overflow path formed between the first charge storage unit and the second charge storage unit;
With
The overflow path under the gate electrode on the first charge storage portion side of the transfer gate portion is formed at a depth that is not affected by the modulation of the transfer gate portion in the bulk,
The overflow path under the gate electrode on the second charge accumulation portion side of the transfer gate portion is a driving method of the solid-state imaging device formed at a depth affected by the modulation of the transfer gate portion near the substrate interface,
At the time of charge accumulation in the first charge accumulation unit, a gate voltage having a voltage value that closes the transfer channel is applied to the gate electrode on the first charge accumulation unit side, and an overflow path is formed on the gate electrode on the second charge accumulation unit side. Apply the gate voltage of the open voltage value,
In the period from the end of accumulation of the first charge accumulation unit to the start of transfer to the second charge accumulation unit, a gate voltage of a voltage value that closes the transfer channel is applied to the gate electrode on the first charge accumulation unit side, A method for driving a solid-state imaging device, wherein a gate voltage having a voltage value at which an overflow path is closed is applied to the gate electrode on the charge storage unit side. A solid-state imaging device in which pixels including a photoelectric conversion unit are arranged; and
A mechanical shutter that selectively takes incident light and guides it to the light-receiving surface of the solid-state imaging device;
Comprising
Each pixel of the solid-state imaging device
A first charge storage unit that photoelectrically converts and stores light incident through the mechanical shutter;
A transfer gate portion having a plurality of gate electrodes for transferring the charge of the first charge storage portion;
A second charge accumulating unit for accumulating charges transferred by the transfer gate unit;
An overflow path formed between the first charge storage unit and the second charge storage unit;
With
The overflow path under the transfer gate portion on the first charge storage portion side is formed at a depth not affected by the modulation of the transfer gate portion in the bulk,
The overflow path below the transfer gate portion on the second charge storage portion side is an electronic device formed to a depth that is affected by the modulation of the transfer gate portion near the substrate interface.

Images