WO2015010364A1 - Shift register unit, gate drive circuit and display device - Google Patents

Abstract

The present invention relates to the technical field of display technologies. Provided are a shift register unit, a gate drive circuit and a display device. The present invention can reduce the coupling capacitance of thin film transistors and the noise of output signals. The shift register unit comprises an input module, a control module, a reset module, a pull-up module, a pull-down module and a noise reduction module. Embodiments of the present invention are used to implement scan driving.

Description

 Shift register unit, gate drive circuit and display device

 The present invention relates to the field of display technologies, and in particular, to a shift register unit, a gate driving circuit, and a display device. Background technique

 Liquid crystal display (LCD) has the advantages of low radiation, small volume and low energy consumption, and is widely used in electronic products such as notebook computers, flat-panel TVs and mobile phones.

 The liquid crystal display is composed of a matrix of pixels arranged in a horizontal direction and a vertical direction. When the liquid crystal display is displayed, the data driving circuit can sequentially latch the input display data according to the timing of the clock signal, convert it into an analog signal, and input it to the liquid crystal. The data line of the panel, the gate drive circuit can convert the input clock signal into a voltage for controlling the on/off of the pixel through the shift register, and apply it to the gate line of the liquid crystal panel row by row.

 In order to further reduce the production cost of the liquid crystal display product, the existing gate drive circuit often adopts a GOA (gate driver on Array) design to integrate a TFT (Thin Film Transistor) gate switch circuit. The array substrate of the display panel is formed to form a scan driving of the display panel, so that the gate driving integrated circuit portion can be omitted, which can not only reduce the product cost from the material cost and the manufacturing process, but also the display panel can be bilaterally symmetric and Beautiful design with a narrow border. This gate switching circuit integrated on the array substrate using GOA technology is also called a GOA circuit or a shift register circuit.

A typical shift register using GOA technology in the prior art is shown in FIG. 1. FIG. 2 is an input/output timing diagram of the shift register. Referring to FIG. 1 and FIG. 2, the working process of the shift register is: T1 phase, the signal input terminal Input is input with a high level, the thin film transistor M1 is turned on to charge the capacitor C1, and the thin film transistor M3 is turned on to make the output output low level. In the T2 phase, the clock signal terminal CLK is input to a high level, and the bootstrapping function of the capacitor C1 further raises the gate level of the thin film transistor M3, the thin film transistor M3 is turned on, and the output output is high level; Reset signal reset input high level, at this time, thin film transistors M2 and M4 are turned on, the gate level of the thin film transistor M3 and the output level are pulled down to Vss low level; T4 stage, the gate of the thin film transistor M3 Level is at Vss Low level, thin film transistor M3 is turned off, and Output output is low level; In stage T5, Input, CLK, and Reset are all input low level, at this time, thin film transistors M1 to M4 are kept off, and Output is output low. Thereafter, until the next Input is high, the shift register repeats the T4 and T5 phases, which can be referred to as the non-working time of the shift register. It can be seen that during the operation of the shift register, the power in the coupling capacitor of M3 itself is not fully released, which causes noise interference to the output of the signal output, thereby reducing the stability of the G0A circuit, and each shift The bit register contains multiple TFTs, which increases the size of the G0A circuit and the production cost of the product. Summary of the invention

 Embodiments of the present invention provide a shift register unit, a gate drive circuit, and a display device. The coupling capacitance of the thin film transistor can be reduced, and the noise of the output signal can be reduced.

 In order to achieve the above object, the embodiment of the present invention adopts the following technical solutions:

 An aspect of an embodiment of the present invention provides a shift register unit, including: an input module, a control module, a reset module, a pull-up module, a pull-down module, and a noise reduction module;

 The input module is respectively connected to the first signal input end and the pull-up control node, and is configured to control a potential of the pull-up control node according to a signal input by the first signal input end;

 The control module is respectively connected to the first clock signal end, the second clock signal end, the first voltage end, the pull-up control node and the pull-down control node, and is configured to input a signal according to the first clock signal end a signal input by the second clock signal terminal or a potential of the pull-up control node controls a potential of the pull-down control section, ^;

 The reset module is respectively connected to the second signal input end, the first voltage end, the pull-up control node and the pull-down control node, for resetting the upper signal according to the signal input by the second signal input end Pull the control section, the potential;

 The pull-up module is respectively connected to the first clock signal end, the pull-up control node and the signal output end, and is configured to enable the signal output end to output the first control under the control of the pull-up control node potential a signal at the end of a clock signal;

 The pull-down module is respectively connected to the first voltage end, the pull-down control node and the signal output end, and is configured to pull down a signal outputted by the signal output terminal to be low under the control of the pull-down control node potential Level

The noise reduction module is respectively connected to the first clock signal end and the pull-up control node And a signal output end, configured to output a signal of the first clock signal end through the signal output end.

 As an example, the input module includes: a first transistor having a first pole and a gate connected to the first signal input terminal, and a second pole connected to the pull-up control node.

 As an example, the reset module includes:

 a second transistor having a first pole connected to the pull-up control node, a gate connected to the second signal input terminal, and a second pole connected to the first voltage terminal;

 And a fifth transistor having a first pole connected to the signal output terminal, a gate connected to the second signal input terminal, and a second pole connected to the first voltage terminal.

 As an example, the pull-down module includes:

 a third transistor having a first pole connected to the pull-up control node, a gate connected to the pull-down control node, and a second pole connected to the first voltage terminal.

 The fourth transistor has a first pole connected to the signal output terminal, a gate connected to the pull-down control node, and a second pole connected to the first voltage terminal.

 As an example, the input module includes: a first transistor having a first pole connected to the second voltage terminal, a gate connected to the first signal input terminal, and a second pole connected to the pull-up control node.

 As an example, the reset module includes: a second transistor having a first pole connected to the pull-up control node, a gate connected to the second signal input terminal, and a second pole connected to the third voltage terminal;

 As an example, the pull-down module further includes:

 a third transistor having a first pole connected to the pull-up control node, a gate connected to the pull-down control node, and a second pole connected to the first voltage terminal.

 a fourth transistor having a first pole connected to the signal output terminal, a gate connected to the pull-down control node, and a second pole connected to the first voltage terminal;

 The fifth transistor has a first pole connected to the signal output terminal, a gate connected to the second clock signal terminal, and a second pole connected to the first voltage terminal.

 As an example, the control module includes:

 a sixth transistor having a gate connected to the first clock signal end, a first pole connected to the second clock signal end, and a second pole connected to the pull-down control node;

a seventh transistor having a first pole and a gate connected to the second clock signal terminal, and a second pole The pull-down control nodes are connected;

 The eighth transistor has a first pole connected to the pull-down control node, a gate connected to the pull-up control node, and a second pole connected to the first voltage terminal.

 As an example, the pull-up module includes:

 a ninth transistor having a first pole connected to the first clock signal terminal, a gate connected to the pull-up control node, and a second pole connected to the signal output end;

 a capacitor connected between the gate and the second pole of the ninth transistor.

 The noise reduction module includes:

 The at least one tenth transistor has a first pole connected to the first clock signal end, a gate connected to the pull-up control node, and a second pole connected to the signal output end.

 Another aspect of an embodiment of the present invention provides a gate driving circuit including a plurality of stages of shift register units as described above.

 Except for the first stage shift register unit, the signal input end of each of the other shift register units is connected to the signal output end of the adjacent shift register unit adjacent thereto;

 Except for the last stage shift register unit, the signal output terminals of each of the other shift register units are connected to the signal input terminals of the adjacent next stage shift register unit.

 Yet another aspect of an embodiment of the present invention provides a display device including the gate circuit as described above.

 The present invention provides a shift register unit, a gate drive circuit, and a display device. The shift register unit includes an input module, a control module, a reset module, a pull-up module, a pull-down module, and a noise reduction module. The noise reduction module connected in parallel with the pull-up module can reduce the size of the thin film transistor in the pull-up module. In this way, the coupling capacitance of the thin film transistor in the pull-up module is reduced, thereby reducing the noise of the output signal. DRAWINGS

 In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description It is merely some embodiments of the present invention, and those skilled in the art can obtain other drawings according to the drawings without any creative work.

1 is a schematic structural diagram of a shift register unit provided by the prior art; 2 is a waveform diagram of signal timing when a shift register unit is provided in the prior art;

 FIG. 3 is a schematic diagram of a circuit connection structure of a shift register unit according to an embodiment of the present invention; FIG.

 4 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention; FIG. 5 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention; Signal timing waveform diagram when the shift register unit is operating;

 FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11 are schematic diagrams showing operation states of a shift register unit according to an embodiment of the present invention;

 FIG. 12 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention. detailed description

 The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

 The transistors used in all the embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics. Since the sources and drains of the transistors used herein are symmetrical, the source and the drain are indistinguishable. of. In the embodiment of the present invention, in order to distinguish the two poles except the gate of the transistor, one of the poles is referred to as a source and the other pole is referred to as a drain. In addition, according to the characteristics of the transistor, the transistor can be divided into an N-type transistor or a P-type transistor. In the embodiment of the invention, when the N-type transistor is used, the first pole can be the source, and the second pole can be the drain. When a P-type transistor is used, its first pole can be the drain and the second pole can be the source. The transistors used in the embodiments of the present invention may be either N-type transistors or P-type transistors. In the following embodiments, the description is made by taking the transistors as N-type transistors as an example. It is conceivable that the timing of the driving signals needs to be adjusted correspondingly when the P-type transistors are used.

An embodiment of the present invention provides a shift register unit, as shown in FIG. 3, which may include: an input module 10, a control module 20, a reset module 30, a pull-up module 40, a pull-down module 50, and noise reduction. The input module 10 can be respectively connected to the first signal input terminal Input and the pull-up control node PU for controlling the potential of the pull-up control node PU according to the signal input by the first signal input terminal Input. For example, when the signal input from the first signal input terminal Input is at a high level, the potential of the pull-up control node PU is pulled high.

 The control module 20 can be respectively connected to the first clock signal terminal CLK and the second clock signal terminal

CLKB, the first voltage terminal VI, the pull-up control node PU, and the pull-down control node PD, for inputting a signal according to the first clock signal terminal CLK, a signal input by the second clock signal terminal CLKB, or a potential of the pull-up control node PU The potential of the pull-down control node PD is controlled. It should be noted that the signal periods input by the first clock signal terminal CLK and the second clock signal terminal CLKB are in the same phase.

 In the embodiment of the present invention, the pull-up control node PU refers to a circuit node for controlling the pull-up module to be turned on or off, and the pull-down control node PD refers to a circuit node for controlling the pull-down module to be turned on or off.

 The reset module 30 can be respectively connected to the second signal input terminal Reset, the first voltage terminal VI, the pull-up control node PU and the pull-down control node PD for resetting the pull-up control node PU according to the signal input by the second signal input terminal Reset. Potential.

 The pull-up module 40 can be respectively connected to the first clock signal terminal CLK, the pull-up control node PU and the signal output terminal Output for outputting the signal output terminal Output to the first clock signal terminal CLK under the control of the pull-up control node PU potential The signal thus causes the shift register unit to output a drive signal.

 The pull-down module 50 can respectively connect the first voltage terminal VI, the pull-down control node PD and the signal output terminal Output, and is used to pull down the signal outputted by the signal output terminal to a low level under the control of the pull-down control node PD potential.

 The noise reduction module 60 can be respectively connected to the first clock signal terminal CLK, the pull-up control node PU and the signal output terminal Output for outputting the signal of the first clock signal terminal CLK through the signal output terminal Output, thereby reducing the output of the pull-up module 40. The noise of the signal.

The present invention provides a shift register unit, which includes an input module, a control module, a reset module, a pull-up module, a pull-down module, and a noise reduction module, and the noise reduction module connected in parallel with the pull-up module can The size of the thin film transistor in the pull-up module is reduced, which reduces the coupling capacitance of the thin film transistor in the pull-up module, thereby reducing the noise of the output signal. The first voltage terminal VI may be a ground terminal, or the first voltage terminal VI may input a low level VSS or VGL. In the embodiment of the present invention, as shown in FIG. 4, the description is made by taking the first voltage terminal VI input low level VSS as an example.

 Further, as shown in FIG. 4, the input module 10 may include: a first transistor M1 having a first pole and a gate connected to the first signal input terminal, and a second pole connected to the pull-up control node PU. In this way, the potential of the pull-up control node PU can be controlled according to the signal input by the first signal input terminal through the first transistor M1.

 Further, the reset module 30 may include: a second transistor M2 and a fifth transistor M5. The first transistor of the second transistor M2 is connected to the pull-up control node PU, the gate is connected to the second signal input terminal, and the second electrode is connected to the first voltage terminal VI. The first transistor of the fifth transistor M5 is connected to the output terminal Output, the gate is connected to the second signal input terminal, and the second electrode is connected to the first voltage terminal VI.

 In this way, the second transistor M2 and the fifth transistor M5 can reset the potential of the pull-up control node PU and the signal output terminal according to the reset signal input by the second signal input terminal.

 Further, the pull-down module 50 may include: a third transistor M3 and a fourth transistor M4. The first transistor of the third transistor M3 is connected to the pull-up control node PU, the gate is connected to the pull-down control node PD, and the second pole is connected to the first voltage terminal VI. The first pole of the fourth transistor M4 is connected to the signal output terminal Output, the gate is connected to the pull-down control node PD, and the second pole is connected to the first voltage terminal VI.

 In this way, when the pull-up control node PU is at a high level, the pull-down control node PD is at a low level, and the third transistor M3 and the fourth transistor M4 are in an off state to ensure the output of the PU node and the Output point; when the pull-up control When the node PU is at a low level, the pull-down control node PD is at a high level, and when the second clock signal terminal CLKB is input to a high level, the signal output from the signal output terminal Output is pulled down through the third transistor M3 and the fourth transistor M4. Level, so as to better avoid the following faults: the signal output terminal becomes high level under the action of other interference signals, and the row line of the gate line controlled by it is turned on under the action of the high level, eventually causing the gate line Open the error.

 Alternatively, as shown in FIG. 5, the input module 10 may include:

The first transistor M1 has a first pole connected to the second voltage terminal V2, a gate connected to the first signal input terminal Input, and a second pole connected to the pull-up control node PU. In this way, through the first The transistor M1 can control the potential of the pull-up control node PU according to the signal input by the first signal input terminal Input.

 Further, the reset module 30 may include: a second transistor M2 having a first pole connected to the pull-up control node PU, a gate connected to the second signal input terminal, and a second pole connected to the first voltage terminal VI. In this way, the potential of the pull-up control node PU can be reset by the second transistor M2 according to the reset signal input by the second signal input terminal.

 It should be noted that, in the structure of the shift register unit shown in FIG. 5, the low voltage VGL is input to the first voltage terminal VI, and the second voltage terminal V2 is input to the high level VDD and the third voltage terminal V3 is input low. The level VSS is taken as an example for explanation.

 Further, the pull-down module 50 may include: a third transistor M3, a fourth transistor

M4 and fifth transistor M5. The first transistor of the third transistor M3 is connected to the pull-up control node PU, the gate is connected to the pull-down control node PD, and the second pole is connected to the first voltage terminal VI. The first pole of the fourth transistor M4 is connected to the signal output terminal Output, the gate is connected to the pull-down control node PD, and the second pole is connected to the first voltage terminal VI. The first transistor of the fifth transistor M5 is connected to the signal output terminal Output, the gate is connected to the second clock signal terminal CLKB, and the second electrode is connected to the first voltage terminal VI.

 In this way, when the pull-up control node PU is at a low level, the pull-down control node PD is at a high level, and the second clock signal terminal CLKB is input to a high level, passes through the third transistor M3, the fourth transistor M4, and the fifth transistor. M5 can pull down the signal output from the output of the signal output to a low level, so as to better avoid the following faults: The output of the signal output becomes high level under the action of other interference signals, and makes one line controlled by it. The gate line is turned on under the high level, which eventually causes the gate line to open incorrectly.

 It should be noted that, as shown in FIG. 4, the signal output ends of the shift register units of each stage output signals from top to bottom and control the gate lines of each row to be sequentially turned on under the action of a high level, thereby performing progressive scan on each row of gate lines. .

As shown in FIG. 5, the signal output terminals of the shift register units of each stage can not only scan the row-by-row lines of the row lines from the top-down output signal, but also scan the row-by-row lines from bottom to top. Specifically, when the input signal and the voltage terminal are as shown in FIG. 5, the shift register units of each stage can perform progressive scan of each row of gate lines from top to bottom, when the first signal input terminal Input and second in FIG. When the signal input terminal is interchanged, and the second voltage terminal V2 is interchanged with the third voltage terminal V3, the shift register units of each stage can output signals from bottom to top and gate lines of each row. Perform a progressive scan so that a two-way scan can be achieved. Therefore, each row of gate lines can be scanned in different directions by changing the input signal of the shift register unit and the potential of the connection voltage, and those skilled in the art can adjust them according to specific conditions.

 Further, as shown in FIG. 4 or FIG. 5, the control module 20 may include: a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8.

 The gate of the sixth transistor M6 is connected to the first clock signal terminal CLK, the first electrode thereof is connected to the second clock signal terminal CLKB, and the second electrode is connected to the pull-down control node PD. The first transistor and the gate of the seventh transistor M7 are connected to the second clock signal terminal CLKB, and the second electrode is connected to the pull-down control node PD. The first transistor of the eighth transistor M8 is connected to the pull-down control node PD, the gate is connected to the pull-up control node PU, and the second pole is connected to the first voltage terminal VI.

 In this way, through the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8, the signal input from the first clock signal terminal CLK, the signal input from the second clock signal terminal CLKB, or the potential of the pull-up control node PU can be The potential of the pull-down control node PD is controlled.

 Further, as shown in FIG. 4 or FIG. 5, the pull-up module 40 may include: a ninth transistor M9 and a capacitor Cl.

 The first pole of the ninth transistor M9 is connected to the first clock signal terminal CLK, the gate is connected to the pull-up control node PU, and the second pole is connected to the signal output terminal Output. The capacitor C1 is connected between the gate of the ninth transistor M9 and the second pole.

 In this way, through the ninth transistor M9 and the capacitor C1, the signal output from the signal output terminal can be pulled up to a high level under the control of the pull-up control node potential.

 In the embodiment of the present invention, the function of the pull-up module 40 is to make the gate of the signal output terminal output after the pre-charging of the capacitor C1 and the first clock signal CLK is at a high level for half a clock cycle. High level signal.

 Further, as shown in FIG. 4 or FIG. 5, the noise reduction module 60 may include: at least one tenth transistor M10, the first pole is connected to the first clock signal terminal CLK, the gate is connected to the pull-up control node PU, and the second pole Connected to the signal output Output.

 It should be noted that the noise reduction module 60 may also be a plurality of transistors connected in the same manner as the tenth transistor M10. Here, only the noise reduction module in FIG. 4 or FIG. 5 includes only one tenth transistor M10 as an example. The description of the noise reduction module of other structures is no longer here - for example, but it should be within the scope of the invention.

In the embodiment of the present invention, the noise reduction module 60 is configured to output the output through the signal output terminal A signal of the clock signal terminal CLK, thereby reducing the noise of the output signal of the pull-up module 40. Specifically, the tenth transistor M10 and the ninth transistor M9 of the pull-up module 40 are connected in a connection manner as shown in FIG. 4 or FIG. 5, so that the size of the tenth transistor M10 does not need to be large, and The coupling capacitance of the ten-transistor M10 and the ninth transistor M9 is smaller than the coupling capacitance of the ninth transistor M9, thereby reducing the influence of the coupling capacitance of the ninth transistor M9, thereby reducing the noise of the output signal of the pull-up module 40; In general, the use of a shift register to implement GOA is mainly to make the display device have a narrow bezel. Therefore, the number of transistors in each shift register unit is very critical, and the smaller the number of transistors used, the easier it is to implement a narrow bezel. In this embodiment, by increasing the scheme of the transistor, it is verified by experiments that the size of the transistor in the output module can be reduced, thereby implementing the noise reduction function.

 The following takes the structure shown in FIG. 5 as an example and combines the input and output timing charts of the shift register. As shown in FIG. 6, the working process of the shift register unit will be described in detail.

 T1 phase: CLK=0; CLKB=1; Pu=l; Input=l; Output=0; Reset=0. As shown in FIG. 7, since the first signal input terminal Input=1, the first transistor M1 is turned on and controls the shift register to start working, and the first signal input terminal Input pulls up the potential of the control node PU through the first transistor M1. Pull high and charge storage capacitor C1. Since the second clock signal terminal CLKB = 1, the fifth transistor M5 is turned on, pulling the signal output terminal Output low to the low level VGL, and at the same time, the seventh transistor M7 is also turned on, but at the same time, since the pull-up control node PU is Pulled high, so the eighth transistor M8 turns on and pulls the pull-down control node PD low to the low level VGL. This keeps the third transistor M3 and the fourth transistor M4 off, so that the third transistor M3 pulls the pull-up control node PU low to the low level VGL. When the pull-up control node PU is at a high level, the ninth transistor M9 and the tenth transistor M10 are turned on, but since the first clock signal terminal CLK = 0, the signal output terminal Output outputs a low level, and the sixth transistor M6 is turned off. , Avoid pulling the pull-down control node PD high. The T1 phase is the charging phase of capacitor C1 in the shift register.

T2 phase: CLK=1; CLKB=0; Pu=l; lnput=0; Output=l; Reset=0. As shown in FIG. 8, since the first signal input terminal Input = 0, the first transistor M1 is turned off, and the bootstrap action of the capacitor C1 further pulls up the pull-up control node PU. Since the second clock signal terminal CLKB = 0, the fifth transistor M5 is turned off to prevent the fifth transistor M5 from pulling the signal output terminal Output low to the low level VGL, while the seventh transistor M7 is turned off, and the pull-up control node PU When pulled high, the eighth transistor M8 is turned on and the pull-down control node PD is pulled low to the low level VGL, so the pull-down control node PD remains low. Since the first clock signal terminal CLK = 1 Therefore, the ninth transistor M9 and the tenth transistor M10 are turned on when the pull-up control node PU is at a high level, and output a high level on the first clock signal terminal CLK to the signal output terminal Output, and then the signal output terminal Output The high level is output to a row of gate lines corresponding to the shift register unit, so that all thin film transistors on the row gate line in the display area of the liquid crystal panel are turned on, and the data line starts to write signals. The T2 phase is the phase in which the shift register outputs a high level.

 T3 phase: CLK=0; CLKB =1; Pu=0; lnput=0; Output=0; Reset=l. As shown in FIG. 9, since the second signal input terminal is reset = 1, the second transistor M2 is turned on. After the second transistor M2 is turned on, the pull-up control node PU is pulled low to VSS. Further, since the second clock signal terminal CLKB = 1, the fifth transistor M5 and the seventh transistor M7 are turned on. After the fifth transistor M5 is turned on, the signal output terminal Output is pulled low to the low level VGL, so that the signal output terminal Output outputs a low level; after the seventh transistor M7 is turned on, the pull-down control node PD is pulled high (at this time, the pull-up is performed) The control node PU is low, so the eighth transistor M8 is turned off). When the pull-down control node PD is at a high level, the third transistor M3 and the fourth transistor M4 are turned on, the third transistor M3 is turned on to pull the pull-up control node PU down to VGL, and the fourth transistor M4 is turned on to output a signal. The output is pulled low to VGL. Since the third transistor M3 and the fourth transistor M4 can be turned on at the same time, and finally the signal output terminal Output can be outputted low level, when one of the two thin film transistors is damaged, the other can still maintain the signal output end. Output output low level, this setting plays the role of double insurance, which can better avoid the following faults: The output of the signal output becomes high level under the action of other interference signals, and makes a row of gates controlled by it. The line is turned on under the high level, which eventually causes the gate line to open incorrectly.

 T4 phase: CLK=1; CLKB=0; Pu=0; lnput=0; Output=0; Reset=0.

 As shown in Fig. 10, since the second clock signal terminal CLKB = 0 and the second signal input terminal Reset = 0, the seventh transistor M7, the second transistor M2, and the fifth transistor M5 are turned off. Since the first clock signal terminal CLK=1, the sixth transistor M6 is turned on, the level of the pull-down control node PD is pulled low, and the third transistor M3 and the fourth transistor M4 are turned off. The pull-up control node PU=0, so the ninth transistor M9 and the tenth transistor M10 are turned off. The signal output is output low.

 T5 phase: CLK=0; CLKB=1; Pu=0; lnput=0; Output=0; Reset=0.

As shown in FIG. 11, since the second clock signal terminal CLKB = 1, the fifth transistor M5 and the seventh transistor M7 are turned on, so that the pull-down control node PD is at a high level. Therefore, the third transistor M3 and the fourth transistor M4 remain turned on. The third transistor M3 is turned on to pull the pull-up control node PU down to VGL, and the fourth transistor M4 is turned on to pull the signal output terminal down to VGL, thus avoiding the following faults: The signal output terminal becomes high level under the action of other interference signals, and the row line of the gate line controlled by it is turned on under the action of the high level, which eventually causes the grid line to open incorrectly.

 Thereafter, until the next time the first signal input Input is high, the shift register unit repeats the T4 and T5 phases, which may be referred to as the non-working time of the shift register unit. The Tl ~ T3 phase can be referred to as the working time of the shift register unit. As can be seen from the above description, during the non-working time of the shift register unit, when the pull-down control node PD is at a low level, the signal output terminal Output outputs a low level. When the pull-down control unit PD is held at a high level, the third transistor M3 and the fourth transistor M4 are kept turned on, thereby keeping the pull-up control node PU and the signal output terminal low. In the T2 phase, since the ninth transistor M9 is connected in parallel with the tenth transistor M10, the size of the ninth transistor M9 in the pull-up module can be reduced by the noise reduction of the tenth transistor M10, and when the size of the tenth transistor M10 is not required When the time is large, the coupling capacitance of the two transistors connected in parallel is still smaller than the coupling capacitance of the ninth transistor Μ9 when the noise reduction module is not connected, thereby reducing the influence of the coupling capacitance of the ninth transistor Μ9 on the output signal, thereby Reduce the noise of the output signal.

 Embodiments of the present invention provide a gate driving circuit, as shown in FIG. 12, including a plurality of stages of shift register units as described above. Wherein, each row of the shift register unit SR outputs a row scan signal G; each shift register unit has a first clock signal CLK input and a second clock signal CLKB input; the second clock signal CLKB The first clock signal CLK has a phase difference of 180 degrees, and the first clock signal CLK and the second clock signal CLKB both output a high level for half of the respective duty cycles, and the other half outputs a low level.

 VGH can be VDD and VGL can be VSS.

 Except for the first stage shift register unit SR0, the first signal input terminal G(N1) of each of the other shift register units is connected to the signal output terminal Output of the adjacent upper shift register unit except the last stage shift. In addition to the bit register unit SRn, the signal output terminal Output of each of the remaining shift register units is connected to the first signal input terminal G(N1) of the adjacent next-stage shift register unit.

In the embodiment of the present invention, the first signal input terminal G(N1) of the first stage shift register unit SR0 may input the frame start signal STV; the second signal input terminal G (N of the last stage shift register unit SRn) +1) The reset signal RST or the reset signal RST of the output signal Output (Gn) of the last stage shift register unit SRn can be input. The present invention provides a gate drive circuit. The gate driving circuit comprises a level shift register unit, the shift register unit comprises an input module, a control module, a reset module, a pull-up module, a pull-down module and a noise reduction module, and the noise reduction module is connected in parallel with the pull-up module The size of the thin film transistor in the pull-up module can be reduced, which reduces the coupling capacitance of the thin film transistor in the pull-up module, thereby reducing the noise of the output signal.

 Embodiments of the present invention also provide a display device including the gate drive circuit as described above. The present invention provides a display device. The display device includes a gate driving circuit including a level shift register unit, the shift register unit including an input module, a control module, a reset module, a pull-up module, a pull-down module, and a noise reduction module, The noise reduction module in parallel with the pull-up module can reduce the size of the thin film transistor in the pull-up module, thereby reducing the coupling capacitance of the thin film transistor in the pull-up module, thereby reducing the noise of the output signal.

 A person skilled in the art can understand that all or part of the steps of implementing the above method embodiments may be completed by using hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed. The foregoing storage medium includes: ROM, RAM, magnetic disk or optical disk, and the like, which can store various program codes, which are only specific embodiments of the present invention, but the protection of the present invention. The scope of the present invention is not limited thereto, and any variations or substitutions may be conceivable within the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the appended claims.

Claims

claims 1. A shift register unit, characterized in that it includes: an input module, a control module, a reset module, a pull-up module, a pull-down module and a noise reduction module; The input module is respectively connected to the first signal input terminal and the pull-up control node, and is used to control the potential of the pull-up control node according to the signal input by the first signal input terminal; The control module is respectively connected to the first clock signal terminal, the second clock signal terminal, the first voltage terminal, the pull-up control node and the pull-down control node, and is used to control the signal inputted by the first clock signal terminal and the The signal input to the second clock signal terminal or the potential of the pull-up control node controls the potential of the pull-down control node; The reset module is respectively connected to the second signal input terminal, the first voltage terminal, the pull-up control node and the pull-down control node, and is used to reset the pull-up control node according to the signal input by the second signal input terminal. Pull the potential of the control node; The pull-up module is respectively connected to the first clock signal terminal, the pull-up control node and the signal output terminal, and is used to cause the signal output terminal to output the third signal under the control of the pull-up control node potential. a signal at the clock signal end; The pull-down module is respectively connected to the first voltage terminal, the pull-down control node and the signal output terminal, and is used to pull down the signal output by the signal output terminal to low under the control of the pull-down control node potential. level; The noise reduction module is respectively connected to the first clock signal terminal, the pull-up control node and the signal output terminal, and is used to output the signal of the first clock signal terminal through the signal output terminal. 2. The shift register unit according to claim 1, characterized in that the input module includes: The first transistor has a first electrode and a gate connected to the first signal input terminal, and a second electrode connected to the pull-up control node. 3. The shift register unit according to claim 2, characterized in that the reset module includes: The second transistor has a first electrode connected to the pull-up control node, a gate connected to the second signal input terminal, and a second electrode connected to the first voltage terminal; The fifth transistor has a first electrode connected to the signal output terminal and a gate connected to the second signal No. input terminal, the second pole is connected to the first voltage terminal. 4. The shift register unit according to claim 3, characterized in that the pull-down module includes: The third transistor has a first electrode connected to the pull-up control node, a gate connected to the pull-down control node, and a second electrode connected to the first voltage terminal; The fourth transistor has a first electrode connected to the signal output terminal, a gate electrode connected to the pull-down control node, and a second electrode connected to the first voltage terminal. 5. The shift register unit according to claim 1, characterized in that the input module includes: The first transistor has a first electrode connected to the second voltage terminal, a gate electrode connected to the first signal input terminal, and a second electrode connected to the pull-up control node. 6. The shift register unit according to claim 5, characterized in that the reset module includes: The second transistor has a first electrode connected to the pull-up control node, a gate connected to the second signal input terminal, and a second electrode connected to the third voltage terminal. 7. The shift register unit according to claim 6, wherein the pull-down module further includes: The third transistor has a first electrode connected to the pull-up control node, a gate connected to the pull-down control node, and a second electrode connected to the first voltage terminal; The fourth transistor has a first pole connected to the signal output terminal, a gate connected to the pull-down control node, and a second pole connected to the first voltage terminal; The fifth transistor has a first electrode connected to the signal output terminal, a gate electrode connected to the second clock signal terminal, and a second electrode connected to the first voltage terminal. 8. The shift register unit according to any one of claims 1 to 7, characterized in that the control module includes: The sixth transistor has its gate connected to the first clock signal terminal, its first pole connected to the second clock signal terminal, and its second pole connected to the pull-down control node; The seventh transistor has a first electrode and a gate connected to the second clock signal terminal, and a second electrode connected to the pull-down control node; The eighth transistor has a first electrode connected to the pull-down control node, a gate electrode connected to the pull-up control node, and a second electrode connected to the first voltage terminal. 9. The shift register unit according to any one of claims 1 to 7, characterized in that the pull-up module includes: The ninth transistor has a first pole connected to the first clock signal terminal, a gate connected to the pull-up control node, and a second pole connected to the signal output terminal; A capacitor connected between the gate electrode and the second electrode of the ninth transistor. 10. The shift register unit according to any one of claims 1 to 7, characterized in that the noise reduction module includes: At least one tenth transistor has a first pole connected to the first clock signal terminal, a gate connected to the pull-up control node, and a second pole connected to the signal output terminal. 11. A gate drive circuit, characterized in that it includes multiple stages of the shift register unit according to any one of claims 1 to 10; Except for the first-level shift register unit, the signal input end of each remaining shift register unit is connected to the signal output end of the adjacent upper-level shift register unit; Except for the last stage shift register unit, the signal output end of each shift register unit is connected to the signal input end of its adjacent next stage shift register unit. 12. A display device, characterized by comprising the gate driving circuit as claimed in claim 11.