WO2015008385A1 - Power module - Google Patents

Abstract

The present invention increases the reliability of a power module and decreases unevenness in characteristics of an SiC unipolar element stemming from unevenness in epi concentration of an SiC wafer. The power module is configured from at least two types of elements differing from each other in surface structure as SiC elements having the same function connected in parallel. When a JBS-structured Schottky barrier diode is used as an SiC element, the on voltage (Vf) is controlled by changing the pattern shape at an n-type semiconductor region and a p-type semiconductor region at the surface, thus cancelling Vf fluctuations stemming from epi concentration.

Description

Power module

The present disclosure relates to a power module, and can be applied to, for example, a semiconductor power module using silicon carbide as a raw material.

In power conversion equipment represented by inverters, power semiconductors are used as main components with rectification and switching functions. Silicon is currently the mainstream material for power semiconductors, but development toward the adoption of silicon carbide (SiC), which has excellent physical properties, is in progress.

SiC has a dielectric breakdown electric field strength that is an order of magnitude higher than that of silicon (Si), is suitable for high voltage applications, has a thermal conductivity three times that of Si, and is less likely to lose its semiconductor properties even at high temperatures. Resistant to rising and can reduce the resistance of the element, it is suitable as a power semiconductor material.

Especially, the development of a hybrid module in which the switching diode and the rectifying element of the power module that constitutes the inverter are replaced with the SiC rectifier free-wheeling diode (free wheeling diode) has been preceded. The reason is that the rectifying element has a simple structure and operation compared to the switching element, facilitates the development of the element, and clearly shows the merit of greatly reducing the switching loss.

As the rectifying element of SiC, SBD having a JBS (Junction Barrier controlled Schottky) structure capable of suppressing reverse leakage current is used (Patent Document 1). Some documents refer to a similar structure as an MPS (Merged PiN Schottky) structure. Depending on which of the two effects is important, leakage current suppression and the use of hole injection from the pn junction may be used separately. However, in the present disclosure, no distinction is made, and this is hereinafter referred to as a JBS structure.

International Publication No. 2011/151901

The sensitivity and temperature characteristics with respect to the impurity concentration (epi concentration) of the epitaxial layer of the unipolar element, combined with the multi-parallel usage of the SiC chip, especially the variation in the epi concentration of the SiC wafer will lower the module reliability.

Other problems and novel features will become apparent from the description of the present disclosure and the accompanying drawings.

The outline of typical ones of the present disclosure will be briefly described as follows.

That is, in the power module, SiC unipolar elements having the same function connected in parallel are composed of at least two kinds of elements having different surface structures.

Specifically, the power module of the present invention includes a first unipolar semiconductor element configured with a silicon carbide chip, and a second unipolar semiconductor element configured with a silicon carbide chip different from the silicon carbide chip. The first unipolar semiconductor element provides the same function as the second unipolar semiconductor element, and the first unipolar semiconductor element is electrically connected in parallel to the second unipolar semiconductor element, The surface structure of the first unipolar semiconductor element is different from the surface structure of the second unipolar semiconductor element.

According to the above power module, it is possible to reduce the variation in characteristics caused by the variation in the epitaxial concentration of the SiC wafer.

FIG. 6 is a schematic diagram illustrating a difference in SBD patterns according to the first embodiment. It is an external view of a power module. It is a figure which shows the circuit structure of a power module. It is sectional drawing of SBD of a simple structure. It is sectional drawing of SBD of a JBS structure. It is sectional drawing of SBD of the JBS structure which introduce | transduced the current spreading layer. It is an external view of a Si / SiC hybrid module 1 is an external view of a Si / SiC hybrid module according to Example 1. FIG. FIG. 6 is a relationship diagram between an impurity concentration of an epi layer and an on-voltage of an SBD according to Example 1. It is explanatory drawing of SBD of the JBS structure which concerns on Example 1. FIG. FIG. 3 is a relationship diagram between an on-voltage and an SBD reverse ratio according to the first embodiment. It is a schematic diagram of the relationship between the impurity concentration of the epi layer which concerns on a comparative example, and the ON voltage of SBD. FIG. 6 is a schematic diagram of a relationship between an impurity concentration of an epi layer and an on-voltage of an SBD according to Example 1. It is explanatory drawing of SBD of the JBS structure at the time of blocking which concerns on Example 1. FIG. It is explanatory drawing of the line & space pattern of SBD of the JBS structure which concerns on Example 1. FIG. It is explanatory drawing of the line & space pattern of SBD of the JBS structure which concerns on Example 1. FIG. It is explanatory drawing of the line & space pattern of SBD of the JBS structure which concerns on Example 1. FIG. It is explanatory drawing of the matrix pattern of SBD of the JBS structure which concerns on the modification 2. FIG. It is explanatory drawing of the matrix pattern of SBD of the JBS structure which concerns on the modification 2. FIG. 6 is a cross-sectional view of a planar SiC-MOSFET according to Embodiment 4. FIG. 10 is a cross-sectional view of a trench type SiC-MOSFET according to Example 5. FIG.

First, the results of the study of the power module using SiC by the inventors will be described below.

Conventional power modules use silicon IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Field Field Effect Transistors) as switching elements, and Si PN diodes are used as free-wheeling diodes combined in reverse parallel with these switching elements. It was. FIG. 2 shows an external view of the power module, and FIG. 3 shows a circuit configuration. The power module 20 includes an IGBT 23 and a Si PN diode 24 connected in parallel to the IBGT 23. The collector terminal C is connected to the collector electrode of the IGBT 23 and the cathode electrode of the PN diode 24. An emitter electrode of the IGBT 23 and an anode electrode of the PN diode 24 are connected to the emitter terminal E. An IGBT gate electrode is connected to the gate terminal G. Four module substrates 50 are stored in the case 25. Each module substrate 50 is configured by mounting four chips of IGBTs 23 and four chips of free-wheeling diodes (PN diodes) 24 in an insulating substrate 22. Each module substrate 50 is in electrical contact with the outside through electrode terminals 21 (collector terminal C, emitter terminal E, etc.). FIG. 2 shows, as an example, a 1 in 1 configuration in which a single power module is combined with a set of IGBTs and diodes. One power module 20 constitutes, for example, an upper arm or a lower arm of the inverter.

Here, it is reported that if the Si PN diode is replaced with a SiC Schottky barrier diode (SBD, Schottky Barrier Diode), the switching loss is reduced to 1/10 because there is no recovery current. This is because minority carriers accumulated during switching flow as a recovery current in the PN diode of the bipolar element, but minority carriers are not accumulated in the SBD of the unipolar element. It is possible to manufacture SBD with silicon, but if the thickness of the body layer is increased in order to increase the breakdown voltage, the resistance increases, which is not practical. By using low-resistance SiC, it becomes possible to apply the SBD of a unipolar element to a high breakdown voltage region where a conventional Si SBD with a breakdown voltage of 600 V to 3.3 kV could not be applied.

A problem when the Si PN diode in the conventional power module is replaced with the SBD of the SiC unipolar element will be described below.

(1) SBD
The disadvantage of SBD is that leakage current from the Schottky barrier tends to increase when a high voltage is applied in the off state. Although depending on the metal species constituting the Schottky junction, the barrier height of the Schottky junction is lower than the barrier height of the pn junction, so that a leak current tends to increase when a strong electric field is applied. As a countermeasure, an SBD having a JBS structure is used.

For comparison, FIG. 4 shows a normal simple structure SBD, and FIG. 5 shows a JBS structure SBD. The SBD 51 having a simple structure shown in FIG. 4 has the following configuration. An n-type epi layer (drift layer) 10 is formed on n + -type SiC substrate 5. Terminations 13 and channel stoppers 14 are formed near both ends in the drift layer 10. A Schottky electrode 15 is formed on the drift layer 10. An anode electrode 6 is formed on the Schottky electrode 15. A cathode electrode 3 is formed under SiC substrate 5.

The SBD 52 having the JBS structure shown in FIG. 5 has a p-type impurity region 2 formed in the n-type impurity region 1 on the surface of the SiC substrate (the surface of the drift layer 10) in addition to the configuration of the SBD 51 having a simple structure. . In the off state, the cathode electrode 3 side in FIG. 5 is at a positive potential, so that the pn junction 4 is reverse-biased, and the depletion layer extending from the junction relaxes the high electric field on the surface of the Schottky junction, thereby reducing the leakage current.

The SBD 52 with the JBS structure in the on state has a loss due to an increase in resistance because the cross-sectional area through which current flows near the Schottky junction is reduced by the area of the p-type impurity region 2. Normally, the ratio of this loss is small as a whole, but FIG. 6 shows a structure for further reducing the loss due to the increase in resistance. In the SBD 53 having the JBS structure, the n + region (current dispersion layer) 11 is formed in the vicinity of the p-type impurity region 2 by increasing the concentration of the n-type impurity region by ion implantation. The resistance of the current path 12 confined by the n + region (current dispersion layer) 11 can be reduced, and the current path can be extended to the lower part of the p-type impurity region 2. It can be reduced to the extent that it is not inferior to the (simple structure) SBD.

(2) SiC crystal Although the JBS-structured SBD has made it possible to reduce the leakage current, there is a problem to be solved in the SiC crystal itself when replacing the Si PN diode.
(A) Crystal size One of the reasons is that the size of the SiC crystal is small and the mass productivity is low. Even in the case of 4H—SiC crystal, which is most often used in power semiconductors, 4 inches are still mainstream, and mass production of 6 inches is still in the stage of starting. 8 inches is for power semiconductors and is different from mainstream Si.
(B) Crystal Defects Further, from the viewpoint of crystal quality, SiC has more crystal defects such as epi defects than Si, causing a decrease in yield.
For these reasons, it is necessary to connect a large number of chips in parallel in the module in addition to improving the current density in order to allow the same current to flow by designing the SiC diode to have a smaller chip size than the Si diode. . The JBS structure is effective in improving the yield in principle because the area of the Schottky junction region sensitive to surface defects is reduced.
(C) Epi concentration variation In relation to the quality of the SiC crystal, the impurity concentration of the epi layer of the wafer is also more varied at this stage than Si. SiC wafers must accept variations of several percent to several tens of percent within a plane and about 10% between wafers. This is larger than the normal silicon content of 5%, and the mobility fluctuates due to variations in the epi concentration. As a result, in SiC, there is a problem in that the loss and the variation in heat generation of each element tend to increase.

(3) Unipolar element Due to the excellent physical properties of SiC, it has become possible to apply unipolar elements such as SBD and MOSFET to high-voltage applications. On the other hand, since the number of carriers is proportional to the impurity concentration, the unipolar element is characterized in that the bulk resistance of the epi layer is sensitive to changes in the impurity concentration. For example, in a bipolar device such as a PN diode, since the minority carriers injected from the pn junction in addition to the majority carriers also contribute to conduction, the number of carriers is not determined only by the impurity concentration. On the other hand, in a unipolar element such as SBD, since the carrier concentration is proportional to the impurity concentration, the resistance varies by the same rate when the impurity concentration varies. A high breakdown voltage product having a breakdown voltage of several kV or more poses a serious problem in a high breakdown voltage product having a breakdown voltage of several kV or more because the resistance of the epi layer occupies much of the entire element.

In addition to this, since the unipolar element has a higher resistance increase rate at a higher temperature than the bipolar element, the effect of variation in impurity concentration appears greatly. According to the technical document 1, the mobility of SiC decreases in inverse proportion to the 2.4th power of the absolute temperature T. That is, the resistance is inversely proportional to the mobility and is proportional to T to the 2.4th power, and increases remarkably at high temperatures.

Technical Reference 1: K. Sheng, “Maximum Junction Temperatures of SiC Power Devices”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 2, FEBRUARY 2009
On the other hand, as described above, the variation in the impurity concentration of the epitaxial layer of the SiC wafer is large, so that the problem becomes more serious for the SiC unipolar element that is easily affected by the variation in the impurity concentration.

(4) Power module In addition, SiC has a significant effect of variation by connecting many small-area chips in parallel as compared with Si. FIG. 2 shows an external view of a power module of silicon withstand voltage of 3.3 kV and 1200A. The power module 20 includes four module substrates 50. Each module substrate 50 is constituted by using four chips of IGBT elements 23 and PN diodes 24 on the insulating substrate 22. In the power module 20, an IGBT element 23 and a PN diode 24 are mounted in 16 chips each.

FIG. 7 shows an external view of the Si / SiC hybrid module. 10 chips of SiC diodes 27 replacing the PN diode 24 of Si are used for one module substrate 50A, and 40 chips are mounted in the Si / SiC hybrid module (power module) 20A. In addition to the large original variation, the maximum and minimum widths of chip characteristics are further expanded by increasing the number of mounted chips more than twice.

From the viewpoint of power module performance, the variation in epi resistance causes the on-voltage (Vf) of the diode to vary. In the case of SBD, Vf is expressed as the sum of the built-in voltage (Vbi) of the Schottky junction and the potential drop (Vepi) in the epi layer, that is, Vf = Vbi + Vepi. The effect of Vepi reaching ˜3V is large. If there is a difference in the ON voltage of each chip of the diodes connected in parallel in the power module, the voltage between the terminals is the same, so that a current larger than the surroundings flows in a chip with a low ON voltage, that is, a low resistance. The reliability determined by the upper limit of the amount of current that can flow, such as surge resistance, is limited by this chip, so the reliability margin is reduced by the amount of variation. In a chip in which a larger current flows than the surroundings, the conduction loss expressed by voltage × current also increases, and the chip temperature also rises from the surroundings. The maximum temperature in the power module is determined by this chip, and the margin of reliability items having strong temperature dependence such as power cycle resistance is similarly reduced.

As described above, the sensitivity and temperature characteristics of the unipolar element with respect to the epi concentration and the temperature characteristics, and the use of multiple SiC chips in parallel, combine with the epi concentration variation of the SiC wafer, particularly reducing the reliability of the power module. The inventors have paid attention to a problem inherent to a power module using this SiC unipolar element, and have proposed a new variation reducing method.

In this embodiment, a power module using a SiC unipolar element has at least two types of SiC elements having the same function, which are connected in parallel to each other, in order to solve the problems caused by the variation in the epitaxial concentration of the SiC wafer. It consists of the above elements. For example, an SBD with a simple structure and an SBD with a JBS structure have the same function and different surface structures. Further, the planar MOSFET and the trench MOSFET have the same function and have different surface structures. However, SBD and MOSFET are not SiC elements having the same function.

The difference in the surface structure between the elements is provided such that the resistance of each element is different in a direction that cancels out the difference in conduction loss corresponding to the difference in the epitaxial concentration of the SiC wafer. Below, the example of the difference of the surface structure between elements is demonstrated.
(A) SBD with JBS structure
When the unipolar element is an SBD having a JBS structure, an element in which the area ratio between the p-type impurity region and the n-type impurity region on the wafer surface is changed is combined as a difference in surface structure. In addition, in the case of an SBD having a JBS structure and an n + region (current distribution layer) having a high impurity concentration in an n-type impurity region, the impurity concentration of the current distribution layer or the depth of the impurity profile is changed as a difference in the surface structure. Combined elements.
(B) SBD (SBD having a simple structure or SBD having a JBS structure)
When the unipolar element is SBD, elements having different metal species forming a Schottky junction are used as the difference in surface structure. Examples of the metal forming the Schottky junction include nickel (Ni), titanium (Ti), manganese (Mn), molybdenum (Mo), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), Palladium (Pd), hafnium (Hf), chromium (Cr), tungsten (W), or the like is used.
Due to the difference in the surface structure provided for each of the diodes (1) and (2), the difference in on-voltage (Vf) is reduced between elements having different epi concentrations.
(C) MOSFET
When the unipolar element is a MOSFET, elements having different gate lengths are combined as a difference in surface structure. As another method, there is a method of combining elements having different impurity concentrations or impurity profiles in the MOS channel portion. Further, in the case of a planar MOSFET, there is a method of combining elements having different widths of JFET (Junction Field Effect Transistor) regions between opposing MOSs. A method of combining elements having different structures of the planar MOSFET and the trench MOSFET can also be applied.
Due to the difference in surface structure provided for each MOSFET in (c) above, the difference in on-resistance (R _on ) between elements having different epi concentrations is reduced.

The power module including the SiC element according to the present embodiment has different element surface structures so as to eliminate differences in element resistance such as on-voltage (Vf) and on-resistance (R _on ) caused by the difference in epi concentration. Manufactured and combined. As a result, SiC wafers with large variations in epi concentration are used, unipolar elements that are sensitive to epi concentration are used, and a large number of small chips are combined in parallel to ensure the yield. Even if the variation is outside the range normally assumed, this can be reduced to a range where there is no problem.

∙ By suppressing resistance variation between elements connected in parallel in the power module, it is possible to suppress variation in on-current between elements. When viewed for each element, the worst value of the on-current is reduced by the amount of variation suppression, so that the reliability of the module whose maximum current such as surge resistance is the dominant factor can be improved.

By reducing the variation in on-current, the variation in conduction loss of each element is also reduced. As a result, the heat generation is also approached uniformly, so that the maximum temperature (Tj _max ) of the element is also reduced by the variation. The maximum temperature greatly affects the reliability of solder bonding and wire bonding. In particular, since the reliability of repeated thermal cycles such as power cycle resistance is sensitive to the maximum temperature, the reliability can be improved by reducing variations in the maximum temperature.

In summary, this embodiment reduces variations in device resistance inside the power module and suppresses the maximum current and temperature of the device by the amount of variation, so it can withstand surge current resistance and power cycle resistance. Thus, a decrease in reliability due to the maximum temperature can be suppressed.

Hereinafter, examples and modifications will be described with reference to the drawings. However, in the following description, the same components are denoted by the same reference numerals, and repeated description is omitted.

As a first embodiment, FIG. 8 shows an external view of a power module in which SBDs having different JBS structures are combined, and FIG. 1 is a schematic diagram for explaining a difference in SBD patterns to be combined.

A Si IGBT 23 and SiC JBS SBDs 28 and 29 are mounted on the insulating substrate 22 of the module substrate 50B constituting the power module 20B of FIG. Here, each of the SBDs 28 and 29 has the same configuration as the SBD 53 having the JBS structure having the current spreading layer of FIG. 6, but the patterns of the p-type impurity region 2 and the n-type impurity region 1 are different between the SBD 28 and the SBD 29. The power module 20B is a 1 in 1 type having a breakdown voltage of 3.3 kV and a current of 1200 A. SBD 28 and SBD 29 differ in the impurity concentration of the epitaxial layer 10 of the wafer. For example, the n-type impurity concentration of the epi layer 10 of the SBD 28 wafer is 3.2 × 10 ¹⁵ cm ⁻³ , and the n-type impurity concentration of the epi layer 10 of the SBD 29 wafer is 2.8 × 10 ¹⁵ cm ⁻³ . . Since the breakdown voltage is 3.3 kV, the thickness of the epi layer is 30 μm, and the center value of the n-type impurity concentration is 3.0 × 10 ¹⁵ cm ⁻³ .

FIG. 9 shows the relationship between the impurity concentration of the epi layer and the on-voltage (Vf) of the SBD. As described above, in the unipolar SBD, Vf is sensitive to the epi concentration, and in the case of the illustrated 125 ° C., when the epi concentration varies by 10%, Vf varies by about 8%. The epiconcentration of the SiC wafer varies in the worst ± 8% within the wafer and 10% between the wafers. Therefore, the epiconcentration between the chips varies in the worst case ± 18%. Therefore, Vf varies ± 15% between the chips in the worst case. Here, a part of the SBD is formed as a p-type impurity region on the n-type SiC substrate (SBD having a JBS structure).

FIG. 10 is an explanatory diagram of an SBD having a JBS structure according to the first embodiment. FIG. 11 is a relationship diagram between the on-voltage and the SBD reverse ratio according to the first embodiment. In FIG. 11, the solid line indicates the relationship between the on-voltage and the epi concentration, and the broken line indicates the relationship between the on-voltage and the SBD reverse ratio. Vf can be changed by changing the area ratio of the p-type impurity region / n-type impurity region of the SBD having the JBS structure. As the p-type impurity region / n-type impurity region, a line & space pattern of a p-type impurity region (p-type semiconductor region) 2 and an n-type impurity region (n-type semiconductor region) 1 was formed as shown in FIG. Vf decreases as the area of the n-type impurity region through which current flows increases. Here, the SBD inverse ratio is defined as follows.
SBD reverse ratio = (S _N + S _P ) / S _N
However,
S _N : n-type impurity region area S _P : p-type impurity region area As shown in FIG. 11, Vf changes in proportion to the SBD inverse ratio. When the SBD reverse ratio is changed by 1, there is a sensitivity that Vf changes by 0.08V. This is used to cancel the variation in Vf due to the epi concentration. Specifically, the epi density measurement data at the time of wafer delivery, SBD inverse ratio with respect to the wafer of 3.0 × ¹⁰ 15 ^{cm -3} or more concentrations of the design center of the 4.6 line and space pattern (Fig. 11) and a line and space pattern (A in FIG. 11) having an SBD inverse ratio of 1 was applied to wafers having a concentration lower than 3.0 × 10 ¹⁵ cm ⁻³ .

FIG. 12 shows a schematic diagram of the relationship between the impurity concentration of the epi layer and the on-voltage of the SBD according to the comparative example. FIG. 13 shows a schematic diagram of the relationship between the impurity concentration of the epi layer and the SBD on-voltage according to Example 1. FIG.
The distribution of Vf in the case of the comparative example in which one type of line & space pattern is applied using this wafer is shown in FIG. 12, corresponding to the epiconcentration variation ± 15%, Vf variation width ΔVf = 0. .8V. On the other hand, as shown in FIG. 13, ΔVf is corrected by using two types of patterns according to the first embodiment (a line & space pattern with an SBD reverse ratio of 1 and a line & space pattern with an SBD reverse ratio of 4.6). The distribution width can be reduced to 0.5V. Similarly, it is possible to further reduce the distribution width by increasing the number of patterns to three types and four types, but a desired number of patterns may be selected in consideration of an increase in the number of masks and man-hours.

The design line & space ratio of the SBD with JBS structure is controlled according to the epi concentration of the SiC wafer and the finished Vf is aligned. By feeding forward the epiconcentration of the incoming wafer and using different masks, it is possible to control the process to offset the Vf difference between wafers and within the wafer surface.

The pattern can be changed simply by specifying in advance the mask to be applied when the wafer is put into the previous process line, and no additional process occurs. It is not necessary to form a cutting-edge fine pattern as a mask, and an inexpensive i-line mask can be applied. Therefore, the cost of preparing a mask with a plurality of patterns is sufficiently smaller than the cost of an expensive SiC wafer. Rather, the wafer yield that can achieve the target Vf is improved, and the wafer cost can be reduced.

FIG. 14 is an explanatory diagram of an SBD having a JBS structure during blocking according to the first embodiment. Here, as a method of changing the pattern of the line and space, a method of changing the width of the p-type impurity region of the p-type impurity region / n-type impurity region and fixing the width of the n-type impurity region is used. As shown in FIG. 14, the width of the n-type impurity region is set to be equal to or smaller than the width at which the depletion layer 8 extends and the Schottky junction is shielded during blocking. As a result, the electric field of the Schottky junction is relaxed and the amount of leakage current is reduced. Therefore, a method of fixing the width of the n-type impurity region is desirable for the purpose of controlling the leakage current amount.

15, 16, and 17 are explanatory diagrams of the line and space pattern of the SBD having the JBS structure according to the first embodiment. 15, 16, and 17 show patterns in which the line & space is changed while the width 7 of the n-type impurity region is fixed when three types of patterns are used. The p-type impurity region width: n-type impurity region width in FIG. 15 is 0.7 μm: 1.3 μm. The p-type impurity region width: n-type impurity region width in FIG. 16 is 1.3 μm: 1.3 μm. The p-type impurity region width: n-type impurity region width in FIG. 17 is 2.7 μm: 1.3 μm. That is, the width 7 of the n-type impurity region is fixed at 1.3 μm.

As other conditions, the Schottky electrode 15 is formed of titanium with a thickness of 50 nm, the nitrogen ion implantation conditions for forming the current spreading layer 11 are a total dose of 1.6 × 10 ¹² cm ^−2, and the epitaxial layer ( The drift layer 10) has a thickness of 30 μm, the SiC substrate 5 uses 4H-SiC that is off by 4 degrees, the p-type impurity region 2 is formed by using aluminum as an impurity, and a total dose of 1.8 × 10 ^14. It is formed by ion implantation at a concentration of cm ⁻² . The depth of the p-type impurity region 2 is 0.75 μm. A structure in which TiN 50 nm is formed as a barrier layer on the Schottky electrode 15 and aluminum 5 μm is formed thereon as a metal film for wire bonding (anode electrode 6).

For the purpose of controlling the leakage current at the time of blocking after determining the desired Vf, the area ratio between the p-type impurity region 2 and the n-type impurity region 1 is kept constant and the pitch of the line & space pattern is changed. To do. Vf is determined by the area ratio of the p-type impurity region / n-type impurity region, and Vf can be reduced as the proportion of the area occupied by the n-type impurity region is increased. The amount of leakage current is determined by the width 7 of the n-type impurity region, and the leakage current can be reduced as the width 7 of the n-type impurity region is reduced.

<Modification 1>
For the purpose of increasing the change width of Vf on the lower Vf side, as a first modification, the width of the p-type impurity region is fixed opposite to that of the first embodiment, and the n-type impurity is changed. A method of changing the width of the region can be used. When the width of the n-type impurity region is increased, the function of the JBS structure as an SBD cannot be obtained if the depletion layer extends beyond the width that can shield the Schottky junction, and the leakage current is equivalent to that of the simple structure SBD. There are disadvantages. However, since the advantage that the surge resistance is improved by injecting holes from the p-type impurity region at the time of high temperature or large current injection does not change, it is meaningful to form the p-type impurity region.

<Modification 2>
As a second modification, a case where a matrix pattern is used instead of the line & space pattern will be described with respect to the first embodiment. FIGS. 18 and 19 are explanatory diagrams of the matrix pattern of the SBD having the JBS structure according to the second modification. If the pattern is compared to a sea island, the n-type impurity region 1 is the sea and the p-type impurity region 2 is the island. Vf is changed by enlarging the size of the p-type impurity region as shown in FIG. 19 without changing the width 7 of the n-type impurity region. When the matrix pattern is used, Vf is reduced because the area of the n-type impurity region is larger even if the width 7 of the n-type impurity region is the same as the line & space pattern even when the width 7 of the n-type impurity region is the same. There is an advantage that can.

As a second embodiment, a method of changing the metal type of the SBD Schottky electrode in order to control the on-voltage (Vf) will be described. Ti, Ag, Mn, Hf, Pt, Co, Pd, Ni, Au, Cr, W, etc. are used as the main metal species (barrier metal) for forming the Schottky junction from the lowest barrier (barrier). it can. The barrier height varies in the range of about 0.8 to 1.3 eV (Technical Document 2). Vf can be changed according to the barrier height simply by changing the metal species to be sputtered in the formation process of the Schottky electrode 15. For the first embodiment, a simple structure SBD is used instead of a JBS structure SBD. Specifically, Ni and Ti are selectively used as barrier metals. With a simple structure SBD, Vf at 125 ° C. is obtained when Ni is used, Vf = 3.8 V, and when Ti is used, Vf = 3.5 V is obtained. By using the difference 0.3V between the two, the difference in Vf due to the epi concentration can be offset. Note that the same amount of Vf shift can be obtained in principle even when an SBD having a JBS structure is used. Since this method differs in the formation process of the Schottky electrode, there is a disadvantage that the number of process steps increases compared to the method of changing only the mask described above. However, since the SBD structure is not limited, the JBS structure SBD has a simple structure. There are advantages that can be applied to other SBDs.

Technical Literature 2: T.Teraji, S. Hara, H.Okushi, and K.Kajimura, “Ideal Ohmic contact to n-type 6H-SiC by reduction of Schottky barrier height”, Appl. Phys. Lett. 71, 689 1997)

As a third embodiment, a method using the impurity concentration of the current dispersion layer as a control parameter with respect to the first embodiment will be described. As shown in FIG. 10, in the SBD having the JBS structure, a current distribution layer 11 that increases the n-type impurity concentration of the n-type epi layer near the wafer surface as compared with the epi layer (drift layer) 10 is formed. Due to the effect of the current spreading layer, the resistance of the n-type impurity region 1 for confining the current is reduced, and the current path is extended to the lower part of the p-type impurity region 2, so that Vf can be lowered. As the n-type impurity, nitrogen is implanted by an ion implantation method. In this case, a total dose amount of 1.6 × 10 ¹² cm ⁻³ is formed by multi-stage implantation up to 30 to 700 keV to form an n + type current spreading layer 11 having a depth of 0.8 μm. With or without the current spreading layer 11, it is possible to cause a change in Vf of 0.3 V from Vf = 3.6 V to Vf = 3.3 V at 125 ° C. Since Vf can be controlled arbitrarily within this range, the Vf difference caused by the difference in epi concentration can be canceled out. Note that the relationship between the impurity implantation amount of the current spreading layer 11 and Vf depends on the pattern size of the SBD of the JBS structure, the impurity concentration of the p-type impurity region 2, and the concentration and thickness of the epi layer 10, respectively. Although the absolute value of the Vf change amount varies depending on the condition of the item, it can be adjusted within a normal design range.

As a method for canceling the Vf difference caused by the difference in wafer epi concentration, a method for changing the pattern shape of the JBS structure (Example 1), a method for changing the metal type of the Schottky junction (Example 2), The method of changing the impurity injection conditions of the current spreading layer (the present embodiment) has been described, but it is possible not only to use each method alone, but also to obtain the effect by combining the above. Although the design is more complicated than when performed alone, there is an advantage that the controllable Vf range is widened.

Next, the case where the semiconductor element is a SiC-MOSFET will be described. Even when the SiC-MOSFET is used, since it is the same unipolar element as the SiC-SBD, the on-resistance during conduction is sensitive to the impurity concentration of the epi layer.

As a fourth embodiment, a method of combining elements having different MOSFET gate lengths with respect to the deviation from the design value of the impurity concentration of the epi layer will be described. FIG. 20 is a sectional view of a planar type SiC-MOSFET. The MOSFET 61 has a DMOSFET structure in which MOSFETs are formed on both sides of the gate electrode 31. The MOSFET 61 has the following configuration. An n-type epi layer (drift layer) 10 is formed on n + -type SiC substrate 5. A p-type impurity region (p base) 33 is formed in the drift layer 10, and an n-type impurity region (source) 32 and a contact p + layer 42 are formed in the p base 33. An insulating film 44 such as SiO ₂ is formed on the source 32. A gate electrode 31 is formed on the drift layer 10 and the p base 33 via a gate insulating film 43. A contact silicide region 35 is formed on the source 32 and the contact p + layer 42. The gate electrode 31 is covered with an insulating film 45 such as SiO ₂ . A source electrode (not shown) is connected on the contact silicide region 35. Except for the wire bonding region of the source electrode and the gate electrode 31, it is covered with a passivation SiO ₂ film 37. A drain electrode 36 is formed under the SiC substrate 5. Current flows from the drain electrode 36 through the channel 38 to the source 32 in the direction of arrow 39. For this reason, even when the potential drop of the epi layer 10 varies, the channel resistance can be changed and canceled by changing the gate length 40. The relationship between the gate length 40 and the channel resistance is such that the channel resistance increases when the gate length 40 is extended.

<Modification 3>
As a third modification, the channel resistance may be changed by changing the impurity concentration of the channel portion 38, while changing the gate length of the fourth embodiment. In the case of an n-type MOSFET, increasing the p-type impurity concentration of the channel 38 increases the threshold voltage, resulting in an increase in the ratio of channel resistance.

<Modification 4>
As a fourth modified example, in the planar MOSFET of FIG. 20, the width of the JFET region 41 also contributes to the overall resistance as a JFET resistance component, so the resistance may be controlled by changing this width. Although there is a disadvantage that the layout is changed by changing the pitch between the MOSFETs on both sides, there is an advantage that the design is easy because the overall resistance can be controlled without changing the characteristics of the MOS channel.

<Modification 5>
As a fifth modification, the channel resistance may be changed by changing the gate length 40 or the impurity concentration of the channel portion 38 of a trench MOSFET of Example 5 described later.

As a fifth embodiment, a method of combining a planar MOSFET and a trench MOSFET will be described. FIG. 21 shows a cross-sectional view of the trench MOSFET. The trench MOSFET 62 has the same components as the planar MOSFET 61, but is different in structure. The trench type MOSFET 62 has the gate electrode 31 embedded in the trench and the channel 38 is formed in the vertical direction with respect to the substrate. Therefore, the trench type MOSFET 62 has higher mobility than the planar type MOSFET due to the crystal orientation. Since the formed JFET region 41 does not exist, the on-resistance (R _on ) is lower than that of the planar MOSFET. By utilizing this difference, the resistance difference caused by the difference in impurity concentration of the epi layer 10 can be offset. For example, if the sheet resistance normalized by the area in the planar type MOSFET of 600V voltage and _{R on A,} when R on A = 2mΩcm ² is obtained, _R on A = 1.3mΩcm ² In the trench MOSFET is obtained The epi-resistance difference can be offset.

8 is mounted with the SiC-MOSFET of the fourth embodiment, the fifth embodiment, or the third to fifth modifications instead of the IGBT 23 on the insulating substrate 22 constituting the power module 20B of FIG. In this case, the drain electrode of the SiC-MOSFET is connected to the collector terminal C of the power module 20B, the source electrode is connected to the emitter terminal E, and the gate electrode is connected to the gate terminal G.

The power modules according to Examples 1 to 5 and Modifications 1 to 5 are applicable to inverters such as railways / steel, elevators, wind power, mega solar, industrial equipment, and hybrid electric vehicles.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments, examples, and modifications. However, the present invention is not limited to the above-described embodiments, examples, and modifications. It goes without saying that various changes can be made.

1 SiC substrate surface n-type impurity region 2 p-type impurity region 3 cathode electrode 4 pn junction 5 SiC substrate 6 anode electrode 7 width of n region 8 depletion layer 10 drift layer (epi layer)
11 n + region (current dispersion layer)
12 Current Path 13 Termination 14 Channel Stopper 15 Schottky Electrode 20, 20A, 20B Power Module 21 Electrode Terminal 22 Insulating Substrate 23 IGBT
24 diode 25 case 26 cover 27 SiC diode 28 SiC diode (pattern A)
29 SiC diode (pattern B)
31 Gate electrode 32 Source region 33 p Base region 34 Source contact region 35 Silicide layer 36 Drain electrode 37 Passivation SiO ₂ film 38 Channel 39 Current direction 40 Gate length 41 JFET region width 42 Contact p + layer 43 Gate insulating film 44 Insulating film 45 Insulating film 61 Planar type MOSFET
62 Trench MOSFET

Claims (15)

A first unipolar semiconductor element composed of a silicon carbide chip;
A second unipolar semiconductor element composed of a silicon carbide chip different from the silicon carbide chip;
With
The first unipolar semiconductor element provides the same function as the second unipolar semiconductor element,
The first unipolar semiconductor element is electrically connected in parallel to the second unipolar semiconductor element;
The surface structure of the first unipolar semiconductor element is different from the surface structure of the second unipolar semiconductor element.
Power module. In claim 1,
The impurity concentration of the epi layer of the first unipolar semiconductor element is different from the impurity concentration of the epi layer of the second unipolar semiconductor element.
Power module. In claim 1,
Each of the first and second unipolar semiconductor elements is a Schottky barrier diode.
Power module. In claim 3,
Each of the first and second unipolar semiconductor elements has a junction barrier Schottky structure;
The shape of the p-type semiconductor region and the n-type semiconductor region on the element surface of the first unipolar semiconductor element is different from the shape of the p-type semiconductor region and the n-type semiconductor region on the element surface of the second unipolar semiconductor element.
Power module. In claim 4,
A dimension of the n-type semiconductor region of the first unipolar semiconductor element is the same as a dimension of the n-type semiconductor region of the second unipolar semiconductor element;
A dimension of the p-type semiconductor region of the first unipolar semiconductor element is different from a dimension of the p-type semiconductor region of the second unipolar semiconductor element;
Power module. In claim 4,
The dimension of the p-type semiconductor region of the first unipolar semiconductor element is the same as the dimension of the p-type semiconductor region of the second unipolar semiconductor element;
A dimension of the n-type semiconductor region of the first unipolar semiconductor element is different from a dimension of the n-type semiconductor region of the second unipolar semiconductor element;
Power module. In any one of Claims 4-6,
The structures of the p-type semiconductor region and the n-type semiconductor region on the device surface of the first and second unipolar semiconductor devices are line and space patterns, respectively.
Power module. In claim 3,
The metal species forming the Schottky junction on the surface of the first unipolar semiconductor element is different from the metal species forming the Schottky junction on the surface of the second unipolar semiconductor element.
Power module. In claim 3,
Each of the first and second unipolar semiconductor elements has a junction barrier Schottky structure;
The first and second unipolar semiconductor elements each include a current distribution region having an impurity concentration higher or equal to the n-type semiconductor region in the p-type semiconductor region and the n-type semiconductor region on the surface of each element,
The impurity concentration of the current distribution region of the first unipolar semiconductor element is different from the impurity concentration of the current distribution region of the second unipolar semiconductor element.
Power module. In claim 1,
Each of the first and second unipolar semiconductor elements is a MOSFET,
The MOSFET structure of the first unipolar semiconductor element is different from the MOSFET structure of the second unipolar semiconductor element.
Power module. In claim 10,
Each of the first and second unipolar semiconductor elements is a planar MOSFET,
The dimension of the JFET region of the MOSFET of the first unipolar semiconductor element is different from the dimension of the JFET region of the MOSFET of the second unipolar semiconductor element.
Power module. In claim 10,
The first unipolar semiconductor element is a planar MOSFET, and the second unipolar semiconductor element is a trench MOSFET.
Power module. A first Schottky barrier diode composed of a silicon carbide chip having an epi layer with a first impurity concentration;
A second Schottky barrier diode composed of a silicon carbide chip having an epi layer with a second impurity concentration;
With
The first impurity concentration is different from the second impurity concentration,
The first Schottky barrier diode is electrically connected in parallel to the second Schottky barrier diode;
The surface structure of the first Schottky barrier diode is different from the surface structure of the second Schottky barrier diode.
Power module. In claim 14,
Each of the first and second Schottky barrier diodes has a junction barrier Schottky structure;
The shapes of the p-type semiconductor region and the n-type semiconductor region on the element surface of the first Schottky barrier diode are different from the shapes of the p-type semiconductor region and the n-type semiconductor region on the element surface of the second Schottky barrier diode,
Power module. In claim 14,
The dimension of the n-type semiconductor region of the first Schottky barrier diode is the same as the dimension of the n-type semiconductor region of the second Schottky barrier diode;
A dimension of the p-type semiconductor region of the first Schottky barrier diode is different from a dimension of the p-type semiconductor region of the second Schottky barrier diode;
Power module.

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