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WO2015089892A1 - 一种阵列基板及其制造方法和显示装置 - Google Patents

一种阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2015089892A1
WO2015089892A1 PCT/CN2014/000562 CN2014000562W WO2015089892A1 WO 2015089892 A1 WO2015089892 A1 WO 2015089892A1 CN 2014000562 W CN2014000562 W CN 2014000562W WO 2015089892 A1 WO2015089892 A1 WO 2015089892A1
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WO
WIPO (PCT)
Prior art keywords
layer
array substrate
bonding
layers
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2014/000562
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English (en)
French (fr)
Inventor
罗强强
权基瑛
周保全
曲坤
李震芳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Hefei BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US14/408,289 priority Critical patent/US20160282659A1/en
Publication of WO2015089892A1 publication Critical patent/WO2015089892A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1341—Filling or closing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H10W90/00—
    • H10W72/073—
    • H10W72/07352—
    • H10W72/074—
    • H10W72/321—
    • H10W72/325—
    • H10W72/352—
    • H10W72/353—
    • H10W72/354—
    • H10W72/931—
    • H10W72/944—
    • H10W72/953—
    • H10W90/732—
    • H10W90/734—

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method of manufacturing the same, and a display device. Background technique
  • ICs integrated circuits
  • PCBs printed circuit boards
  • Bonding Pad bonded pads on array substrates
  • gate electrode pad For large-size display products, it also includes gate electrode pad (Gate Pad) and source/drain pad (S/D Pad), while small size (generally 7 inches or less) display products are usually only available.
  • a pad ie, Pad
  • the gate electrode layer uses GOA (Gate Driver on Array) technology without IC binding, or COG (Chip On Glass abbreviation) technology, that is, directly IC or A chip having an IC is fabricated on a glass substrate, and an IC and a glass substrate are electrically connected by an ACF (an anisotropic conductive film).
  • ACF an anisotropic conductive film
  • the technical problem to be solved by the present invention is how to avoid the occurrence of binding abnormalities due to the gasket.
  • the present invention provides an array substrate, wherein a peripheral area of the array substrate is provided with a plurality of signal lines, and each of the signal lines is provided with at least two different portions for connecting with the driving integrated circuit chip.
  • the number of the bonding layers is two, one of the bonding layers is disposed in the same layer and the same material as the source and drain metal layers on the array substrate, and the other bonding layer is the same as the gate electrode layer on the array substrate. Layer settings and materials are the same.
  • the conductive metal layer is formed in the same layer as the transparent conductive layer in the array substrate. Further, the conductive metal layer is provided with an opening for guiding the output end of the signal line to the surface of the array substrate and connecting with the driving integrated circuit chip.
  • the plurality of signal lines are divided into at least two layers, and the bonding layers disposed between the signal lines of each layer and the portion connected to the driving integrated circuit chip do not overlap each other.
  • the present invention further provides a method of manufacturing a display device, comprising: forming a pattern including a plurality of signal lines in a peripheral region of the array substrate by a first patterning process; Forming a pattern of at least two bonding layers of different thicknesses at each of the signal lines for connecting to the driving integrated circuit chip; forming a pattern of the conductive metal layer by a third patterning process, and each of the bonding The layers are electrically connected by the conductive metal layer.
  • each of the bonding layers is formed of a metal material.
  • one bonding layer is disposed in the same layer and the same material as the source/drain metal layer on the array substrate, and another bonding layer It is disposed in the same layer as the gate electrode layer on the array substrate and has the same material.
  • the conductive metal layer is formed in the same layer as the conductive conductive layer in the array substrate.
  • the method further includes: forming a hole in the conductive metal layer to lead the output end of the signal line to the surface of the array substrate to be connected to the driving integrated circuit chip.
  • the plurality of signal line patterns formed in the first patterning process are divided into at least two layers, and the bonding layers disposed between the signal lines of each layer for connecting with the driving integrated circuit chip do not overlap each other.
  • the present invention further provides a display device including a driving integrated circuit chip, and further comprising the above array substrate, wherein the bonding layer on the array substrate passes through the anisotropic conductive paste and the driving Integrated circuit chip connection.
  • An array substrate and a display device provided by an embodiment of the present invention, wherein an array substrate
  • the structure is characterized in that a plurality of signal lines are disposed in a peripheral area of the array substrate, and each of the signal lines is provided with at least two bonding layers of different thicknesses at a portion connected to the driving integrated circuit chip, and each bonding layer is electrically conductive
  • the metal layer is electrically connected.
  • the present invention is designed to change at least two bonding layer structures of a whole piece of the prior art, that is, to include two bonding layers of different thicknesses at one bonding position, and to pass two layers through the conductive metal layer.
  • the present invention also provides a display device based on the above array substrate, wherein the adhesive layer on the array substrate is connected to the driving integrated circuit chip in the display device through the anisotropic conductive paste.
  • FIG. 1 is a schematic cross-sectional view of a display device provided by the prior art
  • Figure 2 is a partial exploded view of the position of the gasket after the prior art IC is bonded
  • Figure 3 is a cross-sectional view of the structure of Figure 2 taken along the ⁇ - ⁇ direction;
  • Figure 4 is a cross-sectional view of the structure of Figure 2 taken along the ⁇ - ⁇ direction;
  • FIG. 5 is a partial exploded view of a bonding pad provided by the first embodiment of the present invention after IC bonding;
  • Figure 6 is a cross-sectional view of the structure of Figure 5 taken along the line C - C in the first embodiment of the present invention
  • Figure 7 is a cross-sectional view of the structure of Figure 5 taken along the line DD in the first embodiment of the present invention
  • FIG. 1 is a schematic cross-sectional view of a bonded spacer in an integrated circuit.
  • a bonding pad 3 is disposed in a peripheral region of the array substrate 4, and the IC 1 is electrically connected to the bonding pad 3 through the ACF glue 2.
  • double-layer wiring is generally used to save space.
  • the signal line 20 is divided into two layers, one layer is ⁇ - ⁇ '; the other layer is ⁇ - ⁇ ,
  • the two layers of the signal line 20 are provided with bonding layers 6 and 8 at positions connected to the driving IC 1, and the driving IC 1 and the bonding layers 6 and 8 are respectively realized by the ACF glue 2 Electrical connection.
  • FIG. 1 also shows a cross-sectional structural view of the display area of the array substrate in the liquid crystal display panel, that is, the frame pointed by the number 5, because the partial structure is the array substrate and the color film substrate in the prior art, and the liquid crystal is filled between them. The structure, no longer entertained here.
  • the signal line 20 disposed on the periphery of the array substrate 4 passes through the bonding pad.
  • ACF glue 2 is connected with the driving IC 1.
  • the ACF glue 2 realizes the function of the opposite conduction by doping the conductive gold ball in the glue, and can conduct electricity only when the gold ball is deformed to a certain extent by pressing (gold ball)
  • the outside is an insulating layer, which will be destroyed after being deformed by pressing).
  • the schematic diagram of the structure shown in Fig. 2 along A-A is shown in Fig. 3, and the schematic diagram taken along B-B is shown in Fig. 4.
  • 4 1 is a driving IC
  • 4 is an array substrate
  • 6 is an adhesive layer formed in the same layer as the G layer (gate electrode layer)
  • 8 is an S/D layer (source/drain metal layer)
  • 9 is an insulating layer
  • 10 is a conductive ball
  • 11 is a conductive metal layer.
  • an insulating layer 9 is formed over the array substrate 4, and the insulating layer 9 is formed with an adhesive layer 8 formed in the same layer as the S/D layer of the display region, and an S/b layer.
  • An insulating layer 9 is also formed over the bonding layer 8 formed in the same layer, and the insulating layer portion above the bonding layer 8 is etched away, and a conductive metal layer 11 is formed over the insulating layer 9 of the region.
  • the bonding layer 6 formed in the same layer as the G layer is formed by the patterning process on the array substrate 4, and the insulating layer 9 is formed on the bonding layer 6 formed in the same layer as the G layer, similarly to G.
  • the insulating layer 9 above the bonding layer 6 formed by the same layer is partially etched away, and a layer of metal is deposited as a conductive metal layer 1 1 over the remaining insulating layer 9, and only the adhesion formed by the same layer as the G layer is left after etching.
  • the conductive ball 10 is located between the driving IC 1 and the conductive metal layer 11, and the conductive metal layer 11 is connected to the signal line (the signal lines are not shown in Figs. 3 and 4). Since the conductive ball 10 is an outer layer having an insulating layer and a conductive material inside, the insulating layer of the outer layer is destroyed only when it is deformed by compression, thereby achieving a conductive function, and FIG. 3 and FIG. 4 are different. The difference is that: in FIG. 3, the adhesive layer 8 formed in the same layer as the S/D layer is further provided with an insulating layer 9, so that the distance between the driving IC 1 and the bonding layer 8 is smaller, and the conductive ball is compressed. Good electrical conductivity.
  • the two spacers respectively form two spacers, the two spacers having different thicknesses, thereby electrically connecting between the two bonding layers and the driving IC.
  • the metal materials and thicknesses of the G layer and the S/D layer are generally different, which results in a bonding pad and an S/D layer formed in the same layer as the G layer.
  • There is a difference in thickness between the bonding pads formed by the same layer which in turn affects the success rate of the binding.
  • process fluctuations such as the G layer and the S/D layer are offset during the exposure process, the binding pads of the binding area are misaligned, which may cause binding abnormalities.
  • an array substrate is provided in the first embodiment of the present invention.
  • the peripheral area of the array substrate is provided with a plurality of signal lines 20, and each of the signal lines 20 is provided with at least two portions for connecting with the driving integrated circuit chip.
  • Bonding layers 6 and 8 of different thicknesses are electrically connected between the bonding layers through the conductive metal layer 11.
  • the conductive metal layer 11 may be formed in the same layer as the transparent conductive layer in the array substrate.
  • the transparent conductive layer may be made of Indium Tin Oxide (ITO) or Indium Zinc (Indium Zinc). Oxide, referred to as IZO) or other transparent conductive materials.
  • the transparent conductive layer may be a pixel electrode layer or a common electrode layer in the array substrate.
  • Each of the bonding layers may be made of a metal material.
  • the bonding layers 6 and 8 are both metal layers.
  • the number of the bonding layers is two, and one of the bonding layers 8 is disposed in the same layer and the same material as the S/D layer on the array substrate, and the other bonding layer 6 is on the array substrate.
  • the G layers are set in the same layer and have the same material.
  • the conductive metal layer 11 is provided with openings for leading the output end of the signal line 20 to the surface of the array substrate and to the driving integrated circuit chip.
  • the plurality of signal lines 20 are divided into at least two layers.
  • different fillings indicate two layers of signal lines, and each layer of signal lines is disposed between the signal lines for driving the integrated circuit chip.
  • the bonding layers do not overlap each other.
  • FIG. 5 A partially exploded view of the above bonded pad after IC bonding is shown in FIG. 5, and includes a conductive metal layer 11 and a bonding layer 6 formed in the same layer as the G layer and a bonding layer formed in the same layer as the S/D layer.
  • the conductive metal layer 11 may be formed of a transparent metal oxide such as an ITO layer.
  • the improvement of the present invention is that a gasket comprises two bonding layers of different thicknesses, that is, one bonding layer 6 formed in the same layer as the G layer, and the other bonding layer formed in the same layer as the S/D layer. 8. Therefore, it can also be said that a spacer in the embodiment includes two parts, that is, a first spacer and a second spacer, both of which are on a signal line and pass through the conductive metal layer 1 1 1 The connection between the two is sufficient to avoid thickness differences due to the presence of the gasket.
  • FIG. 7 a schematic diagram of the structure of FIG. 5 taken along CC, as shown in FIG. 6, and a schematic diagram of the structure of FIG. 5 along DD, is shown in FIG. 7, wherein FIG. 6 and FIG. 7
  • the driver IC 1 , the array substrate 4 , the bonding layer 6 formed in the same layer as the G layer, the bonding layer 8 formed in the same layer as the S/D layer, the insulating layer 9, the conductive ball 10 and the conductive metal layer 1 1 are all included.
  • a bonding layer 6 formed in the same layer as the G layer on the array substrate 4 is formed over the array substrate 4 by one patterning process, and an insulating layer is formed over the bonding layer 6 formed in the same layer as the G layer. 9.
  • the insulating layer 9 over the bonding layer 6 formed in the same layer as the G layer is partially etched away, leaving only a portion of the insulating layer 9. Thereafter, a bonding layer 8 formed in the same layer as the S/D layer may be formed, and then, a conductive metal layer 1 1 in the same layer as the transparent conductive layer in the array substrate may be formed, wherein the conductive metal layer 11 includes the bonding layer 6 And a portion above the bonding layer 8, the last conductive ball 10 is located between the driving IC 1 and the conductive metal layer 11.
  • the conductive metal layer 11 can also be formed by a separate process, for example, by depositing a bonding layer 8 formed with the same layer of the poison layer and the bonding layer 8 formed with the same layer as the S/D layer. The metal layer is finally etched to leave only the conductive metal layer 1 1 with the bonding layer 6 and the upper portion of the bonding layer 8 and the upper portion of the insulating layer 9 and the edge of the insulating layer 9 to form the conductive metal layer 11.
  • FIG. 6 shows one of the signal lines: the conductive ball 10 at the bonding layer 6 formed in the same layer as the G layer is not compressed, and is formed in the same layer as the S/D layer.
  • the conductive ball 10 at the bonding layer 8 is compressed, and the other signal line is shown in Fig. 7:
  • the conductive ball 10 at the bonding layer 6 formed in the same layer as the G layer is not compressed, and is the same as the S/D layer.
  • the conductive balls at the bonding layer 8 formed by the layers are compressed.
  • there may be multiple cases or the conductive balls at the two bonding layers at each signal line may be compressed, or the conductive balls at any one of the signal lines may be compression.
  • each layer of the signal line or the spacer on each of the signal lines includes two different thicknesses of the bonding layer 6, 8 , it can always be proved in at least one bonding layer.
  • the electrical connection with the driver IC 1 is achieved through the conductive metal layer 11 and the conductive ball 10.
  • the binding gasket in this embodiment has only one pad by changing the existing gasket.
  • the design structure of the chip, two metal pads respectively formed in the same layer as the G layer and the S/D layer are disposed at one binding position, and the two are connected by a conductive metal layer, thereby avoiding film thickness difference and metal layer offset The resulting binding exception, reducing the occurrence of poor wiring due to binding exceptions.
  • the present invention also provides a method of manufacturing a display device.
  • the flow chart of the steps is as shown in FIG. 8, and specifically includes the following steps:
  • Step S101 forming a pattern including a plurality of signal lines in a peripheral region of the array substrate by using a first patterning process
  • Step S102 forming, by using a second patterning process, a pattern of at least two bonding layers of different thicknesses at each of the signal lines for connecting to the driving integrated circuit chip;
  • Step S103 forming a pattern of a conductive metal layer by a third patterning process, and each of the bonding layers is electrically connected by a conductive metal layer.
  • each of the bonding layers in this embodiment may be formed of a metal material.
  • one bonding layer is disposed in the same layer as the S/D layer on the array substrate, and the material is the same, and the other bonding
  • the junction layer is disposed in the same layer as the G layer on the array substrate and has the same material.
  • the conductive metal layer is formed in the same layer as the transparent conductive layer of the array substrate ⁇ in the third patterning process in this embodiment.
  • the method further comprises: forming a hole in the conductive metal layer to lead the output end of the signal line to the surface of the array substrate to be connected to the driving integrated circuit chip.
  • the plurality of signal line patterns formed in the first patterning process in the embodiment are divided into at least two layers, and the bonding layers disposed between the signal lines of each layer for connecting with the driving integrated circuit chip do not overlap each other. .
  • the manufacturing method of the array substrate provided in the embodiment, by changing the design structure of the existing spacer having only one spacer, two metals respectively formed in the same layer as the G layer and the S/D layer are disposed at one binding position.
  • the spacers are connected by a conductive metal layer to avoid binding abnormalities caused by film thickness difference and metal layer offset, and to reduce wiring defects caused by binding abnormalities.
  • Embodiment 3 of the present invention further provides a display device including a driving integrated circuit chip, and including the array substrate provided by the foregoing embodiments of the present invention,
  • the bonding layer on the array substrate is connected to the driving integrated circuit chip through an anisotropic conductive paste.

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Abstract

一种阵列基板（4）及其制造方法和显示装置，其中阵列基板（4）的结构是在阵列基板（4）的周边区域设置有多根信号线（20），每一根信号线（20）用于与驱动集成电路芯片（1）连接的部位设置有至少两个不同厚度的粘结层（6、8），各粘结层（6、8）之间通过导电金属层（11）电连接。通过将现有技术中一整片的粘结层改变设计成至少两个粘结层结构，即在一个绑定位置处包括两个不同厚度的粘结层（6、8），并通过导电金属层（11）将二者连接，可以避免膜厚差异和金属层的偏移造成的绑定异常，减少由于绑定异常造成的布线不良的发生，提高产品质量。所述显示装置中，阵列基板（4）上的粘结层（6、8）通过各向异性导电胶（2）与显示装置中的驱动集成电路芯片（1）连接。

Description

一种阵列基板及其制造方法和显示装置 技术领域
本发明涉及显示技术领域， 特别涉及一种阵列基板及其制造方法 和显示装置。 背景技术
在阵列基板设计以及加工流程中， 集成电路 ( Integrated Circuit, 简称 IC )对电极引线和印刷电路板（ Printed Circuit Board , 简称 PCB ) 起到重要作用，尤其是对阵列基板上的绑定垫片（ Bonding Pad )和 PCB 板路连接。
对于大尺寸的显示产品一般还包括栅电极层垫片（即 Gate Pad )和 源漏层垫片 （即 S/D Pad ) , 而小尺寸 （一般是指 7寸以下） 的显示产 品， 通常只有一个垫片 （即 Pad ) , 栅电极层采用 GOA ( Gate Driver on Array, 阵列基板行驱动）技术不进行 IC绑定， 或者是采用 COG ( Chip On Glass的简称）技术， 即直接将 IC或者是具有 IC的芯片制作在玻 璃基板上，并且 IC和玻璃基板之间通过 ACF胶（ Anisotropic Conductive Film, 即各向异性导电胶）导通。 目前小尺寸产品的垫片设计一般是采 用两层布线， 可以节省空间。
但是采用双层布线的设计存在不足之处， 即不同层的膜厚差异 影响绑定效果， 另外由于工艺波动造成不同层的布线发生偏移也会影 响绑定效果， 导致绑定设备对位报警严重时发生绑定异常。 发明内容
(一）要解决的技术问题
本发明要解决的技术问题是如何避免由于垫片造成绑定异常现象 的发生。
(二）技术方案
为解决上述技术问题， 本发明提供了一种阵列基板， 所述阵列基 板的周边区域设置有多根信号线， 每一根信号线用于与驱动集成电路 芯片连接的部位设置有至少两个不同厚度的粘结层， 各所述粘结层之 间通过导电金属层电连接。 进一步地， 各所述粘结层为金属材料制成。
进一步地， 所述粘结层的数量为两个， 其中一个粘结层与阵列基 板上的源漏金属层同层设置且材料相同， 另一粘结层与阵列基板上的 栅极电极层同层设置且材料相同。
进一步地， 所述导电金属层与阵列基板中的透明导电层同层形成。 进一步地， 所述导电金属层设有开孔用于将信号线的输出端引出 到阵列基板的表面并与驱动集成电路芯片连接。
进一步地， 所述多根信号线分为至少两层， 每层信号线之间用 f 与驱动集成电路芯片连接的部位设置的粘结层互不重叠。 - 为解决上述技术问题， 本发明还提供了一种显示装置的制造方法， 包括： 通过第一次构图工艺在所述阵列基板的周边区域形成包括多根 信号线的图形； 通过第二次构图工艺在每一根信号线用于与驱动集成 电路芯片连接的部位形成至少两个不同厚度的粘结层的图形； 通过第 三次构图工艺形成导电金属层电的图形， 且各所述粘结层之间通过所 述导电金属层电连接。
进一步地， 各所述粘结层采用金属材料形成。
进一步地， 所述第二次构图工艺形成两个不同厚度的粘结层的图 形的步骤中， 一个粘结层与阵列基板上的源漏金属层同层设置且材料 相同， 另一粘结层与阵列基板上的栅极电极层同层设置且材料相同。
进一步地， 所述第三次构图工艺中导电金属层与阵列基板中的導 明导电层同层形成。
进一步地， 所述第三次构图工艺后还包括： 在所述导电金属层上 开孔， 以将信号线输出端引出到阵列基板的表面与驱动集成电路芯片 连接。
进一步地， 所述第一次构图工艺中形成的多根信号线图形分为至 少两层， 每层信号线之间用于与驱动集成电路芯片连接的部位设置的 粘结层互不重叠。
为解决上述技术问题， 本发明还提供了一种显示装置， 包括驱动 集成电路芯片， 还包括以上所述的阵列基板， 所述阵列基板上的粘结 层通过各向异性导电胶与所述驱动集成电路芯片连接。
(三）有益效果
本发明实施例提供的一种阵列基板和显示装置， 其中阵列基板的 结构是在阵列基板的周边区域设置有多根信号线， 每一根信号线用于 与驱动集成电路芯片连接的部位设置有至少两个不同厚度的粘结层， 各粘结层之间通过导电金属层电连接。 本发明通过将改变现有技术中 一整片的粘结层设计成至少两个粘结层结构， 即在一个绑定位置处包 括两个不同厚度的粘结层， 并通过导电金属层将二者连接， 可以避 膜厚差异和金属层的偏移造成的绑定异常， 减少由于绑定异常造成 布线不良的发生， 提高产品质量。 同时本发明还提供了一种基于上述 阵列基板的显示装置， 其中阵列基板上的粘结层通过各向异性导电胶 与显示装置中的驱动集成电路芯片连接。 附图说明
图 1是现有技术提供的显示装置的截面示意图；
图 2是现有技术 IC绑定后垫片位置处的部分分解视图；
图 3是对图 2中结构沿 Α-Α，方向的剖视图；
图 4是对图 2中结构沿 Β-Β，方向的剖视图；
图 5是本发明实施例一中提供的一种邦定垫片进行 IC绑定后的部 分分解视图；
图 6是本发明实施例一中对图 5中结构沿 C - C，方向的剖视图； 图 7是本发明实施例一中对图 5中结构沿 D-D，方向的剖视图； 图 8是本实施例二中提供的一种阵列基板的制造方法的步骤流程 图。 具体实施方式
下面结合附图和实施例， 对本发明的具体实施方式作进一步详细 描述。 以下实施例用于说明本发明， 但不用来限制本发明的范围。
现有的绑定垫片、 驱动集成电路 IC与阵列基板的位置关系示意图 如图 1 所示。 具体地， 图 1 为集成电路中绑定垫片的截面示意图。 在 阵列基板 4的周边区域设置有绑定垫片 3， IC 1通过 ACF胶 2与绑定 垫片 3 电连接。 小尺寸的显示产品在进行外围布线时， 为了节省空间 一般使用双层布线，参照图 2所示，信号线 20分为两层，一层为 Α-Α'; 另一层为 Β-Β，， 信号线 20的这两层在与驱动 IC 1连接的位置均设置 有粘结层 6和 8, 并通过 ACF胶 2分别实现驱动 IC 1与粘结层 6和 8 的电连接。
图 1 的右侧还示出了液晶显示面板中阵列基板显示区域的截面结 构图， 即编号 5 指向的框， 由于该部分结构就是现有技术中阵列基板 和彩膜基板以及他们之间填充液晶的结构， 此处不再赘迷。
参照图 2所示， 设置在阵列基板 4周边的信号线 20通过绑定垫片
3和 ACF胶 2与驱动 IC 1连接， ACF胶 2是通过在胶里面掺杂可导电 的金球实现各向导电的功能， 且只有当金球被压变形到一定程度后 能导电 （金球外面是一层绝缘层， 被压变形后绝缘层会被破坏） 。 对 图 2中结构沿 A-A，剖开得到的示意图如图 3所示， 沿 B-B，剖开得到的 示意图如图 4所示。 在图 3和图 4中， 1为驱动 IC， 4为阵列基板， 6 为与 G层 （栅极电极层） 同层形成的粘结层， 8为与 S/D层 （源漏金 属层） 同层形成的粘结层， 9为绝缘层， 10为导电球， 以及 1 1为导电 金属层。在图 3所示的结构中，阵列基板 4的上方形成有一层绝缘层 9， 该绝缘层 9上形成有与显示区域的 S/D层同层形成的粘结层 8， 与 S/b 层同层形成的粘结层 8上方还形成有绝缘层 9,并且粘结层 8上方的绝 缘层部分被刻蚀掉， 并在该区域的绝缘层 9 上方形成一层导电金属层 1 1。 而在图 4中， 阵列基板 4上方经过一次构图工艺形成与 G层同层 形成的粘结层 6,在与 G层同层形成的粘结层 6上方还形成有绝缘层 9， 同样与 G层同层形成的粘结层 6上方的绝缘层 9被部分刻蚀掉， 在 留的绝缘层 9上方沉积有一层金属作为导电金属层 1 1 , 经过刻蚀只保 留与 G层同层形成的粘结层 6上方和绝缘层 9上方部分区域以及绝缘 层 9边缘的导电金属层 1 1。 最后， 导电球 10位于驱动 IC 1和导电金 属层 11之间， 导电金属层 11连接信号线 （图 3和图 4中未示出信号 线） 。 由于导电球 10是一种外层具有绝缘层、 内部含有导电材质的拿 球， 只有在它被压变形的情况下外层的绝缘层会被破坏， 进而实现导 电功能， 图 3和图 4不同之处在于： 图 3中形成与 S/D层同层形成的 粘结层 8之前还有一层绝缘层 9， 所以驱动 IC 1与粘结层 8之间的距 离更小， 导电球被压缩， 导电良好。
因此通过对比图 3和图 4可知， 对于图 3中所示的粘结层 8和显 示区域中的 S/D层同层形成的情形， 此处的导电球被压缩变形， 能够 实现驱动 IC 1与导电球下方的导电金属层 1 1之间良好的导通，即绑 良好， 但是对于图 4中所示的粘结层 6和阵列基板 4上 G层同层形 A 的情形， 此处的导电球没有被压缩变形， 无法实现驱动 IC 1与导电率 下方的导电金属层 11之间良好的导通， 即出现绑定不良。 图 3和图 中所示的两种粘结层 8和 6分别形成两个垫片， 两个垫片具有不同 厚度， 进而通过两种粘结层和驱动 IC之间实现电连接。 更进一步地， 为了满足电阻率和降低成本等目的， 一般 G层和 S/D层的金属材质和 厚度不一样， 这样会导致与 G层同层形成的绑定垫片和与 S/D层同层 形成的绑定垫片之间存在厚度差异， 进而影响绑定的成功率。 另外， 由于工艺波动， 例如在曝光过程中会造成 G层和 S/D层发生偏移， 因 此造成该绑定区域的绑定垫片错位， 这会造成绑定异常。
实施例一
基于上述， 本发明实施例一中提供了一种阵列基板， 该阵列基板 的周边区域设置有多根信号线 20， 每一根信号线 20用于与驱动集成电 路芯片连接的部位设置有至少两个不同厚度的粘结层 6和 8， 各粘结畢 之间通过导电金属层 11电连接。
例如， 导电金属层 11可以与阵列基板中的透明导电层同层形成, 该透明导电层所采用的材料可以为铟锡氧化物 ITO ( Indium Tin Oxide, 简称 ITO ) 、 铟锌氧化物 (Indium Zinc Oxide, 简称 IZO ) 或其他透明导 电材料。 该透明导电层可以是阵列基板中的像素电极层或者公共电极 层。
其中各粘结层可由金属材料制成。 具体地， 粘结层 6和 8均为金属 层。 ； 优选地在本实施例中， 粘结层的数量为两个， 其中一个粘结层 8与 阵列基板上的 S/D层同层设置且材料相同， 另一粘结层 6与阵列基板上 的 G层同层设置且材料相同。
优选地在本实施例中， 导电金属层 11设有开孔用于将信号线 20的 输出端引出到阵列基板的表面并与驱动集成电路芯片连接。
优选地在本实施例中， 多根信号线 20分为至少两层， 在图 5中利 不同填充表示两层信号线， 每层信号线之间用于与驱动集成电路芯片 连接的部位设置的粘结层互不重叠。
上述绑定垫片进行 IC绑定后的部分分解视图如图 5所示, 包括导电 金属层 11以及与 G层同层形成的粘结层 6和与 S/D层同层形成的粘结层
8, 其中的导电金属层 11可以由例如 ITO层的透明金属氧化物形成。 本发明的改进点就是在于一个垫片包括两个不同厚度的粘结层， 即一个是与 G层同层形成的粘结层 6，另一个是与 S/D层同层形成的粘结 层 8。 因此也可以说本实施例中的一个垫片包括两部分， 即第一垫片和 第二垫片， 这两个垫片均在一层信号线上， 并通过导电金属层 1 1实 ί|1 两者之间的连接， 够避免由于垫片的存在导致的厚度差异。
进一步地， 对图 5中结构沿着 C-C，剖开得到的示意图如图 6所示， 对图 5中结构沿着 D-D，剖开得到的示意图如图 7所示， 其中图 6中和图 7 中都包括驱动 IC 1、 阵列基板 4、 与 G层同层形成的粘结层 6、 与 S/D层 同层形成的粘结层 8、 绝缘层 9、 导电球 10和导电金属层 1 1。 图 6中经过 一次构图工艺在阵列基板 4的上方形成有与阵列基板 4上的 G层同层形 成的粘结层 6， 继续在与 G层同层形成的粘结层 6上方形成有绝缘层 9， 与 G层同层形成的粘结层 6上方的绝缘层 9被部分刻蚀掉 ,只保留部分的 绝缘层 9。 之后可形成与 S/D层同层形成的粘结层 8, 然后， 可形成与阵 列基板中的透明导电层同层的导电金属层 1 1， 其中导电金属层 1 1包括 位于粘结层 6和粘结层 8上方的部分，最后导电球 10位于驱动 IC 1和导 金属层 1 1之间。
当然， 该导电金属层 1 1也可通过单独的工艺形成， 例如， 在与 (3毒 同层形成的粘结层 6和与 S/D层同层形成的粘结层 8的上方再沉积一层 金属层， 最后经过刻蚀只保留与粘结层 6和粘结层 8上方和绝缘层 9上方 部分区域以及绝缘层 9边缘的导电金属层 1 1， 以形成该导电金属层 1 1。
参见图 6和图 7所示， 图 6所示为其中一根信号线中： 与 G层同层形 成的粘结层 6处的导电球 10未被压缩， 与 S/D层同层形成的粘结层 8处的 导电球 10被压缩， 图 7所示为另一根信号线中： 与 G层同层形成的粘结 层 6处的导电球 10未被压缩， 与 S/D层同层形成的粘结层 8处的导电球被 压缩。 当然， 具体情况可以有多种， 也可能是各信号线处的两个粘结 层处的导电球均会被压缩， 或者是一根信号线中的其中任一个粘结层 处的导电球被压缩。 总之， 与现有技术相比， 由于每一层信号线或考 说每一根信号线上的垫片都包括两种不同厚度的粘结层 6、 8 , 总能 证在至少一个粘结层 6、 8处通过导电金属层 11和导电球 10实现与驱 IC 1的电连接。藉此，避免了当一根信号线上只有一种厚度的金属层时， 由于金属层偏移导致的绑定不良现象的发生。
综上所迷， 本实施例中的绑定垫片通过改变现有垫片只有一个垫 片的设计结构， 在一个绑定位置设置分别与 G层和 S/D层同层形成的两 个金属垫片， 并通过导电金属层将二者连接， 可以避免膜厚差异和金 属层偏移造成的绑定异常， 减少由于绑定异常造成的布线不良的发生。
实施例二
本发明还提供了一种显示装置的制造方法， 步骤流程图如图 8所 示， 具体包括以下步骤：
步骤 S101 , 通过第一次构图工艺在阵列基板的周边区域形成包括 多根信号线的图形；
步骤 S102， 通过第二次构图工艺在每一根信号线用于与驱动集成 电路芯片连接的部位形成至少两个不同厚度的粘结层的图形；
步骤 S 103 , 通过第三次构图工艺形成导电金属层电的图形， 且各 粘结层之间通过导电金属层电连接。
优选地， 本实施例中的各粘结层可由金属材料形成。
优选地， 本实施例中第二次构图工艺形成两个不同厚度的粘结层 的图形的步骤中， 一个粘结层与阵列基板上的 S/D层同层设置且材料相 同， 另一粘结层与阵列基板上的 G层同层设置且材料相同。
优选地， 本实施例中第三次构图工艺中导电金属层与阵列基板† 的透明导电层同层形成。
优选地， 本实施例中第三次构图工艺后还包括： 在导电金属层上 开孔， 以将信号线输出端引出到阵列基板的表面与驱动集成电路芯片 连接。
优选地， 本实施例中第一次构图工艺中形成的多根信号线图形分 为至少两层， 每层信号线之间用于与驱动集成电路芯片连接的部位设 置的粘结层互不重叠。
通过使用本实施例中提供的阵列基板的制造方法， 通过改变现有 垫片只有一个垫片的设计结构， 在一个绑定位置设置分别与 G层和 S/D 层同层形成的两个金属垫片， 并通过导电金属层将二者连接， 可以避 免膜厚差异和金属层的偏移造成的绑定异常， 减少由于绑定异常造成 的布线不良的发生。
实施例三
本发明实施例三还提供了一种显示装置， 该显示装置包括驱动集 成电路芯片， 并且包括由本发明的前述实施例提供的阵列基板， 所述 阵列基板上的粘结层通过各向异性导电胶与所述驱动集成电路芯片连 接。
以上实施方式仅用于说明本发明， 而并非对本发明的限制， 有关 技术领域的普通技术人员， 在不脱离本发明的精神和范围的情况下， 还可以做出各种变化和变型， 因此所有等同的技术方案也属于本发明 的范畴， 本发明的专利保护范围应由权利要求限定。

Claims

权 利 要 求
1. 一种阵列基板， 所述阵列基板的周边区域设置有多根信号线， 其特征在于， 每一根信号线用于与驱动集成电路芯片连接的部位设置 有至少两个不同厚度的粘结层， 各所述粘结层之间通过导电金属层电 连接。
2. 如权利要求 1所述的阵列基板， 其特征在于， 各所述粘结层由金 属材料制成。
3. 如权利要求 1所述的阵列基板， 其特征在于， 所述粘结层的数量 为两个， 其中一个粘结层与阵列基板上的源漏金属层同层设置且材料 相同， 另一粘结层与阵列基板上的栅极电极层同层设置且材料相同。
4. 如权利要求 3所述的阵列基板， 其特征在于， 所述导电金属层与 阵列基板中的透明导电层同层形成。
5. 如权利要求 1所述的阵列基板， 其特征在于， 所述导电金属层设 有开孔用于将信号线的输出端引出到阵列基板的表面并与驱动集成电 路芯片连接。
6. 如权利要求 1所述的阵列基板， 其特征在于， 所述多根信号线分 为至少两层， 每层信号线之间用于与驱动集成电路芯片连接的部位设 置的粘结层互不重叠。
7. 一种权利要求 1-6中任一项所述阵列基板的制造方法， 其特征在 于， 所述方法包括： 通过第一次构图工艺在所述阵列基板的周边区 形成包括多根信号线的图形； 通过第二次构图工艺在每一根信号线用 于与驱动集成电路芯片连接的部位形成至少两个不同厚度的粘结层的 图形； 通过第三次构图工艺形成导电金属层电的图形， 且各所述粘结 层之间通过所述导电金属层电连接。
8. 根据权利要求 7所述的制造方法， 其特征在于， 各所述粘结层采 用金属材料形成。
9. 根据权利要求 7所述的制造方法， 其特征在于， 所述第二次构图 工艺形成两个不同厚度的粘结层的图形的步骤中， 一个粘结层与阵列 基板上的源漏金属层同层设置且材料相同， 另一粘结层与阵列基板上 的栅极电极层同层设置且材料相同。
10. 根据权利要求 7所述的制造方法， 其特征在于， 所述第三次构 图工艺中导电金属层与阵列基板中的透明导电层同层形成。
1 1. 根据权利要求 7所述的制造方法， 其特征在于， 所述第三次构 图工艺后还包括： 在所述导电金属层上开孔， 以将信号线输出端引出 到阵列基板的表面与驱动集成电路芯片连接。
12. 根据权利要求 7所述的制造方法， 其特征在于， 所述第一次 图工艺中形成的多根信号线图形分为至少两层， 每层信号线之间用于 与驱动集成电路芯片连接的部位设置的粘结层互不重叠。
13. 一种显示装置， 包括驱动集成电路芯片， 其特征在于， 还包括 权利要求 1 -6中任一项所述的阵列基板，所述阵列基板上的粘结层通过 各向异性导电胶与所述驱动集成电路芯片连接。
PCT/CN2014/000562 2013-12-20 2014-06-05 一种阵列基板及其制造方法和显示装置 Ceased WO2015089892A1 (zh)

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