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WO2015080945A1 - Procédé de réduction du coefficient k d'une couche diélectrique pour la formation avancée d'un transistor finfet - Google Patents

Procédé de réduction du coefficient k d'une couche diélectrique pour la formation avancée d'un transistor finfet Download PDF

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Publication number
WO2015080945A1
WO2015080945A1 PCT/US2014/066652 US2014066652W WO2015080945A1 WO 2015080945 A1 WO2015080945 A1 WO 2015080945A1 US 2014066652 W US2014066652 W US 2014066652W WO 2015080945 A1 WO2015080945 A1 WO 2015080945A1
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Prior art keywords
gate dielectric
ions
gate
barrier layer
dielectric layer
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PCT/US2014/066652
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English (en)
Inventor
Ellie Y. Yieh
Ludovic Godet
Srinivas D. Nemani
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Applied Materials Inc
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Applied Materials Inc
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Priority claimed from US14/505,167 external-priority patent/US9379021B2/en
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of WO2015080945A1 publication Critical patent/WO2015080945A1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0241—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] doping of vertical sidewalls, e.g. using tilted or multi-angled implants
    • H10D64/0134—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H10P30/40—

Definitions

  • Embodiments described herein generally relate to methods of forming a gate in a semiconductor device. More specifically, embodiments described herein relate to methods for reducing the K value of a dielectric layer useful in advanced FinFET formation.
  • devices with three dimensional (3D) structures have been developed.
  • An example of such devices may include FinFETs having conductive fin-like structures that are raised vertically above a horizontally extending substrate.
  • Conventional FinFETs may be formed on a substrate, such as a semiconducting substrate or silicon-on-insulator.
  • the substrate may comprise a semiconducting substrate and an oxide layer disposed on the semiconducting substrate.
  • a method of forming a gate comprises transferring a substrate having a 3D structure comprising a gate dielectric structure disposed adjacent to a dummy gate structure into a plasma processing apparatus.
  • a vertically oriented portion of the gate dielectric structure may be exposed to ions in the apparatus.
  • One or more ion bombardment angles may be selected in response to an aspect ratio of the 3D structure.
  • a method of forming a gate comprises transferring a substrate having a 3D structure comprising a gate dielectric structure disposed adjacent to a dummy gate structure into a plasma processing apparatus.
  • a barrier layer may be formed over the gate dielectric structure. The barrier layer may be exposed to ions in the apparatus along one or more ion bombardment angles which may be selected in response to an aspect ratio of the 3D structure.
  • a method of forming a gate comprises transferring a substrate having a 3D structure comprising a gate dielectric disposed over one or more fin structures into a plasma processing apparatus.
  • the gate dielectric may be exposed to ions in the apparatus and one or more ion bombardment angles may be selected in response to an aspect ratio of the fin structures.
  • FIG. 1 illustrates a schematic diagram of a plasma processing apparatus useful to perform embodiments disclosed herein.
  • Figures 2A-2C are partial, cross-sectional views of a substrate illustrating a bi-directional angular ion bombardment process useful to perform embodiments disclosed herein.
  • Figures 3A-3C are partial, cross-sectional views of a substrate illustrating a sequence of forming a 3D structure according to one embodiment disclosed herein.
  • Embodiments described herein generally relate to methods for forming gate structures and more specifically, to forming gate dielectric layers having a reduced K value.
  • Gate dielectric materials may be formed by exposing as deposited dielectric layers to energetic ions to form a low dielectric constant material. Film properties of the gate dielectric may be altered by ion bombardment to reduce the K value. Ion bombardment of the gate dielectric may modify the gate dielectric composition and/or structure without exceeding a thermal budget of the materials being processed. Gate dielectrics having a low K value may provide for reduced parasitic capacitance.
  • Processes that may be performed to reduce the K value of a gate dielectric material may include light ion implantation of species such as He, H or Ne, direct ion implantation of carbon and/or boron based ions, deposition and knock on of a carbon and/or boron film and deposition, knock on and ion implantation, performed in parallel, of carbon and/or boron ions.
  • species such as He, H or Ne
  • direct ion implantation of carbon and/or boron based ions deposition and knock on of a carbon and/or boron film and deposition
  • knock on and ion implantation performed in parallel, of carbon and/or boron ions.
  • the processes described above benefit from an angular bombardment of the ions at various stages of FinFET formation.
  • the processes may be performed after the gate dielectric has been deposited, after the gate dielectric has been etched and after a dummy gate removal process.
  • Various FinFET formation processes may employ the aforementioned processes during various stages of FinFET formation to provide a gate dielectric having a reduced K value that maintains the integrity of the gate dielectric at reduced critical dimensions.
  • FIG. 1 illustrates a schematic diagram of a plasma processing apparatus 100 useful to perform processes disclosed herein.
  • more traditional ion implantation apparatuses such as beamline ion implantation apparatus, may be used to perform the methods described herein.
  • a beamline ion implantation apparatus is the Varian VllSta ® Trident, available from Applied Materials, Inc. Santa Clara, CA.
  • the plasma processing apparatus 100 includes a process chamber 102, a platen 134, a source 106, and a modifying element 108.
  • the platen 134 may be transferred into and positioned in the processing chamber 102 for supporting a substrate 138.
  • the platen 134 may be coupled to an actuator (not shown) which may cause the platen 134 to move in a scanning motion.
  • the scanning motion may be a back and forth movement within a single plane which may be substantially parallel to the modifying element 108.
  • the source 106 is configured to generate the plasma 140 in the process chamber 102.
  • the modifying element 108 includes a pair of insulators 1 12, 1 14 which may define a gap therebetween having a horizontal spacing (G).
  • the insulators 1 12, 1 14 may comprise an insulating material, a semi-conducting material, or a conductive material.
  • the modifying element also includes a directional element 1 13 disposed in a position relative to the insulators 1 12, 1 14 such that ions 101 are provided toward the substrate 138.
  • a gas source 188 may supply an ionizable gas to the process chamber 102.
  • an ionizable gas may include BF 3 , Bl 3 , N 2 , Ar, PH 3 , AsH 3 , B 2 H 6 , H 2 , Xe, Kr, Ne, He, CH 4 , CF 4 , AsF 5 , PF 3 and PF 5 , among others.
  • species of ions may include He+, H 3 +, H 2 +, H+, Ne+, F+, C+, CF X +, CH X +, C x H y , N+, B+, BF 2 +, B 2 H X +, Xe+ and molecular carbon, boron, or boron carbide ions.
  • the source 106 may generate the plasma 140 by exciting and ionizing the gas provided to the process chamber 102.
  • the ions 101 are attracted from the plasma 140 across the plasma sheath 142.
  • a bias source 190 is configured to bias the substrate 138 to attract the ions 101 from the plasma 140 across the plasma sheath 142.
  • the bias source 190 may be a DC power supply to provide a DC voltage bias signal or an RF power supply to provide an RF bias signal.
  • the modifying element 108 modifies the electric field within the plasma sheath 142 to control a shape of the boundary 141 between the plasma 140 and the plasma sheath 142.
  • the modifying element 108 includes the insulators 1 12, 1 14 and directional element 1 13.
  • the insulators 1 12, 1 14 and directional element 1 13 may be fabricated from materials such as quartz, alumina, boron nitride, glass, silicon nitride and other suitable materials.
  • the boundary 141 between the plasma 140 and the plasma sheath 142 is dependent upon the placement of the directional element 1 13 relative to the insulators 1 12, 1 14 as the directional element 1 13 may alter the electric field within the plasma sheath 142.
  • Ions following a trajectory path 171 may strike the substrate 138 at about an angle of + ⁇ normal to the plane 151 . Ions following trajectory path
  • the 169 may strike the substrate 138 at an angle of about - ⁇ normal to the plane
  • the range of incident angles normal to the plane 151 may be between about +1 ° and about +65° and between about -1 ° and about -65°, excluding 0°.
  • the 150 may be between about +5° and about +65° and a second range of incident angles may be between about -5° and about -65°.
  • the first range of incident angles relative to the plane 151 may be between about -10° and about -20° and the second range of incident angles relative to the plane 151 may be between about +10° and about +20°.
  • some ion trajectories, such as paths 169 and 171 may cross one another.
  • the range of incident angles ( ⁇ ), in one embodiment, may be between about +89° and about -89°, exclusive of 0°.
  • the range of incident angles may be selected based upon an aspect ratio of a 3D feature on the substrate 138.
  • sidewalls 147 of a trench 144 having an exaggerated size for clarity of illustration, may be more uniformly treated by the ions 101 than with conventional plasma processing apparatuses and procedures.
  • the aspect ratio which may be defined as the relationship between a pitch between the sidewalls 147 and a height of the sidewalls 147 extending from the substrate 138, may determine the angles at which the ions 101 are provided to provide more uniform treatment on the sidewalls 147.
  • the aspect ratio of the 3D structures may be provided by the controller 190 prior to performing the ion bombardment process. Alternatively, a sensor in the apparatus 100 may determine the aspect ratio of the 3D structures prior to performing the ion bombardment process. In either example, the ion bombardment angles may be selected in response to the aspect ratio of the 3D structure.
  • a first range of incident angles normal to the plane 151 and adapted to impact the sidewalls 147 may be between about +60° and about +90° and a second range of incident angles may be between about -60° and about -90°.
  • the first range of incident angles normal to the plane 151 and adapted to impact the sidewalls 147 may be between about -70° and about -80° and the second range of incident angles normal to the plane 151 and adapted to impact the sidewalls 147 may be between about +70° and about +80°.
  • angles at which the ions 101 are provided may be selected to avoid contact with material below the sidewalls 147, for example, the substrate 138 in one embodiment, or an insulator in another embodiment.
  • the above-described apparatus 100 can be controlled by a processor based system controller such a controller 190.
  • the controller 190 may be configured to control flow of various precursor gases and purge gases from gas sources, such as the gas source 188, during different stages of a substrate process sequence.
  • the controller 190 includes a programmable central processing unit (CPU) 192 that is operable with a memory 194 and a mass storage device, an input control unit, and a display unit (not shown), such as power supplies, clocks, cache, input/output (I/O) circuits, and the like, coupled to the various components of the apparatus 100 to facilitate control of the substrate processing.
  • the controller 190 also includes hardware for monitoring substrate processing through sensors in the apparatus 100, including sensors monitoring the precursor and purge gas flow. Other sensors that measure system parameters such as substrate temperature and position, chamber atmosphere pressure and the like, may also provide information to the controller 190.
  • 192 may be one of any form of general purpose computer processor that can be used in an industrial setting, such as a programmable logic controller
  • PLC Physical circuit
  • the memory 194 is coupled to the CPU 192 and the memory 194 is non-transitory and may be one or more of readily available memory such as random access memory
  • RAM random access memory
  • ROM read only memory
  • floppy disk drive hard disk, or any other form of digital storage, local or remote.
  • Support circuits 196 are coupled to the CPU 192 for supporting the processor in a conventional manner.
  • Deposition, etching, implantation, and other processes are generally stored in the memory 194, typically as a software routine.
  • the software routine may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by the CPU 192.
  • the memory 194 is in the form of computer-readable storage media that contains instructions, that when executed by the CPU 192, facilitates the operation of the apparatus 100.
  • the instructions in the memory 194 are in the form of a program product such as a program that implements the method of the present disclosure.
  • the program code may conform to any one of a number of different programming languages.
  • the disclosure may be implemented as a program product stored on computer-readable storage media for use with a computer system.
  • the program(s) of the program product define functions of the embodiments (including the methods described herein).
  • Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media ⁇ e.g., read-only memory devices within a computer such as CD-ROM disks readable by a CD-ROM drive, flash memory, ROM chips or any type of solid-state non-volatile semiconductor memory) on which information is permanently stored; and (ii) writable storage media ⁇ e.g., floppy disks within a diskette drive or hard-disk drive or any type of solid-state random-access semiconductor memory) on which alterable information is stored.
  • Such computer-readable storage media when carrying computer-readable instructions that direct the functions of the methods described herein, are embodiments of the present disclosure.
  • Figures 2A-2C illustrate cross-sectional views of a portion of a substrate illustrating bi-directional angular ion bombardment utilized by embodiments disclosed herein.
  • Figure 2A depicts a 3D feature 200 comprising a substrate 202 having a gate 204 formed thereon and a gate dielectric 206 layer formed over the gate 204.
  • the gate 204 may be a dummy gate in certain embodiments. In other embodiments, the gate 204 may be representative of a fin structure having the gate dielectric 206 disposed thereon.
  • the bi-directional angular ion bombardment proceeds by directing ions toward the gate dielectric 206 from a first region 210.
  • the ions may travel along one or more paths 21 1 selected to strike a vertical portion 212 of the gate dielectric 206 and avoid ion bombardment of a material 214 below the gate dielectric 206. Similarly, ions may be accelerated toward the gate dielectric 206 from a second region 208. The ions may travel along one or more paths 209 to strike the vertical portion 212 of the gate dielectric 206 and avoid bombardment of the material 214 below the gate dielectric 206.
  • the angles or trajectories at which the ions are directed toward the substrate 202 are selected based upon an aspect ratio of the 3D features 200.
  • the aspect ratio may be defined as the ratio of a pitch length 220 to a height 222 of the gate dielectric 206 extending above the substrate 202.
  • the ions traveling along paths 21 1 , 209 may impact any point along the vertical portion 212 between a bottom region 216 and a top region 218 of the gate dielectric 206.
  • Figure 2B schematically illustrates the structure Figure 2A after the gate material 204, such as a dummy gate, has been removed.
  • the surfaces of the gate dielectric 206 previously adjacent the gate material 204 are exposed.
  • the bi-directional angular bombardment process may proceed on the exposed surfaces in a manner described above with regard to Figure 2A.
  • FIG. 2C schematically illustrates another embodiment of the bidirectional angular ion bombardment process.
  • fin structures 203 extend from the substrate 202 and an insulator material 201 disposed adjacent a lower portion of the fin structures 203.
  • a gate dielectric is deposited over the fin structures 203 on the sidewalls 212 and the upper surface 213. Both the sidewalls 212 and the upper surface 213 are subjected to ion bombardment.
  • bi-directional ion bombardment may impact the gate dielectric 206 along the entire sidewalls 212 and upper surface 213.
  • Figures 3A-3C depict a sequence of forming a 3D structure according to one embodiment described herein.
  • a substrate 302 having fin structures 310 extending from the substrate 302 may be provided as illustrated in Figure 3A.
  • An insulator 320 such as SiO 2 or SiN, may be formed over the substrate 302 such that a portion of the fin structures 310 remain extended beyond the insulator 320.
  • a gate dielectric layer 350 is formed over the insulator 320 and the fin structures 310 as illustrated in Figure 3B.
  • the gate dielectric layer 350 may act as a spacer between the fin structures 310 and a subsequently deposited gate.
  • the gate dielectric layer 350 may be for example, AI2O3, SiN, BN, SiCN or S1O2, or other dielectric material capable of being treated with processes disclosed herein to lower the K value while maintaining thickness integrity of the gate dielectric layer 350.
  • the gate dielectric layer 350 may be conformally deposited over the insulating layer 320 and the fin structures 310 by suitable processes, such as CVD, ALD, PVD or the like.
  • a silicon nitride layer may be deposited by CVD to form the gate dielectric layer 350.
  • a silicon precursor, such as SiH 4 , and a nitrogen precursor, such as N 2 or NH 3 may be energized into a plasma and deposited via a CVD process to form the gate dielectric layer 350.
  • one or more ion implantation processes to modify the K value of the gate dielectric layer 350 may be performed.
  • a light ion implantation process may be performed on the gate dielectric layer 350.
  • a light ion species such as H, or a halogen ion, for example He, or Ne, may be implanted into the gate dielectric layer 350 to create a cavity inside the dielectric material.
  • the implanted light ions may form bubbles or voids within the dielectric material which results in a lower the K value of the dielectric material by altering the physical structure of the gate dielectric layer 350.
  • a low temperature anneal may optionally be performed after the light ion implantation to diffuse the light ions from the gate dielectric layer 350.
  • an untreated SiN gate dielectric layer 350 may exhibit a K value of about 7.5.
  • the gate dielectric material 350 after performing a light ion implantation process may exhibit a K value of about 5.1 . Thus, the K value of the dielectric material may be lowered.
  • Various aspects of the light ion implantation process may be controlled to tune the K value.
  • the size of the cavity formed within the gate dielectric layer 350 may be controlled by the ion energy and the ion flux/dose.
  • He ion implantation may be provided in a dose of between about 1 E15 (ions/cm 2 ) and about 1 E19, such as about 2E17. As such, the He dose regime may maintain a pre-implantation thickness of the gate dielectric layer 350.
  • the light ion species utilized may also reduce sputtering of the gate dielectric material 350 from the surface of the fin structures 310.
  • the temperature at which the light ion implantation process is performed may also affect the resulting structure by diffusing ions implanted within the gate dielectric layer 350 out of the gate dielectric layer 350 to form the resulting void, which, in certain embodiments, may be empty of filled with He gas.
  • the processing parameters such as chamber pressure, gas flow rate and plasma source power, among others, may be selected to enhance the light ion implantation process.
  • the impact angle of the light ion species impacting the gate dielectric layer may be selected based upon an aspect ratio of features formed by the fin structures 310. Adjusting the bombardment angle may be selective for bombardment on sidewalls 332 of the gate dielectric material 350. As such, implantation on a region 354 below the gate dielectric material 350 may be avoided. However, the gate dielectric layer 350 disposed over a top region 334 of the fin structure may be bombarded with ions because the top region 334 bombardment is not determined by the aspect ratio dependent angular bombardment.
  • the implant angle may be determined by the aspect ratio(s) of the features, which may be fin structures 310.
  • a bombardment angle having a substantially normal orientation (90°) to a surface of the gate dielectric layer 350 may implant the ions a greater depth than an implant angle having a substantially parallel orientation (0°).
  • a continuum of implant angles primarily determined by the aspect ratio of the features to avoid shadowing effects, between the normal and parallel extremes may be utilized to select a depth to which an ion is implanted.
  • the molecular weight of the ions selected for bombardment helps determine the implant depth.
  • An ion having a smaller molecular weight may be implanted deeper than an ion having a greater molecular weight.
  • a hydrogen ion will penetrate the gate dielectric layer 350 deeper than a neon ion, assuming other implant variables are the same.
  • the resulting implant depths of the light ions may be between about 1 nm and about 8 nm in various embodiments.
  • the implant energy utilized to implant the ions also affects the depth of implantation. For example, a high implant energy will provide for deeper implantation.
  • a thermal annealing process may be performed at a temperature lower than about 400°C, such as about 350°C to activate the void formation within the gate dielectric material.
  • a direct ion implantation process of boron and/or carbon containing ions may be performed after the gate dielectric material 350 is deposited.
  • various boron and carbon containing precursors may be ionized and boron and/or carbon ions may be implanted into the dielectric material layer 350.
  • only boron ions may be implanted and in another example, only carbon ions may be implanted.
  • both boron and carbon containing ions may be implanted.
  • the bi-directional angular ion bombardment process may be dictated by the aspect ratio of the features.
  • the processing parameters with which the direct ion implantation process is performed may be selected to enhance direct ion implantation.
  • the ion precursor is provided at a rate of about 25 seem, energized with an RF power of about 1500 W, the precursor is provided in a dose of about 5E16 ions/cm 2 , and the process is performed at a temperature of about 350 °C.
  • the direct ion implantation process which may optionally be performed at an elevated temperature, will materially alter the composition of the gate dielectric layer 350 by changing the chemical makeup of the material.
  • the boron and/or carbon ions may function to dope the gate dielectric layer 350 and create a dielectric material having a reduced K value.
  • a thermal annealing process similar to the annealing process described with regard to the light ion implantation process may also be performed.
  • a deposition and knock on process may be performed after the gate dielectric material 350 is deposited as illustrated in Figure 3B'.
  • the term "knock on” may be defined as a recoil ion implant where an ion is implanted through surface layers formed on a gate dielectric to drive a dopant into the gate dielectric.
  • the deposition and knock on process may begin by depositing a thin barrier layer 360 over the gate dielectric layer 350.
  • the barrier layer 360 may comprise boron and/or carbon atoms deposited on the surface of the gate dielectric layer 350.
  • the barrier layer 360 may function to provide additional protection to the fin structures 310 during subsequent ion implantation and as the source for implanted ions.
  • knock on ions 362 may bombard the barrier layer 360 and push boron and/or carbon ions present in the barrier layer 360 into the gate dielectric layer 350.
  • the knock on ions 362 may be the same ions as the ions used to form the barrier layer 360. As such, boron and/or carbon ions may be utilized for both the barrier layer 360 and as the knock on ions 362. Utilizing the deposition and knock on process may also advantageously benefit from a multiplier effect.
  • the multiplier effect results when a single knock on ion 362 impacts the barrier layer 360 but results in multiple atoms being implanted into the gate dielectric layer 350.
  • the barrier layer 360 is deposited and knock on ions 362 are provided to bombard the barrier layer. The bombardment ions then drive ions present in the barrier layer 360 into the gate dielectric layer 350.
  • the multiplier effect may function to efficiently reduce the K value of the gate dielectric layer 350 and reduce the amount of ions required to bombard the barrier layer 360.
  • boron ions, carbon ions and boron and carbon ions in combination may be implanted into the gate dielectric layer 350 via the deposition and knock on process.
  • the implantation process may be tuned to provide desired results by utilizing the bi-directional angular ion implantation process.
  • 2nm of the barrier layer 360 is deposited utilizing a CH /H 2 or B 2 H6/CH /H 2 mixture with about a 3kV bias and about a +-20° angular bi-directional ion implantation in a dose of about 2E16 cm 2 .
  • the bi-directional angular ion implantation process may be dependent upon an aspect ratio of the features within which the ions are being implanted.
  • a thermal annealing process similar to the annealing process described with regard to the direct ion implantation process may also be performed.
  • an ion assisted deposition and doping (IADD) process may be performed after the gate dielectric layer 350 is deposited as illustrated in Figure 3B".
  • IADD may refer to a process of depositing a film/barrier layer over surfaces of a material. The process may involve directing ions to the material over a range of angles to alter the physical or chemical structure of the underlying material.
  • deposition of the barrier layer 360, knock on of the barrier layer, and direct ion implantation may be performed at the same time in parallel.
  • the deposition process may utilize suitable boron and/or carbon precursors to form the barrier layer 360 containing boron and/or carbon atoms.
  • the knock on ions 362 may be boron and/or carbon ions; however, they may also be ions other than boron and/or carbon.
  • the knock on ion 362 may be arsenic.
  • Other incident ions 364, such as hydrogen, boron and carbon ions may also be provided with the knock on ions 362.
  • arsenic ions may sputter the barrier layer 360 and implant within the barrier layer 360.
  • the knock on ions 362 may knock in atoms (boron and/or carbon) of the barrier layer 360 into the gate dielectric layer 350.
  • the deposition and knock on processes may benefit from the multiplier effect as described above. While the deposition and knock on process is proceeding, the incident ions 364 may also be directly implanted into the gate dielectric layer 350.
  • Utilizing the IADD process may retain the ion dose enhancement within the materials (gate dielectric layer 350) being processed.
  • an IADD process utilizing AsH 3 as the knock on ion source and H 2 as the incident ion source provided for an as retained dose of between about 5.0E14 (at/cm 2 ) and about 1 .5E15 for deposition depths ranging from about 1 .0 nm and about 8.0 nm.
  • the retained dose may saturate the barrier layer 360 as the barrier layer 360 is sputtered away.
  • the knock on ion deposition thickness (amount) may also be a variable in controlling the dose saturation.
  • the IADD process may also be tuned to provide desired results by utilizing the bi-directional angular ion implantation process.
  • the bi-directional angular ion implantation process may be dependent upon an aspect ratio of the features within which the ions are being implanted.
  • Both the knock on ions 362 and incident ions 364 for direct implantation may be provided at a range of angles relative to the surface of the substrate 302.
  • a thermal annealing process similar to the annealing processes described above may also be performed.
  • a portion of the gate dielectric layer 350 may be removed.
  • the horizontally oriented regions 336 of the gate dielectric layer 350 may remain unmasked and exposed to a wet or dry etching process. The etching process will remove the gate dielectric layer 350 from the horizontally oriented regions 336.
  • Figure 3C illustrates the resulting substrate 302 having the gate dielectric layer 350 formed over the fin structures 310.
  • the light ion implantation process, direct ion implantation process, deposition and knock on process and IADD processes described above with regard to Figure 3B' and 3B" may be performed after the gate dielectric layer 350 has been etched instead of directly after the gate dielectric layer 350 deposition as illustrated in Figure 2C.
  • a gate material (not shown) may subsequently be deposited over the substrate for form a completed FinFET structure.
  • the methods described herein may be automated by, for example, tangibly embodying a program of instruction upon a computer readable storage media capable of being read by a machine capable of executing the instructions.
  • a general purpose computer is one example of such a machine.
  • a non-limiting list of appropriate storage media well known in the art includes such devices as a readable or writeable CD, flash memory chips, various magnetic storage media and the like.
  • various ion implantation processes such as light ion implantation, direct ion implantation, deposition and knock on and IADD may be performed at various stages of 3D structure formation, according to various embodiments.
  • the ion implantation processes may benefit from utilizing the bi-directional angular implantation to more precisely tune certain aspects of the ion implantation processes. All of the processes described herein may be performed at room temperature or at an elevated temperature. Certain processes may be performed at both room temperature and elevated temperatures depending upon desired implantation characteristics.
  • the ion implantation processes may advantageously lower the K value of gate dielectric material while maintaining the integrity of the gate dielectric without increasing the thickness of the gate dielectric material.
  • the resulting gate dielectric material may reduce overall gate height while minimizing parasitic capacitances which may provide an improved microelectronic device.

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Abstract

Des modes de réalisation de l'invention concernent généralement des procédés de formation de structures de grille. Divers processus peuvent être mis en œuvre sur un matériau diélectrique de grille pour réduire le coefficient K du matériau diélectrique. Le diélectrique de grille présentant un coefficient K réduit peut entraîner une diminution de la capacité parasite et une diminution totale de la capacité. Le diélectrique de grille peut être modifié sans contrainte thermodynamique.
PCT/US2014/066652 2013-11-27 2014-11-20 Procédé de réduction du coefficient k d'une couche diélectrique pour la formation avancée d'un transistor finfet Ceased WO2015080945A1 (fr)

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