WO2014118710A1

WO2014118710A1 - An image processing module comprising a fpga

Info

Publication number: WO2014118710A1
Application number: PCT/IB2014/058633
Authority: WO
Inventors: Yüksel SERDAR; Umur AKINCI; Fatih ISIK; Cemil KIZILOZ; Coskun Ayyildiz; Cagatay KALELIOGLU; Taner TURKMEN; Ali Erkin ARSLAN
Original assignee: Aselsan Elektronik Sanayi ve Ticaret AS
Current assignee: Aselsan Elektronik Sanayi ve Ticaret AS
Priority date: 2013-01-31
Filing date: 2014-01-29
Publication date: 2014-08-07
Anticipated expiration: 2015-07-31
Also published as: JO3164B1; UA105745U

Abstract

The present invention relates to modules which are designed to be employed preferably in handheld and battery-operated military thermal video cameras and which can perform image processing. The objective of the present invention is to provide an image processing module, which can perform all of the functions that are required to be performed in imaging devices, and which has a smaller volume and lower power consumption compared to the architectures in the state of the art.

Description

AN IMAGE PROCESSING MODULE COMPRISING A FPGA

DESCRIPTION

Field of the Invention

The present invention relates to modules which are designed to be employed preferably in handheld and battery-operated military thermal video cameras and which can perform image processing. Background of the Invention

In the state of the art, two types of architectures are used for performing the functions required in military thermal imaging devices. The type of architecture, wherein the functions are assigned to different modules, boards and/or memories, is the "Distributed Architecture". This kind of devices includes various sub-units such as the image processing module for processing the detector data that produces the thermal image, the symbology module which places symbology/text/menu on the video signal generated by the former module, the processor and control module which has the function of communication with the sub-units in the device, and the interface module which controls the communication with the external devices.

In some cases, "Partial Distributed Architecture", wherein modules having a plurality of functions are combined, is preferred. Even if the modules are combined, there are different memories assigned for each function. Additionally, FPGA and the external memories of the processors are different from each other. Since they cannot use a shared memory, the process results should be sent from FPGA to the processor and from the processor to FPGA. Military thermal imaging devices are day by day getting smaller in terms of volume and more lightweight. In addition to these, their power consumption is also desired to be lower. Devices with distributed or partially distributed architecture (multi module/board/memory) have difficulty in meeting these demands and in some cases they fail to do so.

In the state of the art, provision of a different module/board for each function (Distributed Architecture), provision of a different memory for each function (Partial Distributed Architecture) and provision of separate memories for both the Processor(s) and the FPGA(s) (Distributed Architecture and Partial Distributed Architecture) increase the size and power consumption of the device/module/board. There are too many module/board/external memories in this structure. When a small number of them is used, either the function cannot be fulfilled or the performance of the concerned function decreases.

Due to the fact that FPGAs and the processors are physically separate, FPGA and the processors are enabled to communicate through the complex and difficult routing formed on the printed circuit board. This elongates the development process of the design and these structures have an insufficient speed.

Summary of the Invention

The objective of the present invention is to provide an image processing module, which can perform all of the functions that are required to be performed in imaging devices, and which has a smaller volume and lower power consumption compared to the architectures in the state of the art. Detailed Description of the Invention

The image processing module developed to fulfill the objective of the present invention is illustrated in the accompanying figures, in which,

Figure 1 is a schematic view of the image processing module.

Figure 2 is a schematic view of the data communication in the image processing module. The components shown in the figures are each given reference numbers as follows:

1. Image processing module

2. FPGA (Field Programmable Gate Array) integrated circuit

21. Interface unit

22. Image processing unit

23. Software-based processor

24. Symbology unit

25. Multi port memory controller

3. Memory

31. Processor memory area

32. Interface memory area

33. Image processing memory area

34. Symbology memory area

4. LVDS (Low Voltage Differential Signaling) receiver

5. Video decoder

6. Key interface

7. Raw video output

8. Video coder/multiplexer

9. Video converter 10. Serial communication interfaces

11. 12C interface

12. JTAG (Joint Test Action Group) interface

13. RGB (red, green, blue) output

A. CVBS (Color, Video, Blanking, and Sync.) input

B. CVBS output

C. Discrete signals

The image processing module (1) of the present invention basically comprises: at least one FPGA integrated circuit (2) having at least one interface unit (21) adapted to enable communication with the external devices, at least one image processing unit (22) adapted to process the image data coming from the detector, at least one software-based processor (23) adapted to control the communication between the in-device units, at least one symbology unit (24) adapted to place symbology/text/menu etc. on the image generated by the image processing unit (22), at least one multi port memory controller (25),

at least one memory (3) which has a processor memory area (31) designated for software-based processor (23), an interface memory area (32) designated for the interface unit (21), an image processing memory area (33) designated for the image processing unit (22), a symbology memory area (34) designated for the symbology unit (24).

Preferably a single FPGA integrated circuit (2) and preferably a single physical memory (3) are used on the image processing module (1) of the present invention. The software-based processor (23) is realized as the soft core in the FPGA integrated circuit (2). This structure can fulfill all the functions provided by the architectures in the state of the art. Thanks to the multi port memory controller (25) provided in the FPGA integrated circuit (2), a plurality of high speed read/write interfaces are provided to the single physical memory (3). Thus, each function (image processing, symbology, control, interface, processor) requiring memory has its own memory area (31), (32), (33), (34).

Control of the sub-units, reading the keys on the device where the module (1) is used, menu structure and symbology information and similar functions are carried out by the software-based processor (23). The software -based processor (23) can use the processor memory area (31) designated for it via the multi port memory controller (25).

The image processing module (1) of the present invention further includes an LVDS receiver (4), a video decoder (5) preferably having analog CVBS input(s) (A) and a key interface (6) which receives discrete signals (C) from the keys and power switch on the device where the module (1) is used. The LVDS receiver (4), video decoder (5) and the key interface (6) transmit the data that they receive to the FPGA integrated circuit (2). In the image processing module (1) of the present invention, the FPGA integrated circuit (2) further includes thereon a raw video output (7), a video coder/multiplexer (8) preferably having analog CVBS output(s) (B), a video converter (9) preferably having analog RGB output(s) (13), serial communication (RS 232, RS 422, etc.) interfaces (10), I2C interface (11) and JTAG interface (12).

By means of the image processing module (1) of the present invention, a module (1) design is realized which can provide the desired features particularly in handheld and battery operated military thermal video cameras. By using this module (1), the functions expected from the device are provided with a smaller volume and lower power consumption compared to the architectures in the state of the art. As the number of boards and thus the memories (3) decreases, the cost and power consumption decrease as well. Since a smaller number of boards and interconnection cables is required, volume and thus the weight of the devices can be reduced.

Within the framework of these basic concepts, it is possible to develop various embodiments of the image processing module (1) of the present invention. The invention cannot be limited to the examples described herein and it is essentially as defined in the claims.

Claims

1. An image processing module (1) basically characterized by

at least one FPGA integrated circuit (2) having at least one interface unit (21) adapted to enable communication with the external devices, at least one image processing unit (22) adapted to process the image data coming from the detector, at least one software-based processor (23) adapted to control the communication between the in-device units, at least one symbology unit (24) adapted to place symbology/text/menu etc. on the image generated by the image processing unit (22), at least one multi port memory controller (25),

2. An image processing module (1) according to Claim 1, characterized by an LVDS receiver (4), a video decoder (5) preferably having analog CVBS input(s) (A) and a key interface (6) which receives discrete signals (C) from the keys and power switch on the device where the module (1) is used.

3. An image processing module (1) according to any one of preceding claims, characterized by the LVDS receiver (4), video decoder (5) and the key interface (6) which transmit the data that they receive to the FPGA integrated circuit (2).

4. An image processing module (1) according to any one of preceding claims, characterized by a raw video output (7), a video coder/multiplexer (8) preferably having analog CVBS output(s) (B), a video converter (9) preferably having analog RGB output(s) (13), serial communication (RS 232, RS 422, etc.) interfaces (10), I2C interface (11) and JTAG interface (12) provided on the FPGA integrated circuit (2).