WO2014110173A1 - High-performance amorphous semiconductors - Google Patents

Abstract

Compositions for making amorphous semiconductors are disclosed. Cations for the amorphous semiconductors are selected based on particular criteria, such as to form spherically symmetric 4s-, 5s- or 6s-derived conduction bands and/or to preclude, or at least substantially preclude, crystallization and facilitate formation of an amorphous microstructure. For certain disclosed embodiments the cations (C) typically are selected from C = Zn⁺², Ga⁺³, As⁺³, As⁺⁵, In⁺³, Sn⁺², Sn⁺⁴, Sb⁺³, Sb⁺⁵, Bi⁺³, and Bi⁺⁵, and the anions typically are selected from A = P^-3, As^-3, Sb ^-3, S ^-2, Se ^-2, Te ^-2, and Βi^-3. Additives (W), such as glass formers, dopants, or spectators, also can be incorporated into disclosed amorphous semiconductors. Suitable additives typically are selected from W = Mg⁺², Ca⁺², S^r+2, Ba⁺², B⁺³, Al⁺³, Sc⁺³, Y⁺³, La⁺³, Ce⁺³, Ce⁺⁴, O^-2, and F^-1. Amorphous semiconductors can be used to make a various electronic devices, or components thereof, such as thin-film transistors and photovoltaic devices.

Description

HIGH-PERFORMANCE AMORPHOUS SEMICONDUCTORS

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit U.S. Provisional Application No. 61/750,707, filed January 9, 2013, which is incorporated herein by reference in its entirety.

FIELD

The present disclosure concerns amorphous semiconductors, and methods for making and using the amorphous semiconductors.

BACKGROUND

Amorphous semiconductors, such as amorphous hydrogenated silicon (a-Si:H) and amorphous oxide semiconductors (AOS), are important materials for making a variety of electronic components, such as thin-film transistors and photovoltaic devices. Amorphous hydrogenated silicon is a highly covalent material, whereas amorphous oxide semiconductors are strongly ionic. The type of bonding affects the electron mobility (μ_η) of these two materials. Amorphous hydrogenated silicon typically exhibits a low electron mobility, i.e., about 1 cm V^" V¹. This is thought to be due to the strong p-orbital contribution to the covalent bonds in silicon, which requires nearest-neighbor atoms and their bonds to be precisely aligned in order to efficiently transport electrons in delocalized paths through an atomic microstructure. This precise near-neighbor alignment rarely occurs in an amorphous material. As a result, amorphous hydrogenated silicon has a very low mobility.

In contrast to amorphous hydrogenated silicon, the mobility of an amorphous oxide semiconductor does not depend strongly on the degree of crystallinity because such materials have electrostatic, non-directional bonds. Amorphous oxide semiconductors typically have higher mobilities than amorphous hydrogenated silicon due to conduction bands that arise from spherically symmetric 4s-, 5s-, or 6s-derived cation orbitals with large ionic radii. Spherically symmetric orbitals and large ionic radii combine to provide a high degree of wave function overlap between neighboring orbitals. This leads to more efficient electron transport through the amorphous microstructure, and hence higher electron mobility. Amorphous oxide semiconductor thin-film transistors also are characterized by several attractive attributes, including low-temperature processability. Operating thin-film transistors can be produced even when the channel layer is deposited at room temperature. However, the optimal temperature range for post-deposition annealing of an amorphous oxide semiconductor channel layer is from approximately 300 °C to about 500 °C. Using process temperatures in this range, in conjunction with an appropriate high-quality, low-leakage gate insulator, optimized amorphous oxide semiconductor thin-film transistor performance would be expected to involve a near- zero threshold voltage, a channel electron mobility of approximately 10

and a sub-threshold swing approaching the theoretical limit of 60 mV/decade.

Amorphous oxide semiconductor thin-film transistors also can be produced having very large drain current on-to-off ratios (>10⁶). As a result, the off current is essentially gate voltage independent since an amorphous oxide semiconductor is a unipolar material.

Another attractive attribute of amorphous oxide semiconductor thin-film transistors is that low-resistance source/drain contacts are obtained by simply depositing a metal onto or under the amorphous oxide semiconductor channel layer (i.e., source/drain doping is not required). This leads to a simple process flow design for making thin-film transistors. In short, amorphous oxide semiconductor thin-film transistors appear promising for a variety of commercially important applications, such as pixel switches for active-matrix liquid-crystal displays, pixel switches and drivers for active-matrix, organic light-emitting diode displays, and back-end IC switching applications in which low-temperature processing is required.

Although amorphous oxide semiconductor thin-film transistors hold much promise, their relatively low electron mobility (i.e., about 10-30 cm 2 V -^"1 s -^"1 ) and the fact that they cannot be rendered p-type has, to date, limited their applications. Thus, a need exists for new amorphous semiconductors that exhibit increased electron mobility and the ability to achieve p-type doping.

SUMMARY

High-performance amorphous semiconductors are disclosed. In general, their design involves selecting suitable cation(s), suitable anion(s), and, in some cases, suitable additive(s), for making desired amorphous semiconductors. The cation(s), anion(s), and additive(s) are combined in appropriate stoichiometric amounts, thereby forming a mixture, and the mixture is processed to form the desired amorphous semiconductor. Cations (C) are selected based on particular criteria, such as to form spherically symmetric 4s-, 5s-, or 6s-derived conduction bands and/or to preclude, or at least substantially preclude, crystallization and facilitate formation of an amorphous microstructure. Furthermore, cations are typically selected that provide a closed shell configuration, i.e. an oxidation state that provides a filled or empty frontier orbital. Thus, particularly suitable cations are selected from C = Zn⁺², Ga⁺³, As⁺³, As⁺⁵, In⁺³, Sn⁺², Sn⁺⁴, Sb⁺³, Sb⁺⁵, Bi⁺³, and Bi⁺⁵.

Suitable anions (A) also are selected based on particular criteria, including suppression of crystallization, processability, bandgap, and covalence considerations. Furthermore, anions also are typically selected that provide a closed shell configuration, i.e. an oxidation state that provides a filled or empty frontier orbital. More particularly, suitable anions typically are selected from A = F³, As^"3, Sb^"3, S^"2, Se^"2, Te ², and ΒΓ³.

Additives (W) can also be incorporated into disclosed amorphous semiconductors as glass formers. For example, dopants and/or spectators can be used as additives. Suitable additives typically are selected from W = Mg⁺², Ca⁺², Sr⁺², Ba⁺², B⁺³, Al⁺³, Sc⁺³, Y⁺³, La⁺³, Ce⁺³, Ce⁺⁴, O ², and F¹.

A general chemical description of disclosed amorphous semiconductors is provided by Formula I:

Formula I

With reference to Formula I, C 1 , C2 , and C 3 are different cations; A 1 , A2 , and A 3 are different

and W 3 are different additives; and the subscripts D, E, F, L, M, N, X, Y, Z indicate the number of atoms of each respective element, thereby specifying the target atomic composition of the amorphous semiconductor.

Exemplary amorphous semiconductors include, solely by way of example, Zn₄Sb₂Te, Zn₆Sb₂Te0₂, Zn₂Sb₂Te₅, Zn₃In₃AlAs6, Zn₃Sn₃As₂P₄, and Zn₂Sn₄P₄Te₂0₂. Chemical formulas, and hence target atomic compositions of the amorphous semiconductor, conform to the ideal of simple, closed-shell solids in which the octet rule is satisfied (i.e., each atom has eight electrons in its valence shell, thus resulting in the same electronic configuration as a noble gas atom).

For certain disclosed embodiments, the amorphous semiconductor has a root-mean- square surface roughness over an area of 1 X 1 μιη of less than 3 nm, and in certain

embodiments a root-mean-square surface roughness over an area of 1 X 1 μιη of less than 0.3 nm, as measured by atomic force microscopy. Furthermore, disclosed embodiments of amorphous semiconductors have an electron mobility of at least 50 cm 2 V -^"1 s -^"1 , and perhaps at least 100 cm 2 V -^"1 s -^"1. Certain disclosed amorphous semiconductors also typically have a hole mobility of at least 1 cm 2 V -^"1 s -^"1.

A person of ordinary skill in the art will readily appreciate the value of disclosed amorphous semiconductors. Amorphous semiconductors can be used to make a variety of electronic devices, or components of electronic devices, such as thin-film transistors.

The foregoing and other objects, features, and advantages of the invention will become more apparent from the following Detailed Description, which proceeds with reference to the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic representation of electronic density states of a covalent and an ionic semiconductor, both having the same band gap, E_G, where Ey denotes the top of the valence band and E_c denotes the bottom of the conduction band.

FIG. 2 is graph of solid state energy (eV) for 60 elements arranged in descending energy order, where the dashed horizontal line at 4.5 eV denoted ε(+/-) corresponds to the hydrogen donor/acceptor ionization energy, or, equivalently, the standard hydrogen electrode potential.

FIG. 3 is a schematic drawing illustrating one embodiment of a bottom-gate, coplanar electrode thin film transistor that can be made using disclosed embodiments of amorphous semiconductors.

FIG. 4 is a schematic drawing illustrating one embodiment of a bottom-gate, staggered electrode thin film transistor that can be made using disclosed embodiments of amorphous semiconductors.

FIG. 5 is a schematic drawing illustrating one embodiment of a top-gate, coplanar electrode thin film transistor that can be made using disclosed embodiments of amorphous semiconductors.

FIG. 6 is a schematic drawing illustrating one embodiment of a top-gate, staggered electrode thin film transistor that can be made using disclosed embodiments of amorphous semiconductors. DETAILED DESCRIPTION

I. Definitions

The following explanations of terms and abbreviations are provided to better describe the presently disclosed technology and to guide those of ordinary skill in the art to practice such technology. Unless stated otherwise, all technical and scientific terms used herein have the same meaning as would be commonly understood to a person of ordinary skill in the art to which this disclosure pertains. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the presently disclosed technology, suitable methods and materials are described below. The materials, methods, and examples are illustrative only and are not intended to be limiting. Other features of the disclosure will be apparent to a person of ordinary skill in the art based on the following detailed description and the claims.

Unless otherwise indicated, all numbers stated in this specification and claims to express quantities, such as molecular weights, percentages, and so forth, are understood to be modified by the term "about." Accordingly, unless otherwise indicated, implicitly or explicitly, the numerical parameters set forth are approximations that may depend on the desired properties sought and/or limits of detection under standard test conditions/methods. When directly and explicitly distinguishing embodiments from discussed prior art, the embodiment numbers are not approximates unless the word "about" is recited.

The singular forms "a" or "an" or "the" include plural references unless the context clearly dictates otherwise.

"Additive" refers to the addition of foreign species (e.g., atoms, ions, etc.) into an inorganic solid state structure (e.g., crystal lattice) of a semiconductor to achieve a desired characteristic, such as suppressing crystallization within the structure, producing an n-type or a p-type material, or facilitating formation of the solid state structure without appreciably contributing to the conduction band minimum or valence band maximum density of states.

"Spectator" refers to an additive whose solid state energy differs from ε(+/-) by more than approximately 1.5 eV. As such, the energy levels of the spectator make little or no contribution to the characteristics of the electronic structure near the valence-band maximum (VBM) and the conduction-band minimum (CBM). The electronic characteristics of the VBM and CBM control hole (p type) and electron (n type) transport. Since the spectator does not directly contribute to VBM or CBM, it contributes to an amorphous semiconductor primarily as a structural modifier.

"Amorphous" as used herein refers to thin films that typically have an atomic force microscopy (AFM) surface root-mean-square roughness of less than approximately 3 nm when deposited onto a smooth solid surface. In particular disclosed embodiments, "amorphous" describes a thin film that has an AFM of less than 1.5 nm when deposited onto a silicon wafer covered with a thermal oxide. In exemplary embodiments, "amorphous" indicates a thin film having a root- mean- square surface roughness over an area of 1 x 1 μιη of less than

approximately 0.3 nm as measured by AFM.

"Comprising" means "including."

"Conduction band" is a band in which electrons can move freely in a solid, producing a net charge transport. The conduction band may be the lowest unoccupied energy band in a material.

"Covalent" refers to a chemical bond that arises primarily as a consequence of electron sharing between neighboring atoms.

"Electron Mobility" refers to how effectively an electron moves through a

semiconductor when subjected to an electric field.

"Hole" refers to a deficiency in valence electrons.

"Ionic" refers to a chemical bond that is predominantly electrostatic due to electron transfer from higher to lower energy frontier orbitals.

An "n-type semiconductor" has at least one donor that contributes free electrons.

The term "or" refers to a single element of stated alternative elements or a combination of two or more elements, unless the context clearly indicates otherwise.

A "p-type semiconductor" possesses at least one acceptor to produce "holes," or electron deficiencies.

"Substrate" refers to a physical object operating as a basic workpiece or platform that is transformed by various process operations into a desired microelectronic configuration, such as by deposition of materials, such as amorphous semiconductors, onto the platform or workpiece to form components of a device, such as a thin-film transistor.

"Valence band" refers to a band in which holes may move freely in a solid, producing a net charge transport. The valence band may be the highest occupied energy band. II. Designing Amorphous Semiconductors

Without being limited to a particular theory of operation, the present semiconductors are made by achieving an appropriate balance between covalent and ionic bonding and,

concomitantly, amorphous and crystalline microstructures. Consider amorphous oxide semiconductors and single-crystal or polycrystalline silicon. Chemical bonding is strongly ionic in amorphous oxide semiconductors and purely covalent in silicon. Ionic bonds are non- directional while covalent bonds are highly directional. Moderately large electron mobilities are obtained in amorphous oxide semiconductors - even with an amorphous microstructure - because of the non-directional nature of the ionic bonds. Improving the crystallinity of an amorphous oxide semiconductor would do little to improve mobility because of the ionic nature of the bonds. In contrast, high electron mobility in silicon is obtained only when a high degree of crystallinity is achieved. The mobility of hydrogenated amorphous silicon is approximately three orders of magnitude less than that of single crystal silicon due to covalent bonding and the strong contribution of p orbitals near the band edges (CBM and VBM).

Amorphous oxide semiconductors and silicon are limiting cases of ionic and covalent bonding, respectively. The present invention designs new types of semiconductors with intermediate ionicity. More ionic materials should be more tolerant of a less crystalline microstructure. Ideally, disclosed embodiments of exemplary semiconductors increase the covalent character of the amorphous oxide semiconductor bond to (1) increase the mobility, but (2) retain a sufficient degree of ionic bonding to minimize bandtail state formation.

Understanding covalent/ionic bonding trends is also a consideration for designing new types of amorphous semiconductors. [See B.D. Pelatt, R. Ravichandran, J.F. Wager, and D.A. Keszler, "Atomic Solid State Energy Scale," J. Am. Chem. Soc. 133, 16852-16860 (2011), which is incorporated herein by reference] . A basic problem with amorphous oxide

semiconductors is that the solid state energy (SSE) of oxygen is too negative to allow for p-type doping. This can be remedied by either alloying with or replacing oxygen with anions having less negative solid state energies. Certain disclosed embodiments concern new n- and p-type materials with a minimum band gap of 1 eV.

FIG. 1 is an idealized representation of the electronic density of states of a covalent and an ionic semiconductor, both having the same band gap, E_G. E_v denotes the top of the valence band, i.e., the energy band whose states are typically almost completely filled with electrons. Ec denotes the bottom of the conduction band, i.e., the energy band whose states are typically almost completely empty in terms of electron occupancy. Ionic bands are narrower than covalent bonds. An important consequence of having narrower bands is that the mobility tends to be smaller when the bands are narrower. This is true for both electrons moving near the bottom of the conduction band and for holes moving near the top of the valence band.

Again without being limited by a theory of operation, one premise for designing disclosed high mobility semiconductors is illustrated in FIG. 1. Note that an ionic

semiconductor will, in general, have narrower conduction and valence bands than a covalent semiconductor. Significantly, mobility tends to be smaller when a band is narrower. This is true for both electrons transported in states near the bottom of the conduction band, as well as for holes transported in states near the top of the valence band. Thus, beginning with an amorphous oxide semiconductor as a starting point, one strategy for improving mobility involves modifying the amorphous oxide semiconductor composition so that it is more covalent.

Prior to specifying a strategy for covalence engineering, consider the second problem to be solved - realization of a p-type amorphous semiconductor. Conventional amorphous oxide semiconductor choices, i.e., those not containing copper and silver, are unipolar, n-type materials. These materials cannot be doped p-type, since the top of the valence band is oxygen- derived, resulting in an ionization potential that is simply too deep for p-type doping.

FIG. 2 provides solid state energy values for 60 elements arranged in descending energy order with respect to the vacuum level. Solid state energy is assessed as an average electron affinity (for a cation, shown in blue) or an average ionization potential (for an anion, shown in red) for binary compounds having the atom under consideration as a constituent. Error bars correspond to maximum and minimum values from the available data. The dashed horizontal line at 4.5 eV corresponds to the hydrogen donor/acceptor ionization energy [ε(+/-)] or, equivalently, to the standard hydrogen electrode potential of electrochemistry as measured with respect to the vacuum level.

A convenient way to illustrate this is to employ a recently introduced concept of atomic solid state energy [See B.D. Pelatt, R. Ravichandran, J.F. Wager, and D.A. Keszler, "Atomic Solid State Energy Scale," J. Am. Chem. Soc. 133, 16852-16860 (2011)]. With reference to

FIG. 2, the oxygen solid state energy is located 7.7 eV below the vacuum level. This means that the ionization potential, i.e., the energy of separation between the top of the valence band and the vacuum level, is expected to be approximately 7.7 eV for a material in which the valence band is oxygen-derived. This is 3.2 eV below the hydrogen donor/acceptor ionization energy [ε(+/-)] or, equivalently, to the standard hydrogen electrode potential of electrochemistry.

As evident from FIG. 2, ε(+/-) is a demarcation energy, distinguishing cation/anion behavior. As currently understood, when the ionization energy of a material is greater than approximately 1.5 eV below ε(+/-), i.e., < -6 eV, it is difficult/impossible to dope this material p- type. Similarly when the electron affinity, i.e., the energy difference between the bottom of the conduction band and the vacuum level, is more than approximately 1.5 eV above ε(+/-), it is difficult/impossible to dope this material n-type. Therefore, one approach to preparing semiconductors according to the present invention to make amorphous p-type materials involves modifying an amorphous oxide semiconductor by partially/completely replacing oxygen with an anion having a solid state energy closer to ε(+/-). As evident from FIG. 2, particularly useful candidate anions are Sb, As, Te, Se, P, and perhaps S.

Replacing some or all of the oxygen with these anions in an amorphous oxide

semiconductor increases covalence. This also is evident from FIG. 2. Covalent materials have atoms in which both of their solid state energies are close to ε(+/-). Materials are more ionic as their solid state energies differ more from ε(+/-). Thus, ε(+/-) is a demarcation energy that facilitates distinguishing between covalent and ionic bonding.

For designing disclosed amorphous semiconductors, these solid state energy

considerations can be further refined with the aid of Table 1.

Table 1

Solid State Energy Values for 52 Elements Specified as a Function of Oxidation State with the most Common Oxidation State Denoted with *.

Oxidation SSE

Element State (eV)

Cs 1 -0.3

Rb 1 -0.5

K 1 -0.6

Li 1 -0.8

Na 1 -0.8

Sc 3 -0.9

Ba 2 -1

Se -2 -5.9

S -2 -6.2

C -4 -6.4

I -1 -6.4

0 -2 -7.6

Br -1 -7.9

N -3 -8

CI -1 -8.9

F -1 -12.1

First, amorphous semiconductor cation selection is considered. For a disclosed semiconductor to have adequate covalence, its solid state energy (SSE) should be separated from ε(+/-) by no more than about 1.5 eV such that -4.7 eV < SSE(cation) < -3 eV. Thus, according to Table 1, cations typically are selected from C = Zn⁺², Ga⁺³, As⁺³, As⁺⁵, In⁺³, Sn⁺², Sn⁺⁴, Sb⁺³, Sb⁺⁵, Bi⁺³, and Bi⁺⁵.

With reference to anion selection for making disclosed amorphous semiconductors, for a disclosed semiconductor to have adequate covalence, its SSE should be separated from ε(+/-) by no more than about 1.5 eV such that -6 eV < SSE(anion) < -4.5 eV. Thus, according to Table 1, Sb -^"3 , As -^"3 , Te -^"2 , P -^"3 , Se -^"2 , and S -^"2 satisfy this design guideline. Based on chemical trends, the solid state energy of Bi^" is expected to be near ε (+/-), so it is also added to the anion candidate list. A solid state energy estimate for Bi^" is not yet available.

In summary, for disclosed amorphous semiconductors, anions typically are selected from A = P^"3, As^"3, Sb^"3, S^"2, Se^"2, Te^"2, and Bi^"3.

Thus, one disclosed strategy for designing disclosed embodiments of high-performance amorphous semiconductors comprises first selecting suitable cation(s) and numbers thereof. Cations typically are selected from C = Zn⁺², Ga⁺³, As⁺³, As⁺⁵, In⁺³, Sn⁺², Sn⁺⁴, Sb⁺³, Sb⁺⁵, Bi⁺³, and Bi⁺⁵. Most embodiments select at least two cations to preclude, or at least substantially preclude, crystallization, thereby facilitating forming an amorphous micro structure. Second, suitable anions and numbers thereof are selected. Anions typically are selected from A = P^" ,

As -^"3 , Sb -^"3 , S -^"2 , Se -^"2 , Te -^"2 and Bi -^"3. Third, suitable additives and numbers thereof are selected. Additives typically are selected from W = Mg⁺², Ca⁺², Sr⁺², Ba⁺², B⁺³, Α ³, Sc⁺³, Y⁺³, La⁺³, Ce⁺³, Ce⁺⁴, O^"2, and F^"1. Combining oxygen and one other anion provides an opportunity to exploit the advantages of air processing. Including an additive with a lower solid state energy brings the top of the valence band closer to ε(+/-), affording greater covalence, improved hole mobility, and opportunities for p-type doping.

The maximum processing temperature is a consideration for determining the application space for disclosed embodiments of the high-performance amorphous semiconductors. For electronics -grade plastic substrate applications, a maximum process temperature of

approximately 150-250 °C is likely. For glass substrate applications, the maximum process temperature is approximately 300-400 °C. For back-end, silicon-based, integrated circuit applications, a maximum process temperature of approximately 400-600 °C is probable. A lower process temperature is usually desired because reduced processing temperatures result in fewer manufacturing challenges. Because such amorphous structures can be realized without thermal annealing, they potentially allow high-performance at low temperatures. Where higher performance and mobility are required, thermal annealing can be used to improve nearest- neighbor atom alignment without destroying the defined amorphous nature. Thus, disclosed embodiments of amorphous semiconductor materials satisfy a need for high-performance electronics on large-area glass substrates.

III. Embodiments of Amorphous Semiconductors

New amorphous semiconductors are determined based, at least in part, on the considerations discussed above. Such amorphous semiconductors also can be described with reference to various chemical formulas. A general chemical description of disclosed amorphous semiconductors is provided by Formula I:

Formula I

CW FA'LAWNWW Z

With reference to Formula I, C 1 , C2 , and C 3 are different cations; A 1 , A2 , and A 3 are different anions; W2", and W 3 are different additives; and subscripts D, E, F, L, M, N, X, Y, Z indicate the number of atoms of each element, thereby specifying the target atomic composition of the amorphous semiconductor.

Formula I can be expanded to more particularly describe combinations of elements used to form disclosed exemplary semiconductors. For example, Formula I can be expanded to expressly state numbers of cations, anions and additives, thus specifying the target amorphous semiconductor stoichiometry, as indicated by Formulas IA-IF.

Formula IA

Example: ZnTe + Zn₃Sb₂— > Zn4Sb₂Te

For this example, D = 4, L = 2, and M = 1. The cation (C = Zn) establishes the conduction band minimum (CBM), and the anions (A 1 = Sb and A 2 = Te) form the valence band maximum (VBM). Writing a chemical equation establishes the target stoichiometric composition of the amorphous semiconductor. For subsequent formula examples, constituent element identification is accomplished in the following manner:

CBM→ C = Zn; VBM→ A = Sb, Te

Formula IB

C_DA A'_MW_X

Example: ZnTe + Zn Sb₂ + 2ZnO— > Zn6Sb₂Te0₂

CBM→ C = Zn; VBM→ A = Sb, Te; W = O

In this example, O is an anion spectator additive because its SSE is so remote from ε(+/) compared to the other anions [i.e., ε(+/) = -4.5 eV, SSE(Sb^"3) = -4.9 eV, SSE(Te^{" 2}) = -5.3 eV, SSE(0^~2) = -7.7 eV < -6 eV].

Formula IC

C¹ _DC² _EA_X

Example: 2ZnTe + Sb₂Te — > Zn₂Sb₂Te₅

CBM→ C = Zn, Sb; VBM→ A = Te

In this example, Sb is a cation with SSE(Sb⁺³) = -4.2 eV, whereas in Formula IB Sb is an anion with SSE(Sb^"3) = -4.9 eV.

Formula ID

C c Wz

Example: Zn As₂ + 3InAs + AlAs— > Zn In AlAs₆ CBM→ C = Zn, In; VBM→ A = As; W = Al

In this example, Al is a cation spectator additive because its SSE is so remote from ε(+/) compared to the other cations [i.e., ε(+/) = -4.5 eV, SSE(In⁺³) = -4.6 eV, SSE(Zn⁺²) = -3.9 eV, SSE(Al⁺³) = -2.1 eV > -3 eV].

Formula IE

Example: Zn₃As₂ + Sn₃P₄— > Zn₃Sn₃As₂P₄

CBM→ C = Zn, Sn; VBM→ A = As, P

Formula IF

Example: 2ZnTe + Sn P₄ + Sn0₂-i— > Zn₂Sn₄P₄Te₂0₂

CBM→ C = Zn, Sn; VBM→ A = P, Te; W = O

With reference to Formulas IA-IF, the variables and the relative atomic percentages of the constituents, are as discussed above with reference to Formula I.

In particular disclosed embodiments, the amorphous semiconductor composition is selected to provide electron mobilities greater than 50 cm 2 V -^"1 s -^"1 , preferably greater than 100 cm 2 V-^"1 s-^"1 , and hole mobilities greater than 10 cm 2 V -^"1 s -^"1. Disclosed materials also have relatively low post-deposition annealing temperatures, such as an annealing temperature of 600 °C or less.

IV. Making Disclosed High-Performance Amorphous Semiconductors

Disclosed embodiments of the amorphous semiconductor may be made by any process suitable for forming amorphous semiconductors currently known to those having ordinary skill in the art, or such methods as may be hereafter developed. Once formed, these materials can be used to make a variety of electronic devices.

Typically the amorphous semiconductors pertinent to this disclosure will be employed as thin films. The thin film thickness can vary from approximately 10 nm to approximately 3 μιη, depending on the selected application. Suitable thin film deposition techniques for synthesizing amorphous semiconductors pertinent to this disclosure include: physical vapor deposition (PVD) [e.g., thermal evaporation, electron-beam evaporation, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), DC magnetron sputtering, RF magnetron sputtering, ion beam sputtering, reactive sputtering];

chemical vapor deposition (CVD) [e.g., atmospheric-pressure chemical vapor deposition

(APCVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), remote plasma-enhanced chemical vapor deposition (RPECVD), metal- organic chemical vapor deposition (MOCVD), mist chemical vapor deposition (MCVD), chemical closed-space vapor transport (CCSVT), atomic layer deposition (ALD), plasma- enhanced atomic layer deposition (PEALD), remote plasma-enhanced atomic layer deposition (RPEALD)]; and solution processing [e.g., spin-coating synthesis, slot-coating deposition, capillary coating, sol-gel processing, prompt inorganic condensation (PIC), ink jet printing, gravure printing, chemical bath deposition (CBD)].

Thin film deposition may be accomplished at or near room temperature (i.e., without intentional heating of the substrate upon which the amorphous semiconductor is deposited) or the substrate may be intentionally heated to an elevated temperature during thin film deposition. If a substrate is heated during thin film deposition, the substrate temperature chosen will depend on the substrate selected and on the chemical and physical properties of the amorphous semiconductor being deposited. For electronics-grade plastic substrate applications, a maximum process temperature typically ranges from about 100 °C to about 300 °C; more typically from about 150 °C to about 250 °C. For glass substrate applications, a maximum process temperature typically ranges from about 250 °C to about 450 °C; more typically from about 300 °C to about 250 °C. For back-end silicon-based integrated circuit applications, a maximum process temperature typically ranges from about 250 °C to about 650 °C; more typically from about 350 °C to about 600 °C. In particular disclosed embodiments, a low temperature is desired, such as approximately less than about 500 °C. The temperature considerations just discussed apply both to the substrate temperature during thin film deposition as well as to post-deposition annealing, as discussed in the following.

Post-deposition annealing typically is used for the synthesis of amorphous

semiconductor thin films pertinent to this disclosure. An elevated temperature often improves the electrical and/or optical properties of an as-deposited amorphous semiconductor thin film. The post-deposition anneal may be undertaken in a relatively inert gaseous ambient (e.g., vacuum, argon, or nitrogen), a reducing gaseous ambient (e.g., hydrogen or a hydrogen-nitrogen mixture), a reactive gaseous ambient (e.g., oxygen or an overpressure of an anion-based gaseous species [e.g., a post-deposition anneal of Zn₃In₃AlAs₆ might be accomplished in an AsH₃ overpressure in order to compensate for an As deficiency in the as-deposited film, thereby improving the stoichiometry of the amorphous thin film; anion deficiency is a common problem witnessed in as-deposited thin films]), or an activated reactive gaseous species [e.g., plasma- activated nitrogen, oxygen, or an overpressure of an anion-based gaseous species; plasma activation may be accomplished in a direct or a remote fashion, in which the plasma is either in direct contact with the substrate or is located at a remote distance from the substrate so that a flux of the activated reactive gaseous species is injected into the region of the reactor in which the substrate is placed].

A post-deposition anneal can improve the electrical and/or optical properties of an as- deposited amorphous semiconductor thin film for a variety of reasons, such as modifying film stoichiometry, introducing additives into the film, reducing the concentration of defects in the film, and reshaping the valence and/or conduction band tail state densities of the film.

V. Making Electronic Devices using High-Performance Amorphous Semiconductors

Once formed, the amorphous semiconductor materials are then used to fabricate desired electronic devices. Forming electronic devices requires fabrications processes for fabricating suitable structures from the disclosed amorphous semiconductors. Suitable fabrication processes include, but are not limited to, thin-film deposition techniques selected from sputtering, chemical vapor deposition (e.g. low-pressure, plasma-enhanced, and high density plasma), atomic layer deposition, electron beam deposition, sol-gel deposition, solution processing, thermal evaporation, or chemical bath deposition.

In particular disclosed embodiments, a thin film of a disclosed semiconductor material is deposited onto a suitable substrate using any suitable deposition technique. The substrate may be made from any suitable material, including semiconducting materials, non- semiconducting materials, and combinations of semiconducting materials and non-semiconducting materials. The substrate material optionally is an opaque material or a substantially transparent material. Illustrative substrate materials include glass plate, flexible glass, silicon, plastic (e.g. electronics- grade plastic), particularly for structurally flexible devices, where suitable polymeric materials include polyester, polycarbonate, polyimide sheets and the like, ceramics, and thin metal sheets.

The thin film is deposited onto a substrate material to provide a material layer of desired thickness. For example, the deposited film typically has a thickness of from about 10 nm to about 100 nm, and more typically from about 30 nm to about 50 nm.

The thickness of the substrate also may vary. The substrate thickness typically varies from about 1 μιη to at least about 1 cm, and more typically is from about 10 μιη to over 10 millimeters, with an exemplary thickness being from about 50 μιη to about 100 μιη, especially for a flexible plastic substrate, and from about 0.5 to about 10 millimeters for a rigid substrate, such as glass or silicon.

A person of ordinary skill in the art will recognize that the particular substrate used will affect processing, particularly the processing temperature. For example, in electronics -grade plastic substrate applications, a maximum process temperature typically ranges from about 100 °C to about 300 °C; more typically from about 150 °C to about 250 °C. For glass substrate applications, a maximum process temperature typically ranges from about 250 °C to about 450 °C; more typically from about 300 °C to about 250 °C. For back-end silicon-based integrated circuit applications, a maximum process temperature typically ranges from about 250 °C to about 650 °C; more typically from about 350 °C to about 600 °C. In particular disclosed embodiments, low temperatures are desired, such as approximately less than about 500 °C.

In particular disclosed embodiments, the chemical nature of the amorphous

semiconductor composition promotes or allows the use of low temperatures. In some embodiments, using a thermal annealing process is not required.

Electrical contact to the thin film and/or substrate, as desired, may be provided in any manner. For example, metal lines, traces, wires, interconnects, conductors, signal paths and signaling mediums may provide the desired electrical connections. Metal lines, generally aluminum (Al), copper (Cu) or an alloy of Al and Cu, are conductors that provide signal paths for coupling or interconnecting, electrical circuitry. Conductors other than metal, such as a transparent conducting oxide, may also be utilized. VI. Devices

The amorphous semiconductors disclosed herein are useful for a variety of applications, particularly for manufacturing electronic devices. Examples of electronic devices, or components of devices, that can be made according to this invention include, without limitation, transistors, such as a channel layer for a thin-film transistor or field-effect transistor;

photovoltaic s, such as an absorber for a thin-film solar cell; pixel switches and drivers for active-matrix, liquid-crystal displays; active-matrix, light-emitting displays; electrophoretic displays; analog, digital, and/or power electronics for macroelectronics; radio-frequency identification tags; switches for use in integrated circuits that are fabricated near the back-end of an integrated circuit process; and other suitable devices.

Thin-film transistors are a particular class of components that will be made using disclosed embodiments of the amorphous semiconductors. Various thin-film transistor architectures are possible, as illustrated in FIGS. 3-6, involving permutations of top/bottom gate and staggered/coplanar arrangement of S/D and G contacts. All known and hereafter developed transistor structures are within the scope of the present invention.

Most amorphous oxide semiconductor thin-film transistor development has concentrated on using a staggered/bottom gate structure. This structure is preferred for flat-panel display applications. Another primary architecture of interest is a top-gate thin-film transistor. A thin- film transistor generally includes a substrate, a gate electrode, source electrode, drain electrode, and a dielectric layer in addition to the semiconducting layer.

A bottom gate thin-film transistor (TFT) device typically includes a gate electrode layer disposed on a substrate covered with a gate insulator layer. A semiconductor layer, comprising a disclosed embodiment of an amorphous semiconductor, is disposed over the gate insulator layer. An n-type or p-type layer is disposed over the semiconductor layer. After formation of the doped semiconductor layer, a source-drain metal electrode layer is disposed thereon. A passivation layer is subsequently formed thereon to produce the thin-film transistor device.

The gate electrode is an electrically conductive material. It can be a thin metal film, a conducting polymer film, a conducting film made from conducting ink or paste, or the substrate itself, for example heavily doped silicon. Examples of gate electrode materials include, but are not limited to, aluminum, gold, silver, chromium, indium tin oxide, conductive polymers such as polystyrene sulfonate-doped poly(3,4-ethylenedioxythiophene) (PSS-PEDOT), and conducting ink/paste comprised of carbon black/graphite. The gate electrode can be prepared by vacuum evaporation, sputtering of metals or conductive metal oxides, conventional lithography and etching, chemical vapor deposition, spin coating, casting or printing, or other deposition processes. Gate electrode thicknesses range from about 10 to about 200 nanometers for metal films and from about 1 to about 10 μιη for conductive polymers. Typical materials suitable for use as source and drain electrodes include those of the gate electrode materials such as aluminum, gold, silver, chromium, zinc, indium, conductive metal oxides such as zinc-gallium oxide, indium tin oxide, indium- antimony oxide, conducting polymers and conducting inks. Typical thicknesses of source and drain electrodes are, for example, from about 40 nanometers to about 1 μιη, including more specific thicknesses of from about 100 to about 400 nanometers.

The substrate may be a glass substrate, a plastic substrate, a polymer substrate, a metal substrate, or other suitable substrate suitable for forming a thin-film transistor.

The gate electrode layer may be fabricated from any suitable metallic materials, such as indium tin oxide (ITO), tin oxide (SnO), indium zinc oxide (IZO), indium tin zinc oxide (ΓΓΖΟ), aluminum (Al), tungsten (W), chromium (Cr), germanium (Ge), tantalum (Ta), titanium (Ti), gold (Au), alloy of titanium (Ti) and gold (Au), alloy of tantalum (Ta) and gold (Au), alloy of germanium (Ge) and gold (Au), molybdenum (Mo), or combinations thereof. Suitable materials for the gate insulator layer may be silicon oxide, silicon oxynitride (SiON), or silicon nitride (SiN), high-k materials, such as Hf0₂, or other suitable materials.

The source-drain metal electrode layer may be fabricated using a metallic material. For example, the metallic material may be selected from copper (Cu), gold (Au), silver (Ag), aluminum(Al), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), cobalt (Co), tantalum (Ta), titanium (Ti), gold (Au), and alloys thereof. The passivation layer may be fabricated by dielectric materials including silicon oxide silicon oxynitride (SiON), or silicon nitride (SiN), suitable polymer materials, such as polymethylmethacrylate (PMMA).

Typical materials suitable for use as source and drain electrodes include gold, silver, nickel, aluminum, platinum, conducting polymers, and conducting inks. In specific

embodiments, the electrode materials provide low contact resistance to the semiconductor.

Typical thicknesses are from about 40 nanometers to about 1 μιη with a more specific thickness being about 100 to about 400 nanometers. The semiconductor channel width may be, for example, from about 5 μιη to about 5 millimeters, more typically from about 100 μιη to about 1 millimeter. The semiconductor channel length may be, for example, from about 1 μιη to about 1 millimeter, and more typically from about 5 μιη to about 100 micrometers.

If desired, a barrier layer may also be deposited on top of the TFT to protect it from environmental conditions, such as light, oxygen and moisture, etc., which can degrade its electrical properties. Such barrier layers are known in the art and may simply consist of an inorganic insulating layer or a polymer.

The various components of the thin-film transistor may be deposited upon the substrate in any order. Generally, however, the gate electrode and the semiconducting layer should both be in contact with the gate dielectric layer, and the source and drain electrodes should both be in contact with the semiconducting layer. "In any order" includes sequential and simultaneous formation. For example, the source electrode and the drain electrode can be formed

simultaneously or sequentially.

Disclosed embodiments of the amorphous semiconductors may be used to make a top metal gate structure thin-film transistor device. Top metal gate structure thin-film transistor devices typically include a metal gate electrode disposed on a backside of a substrate. An insulator layer may be formed on an opposite side (e.g., front side) of the substrate. A semiconductor layer comprising a disclosed embodiment of an amorphous semiconductor is disposed over the insulator layer. Subsequently, a source-drain metal electrode layer is then disposed over the semiconductor layer to form the thin-film transistor device.

Another exemplary thin-film transistor device according to one embodiment of the present disclosure includes a semiconductor layer disposed on a substrate. An insulator layer may be formed over the semiconductor layer in between a patterned source-drain metal electrode layer. A gate electrode layer is disposed over the insulator layer to form the thin-film transistor device.

Yet another embodiment of a thin-film transistor device includes a buffer oxide layer disposed on a substrate. A semiconductor layer comprising a disclosed semiconductor is disposed between a patterned source-drain metal electrode layer. A gate insulator layer is then disposed over the semiconductor layer, followed by a metal gate electrode layer. Yet another embodiment of a thin-film transistor device includes a gate insulator layer disposed on a substrate. A layer comprising a disclosed semiconductor is disposed on the gate insulator layer. A patterned source-drain electrode layer is then disposed on the semiconductor layer. Subsequently, a passivation layer is disposed on the patterned source-drain electrode layer.

Display devices also can be made using disclosed embodiments of amorphous semiconductors, or compositions comprising at least one amorphous semiconductor. For example, an exemplary display device might comprise plural thin-film transistors over a substrate; and a pixel electrode connected to the thin-film transistors.

Solar cells also can be made using disclosed embodiments of amorphous

semiconductors.

A person of ordinary skill in the art will appreciate that exemplary semiconductor materials, methods for making semiconductors, and devices that incorporate the semiconductor materials, are disclosed. Other suitable methods and semiconductor devices not disclosed herein and having semiconductor layers or other suitable active or non-active layers formed therein, may also be formed using disclosed embodiments of high-performance semiconductor materials.

Claims

We claim:

1. An amorphous semiconductor having a formula

Formula I

where:

each C is a different cation that is selected based on criteria comprising forming spherically symmetric 4s-, 5s-, or 6s-derived conduction bands, substantially precluding crystallization, facilitating formation of an amorphous microstructure, providing a closed shell configuration, and combinations thereof;

each A is a different anion that is selected based on criteria comprising suppressing crystallization, facilitating processability, providing a desired bandgap, providing a desired covalence, selecting anions to provide a closed shell configuration, and combinations thereof; each W is a different additive; and

D, E, F, L, M, N, X, Y and Z denote relative stoichiometric amounts of C, A and W.

2. The semiconductor according to claim 1 wherein:

C is selected from Zn⁺², Ga⁺³, As⁺³, As⁺⁵, In⁺³, Sn⁺², Sn⁺⁴, Sb⁺³, Sb⁺⁵, Bi⁺³, andBi⁺⁵; A is selected from P^"3, As^"3, Sb^"3, S^"2, Se^"2, Te^"2 and ΒΓ³; and

W is selected from Mg⁺², Ca⁺², Sr⁺², Ba⁺², B⁺³, Al⁺³, Sc⁺³, Y⁺³, La⁺³, Ce⁺³, Ce⁺⁴, O ², and

3. The amorphous semiconductor according to claim 1 having a formula

Formula IA

CDA A'M,

where:

C is selected from Zn⁺², Ga⁺³, As⁺³, As⁺⁵, In⁺³, Sn⁺², Sn⁺⁴, Sb⁺³, Sb⁺⁵, Bi⁺³, andBi⁺⁵; and A is selected from P^"3, As^"3, Sb^"3, S^"2, Se^"2, Te^"2 and Bi^"3.

4. The semiconductor according to claim 1 having a formula

Formula IB C_DA^_MW_X,

where:

C is selected from Zn⁺², Ga⁺³, As⁺³, As⁺⁵, In⁺³, Sn⁺², Sn⁺⁴, Sb⁺³, Sb⁺⁵, Bi⁺³, and Bi⁺⁵; A is selected from P^"3, As^"3, Sb^"3, S^"2, Se^"2, Te^"2 and ΒΓ³; and

W is selected from Mg⁺², Ca⁺², Sr⁺², Ba⁺², B⁺³, Al⁺³, Sc⁺³, Y⁺³, La⁺³, Ce⁺³, Ce⁺⁴, O ², and

5. The semiconductor according to claim 1 having a formula

Formula IC

C^C^Ax,

where:

C is selected from Zn⁺², Ga⁺³, As⁺³, As⁺⁵, In⁺³, Sn⁺², Sn⁺⁴, Sb⁺³, Sb⁺⁵, Bi⁺³, and Bi⁺⁵; and A is selected from P^"3, As^"3, Sb^"3, S^"2, Se^"2, Te^"2 and Bi^"3.

6. The semiconductor according to claim 1 having a formula

Formula ID

C is selected from Zn⁺², Ga⁺³, As⁺³, As⁺⁵, In⁺³, Sn⁺², Sn⁺⁴, Sb⁺³, Sb⁺⁵, Bi⁺³, and Bi⁺⁵; A is selected from P^"3, As^"3, Sb^"3, S^"2, Se^"2, Te^"2 and Bi^"3; and

W is selected from Mg⁺², Ca⁺², Sr⁺², Ba⁺², B⁺³, Al⁺³, Sc⁺³, Y⁺³, La⁺³, Ce⁺³, Ce⁺⁴, O^"2, and

7. The semiconductor according to claim 1 having a formula

Formula IE

C is selected from Zn , Ga , As , As , In , Sn , Sn , Sb , Sb , Bi , and Bi⁺; A is selected from P^"3, As^"3, Sb^"3, S^"2, Se^"2, Te^"2 and Bi^"3; and

W is selected from Mg⁺², Ca⁺², Sr⁺², Ba⁺², B⁺³, Al⁺³, Sc⁺³, Y⁺³, La⁺³, Ce⁺³, Ce⁺⁴, O^"2, and

8. The semiconductor according to claim 1 having a formula

Formula IF

where:

C is selected from Zn , Ga , As , As , In , Sn , Sn , Sb , Sb , Bi , and Bi⁺³; A is selected from P^"3, As^"3, Sb^"3, S^"2, Se^"2, Te^"2 and ΒΓ³; and

W is selected from Mg⁺², Ca⁺², Sr⁺², Ba⁺², B⁺³, Al⁺³, Sc⁺³, Y⁺³, La⁺³, Ce⁺³, Ce⁺⁴, O ², and

F¹.

9. The semiconductor according to claim 1 having an electron mobility greater than

50 cmVY¹.

The semiconductor according to claim 1 having an electron mobility greater than 100 cmVY¹.

11. The semiconductor according to claim 1 having a hole mobility greater than 10 cmVY¹.

12. The semiconductor according to claim 1 having a post-deposition annealing temperature of about 600 °C or less.

13. A method for making an amorphous semiconductor, comprising:

providing at least one cation selected from C = Zn⁺², Ga⁺³, As⁺³, As⁺⁵, In⁺³, Sn⁺², Sn⁺⁴, Sb⁺³, Sb⁺⁵, Bi⁺³, and Bi⁺⁵;

providing at least one anion selected from A = -3

P , As -3 , Sb -3 , S -2 , Se -^"2 Te -2 , and ΒΓ -3; optionally providing an additive selected from W = Mg⁺², Ca⁺², Sr⁺², Ba⁺², B⁺³, ΑΓ³, Sc⁺³, Y⁺³, La⁺³, Ce⁺³, Ce⁺⁴, O^"2, and F¹;

combining the at least one cation C, the at least one anion A, and any optional additive W, in appropriate stoichiometric amounts, thereby forming a mixture; and

processing the mixture to form the amorphous semiconductor.

14. The method according to claim 13 where the amorphous semiconductor has

Formula I

where:

c 1¹, cr2, c 3^J are different cations;

A 1 , A2", A 3^J are different anions;

1 2 3 are different additives; and

subscripts D, E, F, L, M, N, X, Y, Z indicate the number of atoms of each element, thereby specifying the target atomic composition of the amorphous semiconductor.

15. The method according to claim 13 where the amorphous semiconductor has a formula

Formula IA

where:

C is selected from Zn , Ga , As , As , In , Sn , Sn , Sb , Sb , Bi , and Bi⁺³; and A is selected from P^"3, As^"3, Sb^"3, S^"2, Se^"2, Te^"2 and Bi^"3.

16. The method according to claim 13 where the amorphous semiconductor has formula

Formula IB

C_DA A'_MW_X,

where:

C is selected from Zn⁺², Ga⁺³, As⁺³, As⁺⁵, In⁺³, Sn⁺², Sn⁺⁴, Sb⁺³, Sb⁺⁵, Bi⁺³, and Bi⁺⁵;

A is selected from P^"3, As^"3, Sb^"3, S^"2, Se^"2, Te^"2 and Bi^"3; and

W is selected from Mg⁺², Ca⁺², Sr⁺², Ba⁺², B⁺³, Al⁺³, Sc⁺³, Y⁺³, La⁺³, Ce⁺³, Ce⁺⁴, O^"2, and

F ¹.

17. The method according to claim 13 where the amorphous semiconductor has a formula Formula IC

C^C^Ax,

where:

C is selected from Zn⁺², Ga⁺³, As⁺³, As⁺⁵, In⁺³, Sn⁺², Sn⁺⁴, Sb⁺³, Sb⁺⁵, Bi⁺³, and Bi⁺⁵; and A is selected from P^"3, As^"3, Sb^"3, S^"2, Se^"2, Te^"2 and Bi^"3.

18. The method according to claim 13 where the amorphous semiconductor has formula

Formula ID

C c Wz,

where:

C is selected from Zn , Ga , As , As , In , Sn , Sn , Sb , Sb , Bi , and Bi⁺³; A is selected from P^"3, As^"3, Sb^"3, S^"2, Se^"2, Te^"2 and Bi^"3; and

W is selected from Mg⁺², Ca⁺², Sr⁺², Ba⁺², B⁺³, Al⁺³, Sc⁺³, Y⁺³, La⁺³, Ce⁺³, Ce⁺⁴, O^"2, and F^"1.

19. The method according to claim 13 where the amorphous semiconductor has formula

Formula IE where:

C is selected from Zn , Ga , As^+J, As⁺³, In , Sn^+/, Sn⁺⁴, Sb^+J, Sb⁺³, Β , and Bi⁺³; A is selected from P^"3, As^"3, Sb^"3, S^"2, Se^"2, Te^"2 and Bi^"3; and

W is selected from Mg⁺², Ca⁺², Sr⁺², Ba⁺², B⁺³, Al⁺³, Sc⁺³, Y⁺³, La⁺³, Ce⁺³, Ce⁺⁴, O^"2, and F^"1.

20. The method according to claim 13 where the amorphous semiconductor has formula

Formula IF

where: C is selected from Zn , Ga , As , As , In , Sn , Sn , Sb , Sb , Bi , and Bi⁺³; A is selected from P^"3, As^"3, Sb^"3, S^"2, Se^"2, Te^"2 and Bi^"3; and

W is selected from Mg⁺², Ca⁺², Sr⁺², Ba⁺², B⁺³, Al⁺³, Sc⁺³, Y⁺³, La⁺³, Ce⁺³, Ce⁺⁴, O^"2, and

F¹.

21. The method according to claim 13 where the amorphous semiconductor has an electron mobility greater than 50 cm 2 V -^"1 s -^"1.

22. The method according to claim 13 where the amorphous semiconductor has an electron mobility greater than 100 cm 2 V -^"1 s -^"1.

23. The method according to claim 13 where the amorphous semiconductor has a hole mobility greater than 10 cm 2 V -^"1 s -^"1.

24. The method according to claim 13 where the amorphous semiconductor has a post-deposition annealing temperature of about 600 °C or less.

25. A method for making an electronic device, comprising;

providing an amorphous semiconductor according to any of claims 1-12; and making an electronic device comprising the amorphous semiconductor.

26. The method according to claim 25 where providing comprises obtaining.

27. The method according to claim 25 where providing comprises making.

28. The method according to claim 25 where the device is a thin film transistor.

29. An electronic device comprising a semiconductor according to any of claims 1-

12. A thin film transistor comprising a semiconductor according to any of claims 1-

An electronic device made according to any of claims 23-28.

A thin film transistor made according to the method of claim 28.