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WO2014199199A1 - 半导体存储器装置及其ecc方法 - Google Patents

半导体存储器装置及其ecc方法 Download PDF

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Publication number
WO2014199199A1
WO2014199199A1 PCT/IB2013/054868 IB2013054868W WO2014199199A1 WO 2014199199 A1 WO2014199199 A1 WO 2014199199A1 IB 2013054868 W IB2013054868 W IB 2013054868W WO 2014199199 A1 WO2014199199 A1 WO 2014199199A1
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WIPO (PCT)
Prior art keywords
error correction
data
memory
correction circuit
write data
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Ceased
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PCT/IB2013/054868
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English (en)
French (fr)
Inventor
金甫根
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to PCT/IB2013/054868 priority Critical patent/WO2014199199A1/zh
Priority to CN201380077420.3A priority patent/CN105518800B/zh
Priority to US14/895,819 priority patent/US20160132388A1/en
Publication of WO2014199199A1 publication Critical patent/WO2014199199A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction

Definitions

  • the inventive concept described herein relates to a semiconductor memory device including different types of nonvolatile memories.
  • Semiconductor memory devices can be volatile or non-volatile. Volatile memory devices can have fast read and write speeds, while content stored in volatile memory devices can be lost in the event of a power outage. On the other hand, the non-volatile memory device can retain the content stored therein even when the power is turned off. Therefore, the non-volatile memory device can be used to store content that must be saved regardless of whether or not the power is supplied.
  • Flash memory devices are available as high integration and high capacity non-volatile semiconductor memory devices in handheld electronic devices.
  • a magnetic random access memory (hereinafter, referred to as MRAM) can use a magnetic element as a random access, high integration, and large capacity nonvolatile element.
  • MRAM magnetic random access memory
  • the advantages of MRAM can be fast response speed and high integration.
  • An aspect of an embodiment of the inventive concept provides a semiconductor memory device including: a first nonvolatile memory; a second nonvolatile memory having a first nonvolatile memory a type of a different type; the controller is configured to control the first non-volatile memory and the second non-volatile memory; the first error correction circuit is configured to correct the first programming in the first non-volatile memory An error in writing data; and a second error correction circuit included in the controller and configured to correct an error of the first write data or a second non-error based on an error correction algorithm different from an error correction algorithm of the first error correction circuit
  • the volatile memory performs an error of the second write data that is programmed, wherein an error for correcting the first write data is generated using one of the first error correction circuit and the second error correction circuit according to the attribute of the first write data. Wrong data.
  • error correction data is generated using the first error correction circuit.
  • the second error correction circuit is used to generate error correction data.
  • error correction data is generated using a second error correction circuit that is temporarily programmed in the first non-volatile memory to write the buffered data to The data of the second non-volatile memory.
  • the first error correction circuit is included in the first non-volatile memory.
  • the first error correction circuit is included in the controller.
  • the programming speed of the first non-volatile memory is faster than the programming speed of the second non-volatile memory.
  • the first non-volatile memory is a resistive memory that reads a resistance value between the two ends of the memory cell to determine data stored in the memory cell.
  • the first non-volatile memory is a magnetic random access memory.
  • the second non-volatile memory is a NAND flash memory.
  • the first error correction circuit generates error correction data in accordance with an error correction algorithm using a Hamming code.
  • the second error correction circuit generates error correction data according to an error correction algorithm using a BCH code or an LDPC code.
  • Another aspect of an embodiment of the inventive concept provides an ECC method of a semiconductor memory device, the semiconductor memory device including: a first nonvolatile memory; and a second nonvolatile memory having a type of a different type of memory; and a controller that controls the first non-volatile memory and the second non-volatile memory.
  • the ECC method includes: determining an attribute of write data programmed in a first non-volatile memory; using a first non-volatile memory and a second according to an attribute of the write data and a type of the first non-volatile memory One of the nonvolatile memories generates error correction data for correcting the error of the write data; and stores the error correction data, wherein the first error correction circuit and the second error correction circuit generate error correction data according to different error correction algorithms .
  • the semiconductor memory device controls the controller such that error correction data of the write data programmed in the second non-volatile memory is generated using the second error correction circuit.
  • the semiconductor memory device stores error correction data in a first non-volatile memory, a second non-volatile memory, or a controller.
  • a semiconductor memory device including different types of nonvolatile memories may be configured to selectively use a portion of a plurality of error correction circuits to correct an error of writing data, wherein A plurality of error correction circuits apply different error correction algorithms depending on the nature of the write data and the type of non-volatile memory in which the write data is programmed. Therefore, the data can be corrected by using an error correction algorithm that is most suitable for the attributes of the write data and the type of the nonvolatile memory to perform error correction efficiently.
  • FIG. 1 is a block diagram schematically illustrating a semiconductor memory device, according to an embodiment of the inventive concepts
  • FIG. 2 is a block diagram schematically illustrating a semiconductor memory device according to another embodiment of the inventive concepts
  • 3 to 5 are block diagrams schematically showing an ECC method of the semiconductor memory device of Fig. 1;
  • 6 to 8 are block diagrams schematically showing an ECC method of the semiconductor memory device of Fig. 2;
  • Figure 9 is a block diagram schematically showing the first nonvolatile memory of Figure 1;
  • FIG. 10 is a diagram schematically showing a memory unit of the first nonvolatile memory of FIG. 9, in which it is assumed that the first nonvolatile memory 110 (refer to FIG. 9) is an MRAM;
  • Figure 11 is a block diagram schematically showing the second nonvolatile memory of Figure 1;
  • FIG. 12 is a flowchart schematically illustrating an ECC method of a semiconductor memory device, according to an embodiment of the inventive concepts
  • FIG. 13 is a flowchart schematically illustrating an ECC method of a semiconductor memory device, according to another embodiment of the inventive concepts.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, Layers and/or parts are not limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed below may be referred to as a second element, component, region, layer or section, without departing from the teachings of the present invention.
  • FIG. 1 is a block diagram schematically illustrating a semiconductor memory device, according to an embodiment of the inventive concepts.
  • the semiconductor memory device 100 may include a first nonvolatile memory 110, a second nonvolatile memory 120, a controller 130, a first error correction circuit 140, and a second error correction circuit 150.
  • FIG. 1 an example in which semiconductor memory device 100 includes two different types of non-volatile memories 110 and 120 is shown.
  • the semiconductor memory device 100 may further include a nonvolatile memory (not shown) of the same type or type as the first nonvolatile memory 110 or the second nonvolatile memory 120.
  • the first non-volatile memory 110 may include a first error correction circuit 140 and the controller 130 may include a second error correction circuit 150.
  • the first nonvolatile memory 110 can receive and store the first write data WD1 according to the control of the controller 130.
  • the first non-volatile memory 110 may use the first error correction circuit 140 to generate error correction data for correcting the error of the first write data WD1.
  • the error correction data may refer to ECC data.
  • the first non-volatile memory 110 can be a particular type of non-volatile memory.
  • the first non-volatile memory 110 can be an MRAM.
  • the type of the second nonvolatile memory 120 may be different from the type of the first nonvolatile memory 110.
  • the second non-volatile memory 120 may be a NAND flash memory.
  • the second nonvolatile memory 120 can receive and store the second write data WD2 according to the control of the controller 130. Error correction data for correcting the error of the second write data WD2 can be generated by the second error correction circuit 150.
  • the controller 130 can control program operations of the first nonvolatile memory 110 and the second nonvolatile memory 120.
  • the controller 130 may include a second error correction circuit 150 and may use the second error correction circuit 150 to generate error correction data for correcting the error of the first write data WD1 or the second write data WD2.
  • the first error correction circuit 140 may be an error correction circuit that corrects an error of the first write data WD1.
  • the first error correction circuit 140 may generate error correction data of the first write data WD1 according to a predetermined error correction algorithm.
  • the error correction algorithm of the first error correction circuit 140 may be an algorithm suitable for processing data having a small size and requiring high reliability.
  • the first error correction circuit 140 may generate error correction data of the first write data WD1 using an error correction algorithm using a Hamming code.
  • the second error correction circuit 150 can be used to correct an error of the second write data WD2.
  • the semiconductor memory device 100 can generate error correction data of the second write data WD2 using the second error correction circuit 150.
  • the second error correction circuit 150 can be selectively used to correct the error of the first write data WD1.
  • the first write data WD1 may have attributes of metadata, standard data, or buffered data.
  • the second error correction circuit 150 may generate error correction data of the first write data WD1 or the second write data WD2 according to an error correction algorithm different from the error correction algorithm of the first error correction circuit 140.
  • the error correction algorithm of the second error correction circuit 150 may be an algorithm suitable for processing data having a large size and requiring low reliability.
  • the second error correction circuit 150 may use an error correction using a BCH (Bose-Chaudhuri-Hocquenghem) code or an LDPC (Low Density Parity Check) code.
  • BCH Bose-Chaudhuri-Hocquenghem
  • LDPC Low Density Parity Check
  • the first write data WD1 may be programmed in the first non-volatile memory 110
  • the second write data WD2 may be programmed in the second non-volatile memory 120.
  • the minimum programming unit of the first non-volatile memory 110 may be smaller than the minimum programming unit of the second non-volatile memory 120, and the reliability of the first non-volatile memory 110 may be lower than the second non-volatile memory 120 Reliability.
  • the first non-volatile memory 110 may be a resistive random access memory.
  • the resistive random access memory can be MRAM, PRAM or RRAM.
  • the second non-volatile memory 120 can be a NAND flash memory.
  • the semiconductor memory device 100 can selectively use one of the first error correction circuit 140 and the second error correction circuit 150 according to the attribute of the first write data WD1. For example, if the first write data WD1 is metadata having a small size and requiring high reliability, the semiconductor memory device 100 may generate the first using the first error correction circuit 140 most suitable for the first nonvolatile memory 110. The error correction data of the data WD1 is written. On the other hand, if the first write data WD1 is standard data having a large size and requiring low reliability, the semiconductor memory device 100 can generate the first write data using the second error correcting circuit 150 that is most suitable for correcting the erroneous data. WD1 error correction data.
  • the semiconductor memory device 100 can use the second error correction circuit 150 to generate error correction data of the second write data WD2. Since the second write data WD2 is programmed in the second error correction circuit 150 having a relatively small minimum programming unit and low reliability, the second error correction circuit 150, which is most suitable for processing a large amount of data, can be used to generate the second write data WD2. Correct the data.
  • a semiconductor memory device including different types of nonvolatile memories may be configured to selectively use a portion of a plurality of error correction circuits to correct an error of writing data, wherein the plurality of The error correction circuit applies different error correction algorithms depending on the nature of the write data and the type of non-volatile memory in which the write data is programmed. Therefore, the error can be corrected by using an error correction algorithm that is most suitable for the attribute of the write data and the type of the nonvolatile memory to perform the error correction efficiently.
  • FIG. 2 is a block diagram schematically illustrating a semiconductor memory device in accordance with another embodiment of the inventive concepts.
  • the semiconductor memory device 200 may include a first nonvolatile memory 210, a second nonvolatile memory 220, a controller 230, a first error correction circuit 240, and a second error correction circuit 250.
  • the semiconductor memory device 200 includes two different types of nonvolatile memories 210 and 220 is shown.
  • the semiconductor memory device 200 may further include a nonvolatile memory (not shown) of the same type or different type as the first nonvolatile memory 210 or the second nonvolatile memory 220.
  • controller 230 may include both first error correction circuit 240 and second error correction circuit 250.
  • the first nonvolatile memory 210 can receive and store the first write data WD1 according to the control of the controller 230. .
  • the first non-volatile memory 210 can be a particular type of non-volatile memory.
  • the first non-volatile memory 210 can be an MRAM.
  • the first write data WD1 can be generated by the first error correction circuit 240 included in the controller 230. Wrong error correction data.
  • the generated error correction data may be stored in the first non-volatile memory 210, the second non-volatile memory 220, or the controller 230. In a separate register (not shown).
  • the error correction data may refer to ECC data.
  • the type of the second nonvolatile memory 220 may be the same as the first nonvolatile memory 210 The type is different.
  • the second non-volatile memory 220 may be a NAND flash memory.
  • Second non-volatile memory 220 The second write data WD2 can be received and stored according to the control of the controller 230. Error correction data for correcting the error of the second write data WD2 can be generated by the second error correction circuit 250. Second error correction circuit 250 generating error correction data for correcting the error of the second write data WD2, and the generated error correction data may be stored in the first nonvolatile memory 210, the second nonvolatile memory 220, or the controller. In a separate register (not shown) in 230.
  • the controller 230 can control program operations of the first nonvolatile memory 210 and the second nonvolatile memory 220. Controller 230 may include both the first error correction circuit 240 and the second error correction circuit 250, and may use the first error correction circuit 240 or the second error correction circuit 250 to generate a first write data for correcting WD1. Or the wrong error correction data of the second write data WD2.
  • the first error correction circuit 240 may be an error correction circuit that corrects the error of the first write data WD1.
  • First error correction circuit 240 The error correction data of the first write data WD1 can be generated according to a predetermined error correction algorithm.
  • the first error correction circuit 240 The error correction algorithm can be an algorithm suitable for processing data having a small size and requiring high reliability.
  • the first error correction circuit 240 can generate the first write data using an error correction algorithm using a Hamming code. Error correction data.
  • the second error correction circuit 250 can be used to correct the error of the second write data WD2.
  • semiconductor memory device 200 The second error correction circuit 250 can be used to generate error correction data for the second write data WD2.
  • the second error correction circuit 250 can be selectively used to correct the first write data WD1 mistake.
  • the first write data WD1 may have attributes of metadata, standard data, or buffered data.
  • the second error correction circuit 250 may generate error correction data of the first write data WD1 or the second write data WD2 according to an error correction algorithm different from the error correction algorithm of the first error correction circuit 240.
  • the error correction algorithm of the second error correction circuit 250 may be an algorithm suitable for processing data having a large size and requiring low reliability.
  • the second error correction circuit 250 may use an error correction using a BCH (Bose-Chaudhuri-Hocquenghem) code or an LDPC (Low Density Parity Check) code.
  • BCH Bose-Chaudhuri-Hocquenghem
  • LDPC Low Density Parity Check
  • the first write data WD1 may be programmed in the first non-volatile memory 210
  • the second write data WD2 may be programmed in the second non-volatile memory 220.
  • the minimum programming unit of the first non-volatile memory 210 may be smaller than the minimum programming unit of the second non-volatile memory 220, and the reliability of the first non-volatile memory 210 may be lower than the second non-volatile memory 220 Reliability.
  • the first non-volatile memory 210 may be a resistive random access memory.
  • the resistive random access memory can be MRAM, PRAM or RRAM.
  • the second non-volatile memory 220 can be a NAND flash memory.
  • the semiconductor memory device 200 can selectively use one of the first error correction circuit 240 and the second error correction circuit 250 according to the attribute of the first write data WD1. For example, if the first write data WD1 is metadata having a small size and requiring high reliability, the semiconductor memory device 200 may generate the first using the first error correction circuit 240 most suitable for the first nonvolatile memory 210. The error correction data of the data WD1 is written. On the other hand, if the first write data WD1 is standard data having a large size and requiring low reliability, the semiconductor memory device 200 can generate the first write using the second error correcting circuit 250 which is most suitable for correcting errors of a large amount of data. Error correction data of data WD1.
  • the semiconductor memory device 200 can use the second error correction circuit 250 to generate error correction data of the second write data WD2. Since the second write data WD2 is programmed in the second non-volatile memory 220, which is relatively small and has the lowest reliability, the second error correction circuit 250, which is most suitable for processing a large amount of data, can be used to generate the second write. Error correction data of data WD2.
  • a semiconductor memory device including different types of nonvolatile memories may be configured to selectively use a portion of a plurality of error correction circuits to correct an error of writing data, wherein the plurality of The error correction circuit applies different error correction algorithms depending on the type of write data and the type of non-volatile memory in which the write data is programmed. Therefore, the error can be corrected by using an error correction algorithm that is most suitable for the attribute of writing data and the type of nonvolatile memory to perform error correction efficiently.
  • FIGS. 3 to 5 are block diagrams schematically showing an ECC method of the semiconductor memory device of Fig. 1.
  • the semiconductor memory devices 300, 400, and 500 illustrated in FIGS. 3 through 5 can be constructed substantially the same as the semiconductor memory device 100 of FIG.
  • first error correction circuits 340, 440, and 540 may be included in first nonvolatile memories 310, 410, and 510, respectively
  • second error correction circuits 350, 450, and 550 may be Included in controllers 330, 430, and 530, respectively.
  • Metadata can have a relatively small size and requires high reliability.
  • the first non-volatile memory 310 can be adapted to store such data as compared to the second non-volatile memory 320. Therefore, in the case where the first write data WD1 is metadata, the semiconductor memory device 300 can transfer the first write data WD1 to the first nonvolatile memory 310, and can control the first nonvolatile memory 310 such that An error correction circuit 340 generates error correction data for the first write data WD1.
  • the error correction data generated by the first error correction circuit 340 may be stored in a separate register included in the first non-volatile memory 310, the second non-volatile memory 320, or the controller 330 (not Shown).
  • Standard data can be relatively large in size and requires low reliability.
  • the second non-volatile memory 420 can be adapted to store such data as compared to the first non-volatile memory 410. Therefore, in the case where the first write data WD1 is standard data, the semiconductor memory device 400 can control the controller 430 such that the second error correction circuit 450 generates error correction data of the first write data WD1.
  • the controller 430 can transfer the first write data WD1 to the first nonvolatile memory 410, and can control the first nonvolatile memory 410 such that the first write data WD1 is programmed.
  • the error correction data generated by the second error correction circuit 450 may be stored in a separate register included in the first non-volatile memory 410, the second non-volatile memory 420, or the controller 430 (not Shown). In the case where the error correction data is stored in the first nonvolatile memory 410, the error correction data may be transmitted to the first nonvolatile memory 410 together with the first write data WD1.
  • the buffered data may refer to data that is temporarily programmed in the first non-volatile memory 510 to be written to the second non-volatile memory 520.
  • the use of different error correction circuits to generate error correction data is inefficient. Therefore, in the inventive concept, if the first write data WD1 is buffered data, the semiconductor memory device 500 can be used to be most suitable for the second non-easy when the first write data WD1 is programmed in the first non-volatile memory 510.
  • the second error correction circuit 550 of the loss memory 520 generates error correction data of the first write data WD1.
  • the error correction data generated by the second error correction circuit 550 may be stored in a separate register included in the first non-volatile memory 510, the second non-volatile memory 520, or the controller 530 (not Shown). In the case where the error correction data is stored in the first nonvolatile memory 510, the error correction data may be transmitted to the first nonvolatile memory 510 together with the first write data WD1.
  • FIGS. 6 to 8 are block diagrams schematically showing an ECC method of the semiconductor memory device of Fig. 2.
  • the semiconductor memory devices 600, 700, and 800 illustrated in FIGS. 6 through 8 may be constructed substantially the same as the semiconductor memory device 200 of FIG.
  • first error correction circuits 640, 740, and 840 may be included in first nonvolatile memories 610, 710, and 810, respectively
  • second error correction circuits 650, 750, and 850 may be Included in controllers 630, 730, and 830, respectively.
  • Metadata can have a relatively small size and requires high reliability.
  • the first non-volatile memory 610 can be adapted to store such data as compared to the second non-volatile memory 620. Therefore, in the case where the first write data WD1 is metadata, the semiconductor memory device 600 can transfer the first write data WD1 to the first nonvolatile memory 610, and can control the first nonvolatile memory 610 such that An error correction circuit 640 generates error correction data for the first write data WD1.
  • the error correction data generated by the first error correction circuit 640 may be stored in a separate register included in the first non-volatile memory 610, the second non-volatile memory 620, or the controller 630 ( Not shown).
  • Standard data can be relatively large in size and requires low reliability.
  • the second non-volatile memory 720 can be adapted to store such data as compared to the first non-volatile memory 710. Therefore, in the case where the first write data WD1 is standard data, the semiconductor memory device 700 can control the controller 730 such that the second error correction circuit 750 generates error correction data of the first write data WD1.
  • the controller 730 transmits the first write data WD1 to the first nonvolatile memory 710, and can control the first nonvolatile memory 710 such that the first write data WD1 is programmed.
  • the error correction data generated by the second error correction circuit 750 may be stored in a separate register included in the first non-volatile memory 710, the second non-volatile memory 720, or the controller 730 ( Not shown). In the case where the error correction data is stored in the first nonvolatile memory 710, the error correction data may be transmitted to the first nonvolatile memory 710 together with the first write data WD1.
  • the buffered data may refer to data that is temporarily programmed in the first non-volatile memory 810 to be written to the second non-volatile memory 820.
  • buffering data when the buffered data is programmed in the first nonvolatile memory 810 and the second nonvolatile memory 820, respectively, it is inefficient to use different error correction circuits to generate error correction data. Therefore, in the inventive concept, if the first write data WD1 is buffered data, the semiconductor memory device 800 can be used to be most suitable for the second non-easy when the first write data WD1 is programmed in the first non-volatile memory 810.
  • the second error correction circuit 850 of the loss memory 820 generates error correction data of the first write data WD1.
  • the error correction data generated by the second error correction circuit 850 can be stored in a separate register included in the first non-volatile memory 810, the second non-volatile memory 820, or the controller 830 (not Shown). In the case where the error correction data is stored in the first nonvolatile memory 810, the error correction data may be transmitted to the first nonvolatile memory 810 together with the first write data WD1.
  • FIG. 9 is a block diagram schematically showing the first nonvolatile memory of FIG. 1.
  • the first nonvolatile memory 110 is a resistive random access memory.
  • the resistance random access memory may refer to a random access memory configured to sense a resistance value between both ends of a memory cell to determine a program state of the memory cell.
  • the resistive random access memory may include MRAM, PRAM, ReRAM, and the like.
  • the nonvolatile memory 110 may include a memory cell array 111, a word line decoder 112, a bit line selector 113, a write driver 114, a sense amplifier 115, a data input/output circuit 116, and control logic 117.
  • the memory cell array 111 can be connected to the word line decoder 112 through word lines and can be connected to the bit line selector 113 through bit lines.
  • the memory cell array 111 can include a plurality of memory cells.
  • the memory cells in memory cell array 111 can be resistive memory cells.
  • memory cells arranged in the row direction may be connected to word lines.
  • the memory cells arranged in the column direction may be connected to the bit lines.
  • Each of the memory cell arrays 111 may correspond to a word line WL and a bit line BL.
  • Each memory cell can store one or more bits according to a voltage or current applied to word line WL and bit line BL.
  • the memory cells of memory cell array 111 may be MRAM cells.
  • Word line decoder 112 can be coupled to memory cell array 111 by word lines. Word line decoder 112 can be configured to operate in response to control by control logic 117. The word line decoder 112 can be configured to decode the row address of the address ADDR received from the external device. Word line decoder 112 may select word lines based on the decoded row address.
  • the bit line selector 113 can be coupled to the memory cell array 111 through a bit line and can be coupled to the write driver 114 and the sense amplifier 115.
  • the bit line selector 113 can select a bit line in response to control by the control logic 117.
  • the bit line selector 113 can connect the selected bit line to the write driver 114 during a programming operation.
  • the bit line selector 113 can connect the selected bit line to the sense amplifier 115 during a read operation.
  • the write driver 114 can operate in response to control by the control logic 117.
  • the write driver 114 can be configured to program a memory cell connected to the bit line selected by the bit line selector 113 and the word line selected by the word line decoder 112.
  • the write driver 114 can generate a set current or a reset current to be supplied to the selected bit line based on the data received from the data input/output circuit 116.
  • the sense amplifier 115 can operate in response to control of the control logic 117.
  • the sense amplifier 115 can be configured to read data from a memory cell connected to the bit line selected by the bit line selector 113 and the word line selected by the word line decoder 112.
  • Sense amplifier 115 can read data from the memory cells by sensing the current flowing through the selected bit line or the voltage applied to the selected bit line.
  • the sense amplifier 115 can output the read data to the data input/output circuit 116.
  • Data input/output circuit 116 can operate in response to control of control logic 117.
  • the data input/output circuit 116 can transmit data received from an external device to the sense amplifier 115.
  • the data input/output circuit 116 can output data supplied from the sense amplifier 115 to an external device.
  • Control logic 117 can control the overall operation of non-volatile memory device 110. Control logic 117 can operate in response to command CMD and control signal CTRL received from an external device.
  • FIG. 10 is a view schematically showing a memory unit of the first nonvolatile memory in FIG. 9.
  • the first nonvolatile memory 110 (refer to FIG. 9) is an MRAM.
  • the resistance value of the memory unit 10 of the first nonvolatile memory 110 may vary according to the magnetization direction of the magnetic layer included in the memory unit 10.
  • a memory unit 10 can be referred to as an MRAM unit.
  • the MRAM cell may be a memory cell that stores a magnetic polarization state on a magnetic film, and may perform a write operation by switching a magnetic polarization state according to a magnetic field generated by a bit line current or a word line current.
  • the memory cell 10 may include a switching transistor 14 and a magnetic tunnel junction (MTJ) formed of a pinned magnetic layer 11, a free magnetic layer 12, and a tunnel junction layer 13.
  • MTJ magnetic tunnel junction
  • both ends of the memory cell 10 may be connected to one of the plurality of bit lines (refer to FIG. 9) and the source line SL.
  • One of the plurality of word lines (refer to FIG. 9) may be connected to the switching transistor 14 of the memory cell 10, and the memory cell 10 may or may not be selected.
  • the thickness of the pinned magnetic layer 11 may be greater than the thickness of the free magnetic layer 12.
  • a relatively strong magnetic field is applied, the magnetic polarization state of the pinned magnetic layer 11 can be changed.
  • a relatively weak magnetic field is applied, the magnetic polarization state of the free magnetic layer 12 can also be changed.
  • the tunnel junction layer 13 may be placed between the pinned magnetic layer 11 and the free magnetic layer 12.
  • the pinned magnetic layer 11 and the free magnetic layer 12 may have a material such as NiFeCo or CoFe.
  • the tunnel junction layer 13 may have a material such as MgO or AlO3.
  • the switching transistor 14 can be turned on or off by the voltage of the word line WLn.
  • the memory cell 10 can be selected or not selected by turning the switching transistor 14 on or off during a programming operation. For example, when the switching transistor 14 is turned on, a programming current can flow into the memory cell 10.
  • the magnetization direction of the memory cell 10 may vary depending on the direction and level of the programming current (or programming voltage) applied to the bit line BLn.
  • the memory cell 10 having the pinned magnetic layer 11, the tunnel junction layer 13, and the free magnetic layer 12 which are sequentially stacked may have different resistance values depending on the magnetization directions of the pinned magnetic layer 11 and the free magnetic layer 12. For example, if the magnetization directions of the pinned magnetic layer 11 and the free magnetic layer 12 are identical to each other (or in a parallel state), the memory cell 10 may have a relatively low resistance value. On the other hand, if the magnetization directions of the pinned magnetic layer 11 and the free magnetic layer 12 are opposite to each other (in an anti-parallel state), the memory cell 10 may have a relatively high resistance value.
  • the first nonvolatile memory 110 (refer to FIG. 9) can determine the programming state of the memory cell 10 by changing the characteristics of the memory cell 10 according to the magnetization direction of the memory cell 10.
  • FIG. 11 is a block diagram schematically showing the second nonvolatile memory of FIG. 1.
  • the second nonvolatile memory 120 is a NAND flash memory.
  • the second nonvolatile memory 120 may include a memory cell array 121, an address decoder 122, a read/write circuit 123, a data input/output circuit 124, and control logic 125.
  • the memory cell array 121 can be connected to the address decoder 122 through a word line WL and to the read/write circuit 123 through a bit line BL.
  • the memory cell array 121 can include a plurality of memory cells.
  • the memory cells arranged in the row direction may be connected to the word lines, and the memory cells arranged in the column direction may be connected to the bit lines.
  • memory cells arranged in the column direction may form a plurality of cell groups (eg, strings). Multiple cell groups can be connected to the bit lines, respectively.
  • each memory unit may store one or more bits of data.
  • Address decoder 122 may be coupled to memory cell array 121 by word line WL. Address decoder 122 may operate in response to control of control logic 125. The address decoder 122 can receive the address ADDR from an external device.
  • the address decoder 122 can decode the row address of the input address ADDR and can select the word line WL using the decoded row address.
  • the address decoder 122 may decode the column address of the input address ADDR to transfer the decoded column address to the read/write circuit 123.
  • address decoder 122 may include elements such as a row decoder, a column decoder, an address buffer, and the like.
  • the read/write circuit 123 can be connected to the memory cell array 121 through a bit line BL.
  • the read/write circuit 123 can be connected to the data input/output circuit 124 through the data line DL.
  • the read/write circuit 123 can operate in response to control of the control logic 125.
  • the read/write circuit 123 can select the bit line BL in response to the decoded column address DCA from the address decoder 122.
  • the read/write circuit 123 may receive data from the data input/output circuit 124 and then write the data in the memory cell array 121.
  • the read/write circuit 123 can read data from the memory cell array 121 and then output the data to the data input/output circuit 124.
  • the read/write circuit 123 may include constituent elements such as a page buffer (or page register), a column selection circuit, a data buffer, and the like. In another example embodiment, the read/write circuit 123 may include constituent elements such as a sense amplifier, a write driver, a column selection circuit, a data buffer, and the like.
  • the data input/output circuit 124 can be connected to the read/write circuit 123 through the data line DL. Data input/output circuitry 124 can operate in response to control of control logic 125. The data input/output circuit 124 can be configured to exchange data with an external device. The data input/output circuit 124 may be configured to transmit data supplied from an external device to the read/write circuit 123 through the data line DL. The data input/output circuit 124 may be configured to output data transmitted from the read/write circuit 123 to the external device through the data line DL. In an example embodiment, the data input/output circuit 124 may include constituent elements such as a data buffer.
  • Control logic 125 can be coupled to address decoder 122, read/write circuit 123, and data input/output circuit 124. Control logic 125 can be configured to control the overall operation of second non-volatile memory device 120. Control logic 125 may operate in response to control signal CTRL provided from an external device.
  • FIG. 12 is a flowchart schematically illustrating an ECC method of a semiconductor memory device, according to an embodiment of the inventive concepts.
  • an ECC method of a semiconductor memory device according to an embodiment of the inventive concepts may include operations S110 to S130.
  • the semiconductor memory device may have the same structure as that of one of the semiconductor memory devices 100, 200, 300, 400, 500, 600, 700, and 800.
  • the semiconductor memory device may determine an attribute of the write data in operation S110.
  • the write data may have attributes of metadata, standard data, or buffered data.
  • the semiconductor memory device may generate error correction data of the write data using one of the first error correction circuit and the second error correction circuit according to the attribute of the write data.
  • the semiconductor memory device can determine the method for generating the error correction data in consideration of the type of the nonvolatile memory in which the write data is to be stored.
  • the detailed structure of the first error correction circuit and the second error correction circuit of the semiconductor memory device and the error correction data generating method can be substantially the same as those described with reference to FIGS. 1 to 8.
  • the semiconductor memory device can store error correction data in operation S130.
  • the error correction data may be stored in one of the non-volatile memories included in the semiconductor memory device or stored in the controller to control the non-volatile memory.
  • the stored error correction data can be used to verify the integrity of the write data.
  • FIG. 13 is a flowchart schematically illustrating an ECC method of a semiconductor memory device, according to another embodiment of the inventive concepts.
  • an ECC method of a semiconductor memory device may include operations S210 to S290.
  • the semiconductor memory device may have the same structure as that of one of the semiconductor memory devices 100, 200, 300, 400, 500, 600, 700, and 800.
  • the semiconductor memory device may include at least two different types of nonvolatile memories (eg, first nonvolatile memory NVM1 and second nonvolatile memory NVM2) and control first nonvolatile memory NVM1 and second Controller for non-volatile memory NVM2.
  • the first nonvolatile memory NVM1 may be configured to be substantially the same as one of the first nonvolatile memories 110, 210, 310, 410, 510, 610, 710, and 810 described with reference to FIGS. 1 through 8.
  • the second nonvolatile memory NVM2 may be configured to be substantially the same as one of the second nonvolatile memories 120, 220, 320, 420, 520, 620, 720, and 820 described with reference to FIGS. 1 through 8.
  • the controller can be configured to be substantially identical to one of the controllers 130, 230, 330, 430, 530, 630, 730, and 830 described with reference to FIGS. 1 through 8.
  • error correction data of the write data WD can be generated using different error correction circuits in accordance with the attributes of the write data WD and the type of memory in which the write data WD is programmed.
  • the description and effect of selecting the error correction circuit in accordance with the attribute of the write data WD and the type of memory in which the write data WD is programmed may be substantially the same as the description and effects described with reference to FIGS. 1 through 8.
  • the semiconductor memory device may input the write data WD to the controller 130 in operation S210.
  • the semiconductor memory device may determine whether the write data WD is programmed in any of the first nonvolatile memory NVM1 and the second nonvolatile memory NVM2. As described above, the first non-volatile memory NVM1 and the second non-volatile memory NVM2 may have different types, minimum programming units, and programming speeds. If it is determined that the first nonvolatile memory NVM1 is the memory in which the write data WD is programmed, the method may proceed to operation S230. If it is determined that the first nonvolatile memory NVM1 is not the memory in which the write data WD is programmed, the method may proceed to operation S280.
  • the semiconductor memory device may determine whether the write data WD is an attribute having metadata or an attribute having standard data. If it is determined that the write data WD has an attribute of the metadata, the method may proceed to operation S260. If it is determined that the write data WD does not have the attribute of the metadata, the method may proceed to operation S240.
  • the semiconductor memory device can generate the error correction data of the write data WD using the second error correction circuit ECC2.
  • the second error correction circuit ECC2 may be an error correction circuit designed to be suitable for the second nonvolatile memory NVM2.
  • the detailed description of the second error correction circuit ECC2 and the relationship with the second nonvolatile memory NVM2 may be substantially the same as the detailed description and relationship described with reference to FIGS. 1 through 8.
  • the semiconductor memory device can program the write data WD in the first nonvolatile memory NVM1 in operation S250.
  • the semiconductor memory device may store the generated error correction data in the first nonvolatile memory NVM1, the second nonvolatile memory NVM2, while programming the write data WD or before and after programming the write data WD. Or in the controller 130.
  • the method may proceed to operation S260.
  • the semiconductor memory device can generate error correction data of the write data WD using the first error correction circuit ECC1.
  • the first error correction circuit ECC1 may be an error correction circuit designed to be suitable for the first nonvolatile memory NVM1.
  • the detailed description of the first error correction circuit ECC1 and the relationship with the first nonvolatile memory NVM1 may be substantially the same as the detailed description and relationship described with reference to FIGS. 1 through 8.
  • the semiconductor memory device can program the write data WD in the first nonvolatile memory NVM1 in operation S270.
  • the semiconductor memory device may store the generated error correction data in the first nonvolatile memory NVM1, the second nonvolatile memory NVM2, while programming the write data WD or before and after programming the write data WD. Or in the controller 130.
  • the method may proceed Go to operation S280.
  • the semiconductor memory device can generate the write data WD using the second error correction circuit ECC2 suitable for the second nonvolatile memory NVM2. Error correction data.
  • the semiconductor memory device can program the write data WD in the second nonvolatile memory NVM2 in operation S290.
  • the semiconductor memory device may store the generated error correction data in the first nonvolatile memory NVM1, the second nonvolatile memory NVM2, or after programming the write data WD or before and after programming the write data WD. In the controller 130.

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Abstract

提供了一种半导体存储器装置及其ECC方法，所述半导体存储器装置包括：第一非易失性存储器；第二非易失性存储器，具有与第一非易失性存储器的类型不同的类型；控制器；第一纠错电路，被构造成纠正在第一非易失性存储器进行编程的第一写数据的错误；和第二纠错电路，包括在控制器中并被构造成基于与第一纠错电路的纠错算法不同的纠错算法纠正第一写数据的错误或在第二非易失性存储器进行编程的第二写数据的错误。根据第一写数据的属性使用第一纠错电路和第二纠错电路中的一个产生用于纠正第一写数据的错误的纠错数据。

Description

半导体存储器装置及其ECC方法 技术领域
这里描述的本发明构思涉及一种包括不同类型的非易失性存储器的半导体存储器装置 。
背景技术
半导体存储器装置可为易失性或非易失性。易失性存储器装置可具有快速的读写速度，而存储在易失性存储器装置中的内容会在断电时丢失。另一方面，非易失性存储器装置即使在断电时也可以保留存储在其中的内容。因此，非易失性存储器装置可被用于存储无论是否供电都必须保存的内容。
闪速存储器装置作为高集成度且大容量的非易失性半导体存储器装置可用在手持电子装置中。另外，磁随机存取存储器（在下文中，称作MRAM）可使用磁元件作为随机存取、高集成度和大容量的非易失性元件。MRAM的优势可在于快速的响应速度和高集成度。
近年来，可能已经提出了集成地使用不同类型的非易失性存储器（例如，NAND闪速存储器、MRAM等）的半导体存储器装置，以提高非易失性半导体存储器装置的性能。然而，由于不同类型的非易失性存储器具有不同的数据存储方式和管理方法，所以对有效控制不同类型的非易失性存储器的技术的要求会提高。
 技术解决方案
本发明构思的实施例的一方面提供了一种半导体存储器装置，所述半导体存储器装置包括：第一非易失性存储器；第二非易失性存储器，具有与第一非易失性存储器的类型不同的类型；控制器，被构造成控制第一非易失性存储器和第二非易失性存储器；第一纠错电路，被构造成纠正在第一非易失性存储器进行编程的第一写数据的错误；和第二纠错电路，包括在控制器中并被构造成基于与第一纠错电路的纠错算法不同的纠错算法纠正第一写数据的错误或在第二非易失性存储器进行编程的第二写数据的错误，其中，根据第一写数据的属性使用第一纠错电路和第二纠错电路中的一个产生用于纠正第一写数据的错误的纠错数据。
在示例实施例中，如果第一写数据具有元数据的属性，则使用第一纠错电路产生纠错数据。
在示例实施例中，如果第一写数据具有标准数据的属性，则使用第二纠错电路产生纠错数据。
在示例实施例中，如果第一写数据具有缓冲数据的属性，则使用第二纠错电路产生纠错数据，缓冲数据是在第一非易失性存储器被临时编程以将缓冲数据写入到第二非易失性存储器的数据。
在示例实施例中，第一纠错电路被包括在第一非易失性存储器中。
在示例实施例中，第一纠错电路被包括在控制器中。
在示例实施例中，第一非易失性存储器的编程速度比第二非易失性存储器的编程速度快。
在示例实施例中，第一非易失性存储器是读取存储器单元两端之间的电阻值以判断存储在所述存储器单元的数据的电阻存储器。
在示例实施例中，第一非易失性存储器是磁随机存取存储器。
在示例实施例中，第二非易失性存储器是NAND闪速存储器。
在示例实施例中，第一纠错电路根据使用汉明码的纠错算法产生纠错数据。
在示例实施例中，第二纠错电路根据使用BCH码或LDPC码的纠错算法产生纠错数据。
本发明构思的实施例的另一方面提供了一种半导体存储器装置的ECC方法，所述半导体存储器装置包括：第一非易失性存储器；第二非易失性存储器，具有与第一非易失性存储器的类型不同的类型；和控制器，控制第一非易失性存储器和第二非易失性存储器。所述ECC方法包括：确定在第一非易失性存储器进行编程的写数据的属性；根据写数据的属性和第一非易失性存储器的类型，使用第一非易失性存储器和第二非易失性存储器中的一个产生用于纠正写数据的错误的纠错数据；和存储纠错数据，其中，第一纠错电路和第二纠错电路根据不同的纠错算法产生纠错数据。
在示例实施例中，半导体存储器装置控制控制器使得使用第二纠错电路产生在第二非易失性存储器进行编程的写数据的纠错数据。
在示例实施例中，半导体存储器装置在第一非易失性存储器、第二非易失性存储器或控制器存储纠错数据。
 有益效果
根据本发明构思的实施例，一种包括不同类型的非易失性存储器的半导体存储器装置可被构造为选择性地使用多个纠错电路中的一部分来纠正写数据的错误，其中，所述多个纠错电路根据写数据的属性以及写数据被编程所在的非易失性存储器的类型，应用不同的纠错算法。因此，可通过使用最适合于写数据的属性以及非易失性存储器的类型的纠错算法来纠正数据，以有效地执行纠错。
附图说明
通过参照附图进行的详细描述，以上和其它目标和特征将变得清楚，其中，在不同的附图中，相同的标号表示相同的部件，除非另外具体说明，在附图中：
图1是示意性示出根据本发明构思的实施例的半导体存储器装置的方框图；
图2是示意性示出根据本发明构思的另一实施例的半导体存储器装置的方框图；
图3至图5是示意性示出图1中的半导体存储器装置的ECC方法的方框图；
图6至图8是示意性示出图2中的半导体存储器装置的ECC方法的方框图；
图9是示意性示出图1中的第一非易失性存储器的方框图；
图10是示意性示出图9中的第一非易失性存储器的存储器单元的示图，在图10中，假设第一非易失性存储器110（参照图9）是MRAM；
图11是示意性示出图1中的第二非易失性存储器的方框图；
图12是示意性示出根据本发明构思的实施例的半导体存储器装置的ECC方法的流程图；
图13是示意性示出根据本发明构思的另一实施例的半导体存储器装置的ECC方法的流程图。
本发明的实施方式
将参照附图详细描述实施例。然而，本发明构思可以以各种不同的形式实施，不应该被解释为仅限于示出的实施例。相反，提供这些实施例作为示例是为了使本公开将为彻底的和完整的，并将把本发明构思的构思充分地传达给本领域技术人员。因此，关于本发明构思的实施例中的一些实施例，不再描述公知的处理、元件和技术。除非另外指出，否则在所有附图和书面描述中，相同的标号表示相同的元件，因此不再进行重复的描述。在附图中，为了清晰起见，可能会夸大层和区域的尺寸和相对尺寸。
将理解的是，尽管在这里可使用术语“第一”、“第二”、“第三”等来描述不同的元件、组件、区域、层和/或部分，但是这些元件、组件、区域、层和/或部分并不受这些术语的限制。这些术语仅是用来将一个元件、组件、区域、层或部分与另一个区域、层或部分区分开来。因此，在不脱离本发明构思的教导的情况下，下面讨论的第一元件、组件、区域、层或部分可被命名为第二元件、组件、区域、层或部分。
在这里可使用空间相对术语，如“在…下方”、“在…下面”、“下面的”、“在…之下”、“在…上方”、“上面的”等，用来轻松地描述如图中所示的一个元件或特征与其它元件或特征的关系。应该理解的是，空间相对术语意在包含除了在附图中描述的方位之外的装置在使用或操作中的不同方位。例如，如果在附图中装置被翻转，则描述为在其它元件或特征“下面”或“下方”或“之下”的元件随后将被定位为在其它元件或特征“上方”。因此，示例性术语“在…下面”和“在…之下”可包括“在…上方”和“在…下方”两种方位。所述装置可被另外定位（旋转90度或者在其它方位），相应地解释这里使用的空间相对描述符。另外，还将理解的是，当层被称作在两层“之间”时，它可以是所述两层之间的唯一层，或者也可以存在一个或多个中间层。
这里使用的术语仅出于描述具体实施例的目的，而不意图限制本发明构思。如这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式。还将理解的是，当在本说明书中使用术语“包含”和/或“包括”时，说明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或其组合。如这里所使用的，术语“和/或”包括一个或多个相关所列的项目的任意组合和所有组合。另外，术语“示例性”意图指的是示例或举例说明。
将理解的是，当元件或层被称作在另一元件或层“上”、“连接到”、“结合到”或“相邻于”另一元件或层时，该元件可直接位于所述另一元件或层上，直接连接到、直接结合到或直接相邻于所述另一元件或层，或者可存在中间元件或中间层。相反，当元件被称作“直接位于”另一元件或层“上”，“直接连接到”、“直接结合到”或“直接相邻于”另一元件或层时，不存在中间元件或中间层。
除非另有定义，否则这里使用的所有术语（包括技术术语和科技术语）具有与本发明构思所属领域的普通技术人员所通常理解的意思相同的意思。将进一步理解，除非这里明确定义，否则术语例如在通用的字典中定义的术语应该被解释为具有与相关领域的上下文中它们的意思相同的意思，而不是理想地或者过于正式地解释它们的意思。
图1是示意性示出根据本发明构思的实施例的半导体存储器装置的方框图。参照图1，半导体存储器装置100可包括第一非易失性存储器110、第二非易失性存储器120、控制器130、第一纠错电路140和第二纠错电路150。在图1中，示出了半导体存储器装置100包括两个不同类型的非易失性存储器110和120的示例。半导体存储器装置100还可以包括与第一非易失性存储器110或第二非易失性存储器120类型相同或类型不同的非易失性存储器（未示出）。
在示例实施例中，第一非易失性存储器110可包括第一纠错电路140，控制器130可包括第二纠错电路150。
第一非易失性存储器110可根据控制器130的控制接收并存储第一写数据WD1。第一非易失性存储器110可使用第一纠错电路140产生用于纠正第一写数据WD1的错误的纠错数据。这里，纠错数据可指的是ECC数据。第一非易失性存储器110可为特定类型的非易失性存储器。例如，第一非易失性存储器110可为MRAM。
第二非易失性存储器120的类型可与第一非易失性存储器110的类型不同。例如，在第一非易失性存储器110为MRAM的情形下，第二非易失性存储器120可为NAND闪速存储器。第二非易失性存储器120可根据控制器130的控制接收并存储第二写数据WD2。可通过第二纠错电路150产生用于纠正第二写数据WD2的错误的纠错数据。
控制器130可控制第一非易失性存储器110和第二非易失性存储器120的程序操作。控制器130可包括第二纠错电路150，并可使用第二纠错电路150产生用于纠正第一写数据WD1或第二写数据WD2的错误的纠错数据。
第一纠错电路140可为纠正第一写数据WD1的错误的纠错电路。第一纠错电路140可根据预定的纠错算法产生第一写数据WD1的纠错数据。在示例实施例中，第一纠错电路140的纠错算法可为适合于处理具有小尺寸并要求高可靠性的数据的算法。例如，第一纠错电路140可使用采用汉明码的纠错算法来产生第一写数据WD1的纠错数据。
第二纠错电路150可被用于纠正第二写数据WD2的错误。例如，半导体存储器装置100可使用第二纠错电路150产生第二写数据WD2的纠错数据。
基于第一写数据WD1的属性，第二纠错电路150可被选择性地用于纠正第一写数据WD1的错误。这里，第一写数据WD1可具有元数据、标准数据或缓冲数据的属性。
第二纠错电路150可根据与第一纠错电路140的纠错算法不同的纠错算法，产生第一写数据WD1或第二写数据WD2的纠错数据。在示例实施例中，第二纠错电路150的纠错算法可为适合于处理具有大尺寸且要求低可靠性的数据的算法。例如，在第二非易失性存储器120为NAND闪速存储器的情况下，第二纠错电路150可使用采用BCH（Bose–Chaudhuri-Hocquenghem）码或LDPC（低密度奇偶检验）码的纠错算法，产生第一写数据WD1或第二写数据WD2的纠错数据。
第一写数据WD1可在第一非易失性存储器110被编程，第二写数据WD2可在第二非易失性存储器120被编程。第一非易失性存储器110的最小编程单元可小于第二非易失性存储器120的最小编程单元，并且第一非易失性存储器110的可靠性可低于第二非易失性存储器120的可靠性。在示例实施例中，第一非易失性存储器110可为电阻随机存取存储器。电阻随机存取存储器可为MRAM、PRAM或RRAM。另一方面，第二非易失性存储器120可为NAND闪速存储器。
半导体存储器装置100可根据第一写数据WD1的属性来选择性地使用第一纠错电路140和第二纠错电路150中的一个。例如，如果第一写数据WD1是具有小尺寸且要求高可靠性的元数据，则半导体存储器装置100可使用最合适于第一非易失性存储器110的第一纠错电路140来产生第一写数据WD1的纠错数据。另一方面，如果第一写数据WD1是具有大尺寸且要求低可靠性的标准数据，则半导体存储器装置100可使用最合适纠正大量数据的错误的第二纠错电路150来产生第一写数据WD1的纠错数据。
半导体存储器装置100可使用第二纠错电路150来产生第二写数据WD2的纠错数据。由于第二写数据WD2在最小编程单元相对小且具有低可靠性的第二纠错电路150被编程，所以可使用最合适处理大量数据的第二纠错电路150来产生第二写数据WD2的纠错数据。
根据本发明构思的实施例，包括不同类型的非易失性存储器的半导体存储器装置可被构造成选择性地使用多个纠错电路中的一部分来纠正写数据的错误，其中，所述多个纠错电路根据写数据的属性和写数据被编程的非易失性存储器的类型应用了不同的纠错算法。因此，可通过使用最适用于写数据的属性和非易失性存储器的类型的纠错算法来纠正错误，以有效地执行纠错。
图2是示意性示出根据本发明构思的另一实施例的半导体存储器装置的方框图。参照图2，半导体存储器装置200可包括第一非易失性存储器210、第二非易失性存储器220、控制器230、第一纠错电路240和第二纠错电路250。
在图2中，示出了半导体存储器装置200包括两个不同类型的非易失性存储器210和220的示例。然而，本发明构思不限于此。半导体存储器装置200还可包括类型与第一非易失性存储器210或第二非易失性存储器220的类型相同或不同的非易失性存储器（未示出）。
在示例实施例中，控制器230可包括第一纠错电路240和第二纠错电路250两者。
第一非易失性存储器 210 可根据控制器 230 的控制接收并存储第一写数据 WD1 。第一非易失性存储器 210 可为特定类型的非易失性存储器。例如，第一非易失性存储器 210 可为 MRAM 。
可通过包括在控制器 230 中的第一纠错电路 240 产生用于纠正第一写数据 WD1 的错误的纠错数据。产生的纠错数据可存储在包括在第一非易失性存储器 210 、第二非易失性存储器 220 或控制器 230 中的单独的寄存器（未示出）中。这里，纠错数据可指 ECC 数据。
第二非易失性存储器 220 的类型可与第一非易失性存储器 210 的类型不同。例如，在第一非易失性存储器 210 为 MRAM 的情况下，第二非易失性存储器 220 可为 NAND 闪速存储器。第二非易失性存储器 220 可根据控制器 230 的控制接收并存储第二写数据 WD2 。可通过第二纠错电路 250 产生用于纠正第二写数据 WD2 的错误的纠错数据。可通过第二纠错电路 250 产生用于纠正第二写数据 WD2 的错误的纠错数据，并且产生的纠错数据可存储在包括在第一非易失性存储器 210 、第二非易失性存储器 220 或控制器 230 中的单独寄存器（未示出）中。
控制器 230 可控制第一非易失性存储器 210 和第二非易失性存储器 220 的程序操作。控制器 230 可包括第一纠错电路 240 和第二纠错电路 250 两者，并可使用第一纠错电路 240 或第二纠错电路 250 来产生用于纠正第一写数据 WD1 或第二写数据 WD2 的错误的纠错数据。
第一纠错电路 240 可为纠正第一写数据 WD1 的错误的纠错电路。第一纠错电路 240 可根据预定纠错算法产生第一写数据 WD1 的纠错数据。在示例实施例中，第一纠错电路 240 的纠错算法可为适合于处理具有小尺寸且要求高可靠性的数据的算法。例如，第一纠错电路 240 可使用采用汉明码的纠错算法来产生第一写数据 WD1 的纠错数据。
第二纠错电路 250 可被用于纠正第二写数据 WD2 的错误。例如，半导体存储器装置 200 可使用第二纠错电路 250 来产生第二写数据 WD2 的纠错数据。
基于第一写数据 WD1 的属性，第二纠错电路 250 可被选择性地用于纠正第一写数据 WD1 的错误。这里，第一写数据 WD1 可具有元数据、标准数据或缓冲数据的属性。
第二纠错电路250可根据与第一纠错电路240的纠错算法不同的纠错算法，产生第一写数据WD1或第二写数据WD2的纠错数据。在示例实施例中，第二纠错电路250的纠错算法可为适合于处理具有大尺寸且要求低可靠性的数据的算法。例如，在第二非易失性存储器220是NAND闪速存储器的情况下，第二纠错电路250可使用采用BCH（Bose–Chaudhuri-Hocquenghem）码或LDPC（低密度奇偶检验）码的纠错算法，来产生第一写数据WD1或第二写数据WD2的纠错数据。
第一写数据WD1可在第一非易失性存储器210被编程，第二写数据WD2可在第二非易失性存储器220被编程。第一非易失性存储器210的最小编程单元可小于第二非易失性存储器220的最小编程单元，并且第一非易失性存储器210的可靠性可低于第二非易失性存储器220的可靠性。在示例实施例中，第一非易失性存储器210可为电阻随机存取存储器。电阻随机存取存储器可为MRAM、PRAM或RRAM。另一方面，第二非易失性存储器220可为NAND闪速存储器。
半导体存储器装置200可根据第一写数据WD1的属性来选择性地使用第一纠错电路240和第二纠错电路250中的一个。例如，如果第一写数据WD1是具有小尺寸且要求高可靠性的元数据，则半导体存储器装置200可使用最适合于第一非易失性存储器210的第一纠错电路240，产生第一写数据WD1的纠错数据。另一方面，如果第一写数据WD1是具有大尺寸且要求低可靠性的标准数据，则半导体存储器装置200可使用最适合于纠正大量数据的错误的第二纠错电路250，产生第一写数据WD1的纠错数据。
半导体存储器装置200可使用第二纠错电路250来产生第二写数据WD2的纠错数据。由于第二写数据WD2在最小编程单元相对小且具有最低可靠性的第二非易失性存储器220被编程，所以可使用最合适于处理大量数据的第二纠错电路250，产生第二写数据WD2的纠错数据。
根据本发明构思的实施例，包括不同类型的非易失性存储器的半导体存储器装置可被构造为选择性地使用多个纠错电路中的一部分来纠正写数据的错误，其中，所述多个纠错电路根据写数据的类型和写数据被编程所在的非易失性存储器的类型而应用了不同的纠错算法。因此，可通过使用最适合于写数据的属性和非易失性存储器的类型的纠错算法来纠正错误，以有效地执行纠错。
图3至图5是示意性地示出了图1中的半导体存储器装置的ECC方法的方框图。图3至图5中示出的半导体存储器装置300、400和500可被构造成基本与图1中的半导体存储器装置100相同。例如，参照图3至图5，第一纠错电路340、440和540可被分别包括在第一非易失性存储器310、410和510中，第二纠错电路350、450和550可被分别包括在控制器330、430和530中。
将参照图3描述当第一写数据WD1具有元数据的属性时半导体存储器装置300的ECC方法。
元数据可具有相对小的尺寸并要求高可靠性。与第二非易失性存储器320相比，第一非易失性存储器310可适合存储这种数据。因此，在第一写数据WD1是元数据的情况下，半导体存储器装置300可将第一写数据WD1传输到第一非易失性存储器310，并可控制第一非易失性存储器310使得第一纠错电路340产生第一写数据WD1的纠错数据。
在示例实施例中，第一纠错电路340产生的纠错数据可存储在包括在第一非易失性存储器310、第二非易失性存储器320或控制器330中的单独的寄存器（未示出）中。
将参照图4描述当第一写数据WD1具有标准数据的属性时半导体存储器装置400的ECC方法。
标准数据可具有相对大的尺寸并要求低可靠性。与第一非易失性存储器410相比，第二非易失性存储器420可适合于存储这种数据。因此，在第一写数据WD1是标准数据的情况下，半导体存储器装置400可控制控制器430使得第二纠错电路450产生第一写数据WD1的纠错数据。控制器430可将第一写数据WD1传输到第一非易失性存储器410，并可控制第一非易失性存储器410使得第一写数据WD1被编程。
在示例实施例中，第二纠错电路450产生的纠错数据可存储在包括在第一非易失性存储器410、第二非易失性存储器420或控制器430中的单独的寄存器（未示出）中。在纠错数据存储在第一非易失性存储器410中的情况下，纠错数据可与第一写数据WD1一起被发送到第一非易失性存储器410。
将参照图5描述当第一写数据WD1具有缓冲数据的属性时的半导体存储器装置500的ECC方法。
缓冲数据可指的是在第一非易失性存储器510被临时编程以写入第二非易失性存储器520的数据。在缓冲数据的情况下，当缓冲数据分别在第一非易失性存储器510和第二非易失性存储器520被编程时，使用不同的纠错电路来产生纠错数据的效率低。因此，在本发明构思中，如果第一写数据WD1是缓冲数据，则半导体存储器装置500可使用当第一写数据WD1在第一非易失性存储器510被编程时最适合于第二非易失性存储器520的第二纠错电路550，来产生第一写数据WD1的纠错数据。
在示例实施例中，第二纠错电路550产生的纠错数据可存储在包括在第一非易失性存储器510、第二非易失性存储器520或控制器530中的单独的寄存器（未示出）中。在纠错数据存储在第一非易失性存储器510中的情况下，该纠错数据可与第一写数据WD1一起被发送到第一非易失性存储器510。
图6至图8是示意性示出图2中的半导体存储器装置的ECC方法的方框图。图6至图8中示出的半导体存储器装置600、700和800可被构造成与图2中的半导体存储器装置200基本相同。例如，参照图6至图8，第一纠错电路640、740和840可被分别包括在第一非易失性存储器610、710和810中，第二纠错电路650、750和850可被分别包括在控制器630、730和830中。
将参照图6描述当第一写数据WD1具有元数据的属性时半导体存储器装置600的ECC方法。
元数据可具有相对小的尺寸并要求高可靠性。与第二非易失性存储器620相比，第一非易失性存储器610可适合于存储这样的数据。因此，在第一写数据WD1是元数据的情况下，半导体存储器装置600可将第一写数据WD1传输到第一非易失性存储器610，并可控制第一非易失性存储器610使得第一纠错电路640产生第一写数据WD1的纠错数据。
在示例实施例中，第一纠错电路640产生的纠错数据可被存储在包括在第一非易失性存储器610、第二非易失性存储器620或控制器630中的单独的寄存器（未示出）中。
将参照图7描述当第一写数据WD1具有标准数据的属性时半导体存储器装置700的ECC方法。
标准数据可具有相对大的尺寸并要求低可靠性。与第一非易失性存储器710相比，第二非易失性存储器720可适合存储这种数据。因此，在第一写数据WD1是标准数据的情况下，半导体存储器装置700可控制控制器730使得第二纠错电路750产生第一写数据WD1的纠错数据。控制器730将第一写数据WD1传输到第一非易失性存储器710，并可控制第一非易失性存储器710使得第一写数据WD1被编程。
在示例实施例中，第二纠错电路750产生的纠错数据可被存储在包括在第一非易失性存储器710、第二非易失性存储器720或控制器730中的单独的寄存器（未示出）中。在纠错数据存储在第一非易失性存储器710中的情况下，纠错数据可与第一写数据WD1一起被发送到第一非易失性存储器710。
将参照图8描述当第一写数据WD1具有缓冲数据的属性时半导体存储器装置800的ECC方法。
缓冲数据可指的是在第一非易失性存储器810被临时编程以写入第二非易失性存储器820的数据。在缓冲数据的情况下，当缓冲数据分别在第一非易失性存储器810和第二非易失性存储器820被编程时，使用不同的纠错电路来产生纠错数据的效率低。因此，在本发明构思中，如果第一写数据WD1是缓冲数据，则半导体存储器装置800可使用当第一写数据WD1在第一非易失性存储器810被编程时最适合于第二非易失性存储器820的第二纠错电路850，来产生第一写数据WD1的纠错数据。
在示例实施例中，第二纠错电路850产生的纠错数据可存储在包括在第一非易失性存储器810、第二非易失性存储器820或控制器830中的单独的寄存器（未示出）中。在纠错数据存储在第一非易失性存储器810中的情况下，该纠错数据可与第一写数据WD1一起被发送到第一非易失性存储器810。
图9是示意性示出图1中的第一非易失性存储器的方框图。在图9中，假设第一非易失性存储器110是电阻随机存取存储器。这里，电阻随机存取存储器可指的是被构造成感测存储器单元的两端之间的电阻值以判断存储单元的编程状态的随机存取存储器。电阻随机存取存储器可包括MRAM、PRAM、ReRAM等。
参照图9，非易失性存储器110可包括存储器单元阵列111、字线解码器112、位线选择器113、写驱动器114、感测放大器115、数据输入/输出电路116和控制逻辑117。
存储器单元阵列111可通过字线与字线解码器112相连接，并可通过位线与位线选择器113相连接。存储器单元阵列111可包括多个存储器单元。存储器单元阵列111中的存储器单元可为电阻存储器单元。在示例实施例中，布置在行方向上的存储器单元可与字线连接。布置在列方向上的存储器单元可与位线连接。存储器单元阵列111中的每个存储器单元可对应于字线WL和位线BL。每个存储器单元可根据施加到字线WL和位线BL的电压或电流存储一个或多个比特。
在示例实施例中，存储器单元阵列111的存储器单元可为MRAM单元。
字线解码器112可通过字线与存储器单元阵列111相连接。字线解码器112可被构造成响应于控制逻辑117的控制进行操作。字线解码器112可被构造成对从外部装置接收的地址ADDR的行地址进行解码。字线解码器112可根据解码的行地址选择字线。
位线选择器113可通过位线与存储器单元阵列111相连接，并可与写驱动器114和感测放大器115相连接。位线选择器113可响应于控制逻辑117的控制来选择位线。在编程操作时，位线选择器113可将选择的位线与写驱动器114相连接。在读操作时，位线选择器113可将选择的位线与感测放大器115相连接。
写驱动器114可响应于控制逻辑117的控制进行操作。写驱动器114可被构造成对与位线选择器113选择的位线和字线解码器112选择的字线相连接的存储器单元进行编程。写驱动器114可基于从数据输入/输出电路116接收的数据，产生将被提供到选择的位线的设置电流或重置电流。
感测放大器115可响应于控制逻辑117的控制进行操作。感测放大器115可被构造成从与位线选择器113选择的位线和字线解码器112选择的字线相连接的存储器单元读取数据。感测放大器115可通过感测流过选择的位线的电流或施加到选择的位线的电压，从存储器单元读取数据。感测放大器115可将读取的数据输出到数据输入/输出电路116。
数据输入/输出电路116可响应于控制逻辑117的控制进行操作。数据输入/输出电路116可将从外部装置接收的数据传输到感测放大器115。数据输入/输出电路116可将从感测放大器115提供的数据输出到外部装置。
控制逻辑117可控制非易失性存储器装置110的全部操作。控制逻辑117可响应于从外部装置接收的命令CMD和控制信号CTRL进行操作。
图10是示意性示出图9中的第一非易失性存储器的存储器单元的视图。在图10中，假设第一非易失性存储器110（参照图9）是MRAM。
第一非易失性存储器110的存储器单元10的电阻值可根据包括在存储器单元10中的磁层的磁化方向而改变。这种存储器单元10可被称作MRAM单元。MRAM单元可为在磁性薄膜上存储磁偏振状态的存储器单元，并可通过根据位线电流或字线电流产生的磁场切换磁偏振状态来执行写操作。
参照图10，存储器单元10可包括开关晶体管14和磁隧道结（MTJ），磁隧道结（MTJ）由钉扎磁性层11、自由磁性层12和隧道结层13形成。这里，存储器单元10的两端可与多条位线（参照图9）中的一条BLn和源极线SL相连接。多条字线（参照图9）中的一条WLn可与存储器单元10的开关晶体管14相连接，并可选择或不选择存储器单元10。
钉扎磁性层11的厚度可大于自由磁性层12的厚度。当施加相对强的磁场时，钉扎磁性层11的磁偏振状态可被改变。然而，尽管施加了相对弱的磁场，但是自由磁性层12的磁偏振状态也可被改变。
隧道结层13可置于钉扎磁性层11和自由磁性层12之间。钉扎磁性层11和自由磁性层12可具有诸如NiFeCo或CoFe的材料。隧道结层13可具有诸如MgO或AlO3的材料。
开关晶体管14可通过字线WLn的电压被导通或截止。在编程操作时，可通过导通或截止开关晶体管14来选择或不选择存储器单元10。例如，当开关晶体管14导通时，编程电流可流入存储器单元10中。存储器单元10的磁化方向可根据施加到位线BLn的编程电流（或编程电压）的方向和电平而改变。
另一方面，当开关晶体管14截止时，没有编程电流会流入存储器单元10。存储器单元10的磁化方向不会根据施加到位线BLn的电流（或电压）而改变。
具有顺序堆叠的钉扎磁性层11、隧道结层13和自由磁性层12的存储器单元10可根据钉扎磁性层11和自由磁性层12的磁化方向而具有不同的电阻值。例如，如果钉扎磁性层11和自由磁性层12的磁化方向彼此相同（或处于平行状态），则存储器单元10可具有相对低的电阻值。另一方面，如果钉扎磁性层11和自由磁性层12的磁化方向彼此相反（处于反平行状态），则存储器单元10可具有相对高的电阻值。
第一非易失性存储器110（参照图9）可利用存储器单元10的电阻值根据存储器单元10的磁化方向而改变这样的特性，判断存储器单元10的编程状态。
图11是示意性示出图1中的第二非易失性存储器的方框图。在图11中，假设第二非易失性存储器120是NAND闪速存储器。
参照图11，第二非易失性存储器120可包括存储器单元阵列121、地址解码器122、读/写电路123、数据输入/输出电路124和控制逻辑125。
存储器单元阵列121可通过字线WL连接到地址解码器122，并通过位线BL连接到读/写电路123。存储器单元阵列121可包括多个存储器单元。布置在行方向上的存储器单元可与字线连接，布置在列方向上的存储器单元可与位线连接。例如，布置在列方向上的存储器单元可形成多个单元组（例如，串）。多个单元组可分别连接到位线。在示例实施例中，每个存储器单元可存储一个或多个比特的数据。
地址解码器122可通过字线WL连接到存储器单元阵列121。地址解码器122可响应于控制逻辑125的控制进行操作。地址解码器122可从外部装置接收地址ADDR。
地址解码器122可对输入的地址ADDR的行地址进行解码，并可利用解码的行地址选择字线WL。地址解码器122可对输入的地址ADDR的列地址进行解码，从而将解码的列地址传输到读/写电路123。在示例实施例中，地址解码器122可包括诸如行解码器、列解码器、地址缓冲器等的元件。
读/写电路123可通过位线BL连接到存储器单元阵列121。读/写电路123可通过数据线DL连接到数据输入/输出电路124。读/写电路123可响应于控制逻辑125的控制进行操作。读/写电路123可响应于来自地址解码器122的解码的列地址DCA来选择位线BL。
在示例实施例中，读/写电路123可从数据输入/输出电路124接收数据，然后将该数据写入在存储器单元阵列121中。读/写电路123可从存储器单元阵列121读取数据，然后将该数据输出到数据输入/输出电路124。
在示例实施例中，读/写电路123可包括诸如页缓冲器（或页寄存器）、列选择电路、数据缓冲器等的构成元件。在另一示例实施例中，读/写电路123可包括诸如感测放大器、写驱动器、列选择电路、数据缓冲器等的构成元件。
数据输入/输出电路124可通过数据线DL连接到读/写电路123。数据输入/输出电路124可响应于控制逻辑125的控制进行操作。数据输入/输出电路124可被构造成与外部装置交换数据。数据输入/输出电路124可被构造成将外部装置提供的数据通过数据线DL传输到读/写电路123。数据输入/输出电路124可被构造成将从读/写电路123传输的数据通过数据线DL输出到外部装置。在示例实施例中，数据输入/输出电路124可包括诸如数据缓冲器的构成元件。
控制逻辑125可与地址解码器122、读/写电路123和数据输入/输出电路124相连接。控制逻辑125可被构造成控制第二非易失性存储器装置120的全部操作。控制逻辑125可响应于从外部装置提供的控制信号CTRL进行操作。
图12是示意性示出根据本发明构思的实施例的半导体存储器装置的ECC方法的流程图。参照图12，根据本发明构思的实施例的半导体存储器装置的ECC方法可包括操作S110至S130。这里，半导体存储器装置可具有与半导体存储器装置100、200、300、400、500、600、700和800中的一个的结构相同的结构。
在操作S110，半导体存储器装置可确定写数据的属性。在示例实施例中，写数据可具有元数据、标准数据或缓冲数据的属性。
在操作S120，半导体存储器装置可根据写数据的属性使用第一纠错电路和第二纠错电路中的一个来产生写数据的纠错数据。这时，半导体存储器装置可考虑到写数据将被存储所在的非易失性存储器的类型，确定用于产生纠错数据的方法。这里，半导体存储器装置的第一纠错电路和第二纠错电路的详细结构以及纠错数据产生方法可与参照图1至图8所描述的结构和方法基本相同。
在操作S130，半导体存储器装置可存储纠错数据。在示例实施例中，纠错数据可存储在包括在半导体存储器装置中的非易失性存储器中的一个中或者存储在控制器中以控制非易失性存储器。
因此，当稍后读取写数据时，存储的纠错数据可被用于验证写数据的完整性。
图13是示意性地示出根据本发明构思的另一实施例的半导体存储器装置的ECC方法的流程图。参照图13，根据本发明构思的另一实施例的半导体存储器装置的ECC方法可包括操作S210至S290。这里，半导体存储器装置可具有与半导体存储器装置100、200、300、400、500、600、700和800中的一个的结构相同的结构。半导体存储器装置可包括至少两种不同类型的非易失性存储器（例如，第一非易失性存储器NVM1和第二非易失性存储器NVM2）以及控制第一非易失性存储器NVM1和第二非易失性存储器NVM2的控制器。第一非易失性存储器NVM1可被构造成与参照图1至图8描述的第一非易失性存储器110、210、310、410、510、610、710和810中的一个基本相同。第二非易失性存储器NVM2可被构造成与参照图1至图8描述的第二非易失性存储器120、220、320、420、520、620、720和820中的一个基本相同。同样地，控制器可被构造成与参照图1至图8描述的控制器130、230、330、430、530、630、730和830中的一个基本相同。
利用图13中的ECC方法，可根据写数据WD的属性以及写数据WD被编程所在的存储器的类型，使用不同的纠错电路产生写数据WD的纠错数据。根据写数据WD的属性以及写数据WD被编程所在的存储器的类型选择纠错电路的说明以及效果可与参照图1至图8所描述的说明和效果基本相同。
在操作S210，半导体存储器装置可将写数据WD输入到控制器130。
在操作S220，半导体存储器装置可确定写数据WD是否在第一非易失性存储器NVM1和第二非易失性存储器NVM2中的任何一个被编程。如上所述，第一非易失性存储器NVM1和第二非易失性存储器NVM2可具有不同的类型、最小编程单元和编程速度。如果确定第一非易失性存储器NVM1为写数据WD被编程所在的存储器，则该方法可进行至操作S230。如果确定第一非易失性存储器NVM1不是写数据WD被编程所在的存储器，则该方法可进行至操作S280。
在操作S230，半导体存储器装置可确定写数据WD是具有元数据的属性还是具有标准数据的属性。如果确定写数据WD具有元数据的属性，则该方法可进行至操作S260。如果确定写数据WD不具有元数据的属性，则该方法可进行至操作S240。
在操作S240，由于写数据WD不具有元数据的属性，所以半导体存储器装置可使用第二纠错电路ECC2产生写数据WD的纠错数据。这里，第二纠错电路ECC2可为被设计成适合于第二非易失性存储器NVM2的纠错电路。对第二纠错电路ECC2的详细描述以及与第二非易失性存储器NVM2的关系可与参照图1至图8描述的详细描述和关系基本相同。
在操作S250，半导体存储器装置可在第一非易失性存储器NVM1对写数据WD进行编程。在对写数据WD进行编程的同时或者在对写数据WD进行编程之前和之后，半导体存储器装置可将产生的纠错数据存储在第一非易失性存储器NVM1、第二非易失性存储器NVM2或控制器130中。
返回操作S230，如果写数据WD是元数据，则该方法可进行至操作S260。
在操作S260，由于写数据WD是元数据，则半导体存储器装置可使用第一纠错电路ECC1产生写数据WD的纠错数据。这里，第一纠错电路ECC1可为被设计成适合于第一非易失性存储器NVM1的纠错电路。对第一纠错电路ECC1的详细描述以及与第一非易失性存储器NVM1的关系可与参照图1至图8描述的详细描述和关系基本相同。
在操作S270，半导体存储器装置可在第一非易失性存储器NVM1对写数据WD进行编程。在对写数据WD进行编程的同时或者在对写数据WD进行编程之前和之后，半导体存储器装置可将产生的纠错数据存储在第一非易失性存储器NVM1、第二非易失性存储器NVM2或控制器130中。
返回至操作S220，如果第一非易失性存储器NVM1不是写数据WD被编程所在的存储器，即，如果第二非易失性存储器NVM2是写数据WD被编程所在的存储器，则该方法可进行至操作S280。
在操作S280，由于写数据WD是在第二非易失性存储器NVM2被编程的数据，所以半导体存储器装置可使用适合于第二非易失性存储器NVM2的第二纠错电路ECC2产生写数据WD的纠错数据。
在操作S290，半导体存储器装置可在第二非易失性存储器NVM2对写数据WD进行编程。在对写数据WD进行编程同时或者在对写数据WD进行编程之前和之后，半导体存储器装置可将产生的纠错数据存储在第一非易失性存储器NVM1、第二非易失性存储器NVM2或控制器130中。
尽管已经参照示例实施例描述了本发明构思，但是本领域技术人员将清楚的是，在不脱离本发明的精神和范围的情况下，可以做出各种改变和变型。因此，应该理解的是，上述实施例不是限制性的，而是说明性的。

Claims (15)

  1. 一种半导体存储器装置，所述半导体存储器装置包括：
    第一非易失性存储器；
    第二非易失性存储器，具有与第一非易失性存储器的类型不同的类型；
    控制器，被构造成控制第一非易失性存储器和第二非易失性存储器；
    第一纠错电路，被构造成纠正在第一非易失性存储器进行编程的第一写数据的错误；和
    第二纠错电路，包括在控制器中并被构造成基于与第一纠错电路的纠错算法不同的纠错算法来纠正第一写数据的错误或在第二非易失性存储器进行编程的第二写数据的错误，
    其中，根据第一写数据的属性使用第一纠错电路和第二纠错电路中的一个产生用于纠正第一写数据的错误的纠错数据。
  2. 据权利要求1所述的半导体存储器装置，其中，如果第一写数据具有元数据的属性，则使用第一纠错电路产生纠错数据。
  3. 根据权利要求1所述的半导体存储器装置，其中，如果第一写数据具有标准数据的属性，则使用第二纠错电路产生纠错数据。
  4. 根据权利要求1所述的半导体存储器装置，其中，如果第一写数据具有缓冲数据的属性，则使用第二纠错电路产生纠错数据，其中，缓冲数据是在第一非易失性存储器被临时编程以将缓冲数据写入到第二非易失性存储器的数据。
  5. 根据权利要求1所述的半导体存储器装置，其中，第一纠错电路被包括在第一非易失性存储器中。
  6. 根据权利要求1所述的半导体存储器装置，其中，第一纠错电路被包括在控制器中。
  7. 根据权利要求1所述的半导体存储器装置，其中，第一非易失性存储器的编程速度比第二非易失性存储器的编程速度快。
  8. 根据权利要求1所述的半导体存储器装置，其中，第一非易失性存储器是读取存储器单元两端之间的电阻值以判断存储在所述存储器单元的数据的电阻存储器。
  9. 根据权利要求1所述的半导体存储器装置，其中，第一非易失性存储器是磁随机存取存储器。
  10. 根据权利要求1所述的半导体存储器装置，其中，第二非易失性存储器是NAND闪速存储器。
  11. 根据权利要求1所述的半导体存储器装置，其中，第一纠错电路根据使用汉明码的纠错算法产生纠错数据。
  12. 根据权利要求1所述的半导体存储器装置，其中，第二纠错电路根据使用BCH码或LDPC码的纠错算法产生纠错数据。
  13. 一种半导体存储器装置的ECC方法，所述半导体存储器装置包括：第一非易失性存储器；第二非易失性存储器，具有与第一非易失性存储器的类型不同的类型；和控制器，控制第一非易失性存储器和第二非易失性存储器，所述ECC方法包括：
    确定在第一非易失性存储器进行编程的写数据的属性；
    根据写数据的属性和第一非易失性存储器的类型，使用第一非易失性存储器和第二非易失性存储器中的一个产生用于纠正写数据的错误的纠错数据；和
    存储纠错数据，
    其中，第一纠错电路和第二纠错电路根据不同的纠错算法产生纠错数据。
  14. 根据权利要求13所述的ECC方法，其中，半导体存储器装置控制控制器使得使用第二纠错电路产生在第二非易失性存储器进行编程的写数据的纠错数据。
  15. 据权利要求13所述的ECC方法，其中，半导体存储器装置在第一非易失性存储器、第二非易失性存储器或控制器存储纠错数据。
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