WO2014157342A1 - 配線基板およびこれを用いた実装構造体 - Google Patents
配線基板およびこれを用いた実装構造体 Download PDFInfo
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- WO2014157342A1 WO2014157342A1 PCT/JP2014/058548 JP2014058548W WO2014157342A1 WO 2014157342 A1 WO2014157342 A1 WO 2014157342A1 JP 2014058548 W JP2014058548 W JP 2014058548W WO 2014157342 A1 WO2014157342 A1 WO 2014157342A1
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- inorganic insulating
- layer
- resin
- resin layer
- wiring board
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/036—Multilayers with layers of different types
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
- H05K3/4655—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern by using a laminate characterized by the insulating layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0116—Porous, e.g. foam
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0209—Inorganic, non-metallic particles
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0263—Details about a collection of particles
- H05K2201/0266—Size distribution
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09845—Stepped hole, via, edge, bump or conductor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09854—Hole or via having special cross-section, e.g. elliptical
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09863—Concave hole or via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2072—Anchoring, i.e. one structure gripping into another
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
Definitions
- the present invention relates to a wiring board used for electronic devices (for example, various audiovisual devices, home appliances, communication devices, computer devices and peripheral devices thereof) and a mounting structure using the same.
- this wiring board for example, a configuration including an inorganic insulating layer (ceramic layer) and a conductive layer (nickel thin layer) disposed on the inorganic insulating layer is described (for example, JP-A-4-12087). reference).
- the insulating layer is attached to the through hole penetrating in the thickness direction and the inner wall of the through hole.
- a through conductor electrically connected to the conductive layer may be formed.
- the thermal expansion coefficients in the thickness direction of the inorganic insulating layer and the through conductor are different, if heat is applied to the wiring board during mounting or operation of the electronic component, it is between the through conductor and the inner wall of the through hole. Thermal stress is applied, and the through conductor and the inner wall of the through hole may peel off. When this peeling extends and reaches the connection portion between the through conductor and the conductive layer, a crack may occur in the connection portion. As a result, the wiring of the wiring board is disconnected, and the electrical reliability of the wiring board is lowered.
- An object of the present invention is to provide a wiring board excellent in electrical reliability and a mounting structure using the wiring board.
- a wiring board is attached to an inorganic insulating layer having a through hole penetrating in the thickness direction, a conductive layer disposed on the inorganic insulating layer, and an inner wall of the through hole.
- a first conductor including a plurality of inorganic insulating particles partially connected to each other and a resin portion disposed in a gap between the inorganic insulating particles;
- a mounting structure in one embodiment of the present invention includes the above wiring board and an electronic component mounted on the wiring board and electrically connected to the conductive layer.
- the first inorganic insulating particles that are partially connected to each other and the conductor portion that includes a part of the through conductor disposed in the gap between the first inorganic insulating particles. Two portions are interposed between the first portion and the through conductor.
- the mounting structure in one embodiment of the present invention since the wiring board described above is provided, a mounting structure having excellent electrical reliability can be obtained.
- FIG. 2 is an enlarged cross-sectional view showing a portion corresponding to a portion R2 in FIG.
- FIG. 1 is sectional drawing explaining the manufacturing process of the mounting structure shown to Fig.1 (a)
- (b) demonstrates the manufacturing process of the mounting structure shown to Fig.1 (a)
- (A) is sectional drawing explaining the manufacturing process of the mounting structure shown to Fig.1 (a)
- (b) demonstrates the manufacturing process of the mounting structure shown to Fig.1 (a), FIG. It is sectional drawing which expanded and showed the part corresponded to R2 part of (b).
- or (c) is sectional drawing explaining the manufacturing process of the mounting structure shown to Fig.1 (a)
- (d) is the cross section which expanded and showed R4 part of FIG.6 (c).
- (A) is sectional drawing which expanded and showed the part corresponded to R4 part of FIG.6 (c) explaining the manufacturing process of the mounting structure shown to Fig.1 (a), (b), It is sectional drawing which expanded and showed R5 part of Fig.7 (a).
- (A) is sectional drawing which expanded and showed R6 part of Fig.7 (a), (b) demonstrates the manufacturing process of the mounting structure shown to Fig.1 (a), FIG.6 (c). It is sectional drawing which expanded and showed the part corresponded to R4 part of ().
- (A) is sectional drawing explaining the manufacturing process of the mounting structure shown to Fig.1 (a), (b) is sectional drawing which expanded and showed R7 part of Fig.9 (a).
- (A) is sectional drawing which expanded and showed R8 part of FIG.9 (b), (b) is sectional drawing explaining the manufacturing process of the mounting structure shown to Fig.1 (a).
- the mounting structure 1 shown in FIG. 1A is used for electronic devices such as various audiovisual devices, home appliances, communication devices, computer devices or peripheral devices thereof.
- the mounting structure 1 includes an electronic component 2 and a wiring board 3 on which the electronic component 2 is mounted.
- the electronic component 2 is, for example, a semiconductor element such as an IC or LSI, or an acoustic wave device such as a surface acoustic wave (SAW) device or a piezoelectric thin film resonator (FBAR).
- the electronic component 2 is flip-chip mounted on the wiring board 3 via bumps 4 made of a conductive material such as solder.
- the thickness of the electronic component 2 is, for example, not less than 0.1 mm and not more than 1 mm.
- the coefficient of thermal expansion in each direction of the electronic component 2 is, for example, not less than 2 ppm / ° C. and not more than 14 ppm / ° C.
- the thermal expansion coefficient of the electronic component 2 is measured by a measuring method according to JIS K7197-1991 using a commercially available TMA (Thermo-Mechanical Analysis) device.
- TMA Thermo-Mechanical Analysis
- the wiring board 3 has functions of supporting the electronic component 2 and supplying power and signals for driving or controlling the electronic component 2 to the electronic component 2.
- the wiring substrate 3 includes a core substrate 5 and a pair of buildup layers 6 formed on the upper and lower surfaces of the core substrate 5.
- the thickness of the wiring board 3 is, for example, not less than 0.05 mm and not more than 1.5 mm.
- the coefficient of thermal expansion in the main surface direction (XY plane direction) of the wiring board 3 is, for example, 4 ppm / ° C. or more and 20 ppm / ° C. or less.
- the core substrate 5 is intended to enhance electrical connection between the pair of buildup layers 6 while increasing the rigidity of the wiring substrate 3.
- the core substrate 5 includes a base body 7 that supports the buildup layer 6, a cylindrical through-hole conductor 8 that is disposed in a through hole that penetrates the base body 7 in the thickness direction, and a columnar shape that is surrounded by the through-hole conductor 8.
- the insulator 9 is included.
- the base 7 makes the wiring board 3 highly rigid and has a low coefficient of thermal expansion.
- the base 7 includes, for example, a resin such as an epoxy resin, a base material such as a glass cloth coated with the resin, and filler particles made of silicon oxide or the like dispersed in the resin.
- the through-hole conductor 8 electrically connects the pair of buildup layers 6 to each other.
- the through-hole conductor 8 includes a conductive material such as copper.
- the insulator 9 fills the space surrounded by the through-hole conductor 8.
- the insulator 9 includes a resin such as an epoxy resin.
- a pair of buildup layers 6 are formed on the upper and lower surfaces of the core substrate 5.
- one buildup layer 6 is connected to the electronic component 2 via the bump 4, and the other buildup layer 6 is connected to an external circuit via, for example, a solder ball (not shown). (Not shown).
- the buildup layer 6 includes a plurality of insulating layers 10 having via holes V (through holes) penetrating in the thickness direction (Z direction), and a plurality of conductive layers partially disposed on the substrate 7 or the insulating layer 10. 11 and a plurality of via conductors 12 (through conductors) attached to the inner wall W of the via hole V and connected to the conductive layer 11.
- the insulating layer 10 functions as an insulating member between the conductive layers 11 separated in the thickness direction or the main surface direction and an insulating member between the via conductors 12 separated in the main surface direction.
- the thickness of the insulating layer 10 is, for example, 15 ⁇ m or more and 50 ⁇ m or less.
- the insulating layer 10 is a first resin having a thickness smaller than that of the inorganic insulating layer 13 and interposed between the inorganic insulating layer 13 and the conductive layer 11 while being in contact with the inorganic insulating layer 13 and the inorganic insulating layer 13 and the conductive layer 11.
- a second resin layer 15 having a thickness larger than that of the first resin layer 14 disposed on the opposite side of the inorganic insulating layer 13 from the first resin layer 14 while being in contact with the inorganic insulating layer 13. Yes.
- the connecting portion between the conductive layer 11 and the via conductor 12 is interposed.
- the applied thermal stress can be reduced.
- the conductive layer 11 and the via conductor 12 can be reduced by reducing the coefficient of thermal expansion in the thickness direction of the insulating layer 10 and approaching the via conductor 12. The thermal stress applied to the connecting portion can be reduced.
- the inorganic insulating layer 13 includes a plurality of inorganic insulating particles 16 that are partially connected to each other, and a resin portion disposed in a part of a gap 17 between the inorganic insulating particles 16. 18 and a conductor portion 19 composed of a part of the via conductor 12 disposed in another part of the gap 17 between the inorganic insulating particles 16.
- the inorganic insulating layer 13 has a Young's modulus larger than that of the first resin layer 14 and the second resin layer 15, and a coefficient of thermal expansion in each direction is small. Therefore, since the difference in coefficient of thermal expansion between the electronic component 2 and the wiring board 3 can be reduced, the electronic component 2 and the electronic component 2 when the heat is applied to the mounting structure 1 when the electronic component 2 is mounted or operated. Warpage caused by the difference in thermal expansion coefficient with the wiring board 3 can be reduced. Accordingly, it is possible to suppress the breakage of the connection portion between the electronic component 2 and the wiring board 3 due to the warp, and to improve the connection reliability between the electronic component 2 and the wiring board 3.
- the inorganic insulating layer 13 forms a porous body having a three-dimensional network structure by connecting the inorganic insulating particles 16 to each other.
- a resin part 18 is disposed in a part of the gap 17 of the porous body, and a conductor part 19 is disposed in another part of the gap 17.
- a connection part between the plurality of inorganic insulating particles 16 is constricted and has a neck structure.
- the thickness of the inorganic insulating layer 13 is, for example, 3 ⁇ m or more and 30 ⁇ m or less.
- the Young's modulus of the inorganic insulating layer 13 is, for example, 10 GPa or more and 50 GPa or less.
- the coefficient of thermal expansion in each direction of the inorganic insulating layer 13 is, for example, 0 ppm / ° C. or more and 10 ppm / ° C. or less.
- the inorganic insulating particles 16 have a plurality of first inorganic insulating particles 20 that are partially connected to each other and a particle size larger than that of the first inorganic insulating particles 20, and a part is connected to the first inorganic insulating particles 20.
- a plurality of second inorganic insulating particles 21 that are separated from each other with the first inorganic insulating particles 20 in between are included. The second inorganic insulating particles 21 and the first inorganic insulating particles 20 are partially connected to each other, and the plurality of second inorganic insulating particles 21 are bonded to each other via the first inorganic insulating particles 20.
- the first inorganic insulating particles 20 function as connecting members in the inorganic insulating layer 13. Further, since the first inorganic insulating particles 20 have a small average particle diameter and are firmly connected as described later, the inorganic insulating layer 13 can have a low thermal expansion coefficient and a high Young's modulus.
- the first inorganic insulating particles 20 are made of an inorganic insulating material such as silicon oxide or aluminum oxide, and preferably contain silicon oxide as a main component. Silicon oxide is preferably in an amorphous state in order to reduce the anisotropy of the thermal expansion coefficient due to the crystal structure.
- the content rate of the silicon oxide in the 1st inorganic insulating particle 20 is 99.9 mass% or more and 100 mass% or less, for example.
- the first inorganic insulating particles 20 are, for example, spherical.
- the average particle diameter of the first inorganic insulating particles 20 is 3 nm or more and 110 nm or less.
- the Young's modulus of the first inorganic insulating particles 20 is, for example, 40 GPa or more and 90 GPa or less.
- the coefficient of thermal expansion in each direction of the first inorganic insulating particles 20 is, for example, 0 ppm / ° C. or more and 15 ppm / ° C. or less.
- the average particle diameter of the first inorganic insulating particles 20 can be measured by calculating the average value of the particle diameter of each particle in the cross section in the thickness direction of the wiring board 3.
- the average particle diameter of each member is measured in the same manner as the first inorganic insulating particles 20.
- the second inorganic insulating particles 21 suppress the extension of cracks generated in the inorganic insulating layer 13.
- the second inorganic insulating particles 21 can be made of the same material and characteristics as the first inorganic insulating particles 20.
- the second inorganic insulating particles 21 are, for example, spherical, and the average particle size of the second inorganic insulating particles 21 is, for example, not less than 0.5 ⁇ m and not more than 5 ⁇ m.
- the gap 17 is an open pore and has an opening on one main surface and the other main surface of the inorganic insulating layer 13.
- the plurality of inorganic insulating particles 16 that are partially connected to each other form a porous body, at least a part of the gap 17 is surrounded by the inorganic insulating particles 16 in the cross section in the thickness direction of the inorganic insulating layer 13. It is.
- the resin portion 18 is made of a resin material that is more elastically deformed than the inorganic insulating material, the stress applied to the inorganic insulating layer 13 is reduced and the occurrence of cracks in the inorganic insulating layer 13 is suppressed.
- the resin portion 18 of this embodiment is a part of the second resin layer 15 that has entered the gap 17. As a result, the adhesive strength between the inorganic insulating layer 13 and the second resin layer 15 can be increased.
- the first resin layer 14 has a function of relieving thermal stress between the inorganic insulating layer 13 and the conductive layer 11.
- the thickness of the 1st resin layer 14 is 0.1 micrometer or more and 5 micrometers or less, for example.
- the Young's modulus of the first resin layer 14 is, for example, not less than 0.05 GPa and not more than 5 GPa.
- the coefficient of thermal expansion in each direction of the first resin layer 14 is, for example, not less than 20 ppm / ° C. and not more than 100 ppm / ° C.
- the first resin layer 14 includes a first resin 22 and a plurality of first filler particles 23 dispersed in the first resin 22 as shown in FIG.
- the content rate of the 1st filler particle 23 in the 1st resin layer 14 is 0.05 volume% or more and 10 volume% or less, for example.
- the content ratio of the first filler particles 23 in the first resin layer 14 is the content ratio (volume) of the area occupied by the first filler particles 23 in the first resin layer 14 in the cross section in the thickness direction of the wiring board 3. %).
- the content ratio of each particle in each member is measured in the same manner as the first filler particles 23.
- the first resin 22 is made of a resin material such as an epoxy resin, a bismaleimide triazine resin, a cyanate resin, or a polyimide resin, and is preferably made of an epoxy resin.
- the Young's modulus of the first resin 22 is, for example, not less than 0.1 GPa and not more than 5 GPa.
- the coefficient of thermal expansion in each direction of the first resin 22 is, for example, not less than 20 ppm / ° C. and not more than 50 ppm / ° C.
- the first filler particles 23 can be made of the same material and characteristics as the second inorganic insulating particles 21 described above.
- the 1st filler particle 23 is spherical, for example, and the average particle diameter of the 1st filler particle 23 is 0.05 micrometer or more and 0.7 micrometer or less, for example.
- the second resin layer 15 functions as an adhesive member that bonds the insulating layers 10 together.
- the second resin layer 15 is disposed between the conductive layers 11 partially separated in the main surface direction, and the thickness of the second resin layer 15 is larger than that of the first resin layer 14.
- the thickness of the second resin layer 15 is, for example, 3 ⁇ m or more and 30 ⁇ m or less.
- the Young's modulus of the second resin layer 15 is, for example, not less than 0.2 GPa and not more than 20 GPa.
- the coefficient of thermal expansion in each direction of the second resin layer 15 is, for example, not less than 20 ppm / ° C. and not more than 50 ppm / ° C.
- the second resin layer 15 includes a second resin 24 and a plurality of second filler particles 25 dispersed in the second resin 24 as shown in FIG.
- the content rate of the 2nd filler particle 25 in the 2nd resin layer 15 is 3 volume% or more and 60 volume% or less, for example.
- a material having the same material and characteristics as the first resin 22 can be used.
- the second filler particles 25 those having the same material and characteristics as the first filler particles 23 can be used.
- the average particle diameter of the second filler particles 25 is, for example, not less than 0.5 ⁇ m and not more than 5 ⁇ m.
- the content ratio of the first filler particles 23 in the first resin layer 14 is smaller than the content ratio of the second filler particles 25 in the second resin layer 15.
- the Young's modulus of the first resin layer 14 can be reduced at the corners of the insulating layer 10 located at the connection portion between the conductive layer 11 and the via conductor 12.
- the thermal stress applied to the connection portion can be reduced.
- veer resulting from protrusion of the 1st filler particle 23 are used.
- the occurrence of cracks at the connecting portion with the conductor 12 can be reduced.
- the average particle diameter of the first filler particles 23 is smaller than the average particle diameter of the second filler particles 25. As a result, it is possible to reduce the occurrence of cracks at the connection portion between the conductive layer 11 and the via conductor 12 due to the protrusion of the first filler particles 23.
- the inner wall W of the via hole V penetrating the insulating layer 10 in the thickness direction described above and the first region W1 formed of the side surface of the first resin layer 14 and the inorganic insulating layer 13
- the second region W ⁇ b> 2 including one main surface of the first resin layer 14 side and the third region W ⁇ b> 3 including the side surface of the inorganic insulating layer 13 are included.
- the inner wall W of the via hole V includes the first to third regions W1 to W3, the corner portion of the insulating layer 10 located at the connection portion between the conductive layer 11 and the via conductor 12 is brought close to the R shape.
- the thermal stress applied to the connection portion between the conductive layer 11 and the via conductor 12 can be dispersed. Therefore, since it is possible to suppress the occurrence of cracks at the connection portion between the conductive layer 11 and the via conductor 12, it is possible to suppress the disconnection of the wiring of the wiring substrate 3, and thus to obtain the wiring substrate 3 excellent in electrical reliability. Can do.
- the inner wall W of the via hole V penetrating the insulating layer 10 in the thickness direction described above has a fourth region W4 made of the other main surface of the inorganic insulating layer 13 and a fifth region W5 made of the side surface of the second resin layer 15. Including.
- the peeling of the via conductor 12 from the conductive layer 11 at the bottom surface B of the via hole V can be suppressed, disconnection of the wiring of the wiring board 3 can be suppressed.
- the via conductors 12 form stacked vias arranged in a line along the thickness direction of the wiring board 3, stress due to warping of the wiring board 3 is easily applied to the via conductors 12. As a result, the peeling of the via conductor 12 from 11 can be satisfactorily suppressed.
- the width of the second region W2 is, for example, not less than 0.2 ⁇ m and not more than 5 ⁇ m.
- the width of the fourth region W4 is, for example, not less than 0.2 ⁇ m and not more than 5 ⁇ m.
- the width of the second region W2 is desirably the same as the width of the fourth region W4. In this case, the error in the width of the second region W2 and the fourth region W4 is within ⁇ 30%.
- the width of the second region W2 is a length between one end portion on the first region W1 side and the other end portion on the third region W3 side in the second region W2.
- the width of the fourth region W4 is a length between one end portion on the third region W3 side and the other end portion on the fifth region W5 side in the fourth region W4.
- the inclination angle A1 of the first region W1 with respect to the penetration direction of the via hole V is larger than the inclination angle A2 of the third region W3 with respect to the penetration direction of the via hole V.
- the inclination angles A1 and A2 are angles between the imaginary line segments L1 and L2 and the inner wall W that are parallel to the penetration direction and extend from the via hole V to the inner wall W of the via hole V.
- the inclination angle A1 is, for example, not less than 5 ° and not more than 70 °.
- the inclination angle A2 is, for example, not less than 2 ° and not more than 30 °.
- the conductive layers 11 are separated from each other in the thickness direction or the main surface direction, and function as wiring such as ground wiring, power supply wiring, or signal wiring.
- the conductive layer 11 is made of a conductive material such as copper.
- the thickness of the conductive layer 11 is 3 micrometers or more and 20 micrometers or less, for example.
- the thermal expansion coefficient in each direction of the conductive layer 11 is, for example, 14 ppm / ° C. or more and 18 ppm / ° C. or less.
- the Young's modulus of the conductive layer 11 is, for example, 70 GPa or more and 150 or less GPa.
- the Young's modulus of the conductive layer 11 is measured by a method according to ISO14577-1: 2002 using a nanoindenter XP manufactured by MTS. Hereinafter, the Young's modulus of each member is measured in the same manner as the conductive layer 11.
- the conductive layer 11 has a metal foil 26 adhered to the first resin layer 14, an electroless plating layer 27 deposited on the metal foil 26, and an electroplating layer 28 deposited on the electroless plating layer 27. is doing.
- the metal foil 26 for example, a rolled copper foil or an electrolytic copper foil can be used.
- the rolled copper foil or the electrolytic copper foil has a high strength because it has fewer lattice defects than the electroless plating.
- the thickness of the metal foil 26 is, for example, not less than 0.2 ⁇ m and not more than 4 ⁇ m.
- the metal foil 26 has an adhesive portion 29 bonded to the first resin layer 14 and a protruding portion 30 protruding from the first resin layer 14 toward the via hole V.
- the via conductor 12 can be fixed in the thickness direction by the protruding portion 30 of the metal foil 26, the inclination of the via conductor 12 due to the warp of the wiring board 3 is suppressed, and the conduction at the bottom surface B of the via hole V is suppressed. Peeling of the via conductor 12 from the layer 11 can be suppressed.
- the electroless plating layer 27 can use, for example, electroless copper plating.
- the thickness of the electroless plating layer 27 is, for example, not less than 0.3 ⁇ m and not more than 3 ⁇ m.
- the electroplating layer 28 for example, electrolytic copper plating or the like can be used.
- the thickness of the electroplating layer 28 is, for example, 5 ⁇ m or more and 30 ⁇ m or less.
- the via conductor 12 electrically connects the conductive layers 11 separated from each other in the thickness direction, and functions as a wiring together with the conductive layer 11.
- the via conductor 12 is filled in the via hole V.
- via conductors 12 connected to each other in the buildup layer 6 disposed on the electronic component 2 side constitute stacked vias arranged in a line along the thickness direction of the wiring board 3.
- the via conductor 12 is made of the same material as that of the conductive layer 11 and has the same characteristics.
- the via conductor 12 includes an electroless plating film 31 deposited on the inner wall W and the bottom surface B of the via hole V, and an electroplating portion that is deposited on the electroless plating film 31 and filled in the via hole V. 32.
- the electroless plating film 31 is integrally formed with the electroless plating layer 27 of the conductive layer 11 adhered to the first resin layer 14.
- the electroplating portion 32 is formed integrally with the electroplating layer 28 of the conductive layer 11 adhered to the first resin layer 14.
- a part of the electroplating portion 32 of the via conductor 12 is disposed between the second region W2 and the protruding portion 30.
- a portion of the electroplated portion 32 having a higher strength than the electroless plated film 31 is disposed between the second region W2 and the protruding portion 30, and thus the via conductor 12 is firmly fixed in the thickness direction. be able to.
- the thermal expansion coefficients in the thickness direction of the inorganic insulating layer 13 and the via conductor 12 are different, when heat is applied to the wiring board 3 during mounting or operation of the electronic component 2, the inner wall W of the via conductor 12 and the via hole V is provided. Thermal stress is applied between the two.
- the inorganic insulating layer 13 of this embodiment is arranged in a plurality of inorganic insulating particles 16 and gaps 17 between the plurality of inorganic insulating particles 16 that are partially connected to each other.
- a second portion 34 interposed between the first portion 33 and the via conductor 12.
- the coefficient of thermal expansion of the first portion 33 is brought close to the coefficient of thermal expansion of the inorganic insulating particles 16.
- the coefficient of thermal expansion of the first portion 33 can be reduced, and consequently the coefficient of thermal expansion of the inorganic insulating layer 13 can be reduced.
- the second portion 34 includes the conductor portion 19 composed of the inorganic insulating particles 16 and a part of the via conductor 12, the thermal expansion coefficient of the second portion 34 is equal to the thermal expansion coefficient of the first portion 33 and the via conductor 12. It can be set to a value between the coefficient of thermal expansion.
- the second portion 34 is interposed between the first portion 33 and the via conductor 12, the thermal stress applied between the via conductor 12 and the inner wall W of the via hole V can be reduced. Separation of the via conductor 12 and the inner wall W of the via hole can be suppressed. Therefore, since it is possible to suppress the occurrence of cracks at the connection portion between the via conductor 12 and the conductive layer 11 due to this peeling, the occurrence of disconnection in the wiring of the wiring board 3 is suppressed, and thus the electrical reliability is excellent. A wiring board 3 can be obtained.
- the plurality of inorganic insulating particles 16 in the first portion 33 and the second portion 34 have an average particle diameter, as shown in FIG. And a plurality of second inorganic insulating particles 21 that are larger than the first inorganic insulating particles 20 and are separated from each other with the first inorganic insulating particles 20 interposed therebetween.
- the inorganic insulating particles 16 include the first inorganic insulating particles 20 and the second inorganic insulating particles 21 in both the first portion 33 and the second portion 34, the inorganic portions in the first portion 33 and the second portion 34 are inorganic.
- the filling rate of the insulating particles 16 can be made closer to each other, and the thermal expansion coefficients in the first portion 33 and the second portion 34 can be made closer to each other. Therefore, the thermal stress applied between the first portion 33 and the second portion 34 can be reduced, and the separation between the first portion 33 and the second portion 34 can be suppressed. Therefore, this peeling can be prevented from extending and reaching the conductive layer 11, and the occurrence of cracks in the conductive layer 11 can be suppressed.
- the content ratio of the inorganic insulating particles 16 in the second portion 34 is smaller than the content ratio of the inorganic insulating particles 16 in the first portion 33.
- the content ratio of the inorganic insulating particles 16 is increased to reduce the coefficient of thermal expansion
- the content ratio of the inorganic insulating particles 16 is decreased to reduce the thermal conductivity.
- the via conductor 12 is made of plating, the plating solution in the gap 17 can be easily replaced. Therefore, the generation of voids that are not filled with the conductor portion 19 in the gap 17 can be suppressed. Therefore, since the adhesive strength between the second portion 34 and the via conductor 12 can be increased, peeling between the second portion 34 and the via conductor 12 can be suppressed.
- the second portion 34 is arranged in the vicinity of the via conductor 12 in the inorganic insulating layer 13, and the width of the second portion 34 (one end of the second portion 34 on the via conductor 12 side and the side opposite to the via conductor 12).
- the width between the other end is 1 ⁇ m or more and 5 ⁇ m or less, for example.
- the content ratio of the inorganic insulating particles 16 in the first portion 33 is, for example, 60% by volume or more and 90% by volume or less.
- the content ratio of the inorganic insulating particles 16 in the second portion 34 is, for example, 40% by volume or more and 70% by volume or less.
- one main surface of the second portion 34 on the conductive layer 11 side is exposed from the first resin layer 14 and constitutes an inner wall W of the via hole V. That is, one main surface of the second portion 34 constitutes a second region W2 of the inner wall W.
- a part of the via conductor 12 attached to the second region W2 fixes the second portion 34 in the thickness direction, so that the separation between the second portion 34 and the via conductor 12 can be suppressed. Therefore, the occurrence of cracks at the connection portion between the conductive layer 11 and the via conductor 12 can be suppressed.
- the other main surface of the second portion 34 opposite to the conductive layer 11 is exposed from the second resin layer 15 and constitutes the inner wall W of the via hole V. That is, the other main surface of the second portion 34 constitutes a fourth region W4 of the inner wall W.
- a part of the via conductor 12 attached to the fourth region W4 fixes the second portion 34 in the thickness direction, so that the separation between the second portion 34 and the via conductor 12 can be suppressed. Therefore, the occurrence of cracks at the connection portion between the conductive layer 11 and the via conductor 12 can be suppressed.
- a part of the electroless plating film 31 enters the gap 17 of the second portion 34 and constitutes the conductor portion 19.
- a part of the electroplating part 32 enters the gap 17 of the second part 34 together with a part of the electroless plating film 31, thereby constituting the conductor part 19.
- a part of the electroless plating film 31 constituting the conductor part 19 is interposed between a part of the electroplating part 32 constituting the conductor part 19 and the resin part 18.
- the other part of the electroless plating film 31 is attached to the first region W1 and the fifth region W5 of the inner wall W.
- the core substrate 5 is manufactured. Specifically, for example, the following is performed.
- a laminate comprising a base 7 formed by curing a prepreg and a metal foil such as a copper foil disposed on both main surfaces of the base 7 is prepared.
- through holes are formed in the laminate using laser processing, drilling, or the like.
- a cylindrical through-hole conductor 8 is formed by depositing a conductive material in the through-hole using, for example, an electroless plating method, an electroplating method, a vapor deposition method, or a sputtering method.
- the insulator 9 is formed by filling the inside of the through-hole conductor 8 with an uncured resin and curing it.
- a conductive material is deposited on the insulator 9 using, for example, an electroless plating method or an electroplating method, and then the metal foil and the conductive material on the base 7 are patterned to form the conductive layer 11. .
- the core substrate 5 can be manufactured as described above.
- a metal foil 26 such as a copper foil, an inorganic insulating layer 13 disposed on the metal foil 26, and an inorganic insulating layer 13 are disposed.
- a laminated sheet 36 having a resin layer precursor 35 containing an uncured resin is prepared. Specifically, for example, the following is performed.
- a metal foil with resin 37 having a metal foil 26 and a first resin layer 14 disposed on the metal foil 26 is prepared.
- a slurry 39 having inorganic insulating particles 16 and a solvent 38 in which the inorganic insulating particles 16 are dispersed is prepared. Apply to the main surface.
- the solvent 38 is evaporated from the slurry 39 to leave the inorganic insulating particles 16 on the metal foil 26, and the powder composed of the remaining inorganic insulating particles 16.
- Layer 40 is formed. In the powder layer 40, the first inorganic insulating particles 20 are in contact with each other at close positions.
- the powder layer 40 is heated and the adjacent first inorganic insulating particles 20 are connected to each other at a close location, thereby making it more than the first resin layer 14.
- a thick inorganic insulating layer 13 is formed.
- a resin layer precursor 35 including an uncured resin to be the second resin 24 and the second filler particles 25 is laminated on the inorganic insulating layer 13, and the laminated inorganic insulation is laminated. Part of the resin layer precursor 35 is filled in the gap 17 by heating and pressing the layer 13 and the resin layer precursor 35 in the thickness direction.
- the laminated sheet 36 can be produced as described above.
- the average particle diameter of the first inorganic insulating particles 20 is 3 nm or more and 110 nm or less, a part of the plurality of first inorganic insulating particles 20 can be firmly connected to each other even under a low temperature condition. This is because, since the first inorganic insulating particles 20 are very small, the atoms of the first inorganic insulating particles 20, particularly the atoms on the surface, actively move. It is presumed that the temperature connected to is reduced.
- the plurality of first inorganic insulating particles 20 can be firmly connected to each other under a low temperature condition such as less than the crystallization start temperature of the first inorganic insulating particles 20 and further 250 ° C. or less. Further, by heating at such a low temperature in this way, the first inorganic insulating particles 20 and the first inorganic insulating particles 20 and the second inorganic insulating particles 20 and the second inorganic insulating particles 20 are maintained while maintaining the particle shapes of the first inorganic insulating particles 20 and the second inorganic insulating particles 21.
- the inorganic insulating particles 21 can be connected only in the proximity region.
- the temperature at which the first inorganic insulating particles 20 can be firmly connected is, for example, about 250 ° C. when the average particle size of the first inorganic insulating particles 20 is set to 110 nm. When the average particle size of 20 is set to 15 nm, it is about 150 ° C.
- the slurry 39 further including the plurality of second inorganic insulating particles 21 having an average particle diameter of 0.5 ⁇ m or more and 5 ⁇ m or less is applied on the metal foil 26. .
- the powder layer 40 formed by evaporating the solvent 38 can be used. Shrinkage can be reduced. Therefore, the occurrence of cracks along the thickness direction in the powder layer 40 can be reduced by reducing the shrinkage of the powder layer 40 that is flat and easily contracts in the main surface direction.
- the content ratio of the inorganic insulating particles 16 in the slurry 39 is, for example, 10% to 50% by volume, and the content ratio of the solvent 38 in the slurry 39 is, for example, 50% to 90% by volume.
- the solvent 38 for example, methanol, isopropanol, methyl ethyl ketone, methyl isobutyl ketone, xylene, or an organic solvent containing a mixture of two or more selected from these can be used.
- the slurry 39 is dried by, for example, heating and air drying.
- the drying temperature is, for example, 20 ° C. or higher and lower than the boiling point of the solvent 38, and the drying time is, for example, 20 seconds or longer and 30 minutes or shorter.
- the heating temperature at the time of heating the powder layer 40 is not less than the boiling point of the solvent 38 and less than the crystallization start temperature of the first inorganic insulating particles 20, and is not less than 100 ° C. and not more than 250 ° C.
- the heating time is, for example, 0.5 hours or more and 24 hours or less.
- the pressurizing pressure when the laminated inorganic insulating layer 13 and the resin layer precursor 35 are heated and pressurized is, for example, 0.05 MPa or more and 0.5 MPa or less, and the pressing time is, for example, 20 seconds or more and 5 minutes or less.
- the heating temperature is, for example, 50 ° C. or more and 100 ° C. or less. In addition, since this heating temperature is less than the curing start temperature of the resin layer precursor 35, the resin layer precursor 35 can be maintained in an uncured state.
- Conductive layer 11 and via conductor 12 are formed. Specifically, for example, the following is performed.
- the laminated sheet 36 is laminated on the core substrate 5 while arranging the resin layer precursor 35 on the core substrate 5 side.
- the laminated sheet 36 is bonded to the core substrate 5 by heating and pressing the laminated core substrate 5 and laminated sheet 36 in the thickness direction.
- the resin layer precursor 35 is heated to cure the uncured resin to form the second resin 24 and the resin layer precursor 35 to the second resin layer 15. .
- the insulating layer 10 having the first resin layer 14 and the inorganic insulating layer 13 having a thickness larger than that of the first resin layer 14 can be formed.
- a part of the resin layer precursor 35 that has entered the gap 17 in the step (2) becomes the resin portion 18.
- laser processing is used to irradiate the insulating layer 10 in the thickness direction by irradiating laser light from the metal foil 26 side toward the insulating layer 10 side.
- a penetrating via hole V is formed.
- the conductive layer 11 is exposed on the bottom surface B of the via hole V.
- the protruding portion 30 protruding from the inorganic insulating layer 13 toward the via hole V is formed on the metal foil with resin 37.
- the resin portion 18 is removed from a part of the gap 17 near the inner wall W of the via hole V in the inorganic insulating layer 13 using an etching solution. To make voids. Further, the first portion 33 is formed by leaving the resin portion 18 in the other portion of the gap 17 in the inorganic insulating layer 13. Further, a part of the first resin layer 14 is removed by this etching solution, and the second region W2 formed of one main surface of the inorganic insulating layer 13 on the first resin layer 14 side is exposed to the inner wall W of the via hole V.
- a protruding portion 30 protruding from the inorganic insulating layer 13 toward the via hole V is formed on the metal foil 26. Further, a part of the second resin layer 15 is removed by this etching solution, and the fourth region W4 formed of one main surface of the inorganic insulating layer 13 on the second resin layer 15 side is exposed to the inner wall W of the via hole V. Further, by dissolving a part of the inorganic insulating particles 16 with this etching liquid, the content ratio of the inorganic insulating particles 16 in the second portion 34 becomes smaller than the content ratio of the inorganic insulating particles 16 in the first portion 33.
- the plating film 31 is integrally formed. At this time, a part of the electroless plating film 31 is disposed in a part of the gap 17 from which the resin portion 18 is removed. Next, a resist having a desired pattern is formed on the electroless plating layer 27. Next, as shown in FIGS. 9A to 10A, the electroplating layer 28 deposited on the electroless plating layer 27 and the electroplating deposited on the electroless plating film 31 using electroplating.
- the plating part 32 is integrally formed.
- the second portion 34 is formed by forming a conductor portion 19 by arranging a part of the electroplating portion 32 in a portion of the gap 17 from which the resin portion 18 is removed.
- the resist for example, an aqueous sodium hydroxide solution
- the portion of the electroless plating layer 27 covered with the resist is removed with, for example, an aqueous cupric chloride solution or sulfuric acid.
- the via conductor 12 deposited on the inner wall W of the via hole V and the conductive layer 11 disposed on the first resin layer 14 are formed, and at the part of the gap 17 from which the resin portion 18 is removed.
- the second portion 34 can be formed in the inorganic insulating layer 13 by arranging the conductor portion 19 formed of a part of the via conductor 12.
- the metal foil 26 of the protruding portion 30 is left and the first portion of the protruding portion 30 is left.
- One resin layer 14 is removed.
- the first resin layer 14 made of a material different from that of the via conductor 12 and the conductive layer 11 does not remain in the connection portion between the via conductor 12 and the conductive layer 11. Generation of cracks can be suppressed.
- the via hole V penetrating the insulating layer 10 in the thickness direction was formed by irradiating laser light from the metal foil 26 side toward the insulating layer 10 side. Thereafter, a part of the first resin layer 14 is removed using an etching solution.
- the etching solution since heat is transferred from the metal foil 26 to the first resin layer 14 when the laser beam is irradiated, the region in the vicinity of the metal foil 26 of the first resin layer 14 is easily removed by the etching solution. Therefore, when removing a part of the first resin layer 14 using the etching solution, the inclination angle A1 of the first region W1 can be made larger than the inclination angle A2 of the third region W3.
- a CO 2 laser or a UV-YAG laser can be used for the laser processing for forming the via hole V.
- the metal foil 26 is more difficult to be processed, so that the protruding portion 30 of the metal foil 26 can be formed more easily.
- the inclination angle A1 of the first region W1 can be made larger than the inclination angle A2 of the third region W3 more easily.
- the output of the CO 2 laser is, for example, 4 mJ or more and 6 mmJ or less.
- the heating and pressurization when the laminated sheet 36 is bonded to the core substrate 5 can use the same conditions as in the step (2).
- the heating temperature when the uncured resin is cured to form the second resin 24 is, for example, not less than the curing start temperature of the uncured resin and less than the thermal decomposition temperature, and the heating time is, for example, not less than 10 minutes and not more than 120 minutes.
- an alkaline solution such as a sodium hydroxide aqueous solution can be used.
- the processing time of the etching solution is, for example, 1 minute or more and 15 minutes or less.
- the build-up layer 6 is formed on the core substrate 5 by repeating the steps (2) and (3), and the wiring substrate 3 is manufactured.
- the build-up layer 6 can be multi-layered by repeating this process.
- the electronic component 2 is flip-chip mounted on the wiring board 3 via the bumps 4 to produce the mounting structure 1 shown in FIG.
- the electronic component 2 may be electrically connected to the wiring board 3 by wire bonding, or may be incorporated in the wiring board 3.
- the build-up layer 6 has been described as an example in which the build-up layer 6 includes the inorganic insulating layer 13, the first resin layer 14, and the second resin layer 15. 13, the first resin layer 14 and the second resin layer 15 may be included.
- the second portion of the inorganic insulating layer of the core substrate 5 includes a conductor portion made of a part of the through-hole conductor (through conductor).
- the buildup layer 6 includes the inorganic insulating layer 13, the first resin layer 14, and the second resin layer 15, and the inner wall W of the via hole V is in the first to fifth regions.
- the core substrate 5 has a configuration corresponding to the inorganic insulating layer 13, the first resin layer 14, and the second resin layer 15, and penetrates the core substrate 5 in the thickness direction.
- the inner wall of the through hole (through hole) may have a region corresponding to the first to fifth regions W1 to W5.
- a through hole conductor 8 (through conductor) is attached to the inner wall of the through hole.
- the example in which the build-up multilayer substrate including the core substrate 5 and the build-up layer 6 is used as the wiring substrate 3 has been described.
- a single-layer substrate having only the core substrate 5 or a coreless substrate having only the build-up layer 6 may be used.
- the configuration in which the insulating layer 10 includes the inorganic insulating layer 13, the first resin layer 14, and the second resin layer 15 has been described as an example.
- the first resin layer 14 and the second resin layer 15 do not have to be provided.
- the configuration in which the inorganic insulating particles 16 include the second inorganic insulating particles 21 has been described as an example.
- the inorganic insulating particles 16 may not include the second inorganic insulating particles 21. I do not care.
- the resin portion 18 includes the first resin that has entered the gap 17. It may be a part of the layer 14, or may be a part of the first resin layer 14 and a part of the second resin layer 15. In this case, the adhesive strength between the inorganic insulating layer 13 and the first resin layer 14 can be increased.
- the via conductor 12 may be attached to the inner wall W of the via hole V.
- it may be a film.
- the configuration in which the inclination angle A1 of the first region W1 is larger than the inclination angle A2 of the third region W3 has been described as an example, but the inclination angle A1 of the first region W1 and the third region The inclination angle A2 of W3 may be the same.
- the adhesion portion 29 of the metal foil 26 is formed larger toward the via hole V side, the via conductor 12 can be firmly fixed in the thickness direction by the protruding portion 30.
- the configuration in which the first resin layer 14 includes the first filler particles 23 has been described as an example.
- the first resin layer 14 does not include the first filler particles 23, and the first resin layer 14 includes the first filler particles 23. It may be made of only the resin 22.
- the configuration in which the conductive layer 11 includes the metal foil 26 has been described as an example.
- the conductive layer 11 does not include the metal foil 26, and the electroless plating layer 27 and the electroplating are used.
- the layer 28 may be used.
- the metal foil 26 is chemically or mechanically removed, and the electroless plating layer 27 and the electroplating layer. 28 may be formed.
- a resin sheet such as a PET film may be used as a support.
- the configuration in which the metal foil 26 has the protruding portion 30 has been described as an example.
- the metal foil 26 does not have the protruding portion 30 and is composed only of the bonding portion 29. It doesn't matter.
- the configuration in which the evaporation of the solvent 38 and the heating of the powder layer 40 are separately performed in the step (2) has been described as an example, but these may be performed simultaneously.
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Abstract
Description
Claims (9)
- 厚み方向に貫通した貫通孔を有する無機絶縁層と、該無機絶縁層上に配された導電層と、前記貫通孔の内壁に被着しているとともに前記導電層に接続した貫通導体とを備え、
前記無機絶縁層は、一部が互いに接続した複数の無機絶縁粒子および該無機絶縁粒子同士の間隙に配された樹脂部を含む第1部分と、一部が互いに接続した前記複数の無機絶縁粒子および該無機絶縁粒子同士の間隙に配された前記貫通導体の一部からなる導体部を含むとともに前記第1部分と前記貫通導体との間に介在した第2部分とを有することを特徴とする配線基板。 - 請求項1に記載の配線基板において、
前記第1部分および前記第2部分における前記複数の無機絶縁粒子は、一部が互いに接続した複数の第1無機絶縁粒子と、平均粒径が該第1無機絶縁粒子よりも大きく、かつ前記第1無機絶縁粒子を挟んで互いに離れた複数の第2無機絶縁粒子とを含むことを特徴とする配線基板。 - 請求項2に記載の配線基板において、
前記第1無機絶縁粒子の平均粒径は、3nm以上110nm以下であり、
前記第2無機絶縁粒子の平均粒径は、0.5μm以上5μm以下であることを特徴とする配線基板。 - 請求項1に記載の配線基板において、
前記無機絶縁層および前記導電層に接しつつ前記無機絶縁層および前記導電層の間に介在した、前記無機絶縁層よりも厚みの小さい第1樹脂層をさらに備え、
前記無機絶縁層の前記第2部分の前記導電層側の一主面は、前記第1樹脂層から露出しており、
前記貫通孔の前記内壁は、前記第1樹脂層の側面からなる第1領域と、前記無機絶縁層の前記第1樹脂層側から露出した前記一主面からなる第2領域と、前記無機絶縁層の側面からなる第3領域とを含むことを特徴とする配線基板。 - 請求項1に記載の配線基板において、
前記無機絶縁層に接しつつ前記無機絶縁層の前記導電層とは反対側に配された第2樹脂層をさらに備え、
前記無機絶縁層の前記第2部分の前記導電層とは反対側の他主面は、前記第2樹脂層から露出しており、
前記貫通孔の内壁は、前記無機絶縁層の前記第2樹脂層から露出した前記他主面からなる第4領域と、前記第2樹脂層の側面からなる第5領域とを含むことを特徴とする配線基板。 - 請求項4に記載の配線基板において、
前記貫通孔の貫通方向に対する前記第1領域の傾斜角は、前記貫通孔の貫通方向に対する前記第3領域の傾斜角よりも大きいことを特徴とする配線基板。 - 請求項1に記載の配線基板において、
前記絶縁層は、前記無機絶縁層に接しつつ前記無機絶縁層の前記第1樹脂層とは反対側に配された、前記第1樹脂層よりも厚みの大きい第2樹脂層をさらに有しており、
前記第1樹脂層は、第1樹脂および該第1樹脂中に分散した複数の第1フィラー粒子を含み、
前記第2樹脂層は、第2樹脂および該第2樹脂中に分散した複数の第2フィラー粒子を含み、
前記第1樹脂層における前記第1フィラー粒子の含有割合は、前記第2樹脂層における前記第2フィラー粒子の含有割合よりも少ないことを特徴とする配線基板。 - 請求項1に記載の配線基板において、
前記導電層は、前記第1樹脂層に接着した金属箔と、該無金属箔上に配された電気めっき層とを有しており、
前記金属箔は、前記第1樹脂層に接着した接着部と、前記第1樹脂層から前記貫通孔に向かって突出した突出部とを有しており、
前記第2領域と前記突出部との間には、前記貫通導体の一部が配されていることを特徴とする配線基板。 - 請求項1ないし8のいずれかに記載の配線基板と、該配線基板に実装され、前記導電層に電気的に接続された電子部品とを備えたことを特徴とする実装構造体。
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/779,232 US9877387B2 (en) | 2013-03-27 | 2014-03-26 | Wiring board and mounting structure using same |
| KR1020157025021A KR101739401B1 (ko) | 2013-03-27 | 2014-03-26 | 배선 기판 및 이것을 사용한 실장 구조체 |
| CN201480017738.7A CN105191514B (zh) | 2013-03-27 | 2014-03-26 | 布线基板以及使用该布线基板的安装结构体 |
| JP2015508591A JP6099734B2 (ja) | 2013-03-27 | 2014-03-26 | 配線基板およびこれを用いた実装構造体 |
| EP14774851.1A EP2981158B1 (en) | 2013-03-27 | 2014-03-26 | Wiring board and mounting structure using same |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
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| JP2013066115 | 2013-03-27 | ||
| JP2013-066115 | 2013-03-27 | ||
| JP2013092259 | 2013-04-25 | ||
| JP2013-092259 | 2013-04-25 |
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| WO2014157342A1 true WO2014157342A1 (ja) | 2014-10-02 |
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| EP (1) | EP2981158B1 (ja) |
| JP (1) | JP6099734B2 (ja) |
| KR (1) | KR101739401B1 (ja) |
| CN (1) | CN105191514B (ja) |
| WO (1) | WO2014157342A1 (ja) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2015064668A1 (ja) * | 2013-10-29 | 2017-03-09 | 京セラ株式会社 | 配線基板、これを用いた実装構造体および積層シート |
| JP2017212431A (ja) * | 2016-05-23 | 2017-11-30 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | キャパシタ及びこれを含む回路基板 |
| US12010796B2 (en) | 2021-05-28 | 2024-06-11 | Ibiden Co., Ltd. | Wiring substrate and method for manufacturing wiring substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013190748A1 (ja) * | 2012-06-22 | 2013-12-27 | 株式会社ニコン | 基板、撮像ユニットおよび撮像装置 |
| KR101650938B1 (ko) * | 2014-09-25 | 2016-08-24 | 코닝정밀소재 주식회사 | 집적회로 패키지용 기판 |
| DE102015226712B4 (de) * | 2014-12-26 | 2024-10-24 | Omron Corporation | Leiterplatte und elektronisches bauelement |
| WO2016136964A1 (ja) * | 2015-02-27 | 2016-09-01 | 株式会社フジクラ | 配線体、配線基板、配線構造体、及びタッチセンサ |
| JP6333215B2 (ja) * | 2015-05-19 | 2018-05-30 | オムロンオートモーティブエレクトロニクス株式会社 | プリント基板、電子装置 |
| US9706639B2 (en) * | 2015-06-18 | 2017-07-11 | Samsung Electro-Mechanics Co., Ltd. | Circuit board and method of manufacturing the same |
| EP3322267B1 (en) | 2016-11-10 | 2025-02-19 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with adhesion promoting shape of wiring structure |
| MY202414A (en) * | 2018-11-28 | 2024-04-27 | Intel Corp | Embedded reference layers fo semiconductor package substrates |
| CN113474853B (zh) * | 2019-02-27 | 2023-04-04 | 住友电工印刷电路株式会社 | 印刷配线板及印刷配线板的制造方法 |
| KR20230128976A (ko) | 2022-02-28 | 2023-09-05 | 이비덴 가부시키가이샤 | 프린트 배선판 |
| JP2024127498A (ja) * | 2023-03-09 | 2024-09-20 | イビデン株式会社 | 配線基板 |
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| KR101287761B1 (ko) * | 2011-11-10 | 2013-07-18 | 삼성전기주식회사 | 인쇄회로기판 및 그의 제조방법 |
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- 2014-03-26 JP JP2015508591A patent/JP6099734B2/ja active Active
- 2014-03-26 CN CN201480017738.7A patent/CN105191514B/zh not_active Expired - Fee Related
- 2014-03-26 EP EP14774851.1A patent/EP2981158B1/en not_active Not-in-force
- 2014-03-26 KR KR1020157025021A patent/KR101739401B1/ko not_active Expired - Fee Related
- 2014-03-26 US US14/779,232 patent/US9877387B2/en active Active
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| JPH04122087A (ja) | 1990-09-13 | 1992-04-22 | Hitachi Chem Co Ltd | ニッケル薄層付きセラミック複合配線板 |
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| JPWO2015064668A1 (ja) * | 2013-10-29 | 2017-03-09 | 京セラ株式会社 | 配線基板、これを用いた実装構造体および積層シート |
| JP2017212431A (ja) * | 2016-05-23 | 2017-11-30 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | キャパシタ及びこれを含む回路基板 |
| US12010796B2 (en) | 2021-05-28 | 2024-06-11 | Ibiden Co., Ltd. | Wiring substrate and method for manufacturing wiring substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20150119246A (ko) | 2015-10-23 |
| EP2981158A4 (en) | 2017-01-18 |
| US9877387B2 (en) | 2018-01-23 |
| CN105191514A (zh) | 2015-12-23 |
| KR101739401B1 (ko) | 2017-05-24 |
| EP2981158B1 (en) | 2018-09-19 |
| JPWO2014157342A1 (ja) | 2017-02-16 |
| CN105191514B (zh) | 2018-01-23 |
| US20160150642A1 (en) | 2016-05-26 |
| EP2981158A1 (en) | 2016-02-03 |
| JP6099734B2 (ja) | 2017-03-22 |
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