WO2014018273A1

WO2014018273A1 - Method of forming a tapered oxide

Info

Publication number: WO2014018273A1
Application number: PCT/US2013/050046
Authority: WO
Inventors: Vijay Parthasarathy; Sujit Banerjee; Wayne B. Grabowski
Original assignee: Power Integrations Inc
Current assignee: Power Integrations Inc
Priority date: 2012-07-25
Filing date: 2013-07-11
Publication date: 2014-01-30
Anticipated expiration: 2015-01-25
Also published as: JP2015529017A; CN104488084A; CN104488084B; JP6185062B2; KR20150036196A; KR101955321B1

Abstract

Processes for fabricating a tapered field plate dielectric for high-voltage semiconductor devices are disclosed. One example process may include depositing a thin layer of oxide, depositing a polysiricon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device. Another example process may include etching a trench in a semiconductor wafer, depositing an insulating layer on the semiconductor wafer to form a gap within the trench, depositing a masking layer on the insulating layer, and alternating!)' etching the masking layer and the insulating layer to form a tapered field plate dielectric region.

Description

DEPOSIT/ETCH FOR TAPERED OXIDE CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Patent Application Serial No. 13/558,218, filed July 25, 2012, and U.S. Patent Application Serial No. 13/572,492, filed August 10, 2012, the entire disclosures of which are hereby incorporated by reference in their entirety for all purposes as if put forth in full below. BACKGROUND 1. Field

[0002] The present disclosure relates generally to the fabrication of field plate dielectrics for high-voltage semiconductors and, more specifically, the present disclosure relates to the fabrication of tapered field plate dielectrics for high-voltage semiconductor devices. 2. Description of Related Art

[0003] Electronic devices use power to operate. Power is generally delivered through a wall socket as high-voltage alternating current (ac). A device typically referred to as a power converter or power supply can be utilized to transform the high voltage ac input into a well regulated direct current (dc) output through an energy transfer element. One type of power converter is a switch mode power converter, which is commonly used due to its high efficiency, small size, and low weight to power many of today's electronics. Many switch mode power converters that provide electricity to electronics, such as tablet computers, smart phones, and LED lights rely on power semiconductor devices that can handle high-voltages. For example, semiconductor devices in cell phone chargers may be required to handle peak voltages of up to 600 V without breaking down. Some of these high-voltage devices handle high voltages by spreading electric fields over larger areas of semiconductor, which prevents electric fields from exceeding breakdown thresholds. To aid in the spreading of the electrical fields, field plates are sometimes used. [0004] One type of high-voltage transistor is a vertical thin silicon (VTS) high-voltage field effect transistor (HVFET). For example, FIG. 1 depicts an example VTS HVFET 10 built on wafer 11. VTS HVFET 10 includes source regions 15a and 15b, body region 14, and drain regions 12 and 13 (which include a long drain extension) in a silicon pillar. A potential applied to gates 17a and 17b may modulate a channel in body region 14 and control conduction between source regions 15a and 15b and drain regions 12 and 13. The potential of body region 14 may be controlled by body contact 16. HVFET 10 also has field plate 18 separated from the silicon pillar by field plate dielectric 19. Field plate 18 allows for an increase in breakdown voltage by spreading high voltage drops over larger areas in the extended drain region (i.e., spreading out electric fields). DESCRIPTION OF THE FIGURES [0005] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numbers refer to like parts throughout the various views unless otherwise specified. [0006] FIGS. 1-10 illustrate the formation of a tapered oxide by depositing and etching in multiple stages. FIGS. 11-23 illustrate the formation of a tapered oxide by depositing a thick oxide in multiple stages. [0007] FIG. 1 depicts an example HVFET with a field plate. [0008] FIGS. 2A–2C depict the formation of a hardmask according to an example process for forming a tapered field plate dielectric region. [0009] FIGS. 3A and 3B depict the etching of a trench according to the example process for forming the tapered field plate dielectric region. [0010] FIGS. 4A and 4B depict a first cycle of deposition and etching of an insulating layer according to the example process for forming the tapered field plate dielectric region. [0011] FIGS. 5A and 5B depict a second cycle of deposition and etching of an insulating layer according to the example process for forming the tapered field plate dielectric region. [0012] FIGS. 6A and 6B depict a third cycle of deposition and etching of an insulating layer according to the example process for forming the tapered field plate dielectric region. [0013] FIG. 7 depicts a tapered field plate dielectric region ready to receive a conductive material to form an example tapered field plate according the example process. [0014] FIG. 8 depicts a cross-section of another tapered field plate dielectric region with a different profile. [0015] FIG. 9 depicts the conductive material deposited into the tapered region formed by the tapered field plate dielectric region to form the tapered field plate dielectric region. [0016] FIG. 10 depicts a flow chart for an example process for forming a tapered field plate dielectric region. [0017] FIG. 11 depicts another example HVFET structure with a field plate. [0018] FIGS. 12A and 12B depict the formation of a mask for etching a trench for a tapered field plate and field plate dielectric region according to an example process for forming the tapered field plate dielectric region. [0019] FIGS. 13A and 13B depict the etching of a trench according the example process for forming the tapered field plate dielectric region. [0020] FIGS. 14A and 14B depict depositing a first insulating layer and filling a gap in the insulating layer with a mask layer according to the example process for forming the tapered field plate dielectric region. [0021] FIG. 15 depicts etching the mask layer according to the example process for forming the tapered field plate dielectric region. [0022] FIGS. 16A and 16B depict an isotropic etch of the insulating layer according to the example process for forming the tapered field plate dielectric region. [0023] FIGS. 17A and 17B depict a second iteration of etching the mask layer according to the example process for forming the tapered field plate dielectric region. [0024] FIGS. 18A and 18B depict a second iteration of an isotropic etch of the insulating layer according to the example process for forming the tapered field plate dielectric region. [0025] FIGS. 19A and 19B depict a third iteration of etching the mask layer according to the example process for forming the tapered field plate dielectric region. [0026] FIG. 20 depicts a tapered field plate dielectric region after several more iterations of etching the insulating layer and etching the mask layer according to the example process for forming the tapered field plate dielectric region. [0027] FIG. 21 depicts a tapered field plate dielectric region having a less ideal profile. [0028] FIGS. 22A and 22B depict deposition of a conductive material used to form the tapered field plate according to the example process for forming the tapered field plate dielectric region. [0029] FIG. 23 depicts a flow chart for another example process for forming a tapered field plate dielectric. DETAILED DESCRIPTION [0030] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention. [0031] Reference throughout this specification to“one embodiment,”“an embodiment,” “one example,” or“an example” means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases“in one

embodiment,”“in an embodiment,”“one example,” or“an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. Particular features, structures, or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it should be appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale. [0032] As discussed above, FIG. 1 depicts field plate 18 with field plate dielectric 19 that is substantially the same thickness along the depth of field plate 18. To develop a reliable device optimally, it may be suitable to maintain a constant electric field along extended drain region 13. In order to maintain a constant electric field pillar, a graded doping profile for the extended drain region 13 may be necessary. In particular, the graded doping of drain region 13 may be gradually reduced along the depth as the surface of VTS device 10 is approached. In this manner, VTS device 10 is able to deplete between the extended drain region 13 and oxide 19 such that VTS device 10 is capable of supporting the maximum breakdown voltage. However, one disadvantage of having a graded doping profile may be having lighter doping closer to the surface of VTS device 10 that may cause a higher specific resistance and reduced efficiency. [0033] As shown in the figures and described below, the field plate dielectric thickness is varied along the depth of the device. In particular, the oxide thickness is minimal at the surface and increases along the depth of the device 10 until it approaches the bottom which allows for increased doping of extended drain region 13 near the surface of VTS device 10. As a result, the specific resistance of VTS device10 may be reduced by a factor of up to 3 to 4 times. In one example, specific on resistance may be defined as the resistance that is inherent, based on material and design of the semiconductor, when there is substantially zero volts between the drain and source of VTS device 10. It may be appreciated that to improve efficiency of the semiconductor device, the specific resistance may be reduced to reduce power dissipation when the device is conducting. In one example, a varying thickness of the field plate dielectric could be accomplished by tapering. In this manner, a constant distribution of doping may be accomplished. [0034] An example process for forming a tapered field plate dielectric in a semiconductor substrate is described below. This example process may be useful with processes that form a variety of types of devices, such as Schottky diodes, HVFETs, JFET, IGBT, bipolar transistors and the like. The tapered field plate dielectric fabrication is described with respect to figures depicting various stages of the example process. For ease of discussion, the example process is described with respect to the fabrication of one field plate dielectric region. However, it should be understood that only a portion of the substrate is depicted in the figures. In practice, many devices (e.g., HVFETs) with field plates having tapered field plate dielectric regions may be formed in parallel across the substrate. [0035] FIG. 2A depicts substrate 200, which includes wafer 202, protective layer 204, and mask layer 206. Wafer 202 may be made of a variety of materials, such as, for example, silicon, silicon carbide, diamond, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and the like. Wafer 202 may also be made of multiple different materials to form a hetero structure. Wafer 202 may also be formed of a base wafer (e.g., a silicon wafer) with other layers (e.g., epitaxilally grown layers) grown on top of the base wafer. In one example, wafer 202 may be a thickness of 700 -1000 μm. [0036] As shown, protective layer 204 is deposited on the surface of wafer 202 to protect the surface of wafer 202 from defects and damage during processing. Protective layer 204 and mask layer 206 may be optional in some variations of the example process. In a simpler process, the tapered oxide can be formed without mask layer 206 and the silicon pillar itself may be used as the hard mask for the oxide. In variations of the example process that use a silicon wafer for wafer 202, protective layer 204 may be, for example, thermally grown oxide with a thickness of about 200 A. [0037] Mask layer 206 may be a hard mask (e.g., polysilicon, nitride, and the like). Mask layer 206 may be selected to have different etching properties as the insulating material that will be used to form the field plate dielectric. By choosing mask layer 206 to have different etching properties than the field plate dielectric, an etch with a high selectivity to the field plate dielectric material over mask layer 206 may be used, which allows for mask layer 206 to be used throughout the formation of the tapered field plate dielectric. For example, poly silicon may be used for mask layer 206. If the field plate dielectric material will be oxide, then it should be possible to select an etch recipe that has an etch selectivity of oxide to silicon of 10:1 or 20:1. In one example, mask layer 206 may be about 2–5 μm thick, although other thicknesses may be possible depending on the selectivity of the etch recipe used for etching the field plate dielectric material. [0038] FIG. 2B depicts substrate 200 after mask layer 208 has been deposited and patterned to define the location of the trench and field plate dielectric adjacent the silicon pillar where the semiconductor device will be located (these pillars will roughly be under the remaining portions of mask layer 208). Mask layer 208 is a photo resist mask. In another example, protective layer 204 and mask layer may not be used and photoresist layer may be deposited directly on surface of silicon wafer 202. [0039] FIG. 2C depicts substrate 200 after mask layer 206 and protective layer 204 have been etched to expose the surface of wafer 202 in the region where the trench will be etched, as defined by mask layer 208. In one example, the exposed portion of waver 202 is d_EXPOSED and may be about 10–12 μm wide. [0040] FIG. 3A depicts substrate 200 after a trench 302 has been formed. In one example, a deep reactive ion etch (DRIE) step is used, which results in the formation of scallops 304 on the sidewalls 306 of trench 302. Trench 302 may be etched to depth 308, which, in one example, may be about 60 μm deep. It should be appreciated that other etch techniques to etch trench 302 may be used that do not form scallops. [0041] FIG. 3B depicts substrate 200 after mask layer 208 has been removed. Removing mask layer 208 may be accomplished with various steps. For example, if mask layer 208 is a photoresist mask, then a plasma ashing step may be used. In another example, if nitride or oxide are used, a phosphoric acid or hydrofluoric acid, respectively, etch step may be used. FIG. 4A depicts substrate 200 after insulating layer 402 is deposited. As stated above, a field plate dielectric comprises one or more insulating layers 402. The process for depositing insulating layer 402 may be conformal so that approximately a thickness of d_DEP1 of insulating material is present on exposed surfaces which are both vertical (e.g., sidewalls 306) and horizontal surfaces (e.g., the bottom of trench 302 and on top of mask layer 206).

Insulating layer 402 may be silicon dioxide, silicon nitride, boron phosphide silicate glass, and the like. Processes, such as low pressure chemical vapor deposition, high density plasma, plasma enhanced chemical vapor deposition, and the like, may be used to deposit insulating layer 402. The thickness d_DEP1 may be determined in response to temperature, time, and light in processes. In another example d_DEP1 is approximately 0.5 μm. [0042] FIG. 4B depicts substrate 200 after etching a thickness, d_ETCH1of insulating layer 402 with a highly anisotropic etch. In other words, horizontal surfaces of the substrate are etched substantially more than vertical surfaces. For example, the etch ratio of vertical to horizontal, which may also be known as directionality of the etch, can be 100 to 1. In one example, d_ETCH1 may be a distance of 4μm in the vertical direction. The etch recipe used for etching insulating layer 402 may be selected such that the etch rate of insulating layer 402 is much higher than the etch rate of mask layer 206 or wafer 202. If the selectively of the etch recipe is high enough, the same mask layer 206 may be used throughout the process of forming the tapered field plate dielectric. Additionally, if the same material is used for semiconductor wafer 202 and mask layer 206 (e.g., a silicon wafer and a poly silicon mask), then the etch recipe for etching insulating layer 402 may have a similar selectivity for the material of insulating layer 402 over both the exposed portions of semiconductor wafer 202 at the bottom of trench 302 and mask layer 206 at the surface of semiconductor wafer 202. For example, a selectivity of at least 10:1 or even 20:1 may be used. [0043] As shown in FIG. 4B, d_ETCH1 may be greater than d_DEP1 such that the portions of insulating layer 402 on horizontal surfaces (e.g. top surface of mask layer 202 and bottom portion of trench 302) will be completely removed. However, the portions of insulating layer 402 on vertical surfaces will be etched down by approximately d_ETCH1 or in some cases, an amount less than d_ETCH1, as depicted on sidewalls 306 of trench 302. In other words, only an upper portion, which is proportional in depth to d_ETCH1, of insulating layer 402 on vertical surfaces is removed (e.g., the portion of insulating layer 402 on the sidewalls 306 in trench 302). [0044] Note that scallops 304 do not appear in FIG. 4A. The scallops may be removed from the sidewalls of trench 302 prior to the deposition of insulating layer 402. For example, if wafer 202 is silicon, then a thermal oxidation step may be used to consume the scallops and an oxide removal step may be used to remove the thermal oxide leaving a smoother sidewall. Alternatively, in variations of the example process, the scallops may remain. In other variations of the example process, the scallops may not be present due to the trench etch technique used or the scallops may be small enough that the scallops are not readily apparent or of concern. [0045] FIG. 5A depicts substrate 200 after insulating layer 502 has been deposited on substrate 202. Insulating layer 502 may be deposited on top of insulating layer 402 on sidewalls 306 of trench 302 where insulating layer 402 had not been previously removed. The process for depositing insulating layer 502 may be conformal so that approximately a thickness of d_DEP2 of insulating material 502 is deposited on both vertical and horizontal surfaces. Insulating layer 502 may be the same material deposited with the same technique to the same thickness as insulating layer 402. In one alternative, as compared to insulating layer 402, insulating layer 502 may be a different material, deposited with a different technique, or have a different thickness. Portions of sidewalls 306 that did not have insulating layer 402 removed may now have approximately a total thickness of d_DEP1 + d_DEP2 of insulating material. However, portions of wafer 202 that are exposed at the bottom of trench 302 have a thickness of only approximately d_DEP2 of insulating material. In one example, thickness d_DEP1 of insulating layer 402 is substantially the same as thickness d_DEP2 of insulating layer 502. In another example, thickness d_DEP1 and d_DEP2 of insulating layers 402 and 502 are different. [0046] FIG. 5B depicts substrate 200 after etching a thickness, d_ETCH2, of insulating layer 502 and some of insulating layer 402 with an anisotropic etch (e.g., the same etch used to etch insulating layer 402 as discussed with respect to FIG. 4B). In particular, an upper portion of insulating layer 502 on the sidewall of mask 206 and on the sidewall of trench 302 (on insulating layer 402) has been etched. There is now a pillar of insulating layer 502 on a pillar of insulating layer 402. [0047] FIG. 6A depicts substrate 200 after insulating layer 602 has been deposited on substrate 202. The process for depositing insulating layer 602 may be conformal so that approximately a thickness of d_DEP3 of insulating material 602 is deposited on both vertical and horizontal surfaces. Insulating layer 602 may be the same material deposited with the same technique to the same thickness as insulating layer 402 or insulating layer 502. In one alternative, as compared to the insulating layer 402 or insulating layer 502, insulating layer 602 may be a different material, deposited with a different technique, or have a different thickness. Portions of sidewalls 306 that did not have insulating layers 402 and 502 removed may now have approximately a total thickness of d_DEP1 + d_DEP2 + d_DEP3 of insulating material. However, portions of wafer 202 that are exposed at the bottom of trench 302 have a thickness of only approximately d_DEP3 of insulating material. As shown, a first region 609 includes only portions of insulating layer 602 and the insulating material is a thickness of d_DEP3. A second region 611 includes portions of insulating layer 402 and 602 and the total thickness of insulating material along sidewalls 306 in region 611 is d_DEP1 + d_DEP3. A third region 613 includes portions of insulating layer 402, 502, and 602 and the total thickness of insulating material along sidewalls 306 in region 613 is equal to d_DEP1 + d_DEP2 +d_DEP3. [0048] FIG. 6B depicts substrate 200 after etching a thickness d_ETCH3 of insulating layer 602 (and some of insulating layer 402 and insulating layer 502) with an anisotropic etch (e.g., the same etch used to etch insulating layer 402 as discussed with respect to FIG. 4B). There is now a pillar of insulating layer 602 on a pillar of insulating layer 502, which is on a pillar of insulating layer 402. As shown, a first region 615 contains only insulating layer 402 and the insulating material in first region 615 is a thickness of d_DEP1. A second region 617 includes portions of insulating layer 402 and 502 along sidewalls 306 and the total thickness of insulating material in region 617 is d_DEP1 + d_DEP2. A third region 619 includes portions of insulating layers 402, 502, and 602, and the total thickness of insulating material along sidewalls 306 in region 619 is equal to d_DEP1 + d_DEP2 +d_DEP3. [0049] The process of depositing and etching dielectric, as depicted in and described with respect to any one the figure sets of FIGS. 4A–4B, FIGS. 5A–5B, and FIGS. 6A–6B, may be repeated as many time as necessary to fill trench 302. For example, as depicted in FIG. 7, nine cycles of depositing and etching were used to fill the trench depicted in FIG. 7. Specifically, the nine cycles are associated with insulating layer 402, 502, and 602 described above and six additional cycles that produce insulating layers 701-706. In cases where the deposit thicknesses are all approximately the same (e.g., d_DEP1=d_DEP2=d_DEP3=d_DEPX) and the etch amounts are all approximately the same (e.g., d_ETCH1=d_ETCH2=d_ETCH3=d_ETCHX), the slope, m_OX, of the tapered field plate dielectric region may be approximated by d_ETCHX/d_DEPX. [0050] In other variations of the example process, the profile of the tapered field plate dielectric region may be different. For example, by using different thicknesses of insulating layers and etching different amounts of the insulating layers, the profile of the tapered field plate dielectric region may be controlled. In one instance, the profile of the tapered field plate dielectric region will have multiple different slopes along the profile of the tapered field plate dielectric region. [0051] The tapered field plate dielectric region has been depicted to have well-defined steps, with one step representing each deposition/etch cycle. However, in practice, it should be understood that the well-defined steps may not be present. For example, the profile of the tapered field plate dielectric region may have a more linear shape. FIG.8 depicts substrate 800 that has another example of a profile for a tapered field plate dielectric that is not as ideal as the profile shown in FIG. 7. [0052] FIG. 9 depicts substrate 200 after deposition of conductive material 902 which fills the rest of trench 302 (not labeled) that was not filled by tapered field plate dielectric region 710. Conductive material 902 may be any number of materials, such as amorphous silicon, polycrystalline silicon, metal, and the like. If using a semiconductor for conductive material 902, then conductive material 902 may be in-situ doped as it is being deposited. The top of conductive material 902 may be then be planarized using a chemical mechanical polishing (CMP) or etch-back step. Electrical contact may then be made to the remaining portion of conductive material 902, which forms the tapered field plate. [0053] Once the tapered field plate dielectric and tapered field plate have been formed, semiconductor device fabrication flows may be performed to form active devices in active regions of substrate 200 (e.g., pillars of silicon 904 and 906). For example, a VTS HVFET process may be used to form HVFETs in silicon pillars 904 and 906. [0054] FIG. 10 depicts a flow chart for example process 1000 (similar to the example process described above with respect to Figs. 2–9) for forming a tapered field plate dielectric region in a semiconductor substrate. In step 1002, a silicon wafer is obtained. The silicon wafer may have different layers of doping created with, for example, epitaxially grown layers of silicon. In step 1004, a thin layer of oxide is grown on the surface of the silicon wafer to form a protective layer that protects the surface of the silicon wafer from processing damage and debris. In step 1006, a polysilicon hardmask is deposited (e.g., see FIG. 2A). The polysilicon hardmask may be used throughout the formation of the tapered field plate dielectric region that surrounds the tapered field plate. Polysilicon may be preferred for the hardmask because etch recipes may be readily available that provide high selectivity to etching oxide (or other insulating materials) over polysilicon. In step 1008, the hardmask is then patterned and etched using a photolithography step (e.g., see FIGS. 2B and 2C). The hardmask now defines the area where the trench for the sloped field plate will be etched. In step 1010, a DRIE (or Bosch etch) step is performed to define the trench for the sloped field plate (e.g., see FIG. 3A). In some variations of example process 1000, steps 1008 and 1010 may be combined into one step. In step 1012, any photoresist that is left from steps 1008 or 1010 is removed with a plasma ashing step (e.g., see FIG. 3B). In step 1014, a layer of oxide is deposited over vertical and horizontal surfaces of the substrate, including the sidewalls and bottom of the trench formed in step 1010 (e.g., see FIGS. 4A, 5A, and 6A). In step 1016, an anisotropic etch is performed to remove a certain thickness of the oxide deposited in step 1014 (e.g., see FIGS. 4B, 5B, and 6B). Because the etch is anisotropic (i.e., substantially anisotropic), the oxide on horizontal surfaces of the wafer is completely removed while only the upper most portion of the oxide on vertical sides is removed. Accordingly, most of the oxide deposited on the sidewalls of the trench (e.g. all the oxide on the sidewalls except for the upper most portion) will remain. In step 1018, it is determined whether the trench is sufficiently filled with oxide to receive the material that forms the tapered field plate (e.g., see FIG. 7). For example, this may be determined based on the number of oxide dep/etch cycles that have been performed. As another example, cycles of steps 1014 and 1016 may be repeated until a threshold thickness of oxide remains in the center bottom of the trench after the oxide etch step 1016. In step 1020, once the tapered field plate dielectric has been formed in the trench, polysilicon is deposited in the trench to form the tapered field plate (e.g., see FIG. 9). A planarization step may be needed to ensure that the field plate and the surface of the wafer are coplanar. In step 1022 a semiconductor process flow is performed to form a HVFET in the silicon pillar adjacent the trench that contains the sloped field plate. [0055] While example process 1000 has been described with respect to specific materials and layers, it should be understood that some layers may be optional and the materials of the wafer and layers may vary. [0056] FIG. 11 depicts an example VTS HVFET 1100 built on wafer (N+ substrate) 1110. VTS HVFET 1100 includes source regions 1150 (N+), body region 1140 (P Body), and 1130 (N extended drain region), which include a long drain extension in a silicon pillar. A potential applied to gates 1170 may modulate a channel in body region 1140 and control conduction between source regions 1150 and drain regions. HVFET 1100 also has field plate 1180 separated from the silicon pillar by field plate dielectric 1190 (Ox). Field plate 1180 allows for an increase in breakdown voltage by spreading high voltage drops over larger areas in the extended drain region (i.e., spreading out electric fields). [0057] Field plate dielectric 1190 is substantially the same thickness along the depth of field plate 1180. To develop a reliable device optimally, it may be suitable to maintain a constant electric field along extended drain region 1130. In order to maintain a constant electric field, a graded doping profile for the extended drain region 1130 may be necessary. In particular, the graded doping of drain region 1130 may be gradually reduced along the depth as the surface of VTS device 1100 is approached. In this manner, VTS device 1100 is able to deplete between the extended drain region 1130 and oxide 1190 such that VTS device 1100 is capable of supporting the maximum breakdown voltage. However, one disadvantage of having a graded doping profile may be having lighter doping closer to the surface of VTS device 1100 that may cause a higher specific resistance and reduced efficiency. [0058] FIG. 12A depicts substrate 1200, which includes wafer 1202. Wafer 1202 may be made of a variety of materials, such as, for example, silicon, silicon carbide, diamond, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and the like. Wafer 1202 may also be made of multiple different materials to form a hetero structure.

Wafer 1202 may also be formed of a base wafer (e.g., a silicon wafer) with other layers (e.g., epitaxially grown layers) grown on top of the silicon wafer. [0059] FIG. 12B depicts substrate 1200 after mask layer 1204 has been deposited and patterned to define the location of the trench and field plate dielectric adjacent the silicon pillar where the semiconductor device will be located ,which is roughly under the remaining portions of mask layer 1204. Mask layer 1204 may be a hardmask or a softmask. In one example, a soft mask may be a photoresist layer. In some variations of the example process, a protective layer may be deposited on the surface of wafer 1202 prior to deposition and patterning of mask layer 1204. The protective layer may protect the surface of wafer 1202 from defects and damage during processing. If the example process does not use a protective layer (as depicted in FIG. 12B), a restoration step may be used to remove damage or clean defects from the surface of wafer 1202 prior to performing other processing that involves the surface of wafer 1202. For example, if a silicon wafer is used for wafer 1202, a protective layer (not shown) may be, for example, a thermally grown oxide with a thickness of about 200 A. In one example, mask layer 1204 segment may have a length d_MSEG of 1-3 μm. [0060] FIG. 13A depicts substrate 1200 after trench 1302 has been formed. In one example, a deep reactive ion etch (DRIE) step is used, which results in the formation of scallops 1304 on the sidewalls 1306 of trench 1302. Trench 1302 may be etched to depth d_ETCH 1308, which, in one example, may be about 60 μm deep. It should be understood that other etch techniques could also be used that do not form scallops. [0061] FIG. 13B depicts substrate 1200 after mask layer 1204 has been removed.

Removing mask layer 1204 may be accomplished with various steps. For example, if mask layer 1204 is a photoresist mask, then a plasma ashing step may be used. In another example, if nitride or oxide are used for mask layer 1204, then a phosphoric acid or hydrofluoric acid, respectively, etch step may be used. [0062] FIG. 14A depicts substrate 1200 after insulating layer 1402 is deposited. The process for depositing insulating layer 1402 may be conformal so that approximately a thickness of d₁ of insulating material is present on vertical sidewalls 1306, the bottom of trench 1302, and on top of silicon pillars 1407. Insulating layer 1402 will also form gap 1404. Insulating layer 1402 may include silicon dioxide, silicon nitride, boron phosphide silicate glass, and the like. Processes, such as low pressure chemical vapor deposition, high density plasma, plasma enhanced chemical vapor deposition, and the like, may be used to deposit insulating layer 1402. In one example, d₁ may be between 0.5 μm and 10 μm and gap 1404 may be approximately 10 μm across. [0063] Note that scallops 1304 do not appear in FIG. 14A. The scallops may be removed from the sidewalls 1306 of trench 1302 prior to deposition of insulating layer 1402. For example, if wafer 1202 is silicon, then a thermal oxidation step may be used to consume the scallops and an oxide removal step may be used to remove the thermal oxide leaving a smoother sidewall. Alternatively, in variations of the example process, the scallops may remain. In other variations of the example process, the scallops may not be present due to the trench etch technique used or the scallops may be small enough that the scallops are not readily apparent or of concern. [0064] FIG. 14B depicts substrate 1200 after a fill mask layer 1406 has been deposited on substrate 1200. The thickness d₂ of fill mask layer 1406 may be selected to ensure that gap 1404 is completely filled. In other variations of the example process, mask layer 1406 may not completely fill in gap 1404. In particular, due to possible loafing of insulating layer 1402 and fill mask layer 1406, gap 1404 may be pinched off, leaving a portion of gap 1404 unfilled (not shown). In one example, material of fill mask layer 1406 should have different etch properties as compared to the material of insulating layer 1402 so that an etch recipe is available that is highly selective to etching the material of insulating layer 1402 over the material of fill mask layer 1406. For example, if insulating layer 1402 is oxide, then mask layer 1406 may be polysilicon. [0065] FIG. 15 depicts substrate 1200 after mask layer 1406 has gone through a planarized etch to remove fill mask layer 1406 from the top surface of insulating layer 1402 and from a portion of sidewalls of insulating layer 1402 to recreate a portion of gap 1404 (represented by region 1502). In one example, FIG. 15 depicts a starting point of substrate 1200 before proceeding with alternating cycles of etching insulating layer 1402 and etching fill mask 1406 to create a tapered field dielectric region. [0066] FIGS. 16A and 16B depict substrate 1200 before and after an amount, e_1, of insulating layer 1402 is isotropically etched, which means that approximately the same amount of material is etched regardless of the slope of the surface where the etching is taking place. In other words, the amount of insulating layer 1402 that is etched from horizontal surfaces is approximately the same as the amount of insulating layer 1402 that is etched from vertical surfaces. The isotropic nature of the etch is illustrated by line 1602 that approximates the amount of insulating layer 1402 that is removed from FIG. 16A to FIG. 16B during the etch. As can be seen from line 1602, the thickness e₁ of insulating material removed is approximately constant across the surface of insulating layer 1402. If the etch for insulating layer 1402 is selected properly, such that the etch may be selected to have a high selectivity to insulating layer 1402 over fill mask layer 1406, very little of mask layer 1406 should be etched. For example, if insulating layer 1402 is oxide and fill mask layer 1406 is polysilicon, then an etch step in aqueous hydrofluoric acid may be used to perform this isotropic etch. Note that because the sidewalls of insulating layer 1402 adjacent to region 1502 were exposed, the width of region 1502 grew by approximately 2 × e₁. [0067] FIGS. 17A and 17B depict substrate 1200 before and after etching a thickness e₂ of fill mask layer 1406. By etching fill mask layer 1406, a region 1702 defined by the newly exposed sidewalls of insulating material 1402 is formed below region 1502. Region 1702 is narrower than region 1502 and has roughly the same width as region 1502 had when it was first formed (see FIG. 15) since the initial width of region 1702 and region 1502 are both determined by the width of gap 1404 (FIG. 14A). [0068] FIGS. 18A and 18B depict substrate 1200 before and after a thickness e₃ of insulating layer 1402 is isotropically etched, which allows for approximately the same amount of material to be etched regardless of the slope of the surface where the etching is taking place. In other words, the amount of insulating layer 1402 that is etched from horizontal surfaces is approximately the same as the amount of insulating layer 1402 that is etched from vertical surfaces. The isotropic nature of the etch is illustrated by line 1802 that approximates the amount of insulating layer 1402 that is removed from FIG. 18A to FIG. 18B during the etch. As can be seen from line 1802, the amount of insulating material removed is approximately constant across the surface of insulating layer 1402. If the etch for insulating layer 1402 is selected properly, very little of mask layer 1406 should be etched (e.g., the same etch discussed with respect to FIGS. 16A and 16B). Note that because the sidewalls of insulating layer 1402 adjacent regions 1502 and 1702 were exposed, the width of region 1502 grew by approximately 2 * e₃ more (or 2 * e₃ + 2 * e₁ total from the initial width of region 1502), and the width of region 1702 grew by approximately 2 * e₃ (or 2 * e₃ total from the initial width of region 1702). Put another way, there is a thickness e₃ less insulation layer 1402 between the interior sidewall of insulation layer 1402 and the sidewall 1306. [0069] FIGS. 19A and 19B depict substrate 1200 before and after etching a thickness e₄ of fill mask layer 1406. By etching fill mask layer 1406, region 1902 defined by the newly exposed sidewalls of insulating material 1402 is formed below regions 1502 and 1702.

Region 1902 is narrower than region 1702 and has roughly the same width as regions 1502 and 1702 had when first formed (see FIG. 15 and FIG. 17, respectively) because the initial width of regions 1902, 1702, and 1502 are all determined by the width of gap 1404 (FIG. 14A). [0070] Iterations of etching insulating layer 1402 and mask layer 1406 may continue until the desired taper of insulating layer 1402 has been achieved. For example, the process of alternating the two etches (insulating layer and fill mask layer) may continue for some fixed number of iterations known to produce the desired taper. As another example, the process of alternating the two etches may continue until mask layer 1406 is gone or has a thickness below some threshold. Each iteration of alternating etches widens the existing regions (e.g., regions 1502, 1702, and 1902) by some amount and forms a new region of a width approximately the width of gap 1404 (FIG. 14A). Accordingly, by adding iterations, the taper at the top of trench 1302 (FIG. 13A) widens and a new“step” is added deeper in trench 1302. [0071] FIG. 20 depicts substrate 1200 after six total iterations of etching mask layer 1406 and insulating layer 1402. If all etches of insulating layer 1402 remove approximately the same amount of insulating layer 1402 (i.e., e₁=e₃=e_2x-1, where x is the number of etch iterations) and all etches of mask layer 1406 remove approximately the same amount of mask layer 1406 (i.e., e₂=e₄=e_2x), where x is the number of etch iterations) then the slope, m_TAPER, of the taper of insulation layer 1402 may be about e₁/e₂. [0072] In other variations of the example process, the profile of insulating layer 1402 may be different. For example, by etching different amounts of insulating layer 1402 and mask layer 1406 in different iterations, the profile of the insulating region may be controlled. In one instance, the profile of insulating layer 1402 will have multiple different slopes along the exposed sidewall of insulating layer 1402. [0073] The insulating material has been depicted to have well-defined steps, with one step representing each deposition/etch cycle. However, in practice, it should be understood that the well-defined steps may not be present. For example, the profile of the insulating region may have a more linear shape. FIG. 21 depicts substrate 2100 that has another example of a profile for a tapered field plate dielectric that is not as ideal as the profile shown in FIG. 20. [0074] FIG. 22A depicts substrate 1200 after all iterations of the alternating etch steps have been completed and any remaining portion of fill mask layer 1406 has been removed. It should be understood that in variations of the example process, all of fill mask layer 1406 may be etched during the iterations of the alternative etch steps. Other variations of the example process may also leave any remaining portions of fill mask layer 1406 to be part of the field plate that is formed after deposition of a conductive material in the trench formed by the taper in insulating layer 1402 (see FIG. 22B). [0075] FIG. 22B depicts substrate 1200 after deposition of conductive material 2202 which fills the rest of trench 1302 (not labeled) that was not filled by insulating layer 1402 or was etched during the formation of the taper. Conductive material 2202 may be any number of materials, such as amorphous silicon, polycrystalline silicon, metal, and the like. If using a semiconductor for conductive material 2202, then conductive material 2202 may be in-situ doped as it is being deposited. The top of conductive material 2202 may be then be planarized using a chemical mechanical polishing (CMP) or etch-back step. Electrical contact may then be made to the remaining portion of conductive material 2202, which forms the tapered field plate. Once the field plate is formed, insulating layer 1402 becomes tapered field plate dielectric region 2204. [0076] Once tapered field plate dielectric 2204 is formed, and the surface of wafer 1202 has been planarized (if required), semiconductor device fabrication flows may be performed to form active devices in active regions of substrate 1200 (e.g., pillars of silicon 2206 and 2208). For example, a VTS HVFET process may be used to form HVFETs in silicon pillars 2206 and 2208. [0077] FIG. 23 depicts a flow chart for example process 2300 (similar to the example process described above with respect to FIGS.12-22, for forming a tapered field plate dielectric region in a semiconductor process. In step 2302, a silicon wafer is obtained. The silicon wafer may have different layers of doping created with, for example, epitaxially grown layers of silicon (e.g., see FIG. 12A). In step 2304, a photoresist mask is patterned (e.g., see FIG. 12B). The photoresist mask defines the location and size of the trench that contains the tapered field plate and tapered field plate dielectric region. In step 2306, a DRIE (or Bosch etch) step is performed to define the trench for the tapered field plate (e.g., see FIG. 13A) and any remaining photoresist is striped (e.g. see FIG. 13B). In step 2308, a layer of oxide is deposited over vertical and horizontal surfaces of the substrate (e.g., see FIG. 14A). The deposited oxide fills a substantial portion of the trench but leaves a gap in the middle of the trench open. In step 2310, a poly silicon masking layer is deposited over the wafer and in the gap formed by the oxide deposition of step 2308 (e.g., see FIG. 14B). In step 2312, an etch of the polysilicon mask is performed to expose a portion of the sidewalls of the oxide layer in the gap (e.g., see FIG. 15). In step 2314, an isotropic oxide etch is performed to remove a certain thickness of the oxide deposited in step 2308 (e.g., see FIGS. 16A and 18A). Because the etch is isotropic (i.e., substantially isotropic), all exposed surfaces of the oxide layer should be etched by approximately the same amount. In step 2316, the polysilicon mask is etched by a further amount to expose a new portion of the sidewall of the oxide layer from step 2308 in the gap (e.g., see FIGS. 17B and 19B). In step 2318, it is determined whether the taper of the oxide layer has been completed (e.g., see FIG. 20). For example, this may be determined based on the number of oxide etch/poly etch iterations that have been performed. As another example, iterations of steps 2314 and 2316 may be repeated until a threshold thickness of poly (or no poly) remains. In step 2320, once the tapered field plate dielectric has been formed in the trench, polysilicon is deposited in the trench to form the tapered field plate (e.g., see FIG. 22B). A planarization step may be needed to ensure that the field plate and the surface of the wafer are coplanar. In step 2322 a MOSFET process flow is performed to form a HVFET in the silicon pillar adjacent the trench that contains the sloped field plate. [0078] While example process 2300 has been described with respect to specific materials and layers, it should be understood that some layers may be optional and the materials of the wafer and layers may vary. [0079] The above description of illustrated examples of the present invention, including what is described in the Abstract, are not intended to be exhaustive or to be a limitation to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is appreciated that the specific example voltages, currents, frequencies, power range values, times, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings of the present invention. [0080] These modifications can be made to examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. The present specification and figures are accordingly to be regarded as illustrative rather than restrictive.

Claims

CLAIMS What is claimed is: 1. A method of forming a tapered field plate dielectric region in a semiconductor wafer, the method comprising:

etching a trench in the semiconductor wafer, wherein the trench has a sidewall;

depositing a first thickness of a first insulating layer on the semiconductor wafer, including the sidewall;

etching a first amount of the first insulating layer, wherein a first upper portion of the first insulating layer adjacent to the top of the trench is removed;

depositing a second thickness of a second insulating layer on the semiconductor wafer, wherein the second insulating layer overlaps a portion of the first insulating layer, and wherein the second insulating layer overlaps the first upper portion; and

etching a second amount of the second insulating layer, wherein a second upper portion of the second insulating layer on the sidewall of the trench is removed.

2. The method of claim 1, wherein etching the second amount of the second insulating layer exposes at least part of the first insulating layer adjacent the second upper portion.

3. The method of claim 1, further comprising:

depositing a third thickness of a third insulating layer on the semiconductor wafer; and etching a third amount of the third insulating layer, wherein a third upper portion of the third insulating layer on the sidewall of the trench is removed.

4. The method of claim 3, wherein etching the third amount of the third insulating layer exposes at least part of the first insulating layer adjacent the third upper portion and at least part of the second insulating layer adjacent the third upper portion.

5. The method of claim 1, wherein the first and second thicknesses are approximately the same.

6. The method of claim 5, wherein the first and second insulating layers are the same materials.

7. The method of claim 1, wherein the first thickness is substantially independent of the slope of the surface that the first insulating layer is being deposited on.

8. The method of claim 1 further comprising:

prior to etching the trench, patterning a hardmask that defines the location of the trench, wherein patterning the hardmask includes depositing a hardmask material.

9. The method of claim 8, wherein the hardmask is made of polysilicon.

10. The method of claim 9 further comprising:

prior to depositing the hardmask, depositing a protection layer on the surface of the semiconductor wafer.

11. The method of claim 10, wherein the protection layer is an oxide.

12. The method of claim 1 further comprising:

depositing a conductive material on the first insulating layer and the second insulating layer in the trench, wherein the conductive material is separated from direct contact with the sidewall of the trench by the first insulating layer and the second insulating layer.

13. The method of claim 1, wherein etching the first insulating layer and etching the second insulating layer are done with an anisotropic etch.

14. A method of forming a tapered field plate dielectric region in a semiconductor wafer, the method comprising:

etching a trench in the semiconductor wafer;

depositing an insulating layer on the semiconductor wafer, including on sidewalls of the trench, wherein the insulating layer forms a gap in the trench open to the top of the trench; depositing a masking layer on the insulating layer, wherein the masking layer fills at least a portion of the gap;

etching a first amount of the masking layer to expose a first sidewall portion of the insulating layer in the gap;

etching a second amount of the insulating layer, including the first sidewall portion of the insulating layer;

etching a third amount of the masking layer to expose a second sidewall portion of the insulating layer in the gap, wherein the second sidewall portion is deeper in the trench than the first sidewall portion; and

etching a fourth amount of the insulating layer, including the first sidewall portion and the second sidewall portion of the insulating layer.

15. The method of claim 14, wherein etching the first amount and etching the third amount are done in a solution including a hydrofluoric acid.

16. The method of claim 14 further comprising:

depositing a conductive material in the trench on the insulating layer; and

removing a portion of the conductive material outside of the trench.

17. The method of claim 16, wherein removing the portion of the conductive material outside of the trench includes performing a chemical mechanical polishing step.

18. The method of claim 14 further comprising:

etching a fifth amount of the masking layer to expose a third sidewall portion of the insulating layer in the gap, wherein the third sidewall portion is deeper in the trench than the first sidewall portion and the second sidewall portion; and

etching a sixth amount of the insulating layer, including the first sidewall portion, the second sidewall portion, and the third sidewall portion of the insulating layer.

19. The method of claim 14, wherein the masking layer comprises silicon.

20. The method of claim 14, wherein the insulating layer comprises oxide.

21. The method of claim 14 further comprising:

forming an active semiconductor device in the semiconductor wafer adjacent the trench.

22. The method of claim 14, wherein the first amount and the second amount are

approximately equal.

23. The method of claim 14, wherein the second amount and the fourth amount are approximately equal.

24. The method of claim 23, wherein the first amount and the second amount are

approximately equal.

25. A method of forming a tapered field plate dielectric region in a semiconductor wafer, the method comprising:

etching the semiconductor wafer to form a trench therein;

depositing an insulating layer on the semiconductor wafer, wherein after depositing, a gap is formed in the insulating layer within the trench;

depositing a masking layer on the insulating layer, wherein the masking layer fills at least a portion of the gap; and

alternatingly etching portions of the masking layer and the insulating layer within the gap to form a tapered insulating layer within the trench.

26. The method of claim 25, wherein etching of the masking layer is performed using a solution comprising a hydrofluoric acid.

27. The method of claim 25 further comprising:

depositing a conductive material in the trench on the insulating layer; and

removing a portion of the conductive material outside of the trench.

28. The method of claim 27, wherein removing the portion of the conductive material outside of the trench includes performing a chemical mechanical polishing step.

29. The method of claim 25, wherein the masking layer comprises silicon.

30. The method of claim 25, wherein the insulating layer comprises oxide.

31. The method of claim 25 further comprising:

32. The method of claim 25, wherein alternatingly etching portions of the masking layer and the insulating layer comprises:

etching a second amount of the insulating layer, wherein the second amount comprises a first portion of the first sidewall portion of the insulating layer;

etching a fourth amount of the insulating layer, wherein the fourth amount comprises a second portion of the first sidewall portion and a first portion of the second sidewall portion of the insulating layer.

33. The method of claim 32, wherein the second amount and the fourth amount are approximately equal, and wherein the first amount and the second amount are approximately equal.