WO2014015584A1 - Array substrate, display apparatus, and method for producing array substrate - Google Patents

Description

 Array substrate, display device, and manufacturing method of array substrate

 Embodiments of the present invention relate to an array substrate, a display device, and a method of fabricating an array substrate. Background technique

 Among flat panel display devices, Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, relatively low manufacturing cost and no radiation, and has occupied the current flat panel display market. leading position.

 Currently, TFT-LCD display modes mainly include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, and AD-SDS (ADvanced). Super Dimension Switch, advanced super-dimensional field conversion technology, also referred to as ADS) mode.

 The display based on the ADS mode forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that all the liquid crystals in the liquid crystal cell are directly above the slit electrode and above the electrode. The molecules are capable of rotating, thereby improving the efficiency of the liquid crystal and increasing the light transmission efficiency. Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push-free water ripple (push Mura), etc. advantage.

 As shown in FIG. 1 , the TFT-LCD array substrate of the prior ADS mode is taken as an example. The structure of the array substrate includes: a glass substrate 10 and a gate line layer (including a gate line and a gate) which are sequentially formed on the glass substrate 10 . Pole 11), gate insulating layer 12, active layer 13, data line layer (including data line, source 14, drain 15), first passivation layer 16, pixel electrode 17 (plate electrode), second Passivation layer 18 and common electrode 19 (slit electrode). The pixel electrode 17 is connected to the drain electrode 15 through a via 21 on the first passivation layer 16.

In the prior art, forming the via on the first passivation layer 16 generally includes the steps of: coating a photoresist on the first passivation layer; exposing, developing, and removing the substrate coated with the photoresist. The photoresist at the via position (the photoresist other than the via position forms an etch protection mask); the via position is etched to form a via; and the photoresist remaining on the substrate is stripped. A disadvantage of the prior art is that, since the thickness of the first passivation layer is relatively thin (usually between 1 and 3 micrometers), the production process is difficult to control when etching the via hole position, and the etching process is easily etched. Some or all of the metal material under the holes causes excessive etching, which eventually leads to product defects. The thicknesses shown in Figure 1 are for convenience only and are not drawn to scale. Summary of the invention

 Embodiments of the present invention provide an array substrate, a display device, and a method for fabricating an array substrate, which are used to solve the technical problem that the over-hole etching process existing in the prior art is difficult to control, which may cause excessive etching and cause product defects. .

 An aspect of the invention provides an array substrate comprising: a data line layer comprising a plurality of data lines, a conductive barrier layer comprising a conductive barrier over the data line layer, located in the conductive barrier layer a passivation layer thereon, and a transparent conductive layer over the passivation layer, wherein a pass hole is disposed in the passivation layer above each of the data lines; the conductive barrier portion is located under the via hole The transparent conductive layer is connected to the corresponding conductive barrier through the via hole, and is electrically connected to the corresponding data line through the conductive barrier.

 For the array substrate, for example, above each of the data lines, the conductive barrier covers the corresponding data line.

 For the array substrate, for example, the conductive barrier layer includes a plurality of conductive barriers, each of the conductive barriers being disposed at a position corresponding to the via on each of the data lines.

 For the array substrate, for example, the conductive barrier portion is made of the same material as the transparent conductive layer. For the array substrate, for example, the conductive barrier portion is made of indium tin oxide.

 For the array substrate, for example, the data line layer further includes a source and a drain, the drain is integrally formed with a corresponding data line, and the conductive barrier covers the corresponding drain.

 For the array substrate, for example, the passivation layer is made of a non-photosensitive resin.

Another aspect of the present invention provides a display device including the above array substrate. Still another aspect of the present invention provides a method of fabricating an array substrate, comprising: forming a data line layer including a plurality of data lines and a conductive barrier layer, the conductive barrier layer including a conductive barrier portion over each of the data lines Forming a passivation layer over the conductive barrier layer, forming a via hole over the conductive barrier portion in the passivation layer; forming a transparent conductive layer over the passivation layer, the transparent conductive layer passing through the via hole Connected to a corresponding conductive barrier. For the manufacturing method, for example, the data line layer and the conductive barrier layer including a plurality of data lines are formed such that the conductive barrier covers the corresponding data lines above each of the data lines.

 For the manufacturing method, for example, the forming a data line layer including a plurality of data lines and a conductive barrier layer such that the conductive barrier layer includes a plurality of conductive barriers, each of the conductive barriers being disposed on each of the data lines The position corresponding to the via hole.

 For the fabrication method, for example, forming a via over the conductive barrier in the passivation layer includes: dry etching the passivation layer to form a via above the conductive barrier.

 For the manufacturing method, for example, the gas used for the dry etching includes at least one of sulfur hexafluoride, carbon tetrafluoride, oxygen, and helium.

 In the manufacturing method, for example, the passivation layer is made of a non-photosensitive resin; and the conductive resistor is made of the same material as the transparent conductive layer.

 For the manufacturing method, for example, the conductive barrier portion is made of indium tin oxide.

 In the array substrate of the embodiment of the invention, since the conductive barrier portion is located under the via hole and is in contact with the corresponding data line, the conductive barrier portion can be effectively protected when the passivation layer is etched to form a via hole. The metal material of the data line layer is not etched, which greatly improves the yield of the product. DRAWINGS

 In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .

 1 is a schematic structural view of a TFT-LCD array substrate of an existing ADS mode;

 2 is a schematic structural view of a first embodiment of an array substrate according to the present invention;

 3 is a schematic structural view of a second embodiment of the array substrate of the present invention.

 Reference mark:

 10-glass substrate 11-gate

 12-gate insulating layer 13-active layer

 14-source 15-drain

 16-first passivation layer 17-pixel electrode

 18-second passivation layer 19-common electrode

20-transparent substrate 30 - conductive barrier 21-via 22-data line

 23-passivation layer 24-transparent conductive layer

 25-second transparent conductive layer

 The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

 Unless otherwise defined, technical terms or scientific terms used herein shall be of the ordinary meaning understood by those of ordinary skill in the art to which the invention pertains. The words "first", "second" and similar terms used in the specification and claims of the present invention do not denote any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the words "a" or "an" do not denote a quantity limitation, but rather mean that there is at least one. The words "including" or "comprising", etc., are intended to mean that the elements or objects preceding "including" or "comprising" are intended to encompass the elements or Component or object. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationship may also change accordingly.

 In order to solve the technical problem that the over-hole etch process existing in the prior art is difficult to control, which is easy to cause over-etching and cause product defects, embodiments of the present invention provide an array substrate, a display device, and a method of manufacturing an array substrate. .

The array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in a matrix, each of the pixel units including a thin film transistor as a switching element and A pixel electrode that controls the arrangement of liquid crystals. For example, the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line, the source is electrically connected or integrally formed with the corresponding data line, and the drain is electrically connected or integrally formed with the corresponding pixel electrode. In addition, for example, the array substrate may further include a common electrode for cooperating with the pixel electrode to perform alignment of the liquid crystal Control. The following description is mainly made for a single or a plurality of pixel units, but other pixel units may be formed identically.

 As shown in FIG. 2, an array substrate according to an embodiment of the present invention includes: a data line layer including a plurality of data lines 22, and a conductive barrier layer including a conductive barrier 30 above the data line layer. A passivation layer 23 over the conductive barrier layer and a transparent conductive layer 24 over the passivation layer 23 are described.

 Above each of the data lines 22, a via hole 21 is disposed in the passivation layer 23; the conductive barrier portion 30 is located under the via hole 21, and is at least partially exposed by the via hole 21, and corresponding to the data line 22 contact.

 The transparent conductive layer 24 is connected to the corresponding conductive barrier 30 through the via 21 (i.e., partially deposited into the via 21), thereby being electrically connected to the corresponding data line through the conductive barrier 30.

 In the embodiment of the present invention, the data line layer refers to a layer structure of a layer to which a plurality of data lines belong, and in each pixel unit of the array substrate, the data line 22 corresponds to the source 14 and the drain 15, that is, The data line 22 can be integrated with one of the source 14 and the drain 15 of the thin film transistor of the pixel unit. As shown, for example, the data line 22 and the drain 15 are integrated, and the source 14 and the drain 15 are separated. The channel regions are opposite each other. The material forming the data line layer may be a single layer film of a metal material such as an aluminum-niobium alloy (AlNd), aluminum (Al), copper (Cu), molybdenum (Mo), molybdenum-tungsten alloy (MoW), or chromium (Cr). A composite film composed of any combination of these metal materials.

 The array substrate includes a transparent substrate 20, such as a glass or plastic substrate. On the transparent substrate 20, a gate line layer (e.g., including gate lines and gates), a gate insulating layer 12, an active layer 13, and the like may be further formed. The array substrate may be of a top gate type or a bottom gate type.

 The structure of the bottom gate type array substrate shown in Fig. 2 is as follows. A gate line layer (a gate line of the gate line layer includes a gate electrode 11 in each pixel unit) is formed on the transparent substrate 20, a gate insulating layer 12 is formed on the gate line layer, and an active layer 13 is formed on the gate electrode Above the insulating layer 12, a data line layer is formed on the active layer 13, and a conductive barrier layer 30 is formed on the data line layer (specifically, the conductive blocking portion 30 is formed on the drain 15), and the passivation layer 23 A via 21 is formed over the entire substrate 20 and over the conductive barrier 30. The transparent conductive layer 24 is partially deposited in the via 21 to be connected to the conductive barrier 30, and is electrically connected to the drain 15.

The via hole in the embodiment of the present invention is not limited to the position shown in FIG. 2. In the signal guiding region around the substrate, it is also necessary to etch the via hole on the passivation layer. At this time, the conductive barrier portion located in the region The metal material that can effectively protect the data line layer is not etched away.

 The array substrate in the embodiment of the present invention may be in a TN mode, a VA mode, an IPS mode, or an ADS mode. Referring to FIG. 2, the array substrate of the ADS mode further includes: a second passivation layer 18 formed on the transparent conductive layer 24 (the passivation layer 23 may be referred to as a first passivation layer at this time) And a slit-shaped second transparent conductive layer 25 formed on the second passivation layer 18 (the transparent conductive layer 24 may be referred to as a first transparent conductive layer at this time). Here, for example, the first transparent conductive layer may be a pixel electrode, and the second transparent conductive layer may be a common electrode; or the first transparent conductive layer may be a common electrode, and the second transparent conductive layer may be a pixel electrode.

 In the array substrate of the embodiment of the present invention, since the conductive barrier portion is located under the via hole and is in contact with the corresponding data line, the conductive barrier portion can be effective when the passivation layer is etched to form a via hole. The metal material protecting the data line layer is not etched, which greatly improves the yield of the product.

 Preferably, the material of the passivation layer 23 may be a non-photosensitive resin. Compared with the photosensitive resin, the non-photosensitive resin has the following advantages: The dielectric constant of the non-photosensitive resin material is about 3.0, which is lower than the dielectric constant of the photosensitive resin material (about 4.0); and the non-photosensitive resin material The transmittance is close to 100%, which is much higher than that of the photosensitive resin material (about 93%); the non-photosensitive resin material has a higher curing temperature of about 400 degrees, and the gas escapes almost zero. The curing temperature of the photosensitive resin material can only be about 230 degrees. In the subsequent production process, gas evolution easily occurs, which affects the mouth of the product.

 The conductive barrier portion 30 is preferably made of the same material as the transparent conductive layer 24, such as indium tin oxide (Indium Oxide), which has good transmittance and electrical conductivity, and, during processing of the array substrate, When dry etching is performed on the via hole of the passivation layer, indium tin oxide is not easily reacted with the etching gas, and the metal material of the data line layer can be effectively protected from being etched.

Preferably, above each of the data lines 22, the conductive barriers 30 cover the corresponding data lines 22, that is, the conductive barrier layer forms a large conductive barrier on each of the data lines, which extends beyond the vias. . In the embodiment shown in FIG. 2, the conductive barrier portion 30 covers the data line 22, that is, the pattern of the conductive barrier portion 30 completely overlaps with the pattern of the data line 22. The array substrate of the structure is sequentially deposited during processing. After the data line layer material and the conductive barrier layer material, the data line layer 22 and the conductive barrier layer 30 are formed by only one patterning process. Therefore, this is also one of the preferred embodiments of the present invention; as shown in FIG. In another embodiment of the present invention, the conductive barrier portion 30 is disposed only at a position corresponding to the via hole 21 above the data line 22, and the region outside the via hole 21 is basically Not formed. In addition, the conductive barrier can also cover the corresponding entire drain. The array substrate of these structures requires a patterning process to form the data line layer 22 and the conductive barrier layer 30 during processing.

 The embodiment of the present invention further provides a display device, which includes any of the above array substrates, and the display device can be: a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer. A product or part that has any display function.

 The method for manufacturing the array substrate of the embodiment of the present invention may include the following steps.

 Step 101: Form a data line layer and a conductive barrier layer including a plurality of data lines, wherein the conductive resistor layer comprises a conductive barrier located above each of the data lines;

 Step 102, forming a passivation layer over the conductive barrier layer, and forming a via hole above the conductive barrier in the passivation layer;

 Step 103: Form a transparent conductive layer on the passivation layer, and the transparent conductive layer is connected to the corresponding conductive barrier through the via.

 Preferably, the material of the passivation layer may be a non-photosensitive resin; the material of the conductive barrier and the transparent conductive layer may be the same.

 Preferably, the conductive barrier material may be indium tin oxide.

 As a preferred embodiment of the method for fabricating an array substrate of the present invention, the forming a data line layer and a conductive barrier layer including a plurality of data lines may include: sequentially depositing a data line layer material and a conductive barrier layer material on the substrate, by patterning The process forms a plurality of data lines and a plurality of conductive barriers covering each of the data lines, wherein the conductive barrier layer comprises a plurality of conductive barriers, each of the conductive barriers being disposed on each of the data lines corresponding to the vias position. Alternatively, a plurality of data lines and a conductive barrier covering each of the data lines are formed by a patterning process, whereby the conductive barrier covers the corresponding data lines above each of the data lines.

 The patterning process is, for example, a photolithographic patterning process, for example, comprising: coating a photoresist layer on a structure layer to be patterned, exposing the photoresist layer using a mask, and developing the exposed photoresist layer to obtain The photoresist pattern is etched using a photoresist pattern, and then the photoresist pattern is optionally removed. The ashing process may also be included if the mask used is a two-tone mask.

 Forming a via hole over the conductive barrier on the passivation layer by a patterning process includes: dry etching the passivation layer to form a via hole above the conductive barrier.

The gas used in the dry etching includes at least one of sulfur hexafluoride, carbon tetrafluoride, oxygen, and helium, and the gas can quickly etch away the passivation layer at the via position. . An example of the main fabrication process of the array substrate of the embodiment shown in Fig. 2 can be as follows.

 A gate metal is deposited on the transparent substrate, and a gate line layer is formed by the first patterning process.

 A gate insulating layer is deposited on the substrate on which the above steps are completed.

 An active layer film is deposited on the substrate on which the above steps are completed, and an active layer is formed by a second patterning process.

 On the substrate on which the above steps are completed, a data line layer material (material is molybdenum) and a conductive resistor layer material (material is indium tin oxide) are sequentially deposited, and a data line layer and a conductive resistance layer are formed through a third patterning process. In this third patterning process, a conventional mask or a two-tone mask can be used to expose the photoresist. When a patterning process is performed using a conventional mask, the resulting data line layer is the same as the pattern of the conductive barrier layer; when a patterning process is performed using a two-tone mask (for example, a gray tone or a halftone mask), it can be performed twice. The etch, the data line layer and the conductive barrier layer are respectively obtained, and the conductive barrier layer remains only at the position on the data line layer where the passivation layer via is formed.

 Depositing a passivation layer on the substrate on which the above steps are completed, and forming a via hole above the conductive barrier portion by a fourth patterning process; in this step, the gas used for dry etching the via position of the passivation layer is used It includes at least one of sulfur hexafluoride, carbon tetrafluoride, oxygen, and helium.

 A transparent conductive layer is deposited on the substrate on which the above steps are completed, and a transparent conductive layer is formed by a fifth patterning process, and the transparent conductive layer is deposited in the via hole to be connected to the conductive barrier.

 A second passivation layer is deposited on the substrate on which the above steps are completed.

 A transparent conductive layer is deposited on the substrate on which the above steps are completed, and a slit-shaped second transparent conductive layer is formed by the sixth patterning process.

 It can be seen that, in the fourth patterning process, when the through-hole position of the passivation layer is dry-etched, the conductive barrier located under the via position can effectively protect the metal material of the data line layer from being etched away. The product qualification rate has been greatly improved, and in addition, the controllability of the production process has been greatly improved.

 The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

claims 1. An array substrate, comprising: a data line layer including a plurality of data lines, a conductive barrier layer located above the data line layer and including a conductive barrier portion, and a passivation layer located above the conductive barrier layer, and a transparent conductive layer located on the passivation layer, Wherein, above each data line, a via hole is provided in the passivation layer; the conductive blocking part is located below the via hole; the transparent conductive layer is connected to the corresponding conductive blocking part through the via hole, and the conductive blocking part is connected to the passivation layer through the via hole. The conductive blocking part is electrically connected to the corresponding data line. 2. The array substrate according to claim 1, wherein above each data line, the conductive blocking portion covers the corresponding data line. 3. The array substrate of claim 1, wherein the conductive barrier layer includes a plurality of conductive barrier portions, and each of the conductive barrier portions is disposed on each data line at a position corresponding to the via hole. 4. The array substrate according to any one of claims 1 to 3, wherein the conductive blocking part and the transparent conductive layer are made of the same material. 5. The array substrate according to claim 4, wherein the conductive barrier is made of indium tin oxide. 6. The array substrate according to any one of claims 1 to 5, wherein the data line layer further includes a source electrode and a drain electrode, the drain electrode is integrally formed with the corresponding data line, and the conductive blocking part covers corresponding to the drain. 7. The array substrate according to any one of claims 1 to 6, wherein the passivation layer is made of non-photosensitive resin. 8. A display device, including the array substrate according to any one of claims 1 to 7. 9. A method for manufacturing an array substrate, including: Forming a data line layer including a plurality of data lines and a conductive barrier layer, the conductive barrier layer including a conductive barrier portion located on each data line; Forming a passivation layer located above the conductive barrier layer, and forming a via hole located above the conductive barrier part in the passivation layer; A transparent conductive layer is formed on the passivation layer, and the transparent conductive layer is connected to the corresponding conductive blocking part through the via hole. 10. The method of manufacturing an array substrate according to claim 8, wherein the forming includes a plurality of The data line layer and the conductive barrier layer of the data lines are arranged such that above each data line, the conductive barrier part covers the corresponding data line. 11. The method of manufacturing an array substrate according to claim 8, wherein the forming a data line layer and a conductive barrier layer including a plurality of data lines, such that the conductive barrier layer includes a plurality of conductive barrier portions, each of which The conductive blocking part is disposed on each data line at a position corresponding to the via hole. 12. The manufacturing method of an array substrate according to any one of claims 10 to 12, wherein forming a via hole located above the conductive barrier in the passivation layer includes: The passivation layer is dry-etched to form a via hole located above the conductive barrier. 13. The method of manufacturing an array substrate according to claim 12, wherein the gas used in the dry etching includes at least one of sulfur hexafluoride, carbon tetrafluoride, oxygen and helium. 14. The manufacturing method of an array substrate according to any one of claims 9 to 13, wherein the passivation layer is made of non-photosensitive resin; and the conductive blocking part is made of the same material as the transparent conductive layer. 15. The method of manufacturing an array substrate according to any one of claims 9 to 14, wherein the conductive barrier is made of indium tin oxide.