WO2014014091A1 - Target assembly - Google Patents
Target assembly Download PDFInfo
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- WO2014014091A1 WO2014014091A1 PCT/JP2013/069670 JP2013069670W WO2014014091A1 WO 2014014091 A1 WO2014014091 A1 WO 2014014091A1 JP 2013069670 W JP2013069670 W JP 2013069670W WO 2014014091 A1 WO2014014091 A1 WO 2014014091A1
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- Prior art keywords
- target
- oxide
- backing plate
- sputtering
- target assembly
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/3407—Cathode assembly for sputtering apparatus, e.g. Target
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/34—Gas-filled discharge tubes operating with cathodic sputtering
- H01J37/3411—Constructional aspects of the reactor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/34—Gas-filled discharge tubes operating with cathodic sputtering
- H01J37/3411—Constructional aspects of the reactor
- H01J37/3414—Targets
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/34—Gas-filled discharge tubes operating with cathodic sputtering
- H01J37/3411—Constructional aspects of the reactor
- H01J37/3414—Targets
- H01J37/3426—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/34—Gas-filled discharge tubes operating with cathodic sputtering
- H01J37/3411—Constructional aspects of the reactor
- H01J37/3435—Target holders (includes backing plates and endblocks)
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
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- H10P14/22—
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- H10P14/3426—
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- H10P14/3434—
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- H10P14/6329—
Definitions
- the present invention relates to a target assembly used when an oxide thin film useful as a semiconductor layer (active layer) of a thin film transistor (TFT) used in a display device such as a liquid crystal display or an organic EL display is formed by sputtering, More specifically, the present invention relates to a target assembly in which a plurality of oxide target members are arranged at intervals on a single backing plate via a bonding material.
- TFT thin film transistor
- An amorphous (amorphous) oxide thin film (hereinafter sometimes referred to as an oxide semiconductor thin film) used for a TFT semiconductor layer has a higher carrier mobility than general-purpose amorphous silicon (a-Si).
- a-Si general-purpose amorphous silicon
- an oxide semiconductor film typically, a film containing indium (In) and zinc (Zn), and a film containing at least one of gallium (Ga) and tin (Sn) can be given.
- an amorphous oxide semiconductor (In—Ga—Zn—O, hereinafter sometimes referred to as “IGZO”) thin film of In, Ga, Zn, and O is preferable because it has a very high carrier mobility. It is used.
- Patent Document 1 discloses an oxide semiconductor thin film containing elements such as In, Zn, Sn, and Ga, and Mo, and Examples disclose a material in which Mo is added to IGZO.
- a sputtering method is preferably used in which a sputtering target having the same composition as the film is sputtered.
- an inert gas such as Ar gas is introduced into a vacuum, a high voltage is applied between the substrate and the target member, and the ionized inert gas is caused to collide with the target member and be blown off by the collision.
- the constituent material of the target member is deposited on the substrate to form a thin film.
- In-plane uniformity of component composition and film thickness in the film surface direction (in the film surface) is smaller in the thin film formed by sputtering compared to thin films formed by ion plating, vacuum evaporation, and electron beam evaporation. It has an advantage that a thin film having the same composition as the sputtering target can be formed.
- a sputtering target used in a sputtering method is generally used in a state of being bonded onto a backing plate (support) made of a metal member using a bonding material, and such a sputtering target is a target bonded body. Also called.
- a backing plate Cu having excellent heat resistance, conductivity and thermal conductivity is widely used, and is used in the form of pure copper or copper alloy.
- the bonding material low melting point solder materials (for example, In-based and Sn-based materials) having good thermal conductivity and conductivity are widely used.
- FIGS. 1 and 2 which will be described later, a plurality of small pieces of target members are arranged at intervals on a single backing plate.
- a target assembly in which a backing plate is bonded with a bonding material is used. Between adjacent target members, adjust so that there is a spacing (gap) of approximately 0.1 to 1.0 mm at room temperature so that adjacent targets will not come into contact with each other due to the deflection of the backing plate and defects will not occur. Arranged.
- a backing member such as a polymer heat-resistant sheet or a conductive sheet (also called an abutment plate) is usually provided on the back side of the gap (on the bonding side, the side facing the backing plate). May be provided.
- Patent Document 2 warpage of the entire sputtering target due to a difference in thermal expansion coefficient between the target material and the backing plate is suppressed, and further, separation and destruction of the target material and the backing plate due to thermal stress during sputtering are prevented.
- a tape-like spacer is arranged between the target material and the backing plate as a backing member.
- copper or a copper alloy is recommended as in the case of the backing plate.
- An oxide used as a semiconductor layer of a TFT is required not only to have a high carrier concentration (mobility) but also to have excellent TFT switching characteristics (transistor characteristics, TFT characteristics). Specifically, for example, the on-current (maximum drain current when a positive voltage is applied to the gate electrode and the drain electrode) is high, and the off-current (a negative voltage is applied to the gate electrode and a positive voltage is applied to the drain voltage). And the SS value (Subthreshold Swing, subthreshold swing, and gate voltage necessary to increase the drain current by one digit).
- the present inventors formed a Mo-containing IGZO thin film by using a target assembly having a Cu backing plate and a Cu backing member to form a TFT.
- the ON current decreased and the SS value significantly increased compared to IGZO. This result means that Mo cannot effectively suppress the degradation of TFT characteristics due to the contamination phenomenon of Cu in the thin film described above.
- the present invention has been made in view of the above circumstances, and an object of the present invention is to prevent deterioration of TFT characteristics (particularly a decrease in on-current and an increase in SS value) of an oxide semiconductor thin film formed by sputtering. Is to provide a simple target assembly.
- the target assembly of the present invention that has solved the above-described problems is a target assembly in which a plurality of adjacent oxide target members are disposed on a backing plate with a gap therebetween with a bonding material interposed therebetween.
- a backing member made of at least one or more selected from the group consisting of Ni, Si, Hf, and Ta provided across the gap between the oxide target member and the backing plate; It has a gist where it has it.
- the oxide target member contains at least In and Zn.
- the oxide target member further includes at least one of Ga and Sn.
- the backing plate is made of pure Cu or a Cu alloy.
- the backing member is one or more selected from the group consisting of Ni, Hf, and Ta.
- the bonding material is made of In base material or Sn base material.
- the components of the backing plate are prevented from being mixed (contaminated) into the thin film. can do.
- the backing member is made of a material composed of at least one or more of predetermined metal elements (Ni, Si, Hf, and Ta) that do not deteriorate the TFT characteristics of the oxide semiconductor thin film, Even if the predetermined metal element is contaminated, deterioration of TFT characteristics due to contamination can be prevented, and good TFT characteristics can be maintained.
- FIG. 1 is a plan view of a target assembly of the present invention.
- FIG. 2 is an enlarged vertical sectional view taken along line AA in FIG.
- FIGS. 3A to 3G are graphs showing Id-Vg characteristics of TFTs manufactured using the oxide (IGZO + various additive elements) semiconductor described in Example 1.
- FIG. FIG. 4 is a diagram showing Id-Vg characteristics of a TFT manufactured using a target assembly in which a Cu or Ni backing member is arranged on the back side (bonding side) of a gap between IGZO target members in Example 2. is there.
- the present inventors In order to effectively prevent a decrease in TFT characteristics (especially a decrease in on-current and an increase in SS value) of an oxide semiconductor thin film formed by sputtering, the present inventors have established an interval between target members (see FIG. 1 and FIG.
- the backing member used on the back side of (see T in FIG. 2) has been studied repeatedly.
- it is effective to use a backing member made of at least one element selected from the group consisting of Ni, Si, Hf, and Ta (hereinafter sometimes represented by an X group element).
- an X group element hereinafter sometimes represented by an X group element
- the target assembly on which the present invention is based uses a Cu backing plate, and uses an oxide containing at least In and Zn, and further containing at least one of Ga and Sn as an oxide target member. Is. Preferably, a low melting point solder material of In or Sn is used as the bonding material. Further, in providing the backing member that is the subject of the present invention, studies were made focusing on elements that do not degrade the TFT characteristics when added to the oxides that are the subject of the present invention.
- a thin film containing the element in the oxide (useful for improving TFT characteristics) is formed at the substrate position corresponding to the gap. This is because it was considered that the TFT characteristics of the oxide semiconductor thin film after the film formation did not deteriorate.
- at least one or two or more elements selected from the group consisting of Ni, Si, Hf, and Ta (hereinafter may be represented by group X elements) in the form of pure metal or alloy elements. It has been found that it can be used as a backing member.
- FIG. 1 is a plan view of a target assembly of the present invention
- FIG. 2 is an enlarged vertical sectional view taken along line AA of FIG.
- the target assembly of FIGS. 1 and 2 is an example of a preferred embodiment of the present invention, and the target assembly of the present invention is not intended to be limited to this.
- a rectangular sputtering target is shown, but the present invention is not limited to this, and for example, a disk-shaped one may be used.
- a target assembly 1 shown in FIGS. 1 and 2 includes a sputtering target 2 in which four oxide target members 4a to 4d are arranged side by side in front, back, left, and right, and a backing plate 3 that fixes (supports) the target.
- a backing member 5 is provided on the back side of the interval T between the adjacent oxide target members 4a to 4d (on the low melting point solder bonding material 11a side) so as to close the interval T.
- Spacers 12 (Cu wires) are arranged between the oxide target members 4a to 4d and the backing plate 3 so as to form a uniform distance.
- a cooling mechanism is provided on the back side of the backing plate 3 (on the side opposite to the side on which the oxide target members 4a to 4d are disposed).
- the oxide target members 4a to 4d are configured to be indirectly cooled through the gap.
- the oxide target members 4a to 4d are oxides targeted in the present invention (oxides containing at least In and Zn, and further containing Ga and / or Sn; hereinafter, [In—Zn (Ga / Sn) oxide). In some cases.). Specifically, In—Zn—O (IZO), In—Ga—Zn—O (IGZO), In—Zn—Sn—O (IZTO), and In—Ga—Zn—Sn—O (IGZSO) can be given. It is done. The ratio of each element is appropriately determined according to the composition of the oxide thin film formed on the substrate (not shown in FIGS. 1 and 2).
- the oxide target members 4a to 4d are made of a rectangular plate material, but are not limited to this, and may have a commonly used shape (for example, a disk shape). Further, the thickness and size of the oxide target members 4a to 4d are not particularly limited, and those normally used in the field of the target assembly can be selected.
- a space T is provided between the oxide target members 4a to 4d.
- the width of the interval T is preferably set appropriately according to the oxide target member to be used, the sizes of the low melting point solder bonding materials 11a to 11c, the size of the backing plate 3, and the like.
- the thickness is preferably 2 mm to 1.0 mm. Below, the said space
- the backing plate 3 is made of pure Cu or Cu alloy having excellent heat resistance, conductivity, and thermal conductivity. Any Cu backing plate can be used as long as it is normally used in the field of sputtering targets. Examples of the Cu alloy include a Cu—Cr alloy.
- the backing plate 3 has a predetermined plane area and a predetermined thickness so that the oxide target members 4a to 4d can be placed thereon.
- the low-melting-point solder bonding materials 11a to 11c typically, an In-based material or an Sn-based material can be given.
- the type is not particularly limited, and any type can be used as long as it is usually used in the field of sputtering targets.
- Examples of the In base material include an In—Ag alloy.
- Examples of the Sn-based material include a Sn—Zn alloy.
- An In-based material is preferable.
- the same or different low melting point solder bonding materials can be used for 11a to 11c, but it is preferable to use the same material in consideration of work efficiency and the like.
- the spacers 12 are arranged so that a uniform gap is formed between the oxide target members 4a to 4d and the backing plate 3 so that the bonding material can flow in.
- the spacer is not particularly limited as long as it has excellent conductivity and thermal conductivity, and any spacer can be used as long as it is usually used in the field of sputtering targets. Examples of the spacer 12 include a Cu wire. 1 and 2 show a spacer formed in a ring shape, but the present invention is not limited to this shape.
- a pure metal or an alloy element of the X group element used as the backing member can be used as the spacer 12. That is, the backing member used in the present invention is also useful as a spacer.
- the target material and the backing plate are peeled or broken due to thermal stress during sputtering. Can be used for a long period of time.
- the backing member 5 that characterizes the present invention is made of a pure metal of Ni, Ta, Si, or Hf (X group element), or an alloy component composed of two or more of the above X group elements.
- the X group element is not only excellent in conductivity and thermal conductivity, but also when added to the oxide [In—Zn (Ga / Sn) oxide] targeted in the present invention, the mobility of the TFT, The characteristics of the on-current and SS value are not deteriorated, and the same or better characteristics are exhibited (see Table 2 of Example 1 described later).
- the X group elements (Ni, Ta, Hf) excluding Si have a higher specific gravity than In or Sn, which is a typical component of the low-melting-point solder bonding materials 11a to 11c (the table of Example 1 described later). Therefore, it is preferably used in consideration of work efficiency at the time of manufacturing the target assembly.
- Ni and Si are preferable from the viewpoint of on-current and the like, and more preferably Ni.
- the backing member may be composed of a single material (for example, pure Ni), or may be configured as a laminated body (for example, pure Ni and Ni alloy).
- the backing member 5 and the backing plate 3 are joined by a low melting point solder bonding material 11b, and the backing member 5 and the oxide target members 4a and 4b are joined by a low melting point solder bonding material. Joined at 11a. Since the low melting point solder bonding material 11a is scraped and does not exist in the portion Q immediately below the interval T, here, the backing member 5 is directly connected to the oxide target members 4a and 4b without passing through the low melting point solder bonding material 11a. It is joined.
- the backing member is disposed on the back side of the interval T, and the presence form of the backing member is not limited to the mode of FIG.
- the low melting point solder bonding material 11a does not exist in the portion Q immediately below the interval T.
- the bonding material melts and abnormal discharge occurs, and particles and splash are generated.
- the bonding material rises through a gap, such a phenomenon becomes remarkable. Therefore, in order to avoid the phenomenon, it is preferable that the bonding material does not exist as much as possible in the portion Q immediately below.
- the size (width and thickness) of the backing member 5 is appropriately set according to the size of the oxide target members 4a to 4d and the low melting point solder bonding materials 11a to 11c to be used, the size of the backing plate 3, and the like.
- the thickness is preferably about 0.2 to 1.0 mm.
- the thickness of the backing member 5 is thinner than 0.2 mm, the effect of suppressing the warpage of the entire sputtering target due to the difference in thermal shrinkage between the target material and the backing plate is not sufficiently exhibited.
- the thickness of the backing member 5 exceeds 1.0 mm, the low melting point solder bonding materials 11a to 11c may flow out of the gap portion before solidifying.
- a more preferable thickness of the backing member 5 is about 0.25 to 0.50 mm.
- the width of the backing member 5 is preferably about 5 to 30 mm. If the width of the backing member 5 is smaller than 5 mm, alignment becomes difficult when the backing member is disposed immediately below the oxide target members 4a to 4d along the interval. On the other hand, if the width of the backing member 5 exceeds 30 mm, it may be difficult to sufficiently obtain the warp suppressing effect of the entire sputtering target. A more preferable width of the backing member 5 is about 10 to 25 mm.
- the method for manufacturing the target assembly according to the present invention described above is not particularly limited.
- the method described in Patent Document 2 described above can be referred to.
- An example of a preferred manufacturing method embodiment is shown below.
- a bonding material such as a low melting point metal material is filled on the backing plate and heated to a melting point or higher than the melting point of the low melting point metal material.
- the backing member is arranged side by side at a predetermined location. If necessary, arrange a spacer. As a result, the backing member having a larger specific gravity than the low melting point metal material settles in the low melting point metal material. When the specific gravity of the backing member is smaller than that of the low melting point metal material, the backing member is allowed to settle down.
- the plurality of oxide target members are arranged side by side at intervals, and then cooled.
- the low melting point metal material is re-solidified, and a target assembly in which the oxide target member and the backing plate are joined via the low melting point metal layer is obtained.
- Example 1 a TFT including an oxide semiconductor thin film containing an X group element (Ni, Si, Hf, Ta) selected as a constituent component of a backing member in the present invention has mobility and good TFT characteristics. I investigated.
- a TFT was manufactured as follows. First, a Ti thin film of 100 nm and a gate insulating film SiO 2 (200 nm) were sequentially formed as a gate electrode on a glass substrate (Corning Eagle 2000, diameter 100 mm ⁇ thickness 0.7 mm).
- the gate electrode was formed using a pure Ti sputtering target by DC sputtering at a film forming temperature: room temperature, a film forming power: 300 W, a carrier gas: Ar, and a gas pressure: 2 mTorr.
- the gate insulating film was formed by plasma CVD using a carrier gas: a mixed gas of SiH 4 and N 2 O, a deposition power of 100 W, and a deposition temperature of 300 ° C.
- oxide thin films having various compositions described in Table 1 were formed using a sputtering target (described later).
- IGZO-X containing X element in IGZO As the oxide thin film, in addition to IGZO-X containing X element in IGZO, for comparison, IGZO and IGZO containing an element (Cu, Cr, Mo) other than X group element were also formed.
- a sputtering target having an In: Ga: Zn ratio (atomic ratio) of 1: 1: 1 is used to form an oxide semiconductor thin film containing other elements in the IGZO.
- a film was formed using a Co-Sputter method in which two sputtering targets having different compositions were discharged simultaneously.
- a target in which a pure metal chip of an X group element, Cu, Cr, or Mo is mounted on the sputtering target.
- Each content of the metal element in the oxide thin film thus obtained was analyzed by an XPS (X-ray Photoelectron Spectroscopy) method. Specifically, after sputtering the range from the outermost surface to a depth of about 5 nm with Ar ions, analysis was performed under the following conditions.
- X-ray source Al K ⁇
- X-ray output 350W
- Photoelectron extraction angle 20 °
- a pre-annealing process was performed to improve the film quality.
- the pre-annealing was performed at 350 ° C. for 1 hour in a 100% oxygen atmosphere and atmospheric pressure.
- pure Ti was used to form source / drain electrodes by a lift-off method. Specifically, after patterning using a photoresist, a Ti thin film was formed by DC sputtering (film thickness was 100 nm). The method for forming the Ti thin film for the source / drain electrodes is the same as that for the gate electrode described above. Subsequently, unnecessary photoresist was removed by applying an ultrasonic cleaner in acetone, and the channel length of the TFT was 10 ⁇ m and the channel width was 200 ⁇ m.
- a protective film for protecting the oxide semiconductor was formed.
- the formation of the SiO 2 and SiN was performed using “PD-220NL” manufactured by Samco and using the plasma CVD method.
- SiO 2 and SiN films were sequentially formed.
- a mixed gas of N 2 O and SiH 4 was used for forming the SiO 2 film, and a mixed gas of SiH 4 , N 2 , and NH 3 was used for forming the SiN film.
- the film formation power was 100 W
- the film formation temperature was 150 ° C.
- an ITO film (film thickness: 80 nm) was formed using a DC sputtering method with a carrier gas: a mixed gas of argon and oxygen gas, a film formation power: 200 W, and a gas pressure: 5 mTorr, to manufacture a TFT.
- a carrier gas a mixed gas of argon and oxygen gas
- a film formation power 200 W
- a gas pressure 5 mTorr
- transistor characteristics drain current-gate voltage characteristics, Id-Vg characteristics), on-current, SS value, and field-effect mobility (hereinafter referred to as “mobility”) are as follows. ) FE was determined.
- transistor characteristics Id-Vg characteristics
- a semiconductor parameter analyzer “4156C” manufactured by Agilent Technology was used. Detailed measurement conditions are as follows. Source voltage: 0V Drain voltage: 10V Gate voltage: -30V to 30V (measurement interval: 1V)
- the on-current is a drain current with a gate voltage of 30 V and is a current value when the transistor is in an on state, and is the minimum value of the gate voltage required to increase the drain current by one digit.
- the SS value was the SS value.
- Mobility ⁇ FE was derived from the TFT characteristics in a linear region where V g > V d ⁇ V th .
- V g and V d are the gate voltage and drain voltage
- V th is the voltage when the drain current exceeds 1 nA
- I d is the drain current
- L and W are the channel length and channel width of the TFT element, respectively.
- C i is the capacitance of the gate insulating film
- ⁇ FE is the field effect mobility.
- ⁇ FE is derived from the following equation. In this example, the field effect mobility ⁇ FE was derived from the slope of the drain current-gate voltage characteristic (Id-Vg characteristic) in the vicinity of the gate voltage satisfying the linear region.
- each mobility obtained in this way was converted into a percentage (ratio to IGZO) when the mobility of IGZO was 100%, and evaluated based on the following criteria.
- ⁇ Ratio to IGZO is 90% or more
- ⁇ Ratio to IGZO is 70% or more and less than 90%
- ⁇ Ratio to IGZO is 50% or more and less than 70%
- Table 1 shows the results of mobility when each element is added to IGZO.
- Table 1 shows the results of Al, Ge, Sn, and Ti for reference in addition to the X group elements (Ni, Si, Hf, Ta), the conventional example (Mo), and the comparative examples (Cu, Cr). Show.
- the addition amount of each element [addition amount with respect to IGZO (atomic%)] is 2 atomic%.
- Table 1 also shows the specific gravity values of each element. This value is taken from the JIS handbook.
- Table 2 shows the results of on-state current and SS value when using oxide semiconductor thin films in which the addition amount of the X group element (Ni, Si, Hf, Ta) is variously changed with respect to IGZO.
- the addition amount of the group X element is the addition amount (atomic%) with respect to IGZO.
- Table 2 shows that when an X group element is added to IGZO, an on-current and an SS value equal to or higher than those obtained when a conventional IGZO not containing an X group element is used, and good TFT characteristics are obtained. Was confirmed.
- 3 (a) to 3 (g) include, among the experimental examples shown in Table 2, an X group element (addition amount 2 atomic%) or Cu, Cr, and Mo (all addition amounts 0.5 atomic%).
- the result of Id-Vg characteristic is shown.
- FIGS. 3A to 3G show the results of two measurements.
- the X group element is extremely useful as an element for improving the mobility and TFT characteristics of IGZO, and the X group element excluding Si is extremely useful for improving the working efficiency of the target assembly. It was confirmed that it was useful.
- These experimental results show that when the oxide thin film is manufactured by the sputtering method using the target assembly, even if the X group element enters from the target gap, the oxide is placed on the oxide at the substrate position corresponding to the gap. This indicates that since a thin film containing an X group element (an oxide thin film useful for improving TFT characteristics) is formed, the TFT characteristics of the oxide semiconductor thin film after film formation do not deteriorate. The usefulness of a backing member composed of two or more types is indirectly verified.
- Example 2 in order to compare and examine the usefulness as a backing member, a target assembly was manufactured using pure Ni (example of the present invention) or pure Cu (comparative example), and TFT characteristics were evaluated.
- the target assembly was manufactured by the manufacturing method of the preferred embodiment described above.
- a pure Cu backing plate ( ⁇ 132 mm, thickness 8.5 mm) was used as the backing plate, an In-based alloy was used as the bonding material, and a Cu wire was used as the spacer.
- the width of the interval T between the oxide target members was 0.3 mm.
- a TFT was produced in the same manner as in Example 1 except that the target assembly was used, and the on-current and SS value were evaluated.
- the thickness after sputtering (residual thickness) was 6 mm or 1 mm.
- each characteristic was evaluated in the same manner as described above using a target assembly without a gap.
- a target assembly having a gap between target members is manufactured.
- a target without a gap is used for convenience in order to obtain a reference example that eliminates the influence of the gap.
- An assembly was used.
- FIG. 4 is a graph showing Id-Vg characteristics under the conditions described in Table 3 and Table 4.
- the components of the backing plate are prevented from being mixed (contaminated) into the thin film. can do.
- the backing member is made of a material composed of at least one or more of predetermined metal elements (Ni, Si, Hf, and Ta) that do not deteriorate the TFT characteristics of the oxide semiconductor thin film, Even if the predetermined metal element is contaminated, deterioration of TFT characteristics due to contamination can be prevented, and good TFT characteristics can be maintained.
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Abstract
Description
本発明は、液晶ディスプレイや有機ELディスプレイなどの表示装置に用いられる薄膜トランジスタ(TFT)の半導体層(活性層)として有用な酸化物薄膜をスパッタリング法で成膜するときに用いられるターゲット組立体に関し、詳細には、一枚のバッキングプレート上に、ボンディング材を介して、複数の酸化物ターゲット部材が間隔をあけて配置されたターゲット組立体に関するものである。 The present invention relates to a target assembly used when an oxide thin film useful as a semiconductor layer (active layer) of a thin film transistor (TFT) used in a display device such as a liquid crystal display or an organic EL display is formed by sputtering, More specifically, the present invention relates to a target assembly in which a plurality of oxide target members are arranged at intervals on a single backing plate via a bonding material.
TFTの半導体層に用いられるアモルファス(非晶質)酸化物薄膜(以下、酸化物半導体薄膜と呼ぶ場合がある。)は、汎用のアモルファスシリコン(a-Si)に比べて高いキャリア移動度を有し、光学バンドギャップが大きく、低温で成膜できるため、大型・高解像度・高速駆動が要求される次世代ディスプレイや、耐熱性の低い樹脂基板などへの適用が期待されている。 An amorphous (amorphous) oxide thin film (hereinafter sometimes referred to as an oxide semiconductor thin film) used for a TFT semiconductor layer has a higher carrier mobility than general-purpose amorphous silicon (a-Si). However, since it has a large optical band gap and can be formed at a low temperature, it is expected to be applied to next-generation displays that require large size, high resolution, and high-speed driving, and resin substrates with low heat resistance.
酸化物半導体膜としては、代表的には、インジウム(In)および亜鉛(Zn)を含むものや、更には、ガリウム(Ga)およびスズ(Sn)の少なくとも一種以上を含むものが挙げられる。例えば、In、Ga、Zn、およびOからなるアモルファス酸化物半導体(In-Ga-Zn-O、以下「IGZO」と呼ぶ場合がある。)薄膜は、非常に高いキャリア移動度を有するため、好ましく用いられている。また、特許文献1には、In、Zn、Sn、Gaなどの元素と、Moとを含む酸化物半導体薄膜が開示され、実施例には、IGZOにMoを添加したものが開示されている。
As an oxide semiconductor film, typically, a film containing indium (In) and zinc (Zn), and a film containing at least one of gallium (Ga) and tin (Sn) can be given. For example, an amorphous oxide semiconductor (In—Ga—Zn—O, hereinafter sometimes referred to as “IGZO”) thin film of In, Ga, Zn, and O is preferable because it has a very high carrier mobility. It is used.
酸化物半導体薄膜の形成に当たっては、当該膜と同じ組成のスパッタリングターゲットをスパッタリングするスパッタリング法が好適に用いられている。スパッタリング法では、真空中にArガス等の不活性ガスを導入しながら、基板とターゲット部材との間に高電圧を印加し、イオン化した不活性ガスをターゲット部材に衝突させ、その衝突により弾き飛ばされたターゲット部材の構成物質を基板に堆積させて薄膜を形成する。スパッタリング法で形成された薄膜は、イオンプレーティング法や真空蒸着法、電子ビーム蒸着法で形成された薄膜に比べ、膜面方向(膜面内)における成分組成や膜厚などの面内均一性に優れており、スパッタリングターゲットと同じ成分組成の薄膜を形成できるという長所を有している。 In forming an oxide semiconductor thin film, a sputtering method is preferably used in which a sputtering target having the same composition as the film is sputtered. In the sputtering method, an inert gas such as Ar gas is introduced into a vacuum, a high voltage is applied between the substrate and the target member, and the ionized inert gas is caused to collide with the target member and be blown off by the collision. The constituent material of the target member is deposited on the substrate to form a thin film. In-plane uniformity of component composition and film thickness in the film surface direction (in the film surface) is smaller in the thin film formed by sputtering compared to thin films formed by ion plating, vacuum evaporation, and electron beam evaporation. It has an advantage that a thin film having the same composition as the sputtering target can be formed.
スパッタリング法に用いられるスパッタリングターゲットは、一般的に、金属製部材のバッキングプレート(支持体)の上に、ボンディング材を用いて接合した状態で使用されており、このようなスパッタリングターゲットはターゲット接合体とも呼ばれる。バッキングプレートには、耐熱性、導電性、熱伝導性に優れるCuが汎用されており、純銅または銅合金の形で使用される。ボンディング材としては、熱伝導性と導電性が良好な低融点ハンダ材料(例えば、In系、Sn系の材料)が汎用されている。 A sputtering target used in a sputtering method is generally used in a state of being bonded onto a backing plate (support) made of a metal member using a bonding material, and such a sputtering target is a target bonded body. Also called. For the backing plate, Cu having excellent heat resistance, conductivity and thermal conductivity is widely used, and is used in the form of pure copper or copper alloy. As the bonding material, low melting point solder materials (for example, In-based and Sn-based materials) having good thermal conductivity and conductivity are widely used.
近年、スパッタリング法による大型基板への成膜の需要が増加しており、それに伴ってスパッタリングターゲットの大きさも大型化しつつある。スパッタリングターゲットによっては大型化が難しいものもあるため、後記する図1、図2に示すように、一枚のバッキングプレートの上に、複数の小片のターゲット部材を間隔をあけて並べ、ターゲット部材とバッキングプレートとを、ボンディング材で接合したターゲット組立体が用いられている。隣接するターゲット部材の間は、バッキングプレートのたわみにより隣接するターゲット同士が接触して欠陥が生じないように、室温時におおむね、0.1~1.0mmの間隔(隙間)ができるように調整して配置される。また、上記の隙間からボンディング材が漏出しないように、通常、上記間隔の裏側(ボンディング側、バッキングプレートに対向する側)に高分子耐熱シートや導電性シートなどの裏打ち部材(当板とも呼ばれる)が設けられることもある。 In recent years, the demand for film formation on a large substrate by a sputtering method is increasing, and the size of the sputtering target is also increasing. Since there are some sputtering targets that are difficult to increase in size, as shown in FIGS. 1 and 2, which will be described later, a plurality of small pieces of target members are arranged at intervals on a single backing plate. A target assembly in which a backing plate is bonded with a bonding material is used. Between adjacent target members, adjust so that there is a spacing (gap) of approximately 0.1 to 1.0 mm at room temperature so that adjacent targets will not come into contact with each other due to the deflection of the backing plate and defects will not occur. Arranged. Also, in order to prevent the bonding material from leaking out from the gap, a backing member such as a polymer heat-resistant sheet or a conductive sheet (also called an abutment plate) is usually provided on the back side of the gap (on the bonding side, the side facing the backing plate). May be provided.
例えば特許文献2では、ターゲット材とバッキングプレートの熱膨脹率差に起因した、スパッタリングターゲット全体の反りを抑制し、更にはスパッタリング中の熱応力に起因するターゲット材とバッキングプレートとの剥離や破壊を防止して長期間の使用を可能にするため、ターゲット材とバッキングプレートとの間に、裏打ち部材に相当するものとして、テープ状スペーサーを配置している。テープ状スペーサーの材質として、バッキングプレートと同様、銅または銅合金が推奨されている。このようなテープ状スペーサーを、分割ターゲットの継ぎ合わせた部分および端部分に沿って、その全部または一部の直下に配置すると、スパッタリング中の放電が均一になるほか、継ぎ合わせ部分から低融点ハンダがスパッタ両側にしみ上がるのを効果的に防止できる旨、記載されている。
For example, in
TFTの半導体層として用いる酸化物には、キャリア濃度(移動度)が高いだけでなく、TFTのスイッチング特性(トランジスタ特性、TFT特性)に優れていることが要求される。具体的には、例えば、オン電流(ゲート電極とドレイン電極に正電圧をかけたときの最大ドレイン電流)が高く、オフ電流(ゲート電極に負電圧を、ドレイン電圧に正電圧を夫々かけたときのドレイン電流)が低く、SS値(Subthreshold Swing、サブスレッショルド スィング、ドレイン電流を1桁あげるのに必要なゲート電圧)が低いことなどが挙げられる。 An oxide used as a semiconductor layer of a TFT is required not only to have a high carrier concentration (mobility) but also to have excellent TFT switching characteristics (transistor characteristics, TFT characteristics). Specifically, for example, the on-current (maximum drain current when a positive voltage is applied to the gate electrode and the drain electrode) is high, and the off-current (a negative voltage is applied to the gate electrode and a positive voltage is applied to the drain voltage). And the SS value (Subthreshold Swing, subthreshold swing, and gate voltage necessary to increase the drain current by one digit).
一方、ターゲット組立体の製造に当たっては、前述したように、隣接する複数の酸化物ターゲット部材の間に隙間を設けるため、スパッタリング中に、この隙間からイオン化した不活性ガスが侵入するようになる。その結果、ターゲット部材の下に配置されたCu製のバッキングプレートもスパッタリングされ、形成される酸化物薄膜中にCuが混入し、TFT特性が低下する。TFT特性の低下は、ディスプレイを作製した際の画像ムラの主な要因となり、品質の著しい劣化を招く。よって、前述した特許文献2のように、バッキングプレートのみならず、裏打ち部材にもCu製のものを使用すると、Cuのコンタミ現象が一層顕著になるため、好ましくない。
On the other hand, in manufacturing the target assembly, as described above, a gap is provided between a plurality of adjacent oxide target members, so that an ionized inert gas enters through the gap during sputtering. As a result, the Cu backing plate disposed under the target member is also sputtered, Cu is mixed into the formed oxide thin film, and the TFT characteristics are deteriorated. The decrease in TFT characteristics is a major factor in image unevenness when a display is manufactured, and causes a significant deterioration in quality. Therefore, as in
また、前述した特許文献1に記載のMoを含むIGZO半導体について、本発明者らが、Cu製バッキングプレートとCu製裏打ち部材を有するターゲット組立体を用いてMo含有IGZO薄膜を成膜してTFT特性を調べたところ、IGZOに比べ、特にオン電流の低下およびSS値の著しい上昇が見られることが判明した。この結果は、Moは、上述した薄膜中へのCuのコンタミ現象によるTFT特性の低下を有効に抑えられないことを意味している。
In addition, regarding the IGZO semiconductor containing Mo described in
本発明は上記事情に鑑みてなされたものであり、その目的は、スパッタリングにより形成された酸化物半導体薄膜のTFT特性の劣化(特にオン電流の低下およびSS値の上昇)を防止することが可能なターゲット組立体を提供することにある。 The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent deterioration of TFT characteristics (particularly a decrease in on-current and an increase in SS value) of an oxide semiconductor thin film formed by sputtering. Is to provide a simple target assembly.
上記課題を解決することができた本発明のターゲット組立体は、バッキングプレート上に、ボンディング材を介して、隣接する複数の酸化物ターゲット部材が間隔をあけて配置されたターゲット組立体であって、前記酸化物ターゲット部材と前記バッキングプレートとの間に、前記間隔を跨いで設けられた、Ni、Si、Hf、およびTaよりなる群から選択される少なくとも一種または二種以上からなる裏打ち部材を有するところに要旨を有するものである。 The target assembly of the present invention that has solved the above-described problems is a target assembly in which a plurality of adjacent oxide target members are disposed on a backing plate with a gap therebetween with a bonding material interposed therebetween. A backing member made of at least one or more selected from the group consisting of Ni, Si, Hf, and Ta provided across the gap between the oxide target member and the backing plate; It has a gist where it has it.
本発明の好ましい実施形態において、上記酸化物ターゲット部材は、InおよびZnを少なくとも含むものである。 In a preferred embodiment of the present invention, the oxide target member contains at least In and Zn.
本発明の好ましい実施形態において、上記酸化物ターゲット部材は、GaおよびSnのうち少なくとも一つを更に含むものである。 In a preferred embodiment of the present invention, the oxide target member further includes at least one of Ga and Sn.
本発明の好ましい実施形態において、上記バッキングプレートは純CuまたはCu合金からなるものである。 In a preferred embodiment of the present invention, the backing plate is made of pure Cu or a Cu alloy.
本発明の好ましい実施形態において、上記裏打ち部材は、Ni、Hf、およびTaよりなる群から選択される一種または二種以上からなるものである。 In a preferred embodiment of the present invention, the backing member is one or more selected from the group consisting of Ni, Hf, and Ta.
本発明の好ましい実施形態において、上記ボンディング材はIn基材料またはSn基材料からなるものである。 In a preferred embodiment of the present invention, the bonding material is made of In base material or Sn base material.
本発明のターゲット組立体では、酸化物ターゲット部材とバッキングプレートとの間に、間隔を跨いで配置される裏打ち部材を設けることにより、バッキングプレートの成分が薄膜中に混入(コンタミ)するのを防止することができる。さらに、裏打ち部材として、酸化物半導体薄膜のTFT特性を劣化させない所定金属元素(Ni、Si、Hf、およびTa)の少なくとも一種または二種以上からなる材料を用いているため、酸化物半導体薄膜中に上記所定金属元素がコンタミしたとしても、コンタミによるTFT特性の劣化を防止することができ、良好なTFT特性を保つことができる。 In the target assembly of the present invention, by providing a backing member disposed across the gap between the oxide target member and the backing plate, the components of the backing plate are prevented from being mixed (contaminated) into the thin film. can do. Further, since the backing member is made of a material composed of at least one or more of predetermined metal elements (Ni, Si, Hf, and Ta) that do not deteriorate the TFT characteristics of the oxide semiconductor thin film, Even if the predetermined metal element is contaminated, deterioration of TFT characteristics due to contamination can be prevented, and good TFT characteristics can be maintained.
本発明者らは、スパッタリングによって形成された酸化物半導体薄膜のTFT特性の低下(特にオン電流の低下、SS値の上昇)を有効に防止するため、ターゲット部材間の間隔(後記する図1および図2のTを参照)の裏側に用いられる裏打ち部材について検討を重ねてきた。その結果、Ni、Si、Hf、およびTaよりなる群から選択される少なくとも一種または二種以上の元素(以下、X群元素で代表させる場合がある。)からなる裏打ち部材の使用が有効であることを見出し、本発明を完成した。 In order to effectively prevent a decrease in TFT characteristics (especially a decrease in on-current and an increase in SS value) of an oxide semiconductor thin film formed by sputtering, the present inventors have established an interval between target members (see FIG. 1 and FIG. The backing member used on the back side of (see T in FIG. 2) has been studied repeatedly. As a result, it is effective to use a backing member made of at least one element selected from the group consisting of Ni, Si, Hf, and Ta (hereinafter sometimes represented by an X group element). As a result, the present invention has been completed.
まず、本発明に到達した経緯について説明する。本発明の基礎となったターゲット組立体は、Cu製のバッキングプレートを用いると共に、酸化物ターゲット部材として、少なくともInおよびZnを含み、更にはGaおよびSnの少なくとも一種以上を含む酸化物を使用するものである。好ましくは、ボンディング材としてInまたはSnの低融点ハンダ材料を用いるものである。また、本発明で対象とする裏打ち部材の提供に当たっては、本発明で対象とする上記酸化物に添加したとき、TFT特性を劣化させない元素に着目して検討を行なった。このような元素であれば、スパッタリングの際、ターゲット部材の隙間から上記元素が侵入したとしても、隙間に対応する基板位置には、上記酸化物に上記元素を含む薄膜(TFT特性向上に有用な薄膜)が形成されることになり、成膜後の酸化物半導体薄膜のTFT特性は劣化しないと考えたからである。その結果、Ni、Si、Hf、およびTaよりなる群から選択される少なくとも一種または二種以上の元素(以下、X群元素で代表させる場合がある。)を、純金属または合金元素の形態で裏打ち部材として使用すれば良いことを突き止めた。 First, the background to the present invention will be described. The target assembly on which the present invention is based uses a Cu backing plate, and uses an oxide containing at least In and Zn, and further containing at least one of Ga and Sn as an oxide target member. Is. Preferably, a low melting point solder material of In or Sn is used as the bonding material. Further, in providing the backing member that is the subject of the present invention, studies were made focusing on elements that do not degrade the TFT characteristics when added to the oxides that are the subject of the present invention. With such an element, even when the element enters from the gap of the target member during sputtering, a thin film containing the element in the oxide (useful for improving TFT characteristics) is formed at the substrate position corresponding to the gap. This is because it was considered that the TFT characteristics of the oxide semiconductor thin film after the film formation did not deteriorate. As a result, at least one or two or more elements selected from the group consisting of Ni, Si, Hf, and Ta (hereinafter may be represented by group X elements) in the form of pure metal or alloy elements. It has been found that it can be used as a backing member.
以下、本発明のターゲット組立体について、図1および図2を参照しながら、詳細に説明する。図1は、本発明のターゲット組立体の平面図であり、図2は、図1のA-A線拡大縦断面図である。但し、図1および図2のターゲット組立体は、本発明の好ましい実施形態の一例であって、本発明のターゲット組立体は、これに限定する趣旨では決してない。例えば以下の図では、長方形状のスパッタリングターゲットを示しているが、これに限定されず、例えば円盤状のものを用いても良い。 Hereinafter, the target assembly of the present invention will be described in detail with reference to FIG. 1 and FIG. FIG. 1 is a plan view of a target assembly of the present invention, and FIG. 2 is an enlarged vertical sectional view taken along line AA of FIG. However, the target assembly of FIGS. 1 and 2 is an example of a preferred embodiment of the present invention, and the target assembly of the present invention is not intended to be limited to this. For example, in the following drawings, a rectangular sputtering target is shown, but the present invention is not limited to this, and for example, a disk-shaped one may be used.
図1および図2に示すターゲット組立体1は、4枚の酸化物ターゲット部材4a~4dを前後左右に二枚ずつ並べて構成されるスパッタリングターゲット2と、これを固定(支持)するバッキングプレート3と、複数の酸化物ターゲット部材4a~4dとバッキングプレート3とを接合する低融点ハンダボンディング材11a~11cとで構成されている。隣接する複数の酸化物ターゲット部材4a~4dの間隔Tの裏側(低融点ハンダボンディング材11a側)には、間隔Tを塞ぐように、裏打ち部材5が設けられている。酸化物ターゲット部材4a~4dとバッキングプレート3との間には、均一な間隔を形成することができるようにスペーサー12(Cuワイヤ)を配置している。
A
なお、図1および図2には示していないが、バッキングプレート3の背面側(酸化物ターゲット部材4a~4dが配置される側と反対側)には冷却機構が設けられており、バッキングプレート3を介して酸化物ターゲット部材4a~4dを間接的に冷却できるように構成されている。
Although not shown in FIGS. 1 and 2, a cooling mechanism is provided on the back side of the backing plate 3 (on the side opposite to the side on which the
酸化物ターゲット部材4a~4dは、本発明で対象とする酸化物(InおよびZnを少なくとも含み、更にGaおよび/またはSnを含む酸化物;以下、[In-Zn(Ga/Sn)酸化物]で表現する場合がある。)で構成されている。具体的には、In-Zn-O(IZO)、In-Ga-Zn-O(IGZO)、In-Zn-Sn-O(IZTO)、In-Ga-Zn-Sn-O(IGZSO)が挙げられる。各元素の比率は、基板(図1、図2には示さず)に成膜される酸化物薄膜の組成に応じて適切に決定される。
The
図1および図2において、酸化物ターゲット部材4a~4dは、長方形の板材で構成されているが、これに限定されず、通常用いられる形状(例えば円盤状)であっても良い。また、酸化物ターゲット部材4a~4dの厚さやサイズも特に限定されず、ターゲット組立体の分野において通常用いられるものを選択することができる。
1 and 2, the
酸化物ターゲット部材4a~4dの間には、間隔Tが設けられている。間隔Tの幅は、使用する酸化物ターゲット部材や、低融点ハンダボンディング材11a~11cのサイズ、更にはバッキングプレート3のサイズなどに応じて適切に設定されることが好ましいが、おおむね、0.2mm~1.0mmとすることが好ましい。以下では、上記間隔Tを「隙間部」と呼ぶ場合がある。
A space T is provided between the
バッキングプレート3は、耐熱性、導電性、熱伝導性に優れた純CuまたはCu合金で構成されている。Cu製のバッキングプレートはスパッタリングターゲットの分野に通常用いられるものであれば、すべて使用することができる。Cu合金としては、例えば、Cu-Cr合金などが挙げられる。バッキングプレート3は、酸化物ターゲット部材4a~4dを載置できるように、所定の平面積と所定の厚さを有している。
The
低融点ハンダボンディング材11a~11cとしては、代表的にはIn基材料またはSn基材料が挙げられる。その種類は特に限定されず、スパッタリングターゲットの分野に通常用いられるものであれば、すべて使用することができる。In基材料としては、例えば、In-Ag合金などが挙げられる。Sn基材料としては、例えばSn-Zn合金などが挙げられる。好ましくはIn基材料である。図2において、11a~11cは、同一または異なる低融点ハンダボンディング材を使用することができるが、作業効率などを考慮すると、同じ材料を用いることが好ましい。
As the low-melting-point
スペーサー12は、酸化物ターゲット部材4a~4dとバッキングプレート3との間に、均一な間隔を形成し、ボンディング材が流入できるように配置されるものである。スペーサーは、導電性や熱伝導性に優れたものであれば特に限定されず、スパッタリングターゲットの分野に通常用いられるものであれば、すべて使用することができる。スペーサー12としては、例えばCuワイヤなどが挙げられる。なお、図1および図2では、リング状に形成されたスペーサーを示しているが、この形状に限定されない。
The
本発明では、スペーサー12として、裏打ち部材として用いられるX群元素の純金属または合金元素を使用することもできる。すなわち、本発明に用いられる裏打ち部材は、スペーサーとしても有用であり、例えば低融点ハンダボンディング材11で固定して使用すると、スパッタリング中の熱応力に起因するターゲット材とバッキングプレートとの剥離や破壊を防止できるため、長期間の使用が可能となる。
In the present invention, a pure metal or an alloy element of the X group element used as the backing member can be used as the
本発明を特徴付ける裏打ち部材5は、Ni、Ta、Si、またはHf(X群元素)の純金属、または上記X群元素の二種以上からなる合金成分で構成されている。上記X群元素は、導電性及び熱伝導性に優れているだけでなく、本発明で対象とする酸化物[In-Zn(Ga/Sn)酸化物]に添加したとき、TFTの移動度、オン電流、SS値の特性を劣化させず、同等若しくはそれ以上の特性を発揮するものである(後記する実施例1の表2を参照)。また、Siを除く上記X群元素(Ni、Ta、Hf)は、低融点ハンダボンディング材11a~11cの代表的な構成成分であるInまたはSnよりも比重が大きい(後記する実施例1の表1を参照)ため、ターゲット組立体製造時の作業効率を考慮すると、好ましく用いられる。上記X群元素のうちオン電流などの観点から好ましいのはNi、Siであり、より好ましくはNiである。
The
図2において、裏打ち部材は、単一の材料(例えば純Ni)で構成されていても良いし、積層体(例えば、純NiとNi合金)として構成されていても良い。 In FIG. 2, the backing member may be composed of a single material (for example, pure Ni), or may be configured as a laminated body (for example, pure Ni and Ni alloy).
詳細には図2に示すように、裏打ち部材5とバッキングプレート3とは低融点ハンダボンディング材11bで接合されると共に、裏打ち部材5と酸化物ターゲット部材4a、4bとは、低融点ハンダボンディング材11aで接合される。間隔Tの直下部分Qでは、低融点ハンダボンディング材11aは掻き出されて存在しないため、ここでは、裏打ち部材5は、低融点ハンダボンディング材11aを介さず、酸化物ターゲット部材4a、4bと直接接合している。
Specifically, as shown in FIG. 2, the backing
但し、本発明では、間隔Tの裏側に裏打ち部材が少なくとも配置されていれば良く、裏打ち部材の存在形態は、図2の態様に限定されない。また、図2に示すように、間隔Tの直下部分Qに低融点ハンダボンディング材11aは存在しない方が好ましいが、これは、Q部分に低融点ハンダボンディング材があると、スパッタリング中に熱が加わり、ボンディング材が溶け出して異常放電が生じ、パーティクルやスプラッシュが発生するためである。特に、隙間をつたって、ボンディング材が這い上がってくると、このような現象が顕著になるため、当該現象を回避するうえで、直下部分Qにはボンディング材は出来るだけ存在しない方が良い。
However, in the present invention, it suffices that at least the backing member is disposed on the back side of the interval T, and the presence form of the backing member is not limited to the mode of FIG. In addition, as shown in FIG. 2, it is preferable that the low melting point
裏打ち部材5のサイズ(幅、厚さ)は、使用する酸化物ターゲット部材4a~4d、および低融点ハンダボンディング材11a~11cのサイズ、更にはバッキングプレート3のサイズなどに応じて適切に設定されることが好ましいが、厚さは、おおむね、0.2~1.0mmであることが好ましい。裏打ち部材5の厚さが0.2mmより薄いと、ターゲット材とバッキングプレートとの熱収縮率差に起因した、スパッタリングターゲット全体の反りの抑制効果が十分発揮されない。一方、裏打ち部材5の厚さが1.0mmを超えると、低融点ハンダボンディング材11a~11cが固化する前に隙間部から流出してしまう恐れがある。より好ましい裏打ち部材5の厚さは、おおむね0.25~0.50mmである。
The size (width and thickness) of the
裏打ち部材5の幅は、おおむね、5~30mmであることが好ましい。裏打ち部材5の幅が5mmより小さいと、酸化物ターゲット部材4a~4d間の間隔に沿ってその直下に裏打ち部材を配置する際、位置合わせが難しくなる。一方、裏打ち部材5の幅が30mmを超えると、スパッタリングターゲット全体の反り抑制効果が十分得られ難くなる恐れがある。より好ましい裏打ち部材5の幅は、おおむね、10~25mmである。
The width of the
以上、本発明のターゲット組立体について詳述した。 The target assembly of the present invention has been described in detail above.
上述した本発明に係るターゲット組立体の製造方法は特に限定されず、例えば、前述した特許文献2に記載の方法などを参照することができる。好ましい製造方法の実施形態の一例を以下に示す。まず、バッキングプレートの上に低融点金属材料などのボンディング材を充填し、低融点金属材料の融点以上に加熱して溶融状態とする。次いで、裏打ち部材を所定の箇所に並べて配置する。必要に応じて、スペーサーを配置する。その結果、低融点金属材料に比べて比重の大きい裏打ち部材は、低融点金属材料のなかに沈降する。裏打ち部材の比重が低融点金属材料に比べて小さい場合は、押さえ込むようにして沈降させる。次いで、複数の酸化物ターゲット部材を、間隔をあけて並べて配置した後、冷却する。冷却により、低融点金属材料が再凝固し、酸化物ターゲット部材とバッキングプレートとが、低融点金属層を介して接合されたターゲット組立体が得られる。
The method for manufacturing the target assembly according to the present invention described above is not particularly limited. For example, the method described in
以下、実施例を挙げて本発明をより具体的に説明するが、本発明は下記実施例によって制限されず、前・後記の趣旨に適合し得る範囲で変更を加えて実施することも可能であり、それらはいずれも本発明の技術的範囲に包含される。 Hereinafter, the present invention will be described in more detail with reference to examples, but the present invention is not limited by the following examples, and can be implemented with modifications within a range that can meet the purpose described above and below. They are all included in the technical scope of the present invention.
実施例1
本実施例では、本発明で裏打ち部材の構成成分として選択したX群元素(Ni、Si、Hf、Ta)を含む酸化物半導体薄膜を備えたTFTが、移動度および良好なTFT特性を有することを調べた。
Example 1
In this example, a TFT including an oxide semiconductor thin film containing an X group element (Ni, Si, Hf, Ta) selected as a constituent component of a backing member in the present invention has mobility and good TFT characteristics. I investigated.
本実施例では、以下のようにしてTFTを製造した。まず、ガラス基板(コーニング社製イーグル2000、直径100mm×厚さ0.7mm)上に、ゲート電極としてTi薄膜を100nm、およびゲート絶縁膜SiO2(200nm)を順次成膜した。ゲート電極は純Tiのスパッタリングターゲットを使用し、DCスパッタ法により、成膜温度:室温、成膜パワー:300W、キャリアガス:Ar、ガス圧:2mTorrにて成膜した。また、ゲート絶縁膜はプラズマCVD法を用い、キャリアガス:SiH4とN2Oの混合ガス、成膜パワー:100W、成膜温度:300℃にて成膜した。 In this example, a TFT was manufactured as follows. First, a Ti thin film of 100 nm and a gate insulating film SiO 2 (200 nm) were sequentially formed as a gate electrode on a glass substrate (Corning Eagle 2000, diameter 100 mm × thickness 0.7 mm). The gate electrode was formed using a pure Ti sputtering target by DC sputtering at a film forming temperature: room temperature, a film forming power: 300 W, a carrier gas: Ar, and a gas pressure: 2 mTorr. The gate insulating film was formed by plasma CVD using a carrier gas: a mixed gas of SiH 4 and N 2 O, a deposition power of 100 W, and a deposition temperature of 300 ° C.
次に、表1に記載の種々の組成の酸化物薄膜を、スパッタリングターゲット(後記する。)を用いて成膜した。スパッタリングは、(株)アルバック製「CS-200」装置を使用し、DCスパッタ法により、成膜温度:室温、成膜パワー:200W、ガス圧:1mTorr、酸素分圧:100×O2/(Ar+O2)=10%、使用ターゲットサイズ:101.6mmの条件で、膜厚:50nmのIGZO薄膜を成膜した[In:Ga:Zn:O=1:1:1:4(原子比)]。 Next, oxide thin films having various compositions described in Table 1 were formed using a sputtering target (described later). Sputtering uses a “CS-200” apparatus manufactured by ULVAC, Inc., and is formed by DC sputtering using a film forming temperature: room temperature, film forming power: 200 W, gas pressure: 1 mTorr, oxygen partial pressure: 100 × O 2 / ( An IGZO thin film with a film thickness of 50 nm was formed under the conditions of Ar + O 2 ) = 10% and target target size: 101.6 mm [In: Ga: Zn: O = 1: 1: 1: 4 (atomic ratio)] .
酸化物薄膜としては、IGZO中にX元素を含むIGZO-Xのほか、比較のため、IGZO、およびIGZO中にX群元素以外の元素(Cu、Cr、Mo)を含むものも成膜した。 As the oxide thin film, in addition to IGZO-X containing X element in IGZO, for comparison, IGZO and IGZO containing an element (Cu, Cr, Mo) other than X group element were also formed.
これらのうち、IGZOの成膜にあたっては、In:Ga:Znの比(原子比)が1:1:1であるスパッタリングターゲットを用い、IGZO中に他の元素を含む酸化物半導体薄膜の成膜にあたっては、組成の異なる2つのスパッタリングターゲットを同時放電するCo-Sputter法を用いて成膜した。詳細にはスパッタリングターゲットとして、In:Ga:Zn=1:1:1であるスパッタリングターゲットと、上記スパッタリングターゲット上に、X群元素、Cu、Cr、またはMoの純金属チップを装着したターゲットの2つを用いた。 Among these, in forming an IGZO film, a sputtering target having an In: Ga: Zn ratio (atomic ratio) of 1: 1: 1 is used to form an oxide semiconductor thin film containing other elements in the IGZO. In this case, a film was formed using a Co-Sputter method in which two sputtering targets having different compositions were discharged simultaneously. Specifically, as a sputtering target, a sputtering target having In: Ga: Zn = 1: 1: 1, and a target in which a pure metal chip of an X group element, Cu, Cr, or Mo is mounted on the sputtering target. One was used.
このようにして得られた酸化物薄膜中の金属元素の各含有量は、XPS(X-ray Photoelectron Spectroscopy)法によって分析した。詳細には、最表面から5nm程度深さまでの範囲をArイオンにてスパッタリングした後、下記条件にて分析を行なった。
X線源:Al Kα
X線出力:350W
光電子取り出し角:20°
Each content of the metal element in the oxide thin film thus obtained was analyzed by an XPS (X-ray Photoelectron Spectroscopy) method. Specifically, after sputtering the range from the outermost surface to a depth of about 5 nm with Ar ions, analysis was performed under the following conditions.
X-ray source: Al K α
X-ray output: 350W
Photoelectron extraction angle: 20 °
上記のようにして酸化物半導体薄膜を成膜した後、フォトリソグラフィーおよびウエットエッチングによりパターニングを行った。ウエットエッチャント液としては、関東化学製「ITO-07N」を使用した。 After forming the oxide semiconductor thin film as described above, patterning was performed by photolithography and wet etching. “ITO-07N” manufactured by Kanto Chemical Co., Ltd. was used as the wet etchant solution.
酸化物半導体薄膜をパターニングした後、膜質を向上させるためにプレアニール処理を行った。プレアニールは、100%酸素雰囲気、大気圧下にて、350℃で1時間行った。 After patterning the oxide semiconductor thin film, a pre-annealing process was performed to improve the film quality. The pre-annealing was performed at 350 ° C. for 1 hour in a 100% oxygen atmosphere and atmospheric pressure.
次に、純Tiを使用し、リフトオフ法によりソース・ドレイン電極を形成した。具体的にはフォトレジストを用いてパターニングを行った後、Ti薄膜をDCスパッタリング法により成膜(膜厚は100nm)した。ソース・ドレイン電極用Ti薄膜の成膜方法は、前述したゲート電極の場合と同じである。ついで、アセトン中で超音波洗浄器にかけて不要なフォトレジストを除去し、TFTのチャネル長を10μm、チャネル幅を200μmとした。 Next, pure Ti was used to form source / drain electrodes by a lift-off method. Specifically, after patterning using a photoresist, a Ti thin film was formed by DC sputtering (film thickness was 100 nm). The method for forming the Ti thin film for the source / drain electrodes is the same as that for the gate electrode described above. Subsequently, unnecessary photoresist was removed by applying an ultrasonic cleaner in acetone, and the channel length of the TFT was 10 μm and the channel width was 200 μm.
このようにしてソース・ドレイン電極を形成した後、酸化物半導体を保護するための保護膜を形成した。保護膜としては、SiO2(膜厚200nm)とSiN(膜厚200nm)の積層膜を用いた。上記SiO2およびSiNの形成は、サムコ製「PD-220NL」を用い、プラズマCVD法を用いて行った。本実施例ではN2Oガスによってプラズマ処理を行った後、SiO2、およびSiN膜を順次形成した。SiO2膜の形成にはN2OおよびSiH4の混合ガスを用い、SiN膜の形成にはSiH4、N2、NH3の混合ガスを用いた。いずれも成膜パワーを100W、成膜温度を150℃とした。 After forming the source / drain electrodes in this manner, a protective film for protecting the oxide semiconductor was formed. As the protective film, a laminated film of SiO 2 (film thickness 200 nm) and SiN (film thickness 200 nm) was used. The formation of the SiO 2 and SiN was performed using “PD-220NL” manufactured by Samco and using the plasma CVD method. In this embodiment, after performing plasma treatment with N 2 O gas, SiO 2 and SiN films were sequentially formed. A mixed gas of N 2 O and SiH 4 was used for forming the SiO 2 film, and a mixed gas of SiH 4 , N 2 , and NH 3 was used for forming the SiN film. In both cases, the film formation power was 100 W, and the film formation temperature was 150 ° C.
次にフォトリソグラフィー、およびドライエッチングにより、保護膜にトランジスタ特性評価用プロービングのためのコンタクトホールを形成した。次に、DCスパッタリング法を用い、キャリアガス:アルゴン及び酸素ガスの混合ガス、成膜パワー:200W、ガス圧:5mTorrにてITO膜(膜厚80nm)を成膜し、TFTを作製した。 Next, contact holes for probing for transistor characteristic evaluation were formed in the protective film by photolithography and dry etching. Next, an ITO film (film thickness: 80 nm) was formed using a DC sputtering method with a carrier gas: a mixed gas of argon and oxygen gas, a film formation power: 200 W, and a gas pressure: 5 mTorr, to manufacture a TFT.
このようにして得られた各TFTについて、以下のようにして、トランジスタ特性(ドレイン電流-ゲート電圧特性、Id-Vg特性)、オン電流、SS値、および電界効果移動度(以下、「移動度」と称す場合がある)μFEを求めた。 For each TFT thus obtained, transistor characteristics (drain current-gate voltage characteristics, Id-Vg characteristics), on-current, SS value, and field-effect mobility (hereinafter referred to as “mobility”) are as follows. ) FE was determined.
(1)トランジスタ特性の測定
トランジスタ特性(Id-Vg特性)は、Agilent Technology社製「4156C」の半導体パラメータアナライザーを使用した。詳細な測定条件は以下のとおりである。
ソース電圧:0V
ドレイン電圧:10V
ゲート電圧:-30V~30V(測定間隔:1V)
(1) Measurement of transistor characteristics For transistor characteristics (Id-Vg characteristics), a semiconductor parameter analyzer “4156C” manufactured by Agilent Technology was used. Detailed measurement conditions are as follows.
Source voltage: 0V
Drain voltage: 10V
Gate voltage: -30V to 30V (measurement interval: 1V)
(2)オン電流およびSS値
オン電流とは、ゲート電圧が30Vのドレイン電流で、トランジスタがオン状態のときの電流値であり、ドレイン電流を一桁増加させるのに必要なゲート電圧の最小値をSS値とした。
(2) On-current and SS value The on-current is a drain current with a gate voltage of 30 V and is a current value when the transistor is in an on state, and is the minimum value of the gate voltage required to increase the drain current by one digit. Was the SS value.
(3)移動度μFE
電界効果移動度μFEは、TFT特性からVg>Vd-Vthである線形領域にて導出した。線形領域ではVg、Vdをそれぞれゲート電圧、ドレイン電圧、Vthをドレイン電流が1nAを超えたときの電圧、Idをドレイン電流、L、WをそれぞれTFT素子のチャネル長、チャネル幅、Ciをゲート絶縁膜の静電容量、μFEを電界効果移動度とした。μFEは以下の式から導出される。本実施例では、線形領域を満たすゲート電圧付近におけるドレイン電流-ゲート電圧特性(Id-Vg特性)の傾きから電界効果移動度μFEを導出した。
(3) Mobility μ FE
The field effect mobility μ FE was derived from the TFT characteristics in a linear region where V g > V d −V th . In the linear region, V g and V d are the gate voltage and drain voltage, V th is the voltage when the drain current exceeds 1 nA, I d is the drain current, L and W are the channel length and channel width of the TFT element, respectively. C i is the capacitance of the gate insulating film, and μ FE is the field effect mobility. μ FE is derived from the following equation. In this example, the field effect mobility μ FE was derived from the slope of the drain current-gate voltage characteristic (Id-Vg characteristic) in the vicinity of the gate voltage satisfying the linear region.
本実施例では、このようにして得られた各移動度を、IGZOの移動度を100%としたときの百分率(IGZOに対する比率)に換算し、下記基準に基づいて評価した。
◎:IGZOに対する比率が90%以上
○:IGZOに対する比率が70%以上、90%未満
△:IGZOに対する比率が50%以上、70%未満
×:IGZOに対する比率が50%未満
In this example, each mobility obtained in this way was converted into a percentage (ratio to IGZO) when the mobility of IGZO was 100%, and evaluated based on the following criteria.
◎: Ratio to IGZO is 90% or more ○: Ratio to IGZO is 70% or more and less than 90% △: Ratio to IGZO is 50% or more and less than 70% ×: Ratio to IGZO is less than 50%
これらの結果を表1、表2、および図3(a)~(g)に示す。 These results are shown in Tables 1 and 2 and FIGS. 3 (a) to (g).
まず、表1を参照する。表1には、IGZOに各元素を添加したときの、移動度の結果を示す。なお、表1には、X群元素(Ni、Si、Hf、Ta)、従来例(Mo)、比較例(Cu、Cr)のほか、参考のため、Al、Ge、Sn、Tiの結果を示している。各元素の添加量[IGZOに対する添加量(原子%)]は、2原子%である。 First, refer to Table 1. Table 1 shows the results of mobility when each element is added to IGZO. Table 1 shows the results of Al, Ge, Sn, and Ti for reference in addition to the X group elements (Ni, Si, Hf, Ta), the conventional example (Mo), and the comparative examples (Cu, Cr). Show. The addition amount of each element [addition amount with respect to IGZO (atomic%)] is 2 atomic%.
更に表1には、各元素の比重の値も併記している。この値は、JISハンドブックから引用したものである。 Furthermore, Table 1 also shows the specific gravity values of each element. This value is taken from the JIS handbook.
表1より、本発明に用いられる裏打ち部材の材料として選択したX群元素(Ni、Si、Hf、Ta)をIGZOに添加すると、いずれも、良好な移動度を有することが分かる。また、Siを除き、Ni、Hf、Taは、代表的な低融点ハンダボンディング材料であるInおよびSnに比べて比重が大きいため、ターゲット組立体の作業性の点においても非常に有用である。 From Table 1, it can be seen that when the X group element (Ni, Si, Hf, Ta) selected as the material of the backing member used in the present invention is added to IGZO, all have good mobility. In addition to Si, Ni, Hf, and Ta have a higher specific gravity than In and Sn, which are typical low melting point solder bonding materials, and thus are very useful in terms of workability of the target assembly.
これに対し、CuやCrをIGZOに添加した場合には、良好な移動度が得られなかった。また、AlやGeは、本実施例の酸化物組成においては、上記X群元素を添加したほどの高い移動度は得られなかった。また、これらの元素は、InおよびSnに比べて比重が小さいため、ターゲット組立体の作業性に劣る。 On the other hand, when Cu or Cr was added to IGZO, good mobility could not be obtained. In addition, Al and Ge did not have such a high mobility as the X group element was added in the oxide composition of this example. In addition, since these elements have a lower specific gravity than In and Sn, the workability of the target assembly is inferior.
次に表2を参照する。表2には、IGZOに対し、X群元素(Ni、Si、Hf、Ta)の添加量を種々変化させた酸化物半導体薄膜を用いたときの、オン電流とSS値の結果を示している。表2において、X群元素の添加量は、IGZOに対する添加量(原子%)である。 Next, refer to Table 2. Table 2 shows the results of on-state current and SS value when using oxide semiconductor thin films in which the addition amount of the X group element (Ni, Si, Hf, Ta) is variously changed with respect to IGZO. . In Table 2, the addition amount of the group X element is the addition amount (atomic%) with respect to IGZO.
表2より、IGZOにX群元素を添加すると、X群元素を添加しない従来のIGZOを用いたときと同程度またはそれ以上のオン電流およびSS値が得られ、良好なTFT特性が得られることが確認された。 Table 2 shows that when an X group element is added to IGZO, an on-current and an SS value equal to or higher than those obtained when a conventional IGZO not containing an X group element is used, and good TFT characteristics are obtained. Was confirmed.
これに対し、IGZOにCuまたはCrを添加すると、オン電流が低下した。なお、SS値は、トランジスタの静特性が得られておらず、スイッチングしなかったため測定しなかった(表2には「-」と記載)。 On the other hand, when Cu or Cr was added to IGZO, the on-current decreased. Note that the SS value was not measured because the static characteristics of the transistor were not obtained and switching was not performed (described as “−” in Table 2).
また、IGZOにMoを添加すると、従来のIGZOに比べて、オン電流、SS値のいずれも劣化した。 Also, when Mo was added to IGZO, both the on-current and SS value were degraded as compared to conventional IGZO.
次に図3(a)~(g)を参照する。図3(a)~(g)は、表2に示す実験例のうち、X群元素(添加量2原子%)、またはCu、Cr、Mo(いずれも添加量0.5原子%)を含むときのId-Vg特性の結果を示している。図3(a)~(g)には、2回の測定結果を示している。
Next, refer to FIGS. 3 (a) to 3 (g). 3 (a) to 3 (g) include, among the experimental examples shown in Table 2, an X group element (
図3(a)~(g)より、IGZOにX群元素を添加したものは、いずれも、良好なスイッチング特性を示すのに対し、Cu、Cr、Moを添加すると、いずれもトランジスタがスイッチングしなかった。 3 (a) to 3 (g), all of the IGZO added with the group X element exhibit good switching characteristics, but when Cu, Cr, or Mo is added, the transistor switches in any case. There wasn't.
これらの実験結果より、上記X群元素は、IGZOの移動度およびTFT特性を向上させる元素として極めて有用であり、Siを除く上記X群元素は、ターゲット組立体の作業効率を高めるうえでも、非常に有用であることが確認された。これらの実験結果は、ターゲット組立体を用いて酸化物薄膜をスパッタリング法で製造する際、ターゲット隙間から上記X群元素が侵入したとしても、隙間に対応する基板位置には、上記酸化物に上記X群元素を含む薄膜(TFT特性向上に有用な酸化物薄膜)が形成されるため、成膜後の酸化物半導体薄膜のTFT特性は劣化しないことを示すものであり、X群元素の一種または二種以上で構成される裏打ち部材の有用性を、間接的に実証するものである。 From these experimental results, the X group element is extremely useful as an element for improving the mobility and TFT characteristics of IGZO, and the X group element excluding Si is extremely useful for improving the working efficiency of the target assembly. It was confirmed that it was useful. These experimental results show that when the oxide thin film is manufactured by the sputtering method using the target assembly, even if the X group element enters from the target gap, the oxide is placed on the oxide at the substrate position corresponding to the gap. This indicates that since a thin film containing an X group element (an oxide thin film useful for improving TFT characteristics) is formed, the TFT characteristics of the oxide semiconductor thin film after film formation do not deteriorate. The usefulness of a backing member composed of two or more types is indirectly verified.
なお、本実施例では、酸化物としてIGZOを用いたときの結果を示しているが、本発明で対象とするすべての酸化物についても、同様の結果が得られると考えられる。 In addition, although the result when using IGZO as an oxide is shown in the present Example, it is thought that the same result is obtained also about all the oxides made into object by this invention.
実施例2
本実施例では、裏打ち部材としての有用性を比較検討するため、純Ni(本発明例)または純Cu(比較例)を用いてターゲット組立体を製造し、TFT特性を評価した。
Example 2
In this example, in order to compare and examine the usefulness as a backing member, a target assembly was manufactured using pure Ni (example of the present invention) or pure Cu (comparative example), and TFT characteristics were evaluated.
まず、ターゲット組立体は、前述した好ましい実施形態の製造方法により製造した。本実施例では、バッキングプレートとして純Cuのバッキングプレート(φ132mm、厚さ8.5mm)、ボンディング材としてIn基合金、スペーサーとしてCuワイヤを用いた。酸化物ターゲット部材間の間隔Tの幅は0.3mmとした。 First, the target assembly was manufactured by the manufacturing method of the preferred embodiment described above. In this example, a pure Cu backing plate (φ132 mm, thickness 8.5 mm) was used as the backing plate, an In-based alloy was used as the bonding material, and a Cu wire was used as the spacer. The width of the interval T between the oxide target members was 0.3 mm.
次に、上記ターゲット組立体を用いたこと以外は実施例1と同様にしてTFTを作製し、オン電流およびSS値を評価した。なお、スパッタリング後の厚さ(残存厚さ)は、6mmまたは1mmとなるように行なった。 Next, a TFT was produced in the same manner as in Example 1 except that the target assembly was used, and the on-current and SS value were evaluated. The thickness after sputtering (residual thickness) was 6 mm or 1 mm.
また、参考のため、隙間なしのターゲット組立体を用いて、上記と同様にして各特性を評価した。実操業下では、前述したようにターゲット部材の間に隙間を設けたターゲット組立体を製造するが、本実施例では、隙間部の影響を排除した参考例を得るため、便宜上、隙間なしのターゲット組立体を用いた。 For reference, each characteristic was evaluated in the same manner as described above using a target assembly without a gap. Under actual operation, as described above, a target assembly having a gap between target members is manufactured. In this embodiment, a target without a gap is used for convenience in order to obtain a reference example that eliminates the influence of the gap. An assembly was used.
これらの結果を表3、表4および図4に示す。図4は、表3および表4に記載の各条件におけるId-Vg特性を示す図である。 These results are shown in Table 3, Table 4 and FIG. FIG. 4 is a graph showing Id-Vg characteristics under the conditions described in Table 3 and Table 4.
これらの結果より、Ni製の裏打ち部材を用いた場合、隙間なしのターゲット組立体を用いた場合と同程度の、良好なオン電流およびSS値が得られた。これらの結果は、スパッタリング後の厚さにかかわらず、見られた。 From these results, when the Ni backing member was used, good on-current and SS values comparable to those when the target assembly without a gap was used were obtained. These results were seen regardless of the thickness after sputtering.
これに対し、Cu製の裏打ち部材を用いた場合は、オン電流およびSS値の各特性が低下した。特に表4に示すように、スパッタリング後の厚さが1mmになると、上記特性の低下が一層顕著に見られるようになり、オン電流が著しく低下し、SS値は著しく増加した。 On the other hand, when a Cu backing member was used, the on-current and SS value characteristics were degraded. In particular, as shown in Table 4, when the thickness after sputtering became 1 mm, the above-mentioned characteristics were more markedly reduced, the on-current was significantly reduced, and the SS value was significantly increased.
本出願を詳細にまた特定の実施態様を参照して説明したが、本発明の精神と範囲を逸脱することなく様々な変更や修正を加えることができることは当業者にとって明らかである。
本出願は、2012年7月20日出願の日本特許出願(特願2012-162125)に基づくものであり、その内容はここに参照として取り込まれる。
Although this application has been described in detail and with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention.
This application is based on a Japanese patent application filed on July 20, 2012 (Japanese Patent Application No. 2012-162125), the contents of which are incorporated herein by reference.
本発明のターゲット組立体では、酸化物ターゲット部材とバッキングプレートとの間に、間隔を跨いで配置される裏打ち部材を設けることにより、バッキングプレートの成分が薄膜中に混入(コンタミ)するのを防止することができる。さらに、裏打ち部材として、酸化物半導体薄膜のTFT特性を劣化させない所定金属元素(Ni、Si、Hf、およびTa)の少なくとも一種または二種以上からなる材料を用いているため、酸化物半導体薄膜中に上記所定金属元素がコンタミしたとしても、コンタミによるTFT特性の劣化を防止することができ、良好なTFT特性を保つことができる。 In the target assembly of the present invention, by providing a backing member disposed across the gap between the oxide target member and the backing plate, the components of the backing plate are prevented from being mixed (contaminated) into the thin film. can do. Further, since the backing member is made of a material composed of at least one or more of predetermined metal elements (Ni, Si, Hf, and Ta) that do not deteriorate the TFT characteristics of the oxide semiconductor thin film, Even if the predetermined metal element is contaminated, deterioration of TFT characteristics due to contamination can be prevented, and good TFT characteristics can be maintained.
1 ターゲット組立体
2 スパッタリングターゲット
3 バッキングプレート
4a~4d 酸化物ターゲット部材
5 裏打ち部材
11a、11b、11c 低融点ハンダボンディング材
12 スペーサー
T 間隔
Q 間隔Tの直下部分
DESCRIPTION OF
Claims (6)
前記酸化物ターゲット部材と前記バッキングプレートとの間に、前記間隔を跨いで設けられた、Ni、Si、Hf、およびTaよりなる群から選択される一種または二種以上からなる裏打ち部材を有することを特徴とするターゲット組立体。 A target assembly in which a plurality of oxide target members are arranged at intervals on a backing plate via a bonding material,
Between the oxide target member and the backing plate, having a backing member made of one or more selected from the group consisting of Ni, Si, Hf, and Ta provided across the gap A target assembly.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020157001469A KR101643510B1 (en) | 2012-07-20 | 2013-07-19 | Target assembly |
| CN201380031944.9A CN104379802B (en) | 2012-07-20 | 2013-07-19 | Target assembly |
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| Application Number | Priority Date | Filing Date | Title |
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| JP2012-162125 | 2012-07-20 | ||
| JP2012162125A JP6059460B2 (en) | 2012-07-20 | 2012-07-20 | Target assembly |
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| JP (1) | JP6059460B2 (en) |
| KR (1) | KR101643510B1 (en) |
| CN (1) | CN104379802B (en) |
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| WO (1) | WO2014014091A1 (en) |
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| JP6359901B2 (en) * | 2014-07-16 | 2018-07-18 | 三菱マテリアル株式会社 | Sputtering target |
| JP2017014562A (en) * | 2015-06-30 | 2017-01-19 | 株式会社コベルコ科研 | Sputtering target assembly |
| JP7311290B2 (en) * | 2019-03-27 | 2023-07-19 | Jx金属株式会社 | Segmented sputtering target and manufacturing method thereof |
| WO2021084838A1 (en) * | 2019-11-01 | 2021-05-06 | 三井金属鉱業株式会社 | Gap-filling member |
Citations (5)
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|---|---|---|---|---|
| JPH08170170A (en) * | 1994-12-16 | 1996-07-02 | Tosoh Corp | Sputtering target |
| JPH10121232A (en) * | 1996-10-14 | 1998-05-12 | Mitsubishi Chem Corp | Sputtering target |
| WO2010070832A1 (en) * | 2008-12-15 | 2010-06-24 | 出光興産株式会社 | Sintered complex oxide and sputtering target comprising same |
| JP2011122238A (en) * | 2009-11-13 | 2011-06-23 | Semiconductor Energy Lab Co Ltd | Sputtering target and manufacturing method thereof, and transistor |
| WO2012063524A1 (en) * | 2010-11-08 | 2012-05-18 | 三井金属鉱業株式会社 | Divided sputtering target and method for producing same |
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| JP3759673B2 (en) | 1998-01-12 | 2006-03-29 | 三井金属鉱業株式会社 | Sputtering target and manufacturing method thereof |
| CN100396813C (en) * | 2002-08-02 | 2008-06-25 | 出光兴产株式会社 | Sputtering target, sintered body, conductive film produced using the same, organic EL element, and substrate used for the same |
| JP5244331B2 (en) * | 2007-03-26 | 2013-07-24 | 出光興産株式会社 | Amorphous oxide semiconductor thin film, manufacturing method thereof, thin film transistor manufacturing method, field effect transistor, light emitting device, display device, and sputtering target |
| JP5213458B2 (en) | 2008-01-08 | 2013-06-19 | キヤノン株式会社 | Amorphous oxide and field effect transistor |
| JP5377142B2 (en) * | 2009-07-28 | 2013-12-25 | ソニー株式会社 | Target manufacturing method, memory manufacturing method |
| JP2012124446A (en) * | 2010-04-07 | 2012-06-28 | Kobe Steel Ltd | Oxide for semiconductor layer of thin film transistor and sputtering target, and thin film transistor |
-
2012
- 2012-07-20 JP JP2012162125A patent/JP6059460B2/en not_active Expired - Fee Related
-
2013
- 2013-07-19 CN CN201380031944.9A patent/CN104379802B/en not_active Expired - Fee Related
- 2013-07-19 KR KR1020157001469A patent/KR101643510B1/en not_active Expired - Fee Related
- 2013-07-19 WO PCT/JP2013/069670 patent/WO2014014091A1/en not_active Ceased
- 2013-07-19 TW TW102125929A patent/TW201413023A/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08170170A (en) * | 1994-12-16 | 1996-07-02 | Tosoh Corp | Sputtering target |
| JPH10121232A (en) * | 1996-10-14 | 1998-05-12 | Mitsubishi Chem Corp | Sputtering target |
| WO2010070832A1 (en) * | 2008-12-15 | 2010-06-24 | 出光興産株式会社 | Sintered complex oxide and sputtering target comprising same |
| JP2011122238A (en) * | 2009-11-13 | 2011-06-23 | Semiconductor Energy Lab Co Ltd | Sputtering target and manufacturing method thereof, and transistor |
| WO2012063524A1 (en) * | 2010-11-08 | 2012-05-18 | 三井金属鉱業株式会社 | Divided sputtering target and method for producing same |
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| CN104379802B (en) | 2017-04-05 |
| JP6059460B2 (en) | 2017-01-11 |
| TW201413023A (en) | 2014-04-01 |
| KR20150023817A (en) | 2015-03-05 |
| JP2014019930A (en) | 2014-02-03 |
| TWI561657B (en) | 2016-12-11 |
| KR101643510B1 (en) | 2016-07-27 |
| CN104379802A (en) | 2015-02-25 |
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