Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
  • H03F1/52—Circuit arrangements for protecting such amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages

Definitions

• PA over power protection method and device The present application claims priority to Chinese patent application filed on July 6, 2012, the Chinese Patent Office, the application number is 201210235209.7, and the invention name is "a PA over power protection method and device" The entire contents of which are incorporated herein by reference.
• the present invention relates to the field of communications technologies, and in particular, to a power amplifier (PA) overpower protection method and apparatus.
• PA power amplifier
• Time Division Synchronized Code Division Multiple Access (TD-SCDMA) and Time Division Long Term Evolution (TD-LTE) are the current mainstream 3G and 4G wireless communication technology standards.
• the power amplifier (PA) used in the base station equipment is an important device to ensure seamless coverage and reasonable cost performance of the system. How to maximize the protection of the PA and extend the service life of the PA is one of the technical issues that are of primary concern to manufacturers and operators of wireless communication equipment.
• the high power amplifier used in the base station equipment of the wireless communication system operates at a frequency of GHz (GHZ), the rated output power is above 40 dbm, and the gain characteristic at the rated output power is also above 40 db (where dbm is A unit that characterizes the absolute value of power, calculated as lOlog (power value / 1 mW); db is a unit that characterizes the relative value of power, calculated as lOlog (power value 1 / power value 2), using a multistage amplifier
• the structure is realized.
• the protection requirement for the design of this high-power amplifier is mainly that under abnormal conditions, the PA can work for several minutes without full-loading +3dB of output power without burning.
• the abnormal situation can be generally divided into the input side abnormality and the output side abnormality.
• the input side abnormality usually has an abnormality caused by the full load or the overload input
• the output side abnormality usually has an abnormality caused by the short circuit of the antenna port and the open circuit.
• it can be solved in the analog part by designing the current monitoring of the PA and the hardware over-power protection circuit, or by using the pre-prevention and corresponding post-processing design in the digital part.
• the phase output after digital up conversion (DUC), crest factor reduction (CFR), and digital pre-distortion (DPD) is counted in each downlink time slot.
• the inphase and quadrature signals (II Q ) data of the amplitude signal That is, respectively, statistically detecting the energy value ⁇ ( z2 + ) in the downlink time slot of each antenna, where i represents the above-mentioned in-phase component, q represents the above-mentioned orthogonal component, and the sum of the squares of the two corresponds to one or a fraction of a chip.
• the power that is, the energy value, is multi-point accumulated to obtain the energy and value in a certain period of time.
• the length of the time slot counted in the over-power protection is 256 chips. Then, compare this value with the set power protection threshold pwr threshold. When 3 ⁇ 4 2 + 2 ) > pwr _ threshold, the downlink automatically turns off the corresponding antenna. Conversely, if 50 consecutive statistical ⁇ (/ 2 + ⁇ 2 ) ⁇ pwr threshold is detected, that is, when there is no data mutation (energy abnormality), the downlink automatically turns on the corresponding antenna to achieve protection against ⁇ .
• the embodiment of the invention provides a method and device for bypassing power protection, which is used to achieve more complete overpower protection for ⁇ .
• a PA over power protection method provided by an embodiment of the present invention includes:
• a first protection unit configured to calculate each of the first time for the in-phase component and the quadrature component data of the phase- and amplitude-amplitude signals processed by the digitally up-converted DUC, the crest factor-attenuation CFR, and the digital pre-distortion DPD for each antenna The sum of the energy values of the in-phase component data of the phase and amplitude signals in the length and the energy values of the quadrature component data, to obtain a first sum value, and comparing the first sum value with a preset first power protection threshold value, When the first sum value of any antenna is greater than a preset first power protection threshold, the downlink of the antenna is turned off;
• a second protection unit configured to calculate in-phase and quadrature component data of the phase and amplitude signals processed by the DUC, CFR, and DPD for each antenna, and calculate in-phase of the phase and amplitude signals in each second time length respectively
• the sum of the energy value of the component data and the energy value of the orthogonal component data, the second sum value is obtained, and the second sum value is compared with a preset second power protection threshold value, when the second sum value of any antenna
• the second power protection threshold is greater than the preset, the in-phase component and the quadrature component data of the phase and amplitude signals in the second time length are cleared to be sent to the PA;
• the second time length is less than the first time length, and the first power protection threshold is less than the second power protection threshold.
• a first energy value statistic unit for calculating each of the in-phase component and the quadrature component data of the phase- and amplitude-amplitude signals processed by the digitally up-converted DUC, the crest factor-attenuation CFR, and the digital pre-distortion DPD for each antenna The sum of the energy values of the in-phase component data of the phase and amplitude signals and the energy values of the quadrature component data over a length of time to obtain a first sum value;
• a first comparison processing unit configured to compare the first sum value with a preset first power protection threshold, and when the first sum value of any antenna is greater than a preset first power protection threshold, a downlink of the antenna, wherein the A length of time is less than 256 chips.
• a second energy value statistic unit for calculating each of the in-phase component and the quadrature component data of the phase- and amplitude-amplitude signals processed by the digitally up-converted DUC, the crest factor-attenuation CFR, and the digital pre-distortion DPD for each antenna a sum of the energy values of the in-phase component data of the phase and amplitude signals and the energy values of the quadrature component data over a length of time to obtain a second sum value;
• a second comparison processing unit configured to compare the second sum value with a preset second power protection threshold, when the second sum value of any antenna is greater than a preset second power protection threshold,
• the in-phase component and the quadrature component data of the phase and amplitude signals in the second time length are cleared and sent to the PA, wherein the second time length is less than 1 chip.
• the in-phase component data of the phase and amplitude signals in each first time length are respectively calculated for the in-phase component and the quadrature component data of the phase and amplitude signals processed by the DUC, CFR, and DPD for each antenna.
• the sum of the energy value and the energy value of the orthogonal component data, the first sum value is obtained, and the first sum value is compared with a preset first power protection threshold value, when the first sum value of any antenna is greater than the pre-
• the downlink of the antenna is turned off; and the in-phase component and the quadrature component data of the phase and amplitude signals processed by the DUC, CFR, and DPD for each antenna are respectively calculated
• the sum of the energy value of the in-phase component data of the phase and amplitude signals and the energy value of the quadrature component data in each second time length to obtain a second sum value, and the second sum value and the preset second power protection gate Comparing the limit values, when the second sum value of any antenna is greater than a preset second power protection threshold, the in-phase component and the orthogonal component of the phase and amplitude signals in the second time length After the quantity data is cleared, the data is sent to the PA.
• the second time length is less than the first time length, and the first power protection threshold is less than the second power protection threshold, so that the hardware design complexity can be increased.
• the next step is to provide more complete protection for the PA, effectively reducing production costs and equipment operation and maintenance costs.
• FIG. 1 is a schematic flowchart of a PA over power protection method according to an embodiment of the present invention
• FIG. 2 is a schematic flowchart of a PA over power protection method according to an embodiment of the present invention
• FIG. 3 is a schematic flowchart of a PA over power protection method according to an embodiment of the present invention.
• FIG. 4 is a schematic structural diagram of a PA over-power protection device according to an embodiment of the present invention.
• FIG. 5 is a schematic structural diagram of a PA over-power protection device according to an embodiment of the present invention.
• FIG. 6 is a schematic structural diagram of a PA over-power protection device according to an embodiment of the present invention. detailed description
• the embodiment of the invention provides a PA over power protection method and device for implementing more complete over power protection for the PA.
• the technical solution proposed by the embodiment of the present invention can be used for enhancing power protection of a PA in a TD-LTE and a TD-SCDMA base station, so that it is not necessary to design a complex PA current monitoring and hardware over-power protection circuit by using a digital domain.
• the algorithm flow solves the PA damage problem caused by various abnormal conditions in the entire PA input front end.
• the technical solution proposed by the embodiment of the present invention can be used for Universal Telecommunication Radio Access (UTRA) Frequency Division Duplex (FDD), UTRA Time Division Duplex (TDD), TD - Any other high-power data transmission occasions such as SCDMA, TD-LTE, etc., can be completely used by software, or can be implemented by software and hardware coordination or System On Chip (SOC). It can be integrated as a design IP in various needs. System application.
• UTRA Universal Telecommunication Radio Access
• FDD Frequency Division Duplex
• TDD Time Division Duplex
• TD- Any other high-power data transmission occasions such as SCDMA, TD-LTE, etc.
• SOC System On Chip
• the present invention can provide more complete protection for the PA without affecting the complexity of the hardware design, and at the same time take into account the impact on the system performance, thereby effectively Reduce hardware production costs, improve system performance and reduce equipment maintenance costs.
• a power amplifier PA over power protection method provided by an embodiment of the present invention includes the following steps:
• the second time length is less than the first time length, and the first power protection threshold is less than the second power protection threshold.
• steps S101 and S102 may be interchanged, or may be performed in parallel, that is, may be performed simultaneously or sequentially, without a certain order relationship with each other.
• the method further includes:
• the preset number of times is 200 times.
• the first length of time is 32 chips.
• step S101 or S102 may be performed, and the effect of overpower protection may also be exerted.
• a power amplifier ⁇ power protection method provided by an embodiment of the present invention includes the following steps:
• S202 Compare the first sum value with a preset first power protection threshold, and when the first sum value of any antenna is greater than a preset first power protection threshold, turn off the downlink of the antenna. Wherein the first time length is less than 256 chips.
• the method further includes:
• a power amplifier PA overpower protection method provided by an embodiment of the present invention includes:
• the S30K calculates the energy values of the in-phase component data of the phase and amplitude signals for each second time length for the in-phase component and the quadrature component data of the phase and amplitude signals processed by the DUC, CFR, and DPD for each antenna, respectively.
• the following is an example of a dual-mode base station remote radio unit (RRU) for TD-SCDMA and TD-LTE.
• RRU remote radio unit
• the design idea of optimizing statistical energy over-power protection using the digital part has not changed.
• the specific implementation change is to use a shorter statistical interval and a faster recovery interval, that is, in each downlink time slot, for each antenna.
• the I/Q data output after DUC+CFR+DPD is used to count the energy value ⁇ ( ⁇ ' 2 + ⁇ ) of the I/Q data of each antenna in each first time length.
• the first time length may be 32 chips (this value may be appropriately adjusted, for example, the value may be in the range of 16 to 48 chips, which may be determined by long-term system testing according to actual needs), that is, for each The antenna counts the energy value of the I/Q data output after each DUC+CFR+DPD in 32 chips, that is, every 32chip statistics, each time the I/Q data of the latest 32 chip length is counted. Energy value.
• the downlink automatically turns off the antenna, that is, the antenna does not transmit data.
• the threshold value is increased by 3 db than the digital scaled energy value.
• the downlink The antenna is automatically turned on again. In this way, the protection of the cockroach is achieved.
• the value of the 200 times can be appropriately adjusted, and the value range can be between 150 and 250 times, which is determined by long-term system testing according to actual needs.
• the technical solution of instantaneous energy over-power protection implemented by using the digital part is for each output data sample, and the sample power of the sample should be within a certain range, so that each output needs to be detected in real time for this purpose.
• the power of the data sample is not processed if the power is within a reasonable range, otherwise the limiting processing is performed.
• the energy value ⁇ ( ⁇ 2 + ⁇ ) of the I/Q data output after DUC+CFR+DPD in each second time length is counted.
• the second time length may be a fraction of a chip.
• a D AC interface with a sampling rate of 245.76 is used, and the second time length may be l. /8chip. That is, for each antenna, the energy value of the I/Q data output after each DU/CFR+DPD in 1/8 chip is counted, that is, every l/8chip is counted, and the latest l/ is counted each time. The energy value of the I/Q data over the length of 8 chips.
• the value of pwr_threshold 1 is, for example, the threshold value may be increased by 1 Odb than the digital calibration energy value, and the statistical power threshold corresponding to the first power protection threshold pwr threshold is different, and pwr_threshold1 corresponds to the peak power threshold, The difference is the peak-to-average ratio of the I/Q data.
• instantaneous energy over-power protection can be used first, and then statistical energy over-power protection can be optimized, which can provide more complete PA protection without affecting system performance.
• a power amplifier PA over power protection apparatus includes: a first protection unit 11 configured to in-phase phase and amplitude signals processed by DUC, CFR, and DPD for each antenna.
• Component and orthogonal component data respectively calculating the sum of the energy value of the in-phase component data of the phase and amplitude signals and the energy value of the orthogonal component data in each first time length to obtain a first sum value, the first sum value
• the downlink of the antenna is turned off as compared with the preset first power protection threshold;
• a second protection unit 12 configured to calculate phase and amplitude signals for each second time length for each of the in-phase components and quadrature component data of the phase and amplitude signals processed by the DUC, CFR, and DPD for each antenna The sum of the energy value of the in-phase component data and the energy value of the orthogonal component data, to obtain a second sum value, and the second sum value and the preset number Comparing two power protection thresholds, when the second sum value of any antenna is greater than a preset second power protection threshold, the in-phase component and the quadrature component of the phase and amplitude signals in the second time length The data is cleared to zero and sent to the PA;
• the second time length is less than the first time length, and the first power protection threshold is less than the second power protection threshold.
• the first protection unit 11 and the second protection unit 12 may be embedded processors, such as Field Programmable Gated Arrays (FPGAs).
• FPGAs Field Programmable Gated Arrays
• the first protection unit 11 is further configured to:
• the preset number of times is 200 times.
• the first length of time is 32 chips.
• a power amplifier PA over power protection apparatus includes: a first energy value statistics unit 21 configured to process phase and amplitude signals processed by DUC, CFR, and DPD for each antenna.
• the in-phase component and the orthogonal component data respectively calculate the sum of the energy value of the in-phase component data of the phase and amplitude signals and the energy value of the orthogonal component data in each first time length to obtain a first sum value;
• the first comparison processing unit 22 is configured to compare the first sum value with a preset first power protection threshold, when the first sum value of any antenna is greater than a preset first power protection threshold, The downlink of the antenna is closed, wherein the first time length is less than 256 chips.
• the first energy value statistic unit 21 and the first comparison processing unit 22 may be embedded processors, such as Field Programmable Gated Arrays (FPGAs).
• FPGAs Field Programmable Gated Arrays
• the first comparison processing unit 22 is further configured to:
• a power amplifier PA over power protection apparatus includes: a second energy value statistics unit 31 configured to process phase and amplitude signals processed by DUC, CFR, and DPD for each antenna.
• the in-phase component and the orthogonal component data respectively calculate a sum of the energy value of the in-phase component data of the phase and amplitude signals and the energy value of the orthogonal component data in each second time length to obtain a second sum value;
• the second comparison processing unit 32 is configured to compare the second sum value with a preset second power protection threshold, when the second sum value of any antenna is greater than a preset second power protection threshold, And clearing the in-phase component and the quadrature component data of the phase and amplitude signals in the second time length to the PA, wherein the second time length is less than 1 chip.
• the second energy value statistics unit 31 and the second comparison processing unit 32 may be embedded processors, for example Field Programmable Gated Array (FPGA).
• FPGA Field Programmable Gated Array
• the technical solution provided by the embodiment of the present invention can provide more complete protection for the PA without increasing the complexity of the hardware design, thereby effectively reducing the production cost and the operation and maintenance cost of the device in the later stage.
• the PA protection and system performance of the embodiments of the present invention are both balanced and provide an implementation of instantaneous energy protection. Using the first instantaneous energy over-power protection and then optimizing the statistical energy over-power protection method can provide more complete PA protection without affecting system performance. Compared with the statistical energy over-power protection in the prior art, the present invention has a great deal of consideration between the PA protection and the system performance through a faster recovery interval.
• the present invention can be fully implemented using software, or can be implemented using software and hardware synergy or SOC, and can be integrated as a design IP in various required system applications.
• embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the present invention is in the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) in which computer usable program code is embodied.
• the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
• the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
• These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
• the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Citations (5)

• 2012
  • 2012-07-06 CN CN2012102352097A patent/CN102780460A/zh active Pending
• 2013
  • 2013-07-05 WO PCT/CN2013/078892 patent/WO2014005549A1/fr not_active Ceased

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