WO2014001885A1

WO2014001885A1 - Method for fabricating a rear contact heterojunction intrinsic thin layer silicon solar cell with only two masking steps and respective solar cell

Info

Publication number: WO2014001885A1
Application number: PCT/IB2013/001369
Authority: WO
Inventors: Daniel Nilsen WRIGHT
Original assignee: REC CELLS Pte Ltd
Current assignee: REC CELLS Pte Ltd
Priority date: 2012-06-29
Filing date: 2013-06-27
Publication date: 2014-01-03
Anticipated expiration: 2014-12-29
Also published as: GB201211759D0; GB2503515A

Description

Method for fabricating a rear contact heteroj unction intrinsic thin layer silicon solar cell with only two masking steps and respective solar cell

FIELD OF THE INVENTION

The present invention relates to a rear contact heteroj unction intrinsic thin layer silicon solar cell and a method for fabricating such solar cell.

TECHNICAL BACKGROUND

Solar cells are used to convert sunlight into electricity using a photovoltaic effect. A general object is to achieve high conversion efficiency balanced by a need for low production costs.

In order to obtain high efficiency, semiconductor materials of good quality should be used as substrates for the solar cell and the surfaces of the substrates should be highly passivated in order to minimize any recombination losses. Furthermore, contact schemes for electrically contacting the substrate should be optimized in order to minimize resistance losses and optical shading.

In order to keep production costs low, it is generally intended to use as few processing steps as possible and furthermore to prevent complicated and costs- intensive production steps such as e.g. photolithography masking and high temperature processing steps. A solar cell concept has been proposed in WO 03/083955 Al . Therein, a rear- junction type photovoltaic element is proposed in which a pn junction and electrodes are formed on a rear surface opposite to a light incident surface of a semiconductor silicon substrate. The photovoltaic element has an intrinsic semiconductor film on its rear side having a thickness ranging from 0.1 nm to 50 nm. On the back side of the intrinsic semiconductor film, p-type conductive semiconductor portions and n-type conductive semiconductor portions are disposed and each of the conductive semiconductor portions is contacted with a respective first or second electrode. Such interdigitated back contact heteroj unction intrinsic-thin film solar cell is sometimes referred to as IBC HIT solar cell.

Several attempts to improve this solar cell concept and methods for fabricating such solar cells have been proposed. Therein, the fabricating methods comprise several processing steps inter alia including different approaches for passivating the substrate surface, defining the geometry of the various semiconductor electrode layers and insulator layers and/or applying electrical electrodes to the solar cell substrate. For example, it has been proposed to use expensive photolithography processing steps to precisely define areas of semiconductor layers and/or insulator layers on the substrate's rear surface. Furthermore, it has been proposed to locally remove previously deposited layers by locally etching in order to subsequently deposit other layer materials in the prepared openings thereby generating a desired geometry of a rear side layer arrangement.

In UK patent application GB 1 1 11 302.4 and associated PCT application

PCT/EP2012/002274, an improved concept for a HIT solar cell and its fabrication have been proposed. Many details on possible method features as well as possible structural or functional features of the solar cell are presented. These applications are assigned to the same applicant as the present application and shall be incorporated herein in their entirety by reference. However, it seems that many conventional approaches for generating a rear contact heteroj unction intrinsic thin film solar cell scheme may suffer from at least one of the following shortcomings:

- a lack of a cheap mass-production method

- poor passivation at electrode edges due to imperfect definition of electrode areas

- a risk of shunting forcing metallization only over a limited part of the electrodes

- difficulties in controlling the cleanness and deposition homogeneity of the intrinsic thin film in the critical layer closest to the substrate

- expensive layer geometry definition due to the use of lithography and/or use of multiple masks.

SUMMARY OF THE INVENTION

It is an object of the present invention to at least partially overcome shortcomings of the above-mentioned prior art approaches. Particularly, it may be an object of the present invention to provide a rear contact heteroj unction intrinsic thin layer solar cell and a method for fabricating such solar cell allowing high solar cell efficiency while using a relatively simple and cost-efficient fabrication processing sequence. Furthermore, it may be seen as an object of the present invention to refine the solar cell and fabrication approach presented in co-assigned GB 1 111 302.4 and

PCT/EP2012/002274.

Such objects may be achieved with the subject-matter of the independent claims. Advantageous embodiments are defined in the dependent claims.

According to a first aspect of the present invention, a method for fabricating a rear contacted heteroj unction intrinsic thin layer solar cell is proposed. Therein, the rear side is formed by at least the following process steps, preferably in the indicated order:

- providing a silicon substrate with a front surface and a rear surface; - depositing a thin layer of i-a-Si, i.e. intrinsic amorphous Silicon, over at least parts of the rear surface of the silicon substrate, the i-a-Si layer having a front surface adjacent to the rear surface of the silicon substrate and having a back surface opposite to the front surface;

- depositing a first semiconductor layer comprising a doped semiconducting material, such as doped a-Si, of a first doping polarity wherein the first semiconductor layer is deposited through a first mask such that it covers first portions of the back surface of the i-a-Si layer;

- depositing a first separation layer comprising an electrically insulating material, such as preferably silicon nitride (SiN) or i-a-Si or another dielectric material, wherein the first separation layer is deposited through the same first mask such that it covers at least an entire back surface of the first semiconductor layer; and

- depositing a second semiconductor layer comprising a doped semiconducting material, such as doped a-Si, of a second doping polarity opposite to the first doping polarity wherein the second semiconductor layer is deposited though a second mask at regions of second portions adjacent to the first portions.

The method requires only two masks and results in the second semiconductor layer being separated from the first semiconductor layer by at least the intermediate first separation layer.

According to a second aspect of the present invention, a rear contact heteroj unction solar cell is proposed comprising

- a silicon substrate with a front surface and a rear surface;

- a passivating layer at the front surface of the silicon substrate;

- a thin i-a-Si layer covering at least first and second portions of the rear surface of the substrate, the i-a-Si layer having a front surface adjacent to the rear surface of the silicon substrate and having a back surface opposite to the front surface;

- a first semiconductor layer comprising a doped semiconducting material of a first doping polarity and covering first portions of the back surface of the i-a-Si layer; - a second semiconductor layer comprising a doped semiconducting material of a second doping polarity opposite to the first doping polarity and covering second portions of the back surface of the i-a-Si layer neighboring the first portions;

- a first separation layer comprising an electrically insulating material and covering an entire back surface of the first semiconductor layer and separating the first semiconductor layer in the first portions from the second semiconductor layer in the second portions.

A gist of the present invention and its embodiments may be seen as based on the following ideas and recognitions:

A concept for a HIT solar cell and its fabrication has been described in

GB 1 1 1 1 302.4 and PCT/EP2012/002274. Embodiments of the invention described herein aim at further simplifying a processing sequence for fabricating a rear contact HIT solar cell and further increasing its efficiency.

Like in other HIT solar cell concepts, a thin i-a-Si layer is deposited on top of a rear surface of a silicon substrate. On top of the back surface of this thin i-a-Si layer, first and second semiconductor layers are deposited in areas neighbouring each other and possibly partly laterally overlapping each other. The first and second semiconductor layers may be doped a-Si layers and have opposite doping polarities.

In the prior application documents mentioned above, it is taught to separate such first and second semiconductor layers from each other by an intermediate separation layer which is deposited before each of the first and semiconductor layer is deposited. Therein, each of the separation layer, the first semiconductor layer and the second semiconductor layer is deposited through a mask. Accordingly, three masking steps were necessary resulting in increased working efforts and costs. Furthermore, minimum lateral dimensions of each of the layers were predetermined by the technical feasibility of minimum dimensions of openings provided in the various masks. For example, such minimum dimensions are in the range of at least several micrometers, for example more than 10 μιη. Furthermore, when very small openings are to be used, the mask should be very thin, e.g. about or less than ΙΟΟμηι thick, in order to prevent shadowing and aspect-ratio problems. Such thin masks are however difficult to handle and durability may be short. Finally, using three separate masks requires very precise alignment of all these masks.

In contrast hereto, a method for fabricating a rear contacted HIT solar cell is proposed herein which requires only two masking steps, one masking step for depositing each of the first and second semiconductor layers.

Therein, it is proposed to, subsequently to depositing the first semiconductor layer through the first mask, additionally depositing a first separation layer comprising an electrically insulating material such as silicon nitride (SiN), i-a-Si or any other dielectrics, which may be deposited using e.g. PECVD (Plasma Enhanced Chemical Vapour Deposition), such as silicon oxide (SiO), silicon carbide (SiC), etc. Such separation layer may be deposited using the same first mask as used for depositing the first semiconductor layer such that the first separation layer covers the entire back surface of the first semiconductor layer and thereby electrically isolates this first semiconductor layer against any neighbouring or even overlapping further semiconductor layers. Only after this first separation layer has been deposited on top of the back surface of the first semiconductor layer, a second semiconductor layer is deposited using second mask different from the first mask.

While the first semiconductor layer is deposited using the first mask for covering first portions of the back surface of the underlying i-a-Si layer, the second semiconductor layer is deposited using the second mask for covering adjacent second portions of the back surface of the underlying i-a-Si layer. The first and second masks may have a geometry and may be aligned with respect to the first and second portions such that first and second portions are arranged next to each other forming e.g. an interdigitated pattern. However, in such geometry and alignment, inaccuracies may occur such that, in the final product, the second semiconductor layer may locally laterally overlap with the first semiconductor layer.

The first separation layer deposited intermediate to~the first semiconductor layer and the second semiconductor layer may however prevent any detrimental electrical contact between such laterally overlapping portions of the first and second semiconductor layers.

Furthermore, while in prior art approaches first and second semiconductor layers were separated from each other by an intermediate separation layer the lateral dimension of which was predetermined by the masking techniques used for depositing such separation layer and was in the range of at least several micrometers, according to the approach described herein, the first and second semiconductor layers may be separated from each other by the intermediate first separation layer. Accordingly, a separation distance between the first and second semiconductor layer is given by the thickness of the separation layer. With conventional deposition techniques, a separation layer having a thickness of only a few nanometers may be deposited. It has been observed that depositing the first separation layer with a thickness of between 1 and lOOOnm, preferably between 3 and 300nm and more preferably between 10 and lOOnm may be sufficient for reliably electrically insulating the adjacent first and second semiconductor layers from each other.

Enabling the first and second semiconductor layers to be separated from each other only by a thin intermediate isolating layer, i.e. being very close to one another, has been observed to be beneficial for the efficiency of the resulting solar cell, particularly for increasing its fill factor. According to an embodiment of the present invention, the process of depositing the first separation layer is performed with a less directional deposition technique than the process of depositing the first semiconductor layer.

In other words, when depositing the first semiconductor layer through the first mask, process parameters are adapted such that material for forming the first semiconductor layer is transmitted through the first mask in a predetermined main deposition direction, for example orthogonal to the plane of the mask, and deviations from such main deposition direction are small. Accordingly, an area and geometry of the resulting first semiconductor layer generally corresponds to an area and geometry of an opening in the first mask. Subsequently, the first separation layer is deposited on top of the first semiconductor layer with a significantly smaller directionality, i.e. deviations from a main deposition direction may be larger. Accordingly, an area of the first separation layer may be slightly larger than an area of a respective opening in the first mask and tails of the first separation layer may extend laterally beyond edges of the underlying first semiconductor layer.

The presence of such lateral tails may further ensure that the separation layer reliably covers the entire underlying first semiconductor layer and prevents any portions of the first semiconductor layer to remain exposed, thereby preventing any electrical contact with adjacent or overlapping neighbouring semiconductor layers.

A directionality of a depositing process may be influenced for example during PECVD deposition by operating pressure, temperature and substrate bias. For example, decreasing the operating temperature, increasing the pressure and/or increasing the DC bias on the substrate is assumed to increase directionality of the deposition process.

Due to the self-aligning nature of the processes of depositing the first semiconductor layer and depositing the first separation layer within the first portions of the back surface of the i-a-Si layer as well as of the processes of depositing the second semiconductor layer and depositing the second separation layer within the second portions of the back surface of the i-a-Si layer, these processes may be performed using a non-contacting mask. In other words, the masks used for depositing the semiconductor layers and the separation layers does not need to be arranged in direct mechanical contact to the silicon substrate but there may be a gap between such masks and the surface of the silicon substrate. While such gap may result in the deposited layers having enlarged lateral tail regions, i.e. having fuzzy edges, such enlarged tail regions may be accepted as the separation layer is self-aligned on top of the associated semiconductor layer and any tail region of the semiconductor layer is covered by a corresponding tail region of the separation layer. Using a non- contacting mask may reduce any risk of surface contamination and damage to the surface of the silicon substrate.

In an embodiment according to a first concept of the present invention, the thin layer of i-a-Si is deposited as a blanket layer covering the entire rear surface of the silicon substrate. While the first semiconductor layer is deposited through the first mask such that it covers first portions of the back surface of the i-a-Si layer, the second semiconductor layer is then deposited through a second mask such that it covers second portions of the back surface of the i-a-Si layer adjacent to the first portions.

In other words, according to such first concept, the thin intrinsic amorphous silicon layer is deposited over the entire rear surface of the silicon substrate before subsequently depositing the first and second semiconductor layers in respective first and second portions on the back side of this layer. Such blanket depositing of the i-a- Si layer may be performed in a single deposition procedure and may beneficially allow for very good passivation of the entire rear surface of the silicon substrate. On top of such highly passivated silicon substrate rear surface, the respective first and second semiconductor layers for subsequently forming associated electrode layers may then be formed. In an embodiment according to a second concept of the present invention, the thin intrinsic amorphous silicon layer is deposited in two parts. A first part is deposited prior to the process of depositing the first semiconductor layer and the first separation layer. Therein, the first part of the thin i-a-Si layer is deposited through the first mask thereby locally covering the rear surface of the silicon substrate in first portions. A second part of the thin i-a-Si layer is deposited at a later stage of the processing sequence between the process of depositing the first separation layer and the process of depositing the second semiconductor layer. Therein, the second part of the thin i-a-Si layer is deposited through the second mask thereby locally covering the rear surface of the silicon substrate in second portions adjacent to the first portions. Subsequently, the second semiconductor layer is deposited through the second mask such that it covers the back surface of the second part of the i-a-Si layer in the second portions.

Accordingly, while the i-a-Si layer is deposited in two separate steps with a first part covering first portions and a second part covering second portions of the silicon substrate, in the finalized solar cell almost the entire surface of the silicon substrate is covered and passivated by one of the first and second parts of the thin i-a-Si layers. Therein, on top of the first parts, portions of the first semiconductor layer are arranged and, on top of the second parts, portions of the second semiconductor layer are arranged while, in between these first and second semiconductor layer portions, the first separation layer deposited on top of the back surface of the first

semiconductor layer serves for reliably electrically separating these first and second semiconductor layer portions.

According to a further embodiment of the present invention, a second separation layer comprising an electrically insulating material may be additionally deposited through the second mask such that it covers at least the entire back surface of the second semiconductor layer. Such second separation layer may be beneficial in subsequently preparing any metal contacts for contacting the first and second semiconductor layer and may prevent for example any short circuits occurring due such metal contacts.

It may be noted that possible features and advantages of embodiments of the present invention are described herein with respect to the proposed rear contact

heteroj unction solar cell or with respect to the proposed method for fabricating such solar cell. One skilled in the art will recognize that the different features may be suitably combined and features of the solar cell may be realized in a corresponding manner in the fabricating method and vice versa in order to implement further advantageous embodiments and realize synergetic effects.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following, features and advantages of embodiments of the present invention will be described with respect to the enclosed drawings. Therein, neither the description nor the drawings shall be interpreted as limiting the invention.

Fig. 1 illustrates a processing sequence of a method for fabricating a HIT solar cell according to a first embodiment of the present invention.

Fig. 2 illustrates a processing sequence of a method for fabricating a HIT solar cell according to a second embodiment of the present invention.

The figures are only schematically and not to scale. Same or similar features are designated with same reference signs throughout the figures. DESCRIPTION OF PREFERRED EMBODIMENTS

With reference to Figs. 1 and 2, two concepts of processing sequences according to embodiments of the present invention for fabricating a rear contacted heteroj unction intrinsic thin layer solar cell will be described.

It shall be noted that the illustrated sequences are mainly used for explaining the processing steps relevant for the respective embodiment of the inventive method. One skilled in the art realizes that further processing steps may be added or some of the described processing steps may be replaced by equivalent processing steps for fabricating the solar cell.

Particularly, it shall be noted that in the described processing sequences, any suitable processing means and techniques may be applied such as, inter alia, those described in detail in GB 1 1 1 1 302.4 and PCT/EP2012/002274.

In the first concept of a processing sequence, as shown in Fig. 1 , first an n-type silicon wafer is provided as a silicon substrate 3 (Fig. 1(a)). On a front surface of this silicon substrate 3, a passivating layer 6 is deposited. This passivating layer 6 may additionally serve as an antireflection coating and may be made for example with a dielectric material such as silicon nitride or silicon oxide.

Subsequently, a thin intrinsic amorphous silicon layer 7 having a thickness of e.g. less than 50 nm is deposited on a rear surface 5 of the silicon substrate 3 (Fig. 1(b)). The i-a-Si layer 7 is deposited in a single deposition step as a blanket layer and covers the entire rear surface 5 of the silicon substrate 3. The thickness is selected to be, on the one hand, sufficiently thick for good passivation of the underlying silicon substrate (3) rear surface (5) and, on the other hand, thin enough for charge carriers to tunnel through such thin layer. Then, a first semiconductor layer 13 such as e.g. a p-type-doped amorphous silicon layer is deposited through a first mask 1 1 (Fig. 1 (c)). This first mask 1 1 has openings 12 and the deposition process is performed with high directionality such that deposition takes place mainly at first portions 15 of the back surface 9 of the i-a-Si layer 7 such first portions coinciding with the areas of the openings 12 in the first mask 1 1.

Subsequently, a first separation layer 19 is deposited on top of the previously deposited first semiconductor layer portions 13 while the first mask 1 1 remaining at the position as used during depositing the first semiconductor layer 13 (Fig. 1(d)). The separation layer comprises an electrically insulating material. Silicon nitride may be preferred as it may be locally removed by etching in hydrofluoric acid which does not etch the underlying a-Si layer 13 thereby allowing for simply locally opening the first separation layer 19 by selective etching during metal contact formation.

Alternatively, other insulating materials such as i-a-Si or any other dielectric materials such as silicon oxide, silicon carbide, etc may be used. The separation layer 19 is deposited with a thickness of 50nm to 300nm.

While both the first semiconductor layer 13 and the first separation layer 19 are deposited using the same first mask 1 1 , deposition parameters influencing a directionality of a deposition process may be different. When the first semiconductor layer 13 is deposited, a higher directionality is desired in order to keep any tails 14 at the edges of the first semiconductor layer portions 13 as small as possible. Such high directionality may be achieved by adjusting parameters such as pressure, substrate temperature and substrate bias. When depositing the first separation layer 19, less directionality is desired such that tails 20 of the first separation layer 19 may reach laterally relatively far beyond the edges of the first mask 11. Accordingly, the separation layer 19 including these tails 20 completely covers and isolates the underlying first semiconductor layer 13 including its tails 14. Subsequently, a second semiconductor layer 21 is deposited through a second mask 27 (Fig. 1(e)). The second mask 27 may be approximately complementary to the first mask 11 and has openings 28 associated to second portions 29 adjacent to the first portions 15 at which the first semiconductor layer 13 has been applied. Accordingly, the second semiconductor layer 21 comes into contact with the underlying i-a-Si layer 7 in these second portions 29, except for the small regions covered by the tails 14, 20 of the first semiconductor layer 13 and the first separation layer 19. In those small regions of the tails 14, 20, the first and second semiconductor layers 13, 21 laterally slightly overlap.

In a next step, a second separation layer 23 is deposited through the second mask 27 thereby covering at least the entire back surface of the semiconductor layer 21 (Fig. 1(f)). While this deposition step may be optional, it may be advantageous to ensure that any subsequently formed metal contact to the first semiconductor layer does not come into contact to the second semiconductor layer. Preferably, this second separation layer 23 is formed with silicon nitride.

Finally, contact openings may be prepared in partial areas of the first and second separation layers 19, 23 in order to locally expose the underlying first and second semiconductor layers 13, 21 (Fig. 1(g)). For example, such contact openings may be formed by temporarily or permanently depositing additional masking layers and then locally etching at least one of the second separation layer 23 and the first separation layer 19 though openings of such masks. Therein, benefit may be taken from the fact that SiN may be etched e.g. in HF which does hardly attack a-Si such that the contact openings may be formed using selective etching. Metal contacts 39, 41 may be formed at these exposed areas of the contact openings. For example, such metal contacts may be applied by patterned depositions using e.g. screen printing techniques or metal deposition through masks. Alternatively, a blanket metal deposition covering the entire area of the rear surface 5 may be applied and subsequently areas for forming the first type contacts 39 and areas for forming the second type contacts 41 may be separated from each other using e.g. laser scribing.

In the finalized solar cell 1 as shown in Fig. 1 (g), the first portions with the first semiconductor layer 13 are completely electrically isolated from the second portions with the second semiconductor layer 21 by the intermediate thin first separation layer 19. Therein, an isolation characteristics is determined inter alia by the thickness of the first separation layer 19 and by the size of the tails 20 of the first separation layer 19.

With respect to fig. 2, an embodiment of a processing sequence according to a second concept will now be described.

Similar to the above described first concept, an n-type silicon wafer serves as a silicon substrate 3 with a passivating dielectric layer 6 at its front side and a cleaned rear surface 5 (fig. 2(a)).

However, contrary to the above described first concept, an i-a-Si layer 7 is not deposited as a blanket layer. Instead, only parts 7a of such thin i-a-Si layer are deposited by depositing through the first mask 11 (fig. 2(b)). On top of these first i-a- Si layer parts 7a, a first doped semiconductor layer 13 is locally deposited through the same mask 11. Finally, a first separation layer 19 is locally deposited through the same mask 11. In this concept, on the one hand, it may be beneficial to use i-a-Si as insulating material for the first separation layer 19 due to its superior surface passivating properties. On the other hand, using a dielectric material such as SiN for the first separation layer 19 may be beneficial due to enabling selective etching as described above. While the first mask 11 is used in depositing all of the first i-a-Si layer parts 7a, the first semiconductor layer 13 and the first separation layer 19, different processing parameters may be used during each of these three deposition processes.

For example, as direct contact of the first semiconductor layer 13 and the first separation layer 19 with the rear surface 5 of the silicon substrate 3 may be detrimental for the efficiency of a resulting solar cell due to deteriorated surface passivation of the rear surface 5 of the silicon substrate 3, the first i-a-Si layer parts 7a may be deposited with low directionality such that large tails 8 extend laterally beyond the borders of the first regions 15 defined by the openings 12 in the first mask 11. Subsequently, the first doped semiconductor layer 13 and the first separation layer 19 may be deposited through the first mask 11 with higher directionality such that only small tails 14, 20 are formed. Ideally, these tails 14, 20 are sufficiently small that they do not laterally extend beyond the tails 8 of the first i- a-Si layer 7 such that none of the first semiconductor layer 13 and the first separation layer 19 comes into direct contact with the rear surface 5 of the substrate 3. At least, tails 14,20 should be keep small such that any such direct contact is minimized. Furthermore, the first separation layer 19 is preferably deposited with less directionality than the first semiconductor layer 13 in order to assure that its tails 20 are extending further than the tails 14 of the semiconductor layer 13.

Subsequently, a second mask 27 is placed above the silicon substrate 3. Second parts 7b of the thin i-a-Si layer 7, a second semiconductor layer 21 and a second separation layer 23 are deposited through openings 28 of this second mask 27 (fig. 2(c)).

Therein, the deposition of the second semiconductor layer 21 should be more directional than the deposition of the second i-a-Si layer parts 7b.

Finally, contacts 39, 41 are formed (fig. 2 (d)) in a similar manner as described above with respect to the first concept. Openings are formed in the separation layers 19, 23 to expose an underlying first or second semiconductor layer 13, 21. Then, metal contacts 39, 41 are formed using patterned deposition or using blanket deposition and subsequently separating the portions of the respective contacts 39, 41.

In the finalized solar cell 1 as shown in Fig. 2(d), almost the entire rear surface 5 of the silicon substrate 3 is covered by a thin i-a-Si layer 7 which is divided into first and second parts 7a, 7b. Furthermore, first portions in which a first part 7a of the i-a- Si layer is covered with the first semiconductor layer 13 are completely electrically isolated from second portions in which a second part 7b of the i-a-Si layer is covered with the second semiconductor layer 21 by the intermediate first separation layer 19. Therein, an isolation characteristics is determined inter alia by a gap between the doped first and second semiconductor layers 13, 21. This gap is influenced by the thickness of the first separation layer 19 and by the size of the tails 20 of the first separation layer 19.

With the proposed fabrication methods, simple fabrication using only two masking steps may be possible. Furthermore, high efficiency with high fill factors of the resulting IBC HIT solar cell may be achieved due to the obtainable small gaps and good electrical separation between the first and second semiconductor layers 13, 21.

Finally, it should be noted that the term "comprising" does not exclude other elements or steps and the "a" or "an" does not exclude a plurality. Also elements described in association with different embodiments may be combined. It should also be noted that reference signs in the claims should not be construed as limiting the scope of the claims. LIST OF REFERENCE SIGNS solar cell

3 silicon substrate

5 rear surface of silicon substrate

6 passivating layer on front surface of silicon substrate

7 intrinsic amorphous silicon (i-a-Si) layer

7a first parts of i-a-Si layer

7b second parts of i-a-Si layer

9 back surface of i-a-Si layer

1 1 first mask

12 openings in first mask

13 first semiconductor layer

15 first portions of rear surface of silicon substrate

17 back surface of the first semiconductor layer

19 first separation layer

21 second semiconductor layer

23 second separation layer

27 second mask

28 openings in second mask

29 second portions of rear surface of silicon substrate

39, 41 metal contacts

Claims

1. A method for fabricating a rear contacted heterojunction intrinsic thin layer solar cell (1) wherein the rear side is formed by at least:

- providing a silicon substrate (3) with a front surface and a rear surface (5);

- depositing a thin layer (7) of i-a-Si over at least parts of the rear surface (5) of the silicon substrate (3), the i-a-Si layer (7) having a front surface adjacent to the rear surface (5) of the silicon substrate (3) and having a back surface (9) opposite to the front surface;

- depositing a first semiconductor layer (13) comprising a doped semiconducting material of a first doping polarity wherein the first semiconductor layer (13) is deposited through a first mask (11) such that it covers first portions (15) of the back surface (9) of the i-a-Si layer (7);

- depositing a first separation layer (19) comprising an electrically insulating material wherein the first separation layer (19) is deposited through the first mask (1 1) such that it covers at least an entire back surface (17) of the first semiconductor layer (13);

- depositing a second semiconductor layer (21) comprising a doped semiconducting material of a second doping polarity opposite to the first doping polarity wherein the second semiconductor layer (21) is deposited though a second mask (27) at regions of second portions (29) adjacent to the first portions (15),

such that the second semiconductor layer (21) is separated from the first

semiconductor layer (13) by at least the intermediate first separation layer (19).

2. The method of claim 1 , wherein the process of depositing the first separation layer (19) is performed with a less directional deposition technique than the process of depositing the first semiconductor layer (13).

3. The method of claim 1 or 2, wherein the first separation layer (19) has a thickness of between 1 and lOOOnm

4. The method of one of claims 1 to 3, wherein the first separation layer (19) comprises at least one of silicon nitride, silicon oxide, i-a-Si and silicon carbide.

5. The method of one of claims 1 to 4, wherein at least one of the process of depositing the first semiconductor layer (13) and depositing the separation layer (19) and the process of depositing the second semiconductor layer (21) is performed using a non-contacting first mask (1 1) and a non-contacting second mask (27).

6. The method of one of claims 1 to 5, wherein the thin layer (7) of i-a-Si is deposited as a blanket layer covering the entire rear surface (5) of the silicon substrate (3) and wherein the second semiconductor layer (21) is deposited through the second mask (27) such that it covers second portions (29) of the back surface (9) of the i-a-Si layer (7) adjacent to the first portions (15).

7. The method of one of claims 1 to 5, wherein a first part (7a) of the thin layer (7) of i-a-Si is deposited prior to the process of depositing the first separation layer (19) and wherein the first part (7a) of the thin layer (7) of i-a-Si is deposited through the first mask (11) thereby locally covering the rear surface (5) of the silicon substrate (3) in the first portions (15), and

wherein a second part (7b) of the thin layer (7) of i-a-Si is deposited between the process of depositing the first separation layer (19) and the process of depositing the second semiconductor layer (21) and wherein the second part (7b) of the thin layer (7) of i-a-Si is deposited through the second mask (27) thereby locally covering the rear surface (5) of the silicon substrate (3) in the second portions (29),

wherein the second semiconductor layer (21) is deposited through the second mask (27) such that it covers a back surface of the second part (7b) of the i-a-Si layer (7) in second portions (29) adjacent to the first portions (15).

8. The method of one of claims 1 to 7, further comprising depositing a second separation layer (23) comprising an electrically insulating material wherein the second separation layer (23) is deposited through the second mask (27) such that it covers at least the entire back surface of the second semiconductor layer (21).

9. A rear contacted heteroj unction intrinsic thin layer solar cell (1) comprising:

- a silicon substrate (3) with a front surface and a rear surface (5);

- a passivating layer (6) at the front surface of the silicon substrate (3);

- a thin i-a-Si layer (7) covering at least first (15) and second portions (29) of the rear surface (5) of the substrate (3), the i-a-Si layer (7) having a front surface adjacent to the rear surface (5) of the silicon substrate (3) and having a back surface (9) opposite to the front surface;

- a first semiconductor layer (13) comprising a doped semiconducting material of a first doping polarity and covering first portions (15) of the back surface (9) of the i-a- Si layer (7);

- a second semiconductor layer (21) comprising a doped semiconducting material of a second doping polarity opposite to the first doping polarity and covering second portions (29) of the back surface (9) of the i-a-Si layer (7) neighboring the first portions (1 );

- a first separation layer (19) comprising an electrically insulating material and covering an entire back surface (17) of the first semiconductor layer (13) and separating the first semiconductor layer (13) in the first portions (15) from the second semiconductor layer (21) in the second portions (29).

10. The solar cell of claim 9, wherein the first separation layer (19) has a thickness of between 1 and 1 OOOnm.

1 1. The solar cell of claim 9 or 10, wherein the thin i-a-Si layer (7) covers the entire area of the rear surface (5) of the substrate (3).

12. The solar cell of claim 9 or 10, wherein parts (7a, 7b) of the thin i-a-Si layer (7) cover the first and second portions (15, 29) of the rear surface (5) of the substrate (3) and wherein the parts (7a) of the thin i-a-Si layer (7) covering the first portions (15) are separated from the parts (7b) of the thin i-a-Si layer (7) covering the second portions (21) by the intermediate first separation layer (19).