WO2014059750A1 - Method for removing deviation among high-speed serial communication channels - Google Patents

Abstract

Based on a point-to-point high-speed serial communication protocol, the present invention provides a method for removing deviation among high-speed serial communication channels. A data message is usually transmitted in parallel to a peer-end receiving module via a plurality of channels, and delay deviation among channels caused by PCB or chip packaging is unavoidable, so that a channel aligning function needs to be achieved at a physical layer training initialization phase after serial-parallel data is converted into parallel data. The method comprises two steps: a first step of detecting characteristic characters and performing data buffering, and a second step of sending out the characteristic characters at the same time after all channels are detected, thereby naturally achieving alignment among the channels. The method has the following beneficial effects: 1) the time delay is short, and the alignment operation can be finished within five clock cycles; 2) the method is easy to implement with a few logical resources; and 3) the maximum allowed derivation is (characteristic character length/2-1)UI.

Description

 Method for deviating between high-speed serial communication channels

 The present invention relates to the field of high-speed data communication, and more particularly to a method for implementing de-biasing between high-speed serial communication channels, particularly in the field of high-speed serial interconnection communication in point-to-point, which is applied to communication protocols for parallel transmission of multiple channels. Background technique

 Point-to-point high-speed serial communication technology has been widely used in inter-chip or inter-processor interconnections. Interconnection communication protocols such as QPI, HT, PCIe, and InfiniBand are examples based on this technology. It is a logical interface to realize the transmission of data messages. Each channel is composed of two independent channels, which can realize the simultaneous transmission of bidirectional data. Each direction has a low-voltage differential signal pair for high-speed serial transmission. Transmission media include copper wires, board-to-board connectors, or fiber optics.

 At present, various data communication protocols are based on hierarchical transport protocols. From top to bottom, the protocol layer, the routing layer, the link layer, and the physical layer are respectively implemented at different levels, which are easy to reuse or upgrade. The protocol layer transaction includes Cache - Consistent and non-coherent memory access, 10 access, configuration, and interrupt handling. The routing layer implements the correct routing of packets from the source address to the destination address. The link layer implements packet reliability transmission and flow control. The reliable transmission is realized by the CRC error detection and retransmission mechanism, and the physical layer realizes the high-speed transmission of the data stream on the actual physical link.

The physical layer serves the link layer upwards, and connects various transmission media downwards. The physical layer is subdivided into physical sub-layers and logical sub-layers according to the implementation. The physical sub-layer realizes high-speed signal serial-to-parallel conversion and clock frequency through analog circuits. Or phase locking, the logic sublayer implements training initialization functions through digital logic circuits, including link detection, de-biasing between channels, configuration of link bandwidth and rate, and scrambling. For data packet splitting in multiple channel parallel transmission protocols, since the physical channel delay cannot be guaranteed to be consistent, and the serial-to-parallel conversion of the analog front end does not guarantee the validity of the converted parallel data, a synchronization and de-biasing process is required. The data message is correctly recovered at the receiving end and provided to the link layer. Summary of the invention

 It is an object of the present invention to provide a method of de-biasing between high speed serial communication channels.

 The object of the present invention is achieved in the following manner, including the following steps:

 The first step is to perform feature character detection and data buffering on each channel, and the parallel out-of-order data received from the analog front end, and the parallel out-of-order data is multi-level registered, and the transmission is started only after the feature characters are detected. Data, the detection method of the characteristic character is realized by the parallel comparison method, the position of the feature character is determined in one clock cycle, and the effective feature character and data can be output in the subsequent two beats;

 The second step is to send the feature characters at the same time after all the channels have detected the feature characters, and naturally realize the alignment between the channels. In the process of detecting the feature characters in the first step, there may be two channels detecting characters. It will be different by one clock cycle, so the channel that detects the characteristic character in advance should be delayed by one clock cycle to output valid data, so as to ensure that the two pass-through outputs the valid feature characters and data synchronously;

 It is important for which channels to detect the feature characters first, and whether the data after the combination of multiple channels is directly correct, so each channel first informs the link state machine before the alignment is enabled, and then the link state machine gives All channels initiate channel alignment enable signals, thus providing a reference for each channel, knowing who will arrive first, who will be the last, and then delay the output of one cycle, then the direct output can be achieved, naturally realized more Deviation between channels.

 The beneficial effects of the invention are as follows: 1) The delay is short, and the alignment operation can be completed in 5 clock cycles.

2) Simple implementation, less use of logical resources. 3) The maximum deviation is allowed (character character length / 2-1) UI. detailed description

 The object of the present invention is to solve the problem of deviation of multiple channels of a point-to-point high-speed serial communication receiving end. Usually, multiple channels are transmitted in parallel to the opposite receiving module, and physical reasons such as PCB or chip encapsulation cannot guarantee multiple channels. The delay is exactly the same, resulting in serial data not reaching the receiving end of each channel;

 The invention is suitable for the physical transmission coding mode using the scrambling code. In the link initialization deviation phase, only the specific channel alignment pattern is received, and the subsequent data transmission is back-to-back transmission, and the alignment of the subsequent data can be ensured after the alignment of the feature characters is realized. Therefore, the problem of channel deviation is solved during the training initialization process.

 Based on the point-to-point high-speed serial communication protocol, the present invention provides a method for implementing de-biasing between channels. The invention can significantly reduce the transmission delay, and is simple to implement and saves logic resources.

 The object of the present invention is achieved in the following manner, including the following steps:

 The first step is to perform feature character detection and data buffering on each channel, and the parallel out-of-order data received from the analog front end is stored in multiple levels because the data cannot be directly used, only after detecting the characteristic characters. In order to recognize the data actually transmitted after the feature character, the detection method of the feature character is realized by the parallel comparison method, and the position of the feature character is determined in one clock cycle, and the valid feature character and data can be output in the subsequent two beats.

 The second step is to send the feature characters at the same time after all the channels are detected, and naturally realize the alignment between the channels. In the process of detecting the feature characters in the first step, there may be a problem that the characters detected by the two channels are different. One clock cycle, so that the effective data output is also output one cycle ahead of time, so the valid data must be outputted one channel clock delay in advance detection.

Note that it is important for which channels to detect the feature characters first. It is directly related to whether the data combined by multiple channels is correct, so each channel will be detected before enabling alignment. The result tells the link state machine, and then the link state machine initiates a channel alignment enable signal for all channels, thus providing a reference to each channel, knowing who is coming first, who is coming to the end, and finally to whom, one delay Output, direct output to the back, naturally achieve deviation between multiple channels.

 Example:

 The method of deviating between multiple channels is implemented in two steps. The first is the detection of characteristic characters and the multi-level registration of data. Then, after all channels are detected, the feature characters are sent out at the same time, which naturally realizes between the channels. Align.

 The detection of the feature characters is determined by parallel comparison of the N M-bit width comparators, where N is the data width after serial-to-parallel conversion, and M is the length of the header identifier of the feature character.

 Applying this method to achieve the maximum deviation between channels is (characteristic character length / 2-1) UI.

 In addition to the technical features described in the specification, they are all known to those skilled in the art.

Claims

Claim  What is claimed is: 1. A method of deviating between high speed serial communication channels, comprising the steps of:  The first step is to perform feature character detection and data buffering on each channel, and the parallel out-of-order data received from the analog front end, and the parallel out-of-order data is multi-level registered, and the transmission is started only after the feature characters are detected. Data, the detection method of the characteristic character is realized by the parallel comparison method, the position of the feature character is determined in one clock cycle, and the effective feature character and data can be output in the subsequent two beats;  The second step is to send the feature characters at the same time after all the channels have detected the feature characters, and naturally realize the alignment between the channels. In the process of detecting the feature characters in the first step, there may be two channels detecting characters. It will be different by one clock cycle, so the channel that detects the characteristic character in advance should be delayed by one clock cycle to output valid data, so as to ensure that the two pass-through outputs the valid feature characters and data synchronously;  It is important for which channels to detect the feature characters first, and whether the data after the combination of multiple channels is directly correct, so each channel first informs the link state machine before the alignment is enabled, and then the link state machine gives All channels initiate channel alignment enable signals, thus providing a reference for each channel, knowing who will arrive first, who will be the last, and then delay the output of one cycle, then the direct output can be achieved, naturally realized more Deviation between channels.