WO2014059564A1 - Semiconductor device manufacturing method - Google Patents

Abstract

A bulk silicon FinFET manufacturing method, using a gate-last process, involves forming a dummy gate (4) first, then forming a inter dielectric layer (6), removing the dummy gate (4), and forming protective dielectric layers (7), then etching the STI (5) to expose a part of side walls of a semiconductor pole (2); removing a part of or all of the exposed semiconductor pole (2) by etching, and oxidizing the last material, thus as, forming an insulated isolation structure (9) between the channel region and the substrate (1) of the transistor, avoiding the formation of leak circuit, at the same time, the heat created by the transistor can radiates through the portion connecting the source/drain regions and the substrate, ensures the advantages of the bulk silicon FinFET.

Description

 Semiconductor device manufacturing method

 The present application claims priority to Chinese Patent Application No. 201210392, the entire disclosure of which is hereby incorporated by reference. Technical field

 The present invention relates to the field of semiconductor device fabrication methods, and more particularly to a bulk silicon substrate based FinFET (Fin Field Effect Transistor) device fabrication method. Background technique

 In the past 30 years, semiconductor devices have been scaled down according to Moore's Law, and the feature size of semiconductor integrated circuits has been shrinking and the integration has been increasing. As technology nodes enter the deep submicron domain, such as within 100 nm, or even within 45 nm, traditional field effect transistors (FETs), or planar FETs, begin to suffer from various basic physical laws, limiting their prospects of scaling down. challenge. Many new types of FETs have been developed to meet the needs of reality. Among them, FinFET is a new structural device with equal potential for scaling down.

 FinFET, a fin field effect transistor, is a multi-gate semiconductor device. Due to its unique structural features, FinFETs are a promising device in the field of deep submicron integrated circuits. As the name suggests, FinFETs include a Fin that is perpendicular to the bulk silicon substrate. Fin is called a finned semiconductor pillar, and different FinTETs are separated by the STI structure. Unlike conventional planar FETs, the channel region of the FinFET is located within Fin. The gate insulating layer and the gate surround Fin on the side and top surfaces, thereby forming gates of at least two sides, that is, gates on both sides of Fin; and, by controlling the thickness of Fin, the FinFET has excellent characteristics. : Better short channel effect rejection, better subthreshold slope, lower off-state current, eliminates floating body effect, lower operating voltage, and is more conducive to scaling down.

In the current FinFET manufacturing method, there are some technical problems that must be solved, and there are also problems compatible with the conventional process. Generally, there are two types of FinFET substrates: SOI (Silicon On Insulator) ^"Bottom and Bulk Silicon. The SOI bottom layer includes the top silicon, the back substrate, and the buried oxide layer between them. The presence of a buried oxide layer, in SOI FmFET fabrication on the substrate is easier, and natural electrical isolation between the source and drain and between the devices is formed, which can effectively suppress leakage and avoid latch-up effects. However, SOI substrates have several problems: high wafer cost, high defect density, and self-heating effects. The thermal conductivity of silicon dioxide is low (about two orders of magnitude smaller than silicon). The presence of the buried oxide layer of the SOI substrate prevents the heat generated by the device from rapidly diffusing out, accumulates in the channel, increases the temperature of the device, and produces self-heating. effect. The device's mobility, threshold voltage, drain current, and subthreshold slope are all affected by temperature, which causes device performance degradation, and inevitably introduces large parasitic parameters, and the cost of the SOI substrate itself is high, increasing manufacturing cost. The bulk silicon substrate is superior to the SOI substrate in terms of cost, defect density, and heat transfer capability, and thus has received extensive attention. For bulk silicon FinFET devices, Fin is directly connected to the bulk silicon substrate. The heat dissipation problem of the device is much better than that of the SOI-based FinFET. However, due to the direct connection of Fin to the bulk silicon substrate, leakage current and short channel effect. It is more serious than SOI-based FinFET. In order to solve the above problems of bulk silicon substrate-based FinFET devices, it is desirable to provide a novel FinFET device fabrication method that overcomes its existing drawbacks while ensuring the advantages of bulk silicon FinFET devices. Summary of the invention

 The invention proposes a novel bulk silicon substrate FinFET manufacturing method for the problem of leakage current and short channel effect of a bulk silicon substrate FinFET device.

 According to an aspect of the invention, there is provided a method of fabricating a FinFET, comprising the steps of:

 Providing a semiconductor substrate on which a fin-shaped semiconductor pillar is formed, the fin-shaped semiconductor pillar being directly connected to the semiconductor substrate;

 Forming an STI structure;

 Forming a dummy gate insulating layer of the FinFET, a dummy gate, a gate spacer, and a source/drain region;

 Fully forming a layer of deposited intermediate medium;

 Using a CMP process, removing a portion of the intermediate dielectric layer to open a top surface of the dummy gate;

 Removing the dummy gate and the dummy dummy gate insulating layer to expose a FinFET channel region in the fin-shaped semiconductor pillar;

 Forming a protective dielectric layer on the exposed finned semiconductor pillar;

Removing a portion of the thickness of the STI structure, exposing the portion below the protective dielectric layer Dividing the side of the finned semiconductor column;

 Etching the side of the portion of the finned semiconductor pillar exposed under the protective dielectric layer to remove partially exposed material of the finned semiconductor pillar, in the FinFET channel region of the finned semiconductor pillar Forming a thinner semiconductor portion that is thinner than the thickness of the finned semiconductor pillar;

 Oxidizing the thinned semi-semiconductor portion to form an oxide isolation portion;

 Removing the protective dielectric layer;

 A gate insulating layer and a gate are sequentially formed.

In this method of the invention, the protective dielectric layer is Si ₃ N ₄ and has a thickness of 5 to 100 nm.

In the method of the present invention, the dummy gate insulating layer is Si0 ₂ , the dummy gate is polysilicon or amorphous silicon; the gate insulating layer is a high-K insulating material, and the gate is a metal or a doped Polysilicon.

 In this method of the invention, the intermediate medium layer is TEOS.

 According to another aspect of the present invention, there is provided a method of fabricating a FinFET, comprising the steps of:

 Providing a semiconductor substrate on which a fin-shaped semiconductor pillar is formed, the fin-shaped semiconductor pillar being directly connected to the semiconductor substrate;

 Forming an STI structure;

 Forming a dummy gate insulating layer of the FinFET, a dummy gate, a gate spacer, and a source/drain region;

 Fully forming a layer of deposited intermediate medium;

 Using a CMP process, removing a portion of the intermediate shield layer, opening a top surface of the dummy gate;

 Removing the dummy gate and the dummy dummy gate insulating layer to expose a FinFET channel region in the fin-shaped semiconductor pillar;

 Forming a protective dielectric layer on the exposed finned semiconductor pillar;

 Removing a portion of the thickness of the STI structure, exposing a portion of the finned semiconductor pillar below the protective dielectric layer;

Etching the side of the portion of the finned semiconductor pillar exposed under the protective dielectric layer to remove all exposed material of the finned semiconductor pillar, in the FinFET channel region of the finned semiconductor pillar a void is formed in the lower portion; Removing the protective dielectric layer;

 A gate insulating layer and a gate are sequentially formed.

 In this other method of the present invention, after the cavity is formed in the lower portion of the FinFET channel region in the fin-shaped semiconductor pillar, the exposed semiconductor material of the cavity is oxidized.

In this another method of the present invention, the protective dielectric layer is Si ₃ N ₄ and has a thickness of

5-100 nm.

In another method of the present invention, the dummy gate insulating layer is Si0 ₂ , the dummy gate is polysilicon or amorphous silicon; the gate insulating layer is a high-K insulating material, and the gate is metal or Doped with polysilicon.

 In this other method of the invention, the intermediate medium layer is TE〇S.

 The invention has the advantages that: a gate-lasting process is adopted, a dummy gate is first formed, and then a dummy gate is formed by forming an intermediate dielectric layer, and a protective dielectric layer is formed, and then the STI is etched to expose a portion of the semiconductor pillar. The side portion; corrodes to remove part or all of the exposed semiconductor pillar, and oxidizes the remaining material, thus forming an insulating isolation structure between the channel region of the transistor and the substrate, thereby avoiding leakage current generation, and at the same time, generating a transistor The heat can be dissipated through the portion of the source and drain regions that are connected to the substrate, ensuring the advantages of the bulk silicon FinFET. DRAWINGS

 1 to 16 are schematic diagrams showing the flow of a FinFET device manufacturing method and a structure thereof. detailed description

 Hereinafter, the present invention will be described by way of specific embodiments shown in the drawings. However, it should be understood that the description is only illustrative, and is not intended to limit the scope of the invention. In addition, descriptions of well-known structures and techniques are omitted in the following description in order to avoid unnecessarily obscuring the inventive concept.

 First, the present invention provides a FinFET manufacturing method, the manufacturing process of which is shown in Fig. 16.

First, referring to Fig. 1, a Fin (Fin-Piece Semiconductor Pole) 2, a dummy gate insulating layer 3 and a dummy gate 4, and an STI structure 5 for isolating the respective FinFETs are formed on the semiconductor substrate 1. A semiconductor substrate 1 is provided, which is a bulk silicon substrate in this embodiment. Forming Fin 2 having a top surface and a side surface on the semiconductor substrate 1 includes: first depositing a hard mask on the semiconductor substrate 1 a film layer (not shown), then coating a photoresist, then etching a Fin 2 pattern, sequentially etching the mask layer and the semiconductor substrate, thereby obtaining Fin 2 , thus obtaining Fin 2 directly with the substrate 1 Connected, the hard mask layer remains on the top surface of the Fin 2. Next, the STI structure 5 is formed by a conventional process. Thereafter, forming the dummy gate insulating layer 3 and the dummy gate 4 specifically includes: first depositing a material of the dummy gate insulating layer 3, for example, Si0 ₂ , and then depositing a material of the dummy gate 4, such as polysilicon Or amorphous silicon, then patterned and photolithographically patterned to form a dummy gate. The thickness of the dummy gate insulating layer 3 is 0.5-10 nm, and the thickness of the dummy gate 4 is 100-300 nm. In Figure 1, the dummy gate 4 spans Fin 2 and surrounds the two sides and top surface of Fin 2. 2 is a schematic cross-sectional view of the direction along which Fin 2 extends in FIG. 1, and FIG. 3 is a schematic cross-sectional view along the direction in which the vertical Fin 2 extends, that is, a cross-sectional view along the direction in which the dummy gate extends. After the dummy gate insulating layer 3 and the dummy gate 4 are formed, a gate spacer (not shown) is formed, and after the gate spacer is formed, source-drain implantation is performed to form on Fin 2 Source and drain area (not shown).

 4 and 5, respectively, are a schematic cross-sectional view along the extending direction of the vertical Fin 2 and a schematic cross-sectional view along the extending direction of the Fin 2, depositing the intermediate dielectric layer 6 in a comprehensive manner, and opening the dummy gate 4 by a CMP process. Top surface. The material of the intermediate medium layer 6 is usually TEOS, and the deposition thickness covers the entire FinFE. A portion of the thickness of the intermediate dielectric layer 6 is removed by the CMP process until the top surface of the dummy gate 4 is exposed.

6 and 7 are respectively a schematic cross-sectional view along the extending direction of the vertical Fin 2 and a cross-sectional view along the extending direction of the Fin 2, and sequentially removing the dummy gate 4 and the dummy gate insulating layer 3, which may be wet etched. The dummy gate 4 and the dummy gate insulating layer 3 are removed. In this way, ? 1 ₁ ^ 5 Ding? ^ 2 is partially exposed, that is, the channel region of the FinFET is exposed.

Next, referring to Fig. 8, a cross-sectional view in the direction in which the vertical Fin 2 extends, a protective dielectric layer 7 is formed on the side of the exposed Fin 2 portion. Specifically, the material comprising a protective dielectric layer, for example, Si ₃ N ₄ , is then etched back to form a protective dielectric layer 7 . The protective dielectric layer has a thickness of 5 to 100 nm to protect Fin 2 from damage during subsequent etching processes.

 Next, referring to Fig. 9, for a schematic cross-sectional view along the direction in which the vertical Fin 2 extends, a portion of the thickness of the STI structure 5 is removed, exposing the side of the portion Fin 2 below the protective dielectric layer 7.

Next, referring to FIG. 10, which is a schematic cross-sectional view along the direction of the vertical Fin 2, the side of the exposed portion Fin 2 is etched to remove the material of the portion Fin 2, in Fin 2 The lower portion forms a thinned semiconductor portion 2 that is thinner than the thickness of Fin 2. 13 and 14, which are schematic cross-sectional views in the direction in which the vertical Fin 2 extends and a cross-sectional view in the direction in which Fin 2 extends, oxidize the thinned semiconductor portion 2' to form an oxide in the lower portion of the Fin 2 channel region. Isolation section 9.

 Optionally, referring to FIGS. 11 and 12, respectively, are schematic cross-sectional views along the direction of the vertical Fin 2 extension and cross-sectional views along the extending direction of the Fin 2, and the sidewalls of the exposed portion Fin 2 are etched through, that is, the Fin is completely removed. 2 The lower semiconductor material forms a void 8 in the lower portion of the Fin 2 channel region. If the exposed side wall of the Fin 2 is etched through to form the cavity 8, the oxidation treatment may be optionally performed to oxidize the exposed semiconductor material of the cavity 8 to obtain a good insulating effect, or may not be oxidized in this step. , the cavity 8 can be used as an insulation with air as an insulating material.

 The oxidation isolating portion 9 (optionally, the exposed etched semiconductor material of the void 8 and/or the void 8) is located between the Fin 2 channel region of the FinFET and the semiconductor substrate 1, blocking the leakage current of the channel region, improving The short channel effect of the FinFET. At the same time, since the source and drain regions of the Fin 2 of the FinFET are still directly connected to the semiconductor substrate 1, excellent heat dissipation can be provided, and the advantages of the bulk silicon FinFET device are retained.

After that, referring to Figures 15 and 16, are schematic cross-sectional views along the direction of the vertical Fin 2, respectively illustrating an embodiment in which the silicon oxide spacers 9 and the voids 8 are formed in the lower portion of the Fin 2 channel region, and the protective dielectric layer 7 is removed, in turn. A gate insulating layer 10 and a gate electrode 11 are formed. The forming the gate insulating layer 10 and the gate electrode 1 1 specifically includes: firstly depositing a material of the gate insulating layer, which is preferably a high-k gate insulating material, and generally, the high-k gate insulating material layer is selected from one of the following materials or One or more layers composed of a combination: A1 ₂ 0 ₃ , Hf0 ₂ , bismuth-based high-k dielectric including at least one of HfSiO _x , HfSi 〇 _N , HfA10 _x , HfTaO _x , HfLaO _x , HfAlSiO _{x ,} and HfLaSiO _x materials, including _{Zr0 2, La 2 0 3,} LaA10 3, Ti〇 inner, or at least one of the ₂ Y ₂ 0 ₃ to the rare earth group Κ high dielectric material; Subsequently, gate material is deposited, preferably a metal, may be The doped polysilicon is used, and then a CMP process is performed to remove excess gate insulating material and gate material to complete the fabrication of the gate insulating layer 10 and the gate 11.

Thus far, the present invention has described in detail a method of fabricating a bulk silicon FinFET device. In the present invention, a back gate process is employed, first forming a dummy gate, then forming an intermediate dielectric layer, removing the dummy gate, and forming a protective dielectric layer, and then etching the STI to expose a portion of the semiconductor pillar Side removing; partially or completely exposing the exposed semiconductor pillars, and oxidizing the remaining material, thus forming a shape between the channel region of the transistor and the substrate The insulating isolation structure avoids the generation of leakage current. At the same time, the heat generated by the transistor can be dissipated through the portion where the source and drain regions are connected to the substrate, which ensures the advantages of the bulk silicon FinFET.

 The invention has been described above with reference to the embodiments of the invention. However, these examples are for illustrative purposes only and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Numerous alternatives and modifications may be made by those skilled in the art without departing from the scope of the invention.

Claims

Rights request A method of fabricating a semiconductor device for fabricating a FinFET device, comprising the steps of:  Providing a semiconductor substrate on which a fin-shaped semiconductor pillar is formed, the fin-shaped semiconductor pillar being directly connected to the semiconductor substrate;  Forming an STI structure;  Forming a dummy gate insulating layer of the FinFET, a dummy gate, a gate spacer, and a source/drain region;  Fully forming a layer of deposited intermediate medium;  Using a CMP process, removing a portion of the intermediate dielectric layer to open a top surface of the dummy gate;  Removing the dummy gate and the dummy gate insulating layer to expose a FinFET channel region in the finned semiconductor pillar;  Forming a protective dielectric layer on the exposed finned semiconductor pillar;  Removing a portion of the thickness of the STI structure, exposing a portion of the finned semiconductor pillar below the protective dielectric layer;  Etching the side of the portion of the finned semiconductor pillar exposed under the protective dielectric layer to remove partially exposed material of the finned semiconductor pillar, in the FinFET channel region of the finned semiconductor pillar Forming a thinner semiconductor portion that is thinner than the thickness of the finned semiconductor pillar;  Oxidizing the thinned semi-semiconductor portion to form an oxide isolation portion;  Removing the protective dielectric layer;  A gate insulating layer and a gate are sequentially formed. 2. The method according to claim 1, wherein the protective medium layer is Si ₃ N ₄ and has a thickness of 5-100 The method according to claim 1, wherein the dummy gate insulating layer is Si 〇 ₂ , the dummy gate is polysilicon or amorphous silicon; and the gate insulating layer is high K insulating Material, the gate is metal or doped polysilicon.  4. The method according to claim 1, wherein the intermediate medium layer is TEOS. A method of fabricating a semiconductor device for fabricating a FinFET device, characterized in that Including the following steps:  Providing a semiconductor substrate on which a fin-shaped semiconductor pillar is formed, the fin-shaped semiconductor pillar being directly connected to the semiconductor substrate;  Forming an STI structure;  Forming a dummy gate insulating layer of the FinFET, a dummy gate, a gate spacer, and a source/drain region;  Fully forming a layer of deposited intermediate medium;  Using a CMP process, removing a portion of the intermediate dielectric layer to open a top surface of the dummy gate;  Removing the dummy gate and the dummy dummy gate insulating layer to expose a FinFET channel region in the finned semiconductor pillar;  Forming a protective dielectric layer on the exposed finned semiconductor pillar;  Removing a portion of the thickness of the STI structure, exposing a portion of the finned semiconductor pillar below the protective dielectric layer;  Etching the side of the portion of the finned semiconductor pillar exposed under the protective dielectric layer to remove all exposed material of the finned semiconductor pillar, in the FinFET channel region of the finned semiconductor pillar a void is formed in the lower portion;  Removing the protective dielectric layer;  A gate insulating layer and a gate are sequentially formed.  6. The method according to claim 5, wherein the exposed semiconductor material of the cavity is oxidized after forming a cavity in a lower portion of the FinFET channel region in the fin-shaped semiconductor pillar. 7. The method as claimed in claim 5, wherein said protective dielectric layer is a Si ₃ N _4, having a thickness of 5-100nm. The method according to claim 5, wherein the dummy gate insulating layer is Si0 ₂ , the dummy gate is polysilicon or amorphous silicon; and the gate insulating layer is a high-K insulating material. The gate is metal or doped polysilicon.  9. The method according to claim 5, wherein the intermediate medium layer is TE〇S.