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WO2013113232A1 - 阵列基板及其制造方法 - Google Patents

阵列基板及其制造方法 Download PDF

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Publication number
WO2013113232A1
WO2013113232A1 PCT/CN2012/084880 CN2012084880W WO2013113232A1 WO 2013113232 A1 WO2013113232 A1 WO 2013113232A1 CN 2012084880 W CN2012084880 W CN 2012084880W WO 2013113232 A1 WO2013113232 A1 WO 2013113232A1
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Prior art keywords
thin film
film transistor
active layer
array substrate
oxygen content
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English (en)
French (fr)
Inventor
李延钊
王刚
黄国东
田香军
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • Embodiments of the present invention relate to an array substrate and a method of fabricating the same. Background technique
  • Thin Film Transistor is one of the types of field effect transistors and is mainly used in flat panel display devices.
  • Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, relatively low manufacturing cost and no radiation, and it has a dominant position in the current flat panel display market.
  • the AMOLED (Active Matrix Organic Light Emitting Diode, AMOLED) panel is called the next-generation display technology. Compared with the traditional TFT-LCD panel, it has fast response, high contrast, and wide viewing angle. .
  • the oxide semiconductor indium gallium oxide (InGaZn04: IGZO) has been extensively studied for its high mobility, uniformity and preparation at room temperature, in order to replace Low Temperature Poly-silicon (LTPS).
  • LTPS Low Temperature Poly-silicon
  • the industrialization of large-size AMOLED panels is realized as an active layer of the array substrate.
  • an IGZO semiconductor is used as an active layer channel material of an array substrate, and generally only utilizes its depletion type or enhancement type characteristics, which makes the array substrate
  • the structure (such as timing control circuit, static control circuit, etc.) is complicated, has poor stability, and further affects the effective pixel area of the array substrate. Summary of the invention
  • the embodiment of the invention provides an array substrate and a manufacturing method thereof, which can solve the problem that when the IGZO semiconductor is used as the active layer channel material of the array substrate in the prior art, only the depletion type or the enhanced type can be utilized.
  • the characteristics cause the structure of the array substrate to be complicated, the stability is poor, and the effective pixel area cannot be further increased.
  • An aspect of an embodiment of the present invention provides an array substrate, including: a substrate plate and a bit position a first thin film transistor and a second thin film transistor on the substrate, wherein the first thin film transistor is of an enhancement type and the second thin film transistor is of a depletion type.
  • the active layer of the first thin film transistor and the active layer of the second thin film transistor include, for example, an oxide semiconductor.
  • the oxide semiconductor may be indium gallium oxide or germanium indium oxide.
  • an active layer of the first thin film transistor has an oxygen content higher than an oxygen content of an active layer of the second thin film transistor.
  • the active layer of the first thin film transistor is an IGZO active layer including a higher oxygen content
  • the active layer of the second thin film transistor is an IGZO active layer including a lower oxygen content.
  • the array substrate may be a top gate type or a bottom gate type.
  • the array substrate can be applied to a TFT-LCD panel or an AMOLED panel.
  • Another aspect of the present invention provides a method for fabricating an array substrate, comprising: forming a first thin film transistor and a second thin film transistor at a set position on a substrate plate, wherein the first thin film transistor is enhanced,
  • the two thin film transistors are depletion type.
  • Forming the first thin film transistor and the second thin film transistor at the set position on the substrate plate may include the following steps:
  • the oxide semiconductor is indium gallium oxide or germanium indium oxide.
  • the oxygen content of the active layer in the set substrate setting position may include a gas atmosphere treatment, and the gas used in the gas atmosphere treatment includes a reducing gas or an oxidizing gas, and the processing method includes thermal annealing. Or plasma bombardment.
  • the oxygen content of the active layer in the set substrate setting position may include a liquid atmosphere treatment, and the liquid used in the liquid atmosphere treatment includes a reducing liquid or an oxidizing liquid, and the processing method includes a chemical reaction. Or elemental diffusion.
  • the liquid atmosphere treatment may be dilute Chemical reaction corrosion treatment of hydrochloric acid or hydrofluoric acid.
  • the liquid atmosphere treatment is a chemical reaction etching treatment using dilute hydrochloric acid or hydrofluoric acid.
  • the adjusting the oxygen content of the active layer of the substrate setting position may include a solid atmosphere treatment, and the solid used in the solid atmosphere treatment includes a reducing solid or an oxidizing solid, and the processing manner includes a chemical reaction. Or elemental diffusion.
  • the solid atmosphere treatment may be a thermal diffusion treatment using a portion of the gate insulating layer or the passivation layer in contact with the active layer.
  • the solid atmosphere treatment is a thermal diffusion treatment using a portion of a gate insulating layer or a passivation layer in contact with the active layer.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic view showing a manufacturing process of the array substrate shown in FIG. 2;
  • FIG. 4 is a transfer characteristic diagram of a thin film transistor having different oxygen contents on an array substrate.
  • the depletion type or the enhancement type characteristic can be used only for the single use, the structure of the array substrate is complicated, the stability is poor, and the effective pixel area cannot be Further, the present invention provides an array substrate and a method of fabricating the same.
  • an array substrate includes: a substrate board 10 and a first thin film transistor 201a and a second thin film transistor 201b respectively located on the substrate board 10, wherein The thin film transistor 201a is of an enhancement type, and the second thin film transistor 201b is of a depletion type.
  • the active layer of the first thin film transistor 201a and the active layer of the second thin film transistor 201b include an oxide semiconductor such as InGaZn0 4 or HflnZnO.
  • the active layer may be doped to improve the performance of the thin film transistor.
  • the oxide semiconductor is an indium gallium oxide, which has the advantages of high mobility, good homogeneity, and preparation at room temperature.
  • the array substrate may be a top gate type structure or a bottom gate type structure, and may be an overlap type or a reverse overlap type structure.
  • the array substrate can be a coplanar or anti-coplanar structure.
  • the array substrate can also be configured to prepare a highly reflective layer on the back side of the substrate plate to prepare a top emission device.
  • the material of the substrate plate 10 may include glass, quartz, or the like, but is not limited to these transparent materials.
  • the substrate plate 10 may also be formed of ceramic, metal or the like for use in preparing a top emission device.
  • the array substrate of the embodiment of the invention can be applied to a TFT-LCD panel or an AMOLED panel.
  • a first thin film transistor and a second thin film transistor are formed at a set position on the substrate plate, wherein the first thin film transistor is of an enhancement type and the second thin film transistor is of a depletion type.
  • the set positions at which the first thin film transistor and the second thin film transistor are formed can be designed according to respective functions and structural needs.
  • the thin film transistor when used as a driving transistor in the pixel region and the sub-pixel region, it can function to control the luminance of the light, but the present invention is by no means limited thereto.
  • the first and second thin film transistors can also be used in a timing control circuit, or in a scan driving circuit and a data driving circuit, or in an array substrate test area, or in an array substrate peripheral static control circuit or the like.
  • forming the active layer may include:
  • Step 101 forming an active layer pattern including an oxide semiconductor
  • Step 102 forming a mask pattern on the substrate on which the active layer pattern is formed, and adjusting the oxygen content of the active layer at the substrate setting position by using the mask pattern to form an active of the first thin film transistor having a higher oxygen content a layer and an active layer of a second thin film transistor having a lower oxygen content.
  • a mask pattern can be formed on a substrate on which an active layer pattern is formed by, for example, a patterning process.
  • the patterning process referred to in the embodiments of the present invention includes photoresist coating, masking, exposure, development, etching, photoresist stripping, etc., and the photoresist is made of a positive photoresist.
  • this is not a limitation of the invention.
  • the oxide semiconductor is indium gallium oxide or germanium indium oxide.
  • the oxygen content of the active layer at the substrate setting position may be adjusted by means of gas atmosphere treatment, liquid atmosphere treatment or solid atmosphere treatment.
  • the gas used in the gas atmosphere treatment includes a reducing gas or an oxidizing gas such as 3 ⁇ 4, 0 2 , C3 ⁇ 4, etc., and the treatment includes thermal annealing or plasma bombardment.
  • the liquid used in the liquid atmosphere treatment includes a reducing liquid or an oxidizing liquid, and the treatment includes chemical reaction or elemental diffusion, for example, by chemical reaction etching with dilute hydrochloric acid or hydrofluoric acid.
  • the solids used in the solid atmosphere treatment include a reducing solid or an oxidizing solid, and the treatment includes chemical reaction or elemental diffusion, for example, thermal diffusion treatment by a portion of the gate insulating layer or the passivation layer in contact with the active layer.
  • the specific step may be: thermally annealing the substrate on which the mask pattern is formed in an atmosphere of 0 2 at an annealing temperature of 130 °C, the annealing time is 1 hour, and finally the oxygen content of the active layer at the set position is increased to form a higher oxygen content active layer.
  • the specific step may be: feeding the substrate on which the mask pattern is formed into a reactive ion etching apparatus having a 3 ⁇ 4 atmosphere for plasma bombardment treatment, The power level is 2 to 8 kW, and the processing time is 180 seconds. Finally, the oxygen content of the active layer at the set position is lowered to form a lower oxygen content active layer.
  • the substrate on which the mask pattern is formed may be formed by a patterning process.
  • the step of forming an active layer pattern including an oxide semiconductor may specifically be: depositing an active layer film layer by a sputtering method (for example, a low oxygen content active layer film layer or a high oxygen content active layer film) Layer), the oxygen content of the gas atmosphere during the sputtering process is 10% to 80%, the deposition thickness of the active layer film layer is 50 nm, and then the active layer pattern is formed by a mask etching process.
  • a sputtering method for example, a low oxygen content active layer film layer or a high oxygen content active layer film
  • the oxygen content of the gas atmosphere during the sputtering process is 10% to 80%
  • the deposition thickness of the active layer film layer is 50 nm
  • the active layer pattern is formed by a mask etching process.
  • FIG. 2 illustrates an array substrate in accordance with an embodiment of the present invention.
  • the array substrate is of a bottom gate type structure and can be used to fabricate an AMOLED panel or a TFT-LCD panel.
  • the formation process of the array substrate comprises: sequentially forming on the transparent substrate plate 10: an insulating buffer layer (not shown), a gate electrode 11, a gate insulating layer 12, and a gas atmosphere treatment.
  • Two IGZO active layers having different oxygen contents ie, high oxygen content active layer 13a and low oxygen content active layer 13b
  • etch barrier layer 14 source 15 and drain 16, and passivation layer
  • passivation layer not shown
  • FIGS. 2 and 3 are only for explaining the enhancement TFT and the depletion TFT.
  • the structure is not used to define the positional relationship between the enhancement type TFT and the depletion type TFT.
  • the enhancement type TFT including the high oxygen content active layer 13a and the depletion type TFT including the low oxygen content active layer 13b are not necessarily arranged adjacently.
  • a depletion TFT is mainly used in a pixel region of a liquid crystal display device, and an enhancement TFT and a depletion TFT are used in combination in a peripheral circuit region.
  • the material of the transparent substrate may be glass or quartz; the gate may be formed of metal such as molybdenum or copper; and the material of the gate insulating layer may be silicon dioxide, silicon nitride, etc.;
  • IGZO The active layer includes two active layer regions of high oxygen content and low oxygen content; the etch stop layer may be formed of a material such as silicon dioxide to prevent the source and the drain from being formed during wet etching.
  • the IGZO active layer as a channel causes damage; the source and the drain may be made of the same material, such as a metal such as molybdenum, aluminum, titanium, or copper, or a composite layer of these metals, or an alloy of these metals.
  • Transfer characteristics of thin film transistors of different oxygen contents on the array substrate (when the voltage between the drain and the source of the thin film transistor remains unchanged, the relationship between the voltage between the gate and the source and the drain current is called transfer characteristic , which describes the control of the drain current by the voltage between the gate and the source) as shown in FIG.
  • the array substrate shown in FIG. 2 is prepared by the method for manufacturing an array substrate according to the first embodiment of the present invention, and the specific method is as follows:
  • the transparent substrate plate is cleaned by a standard method (for example, UV decomposition cleaning method, chemical spray cleaning method, ultrasonic cleaning method, etc.), and then a silicon dioxide film is deposited as an insulating buffer layer by chemical vapor deposition method, and the deposition thickness is 200.
  • a standard method for example, UV decomposition cleaning method, chemical spray cleaning method, ultrasonic cleaning method, etc.
  • a gate metal layer is deposited on the insulating buffer layer by sputtering, the material is molybdenum, the deposition thickness is 200 nm, and the desired gate pattern is photolithographically etched;
  • a gate insulating layer is deposited on the gate metal layer by a chemical vapor deposition method at 370 ° C, and the material is silicon dioxide, and the deposition thickness is 150 nm;
  • a low-oxygen IGZO active layer film layer is deposited on the gate insulating layer by sputtering, sputtering
  • the gas atmosphere in the process has an oxygen content of 10% to 30%, a deposition thickness of about 50 nm, and photolithographic etching of the desired active layer pattern;
  • an etch barrier layer in a desired region, the material being silicon dioxide, having a thickness of about 50 nm;
  • a source and a drain electrode metal layer are deposited on the obtained structure by sputtering, and the material is molybdenum or aluminum, and the thickness is 200 nm, and the desired source and drain patterns are lithographically etched; the thickness is about 100 to 500. Nano, and then photolithographically etched through vias;
  • an acrylic material is spin-coated on the back sheet and photolithographically cured to form a pixel defining layer having a thickness of about 1.5 ⁇ m, and finally an array substrate including both the enhancement type thin film transistor and the depletion type thin film transistor is completed.
  • the subsequent specific process may be: ⁇ treating the surface of the array substrate with 0 2 plasma, further improving the surface work function of the transparent electrode, and simultaneously passivating the surface layer of the substrate; in the high-vacuum system for depositing an organic metal film A thin layer of organic material and an anode metal is thermally evaporated onto the array substrate; a hole transport layer (about 170 ° C), an organic light-emitting layer, and an electron transport layer are sequentially formed by thermal evaporation evaporation under a vacuum of T 5 Pa.
  • the hole transport layer may be 50 nm thick ruthenium ( ⁇ , ⁇ '-diphenyl-N-N' bis(1-naphthyl)- 1,1'diphenyl-4,4'-diamine);
  • the organic light-emitting layer may be formed by a pixel-substrate mask evaporation process, and the green, blue, and red pixel regions respectively include a doped phosphor material,
  • the host material of the doped phosphor material may be 25 nm thick CBP: (ppy) 2 Ir(acac) (4,4'- ⁇ , ⁇ '-dicarbazole-biphenyl: bis(2-phenylpyridine)acetyl Acetone oxime),
  • the AMOLED panel is full-color light-emitting, and the light-emitting mode is bottom light.
  • a peripheral circuit, an antistatic circuit, or the like may be provided with a dual type (ie, including an enhancement type and a depletion type) thin film transistor.
  • the red light and blue OLED devices have lower luminous efficiency, and the corresponding driving thin film transistor uses a low oxygen content IGZO active layer; because the green OLED device has higher luminous efficiency, the corresponding driving thin film transistor A high oxygen content IGZO active layer is used.
  • the array substrate shown in FIG. 3 is prepared by the method for manufacturing an array substrate according to the second embodiment of the present invention, and the specific method is as follows:
  • the transparent substrate plate is cleaned by a standard method, and then a silicon dioxide film is deposited by using a chemical vapor deposition method as an insulating buffer layer, and the deposition thickness is 200 nm;
  • a gate metal layer is deposited on the insulating buffer layer by sputtering, the material is molybdenum, the deposition thickness is 200 nm, and the desired gate pattern is photolithographically etched;
  • a gate insulating layer is deposited on the gate metal layer by a chemical vapor deposition method at 370 ° C, and the material is silicon dioxide, and the deposition thickness is 150 nm;
  • a high oxygen content IGZO active layer film layer is deposited on the gate insulating layer by sputtering method, and the oxygen content of the gas atmosphere during the sputtering process is 60% to 80%, the deposition thickness is about 50 nm, and the photolithography is performed. Etching the desired active layer pattern;
  • an etch barrier layer is deposited and photolithographically etched in a desired region, and the material is silicon dioxide, and has a thickness of about 50 nm;
  • the source and drain electrode metal layers are deposited by sputtering, and the material is molybdenum or aluminum, and the thickness is 200 nm, and the desired source and drain patterns are lithographically etched;
  • the passivation layer is prepared by chemical vapor deposition, and the material is silicon dioxide, and the thickness is about 100-500 nm, and the connection holes are lithographically etched;
  • a transparent electrode layer is sputter deposited on the passivation layer, and a pixel region or a sub-pixel region transparent electrode pattern is photolithographically etched to form an array substrate including both the enhancement thin film transistor and the depletion thin film transistor.
  • the above process is slightly different from the process shown in FIG. In this method, a high oxygen content active layer 13a is first deposited, and then a portion of the high oxygen content active layer is converted into a low oxygen content active layer 13b by a plasma treatment process.
  • the subsequent process is an alignment layer coating and imprint orientation process, and a spacer pad preparation and a corresponding color film substrate preparation process, and performing a process of boxing, cutting, filling, and sealing.
  • the TFT-LCD panel is full color light.
  • the pixel area and the peripheral circuit portion can be separately set to a dual type (i.e., including an enhancement type and a depletion type) thin film transistor as needed.
  • the array substrate since the array substrate has both the enhanced first thin film transistor and the depletion type second thin film transistor, the two types of thin film transistors are respectively formed at the set positions of the array substrate to perform their functions.
  • the array substrate of the embodiment can reduce the number of thin film transistors, simplify circuit traces, and greatly simplify the structure of the entire array substrate, compared with a single depletion thin film transistor or a single enhancement thin film transistor of the prior art array substrate.
  • the structural stability is greatly improved, and the effective pixel area of the array substrate is further increased.

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  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Description

阵列基板及其制造方法 技术领域
本发明实施例涉及一种阵列基板及其制造方法。 背景技术
薄膜晶体管（ Thin Film Transistor, 简称 TFT )是场效应晶体管的种类之 一，主要应用于平板显示装置中。薄膜晶体管液晶显示器（ Thin Film Transistor Liquid Crystal Display, 简称 TFT-LCD )具有体积小、 功耗低、 制造成本相 对较低和无辐射等特点， 在当前的平板显示器市场占据了主导地位。 AMOLED ( Active Matrix Organic Light Emitting Diode, 有源矩阵有机发光二 极管， 简称 AMOLED )面板，被称为下一代显示技术，相比传统的 TFT-LCD 面板， 具有反应速度快、 对比度高、 视角广等特点。
氧化物半导体铟镓辞氧（InGaZn04: IGZO ) 因其迁移率高、 均匀性好 和可在室温下制备等特点而被广泛地进行研究， 以期能够替代低温多晶硅 ( Low Temperature Poly-silicon, 简称 LTPS )作为阵列基板的有源层而实现 大尺寸 AMOLED面板的产业化。
然而，在现有技术当中，无论是 TFT-LCD显示器，还是 AMOLED面板， IGZO 半导体作为阵列基板的有源层沟道材料， 通常只单一利用其耗尽型或 增强型的特性， 这使得阵列基板的结构 （例如时序控制电路、 静电防治电路 等）较为复杂， 稳定性较差， 并且， 也会进而影响到阵列基板的有效像素面 积。 发明内容
本发明实施例提供了一种阵列基板及其制造方法， 其可以解决在现有技 术中当 IGZO半导体作为阵列基板的有源层沟道材料时， 只能单一利用其耗 尽型或增强型的特性， 导致阵列基板的结构较为复杂， 稳定性较差， 有效像 素面积不能够进一步增加的技术问题。
本发明实施例的一个方面提供了一种阵列基板， 包括： 衬底板和分别位 于衬底板上的第一薄膜晶体管和第二薄膜晶体管， 其中， 第一薄膜晶体管为 增强型， 第二薄膜晶体管为耗尽型。
在该阵列基板中， 第一薄膜晶体管的有源层和第二薄膜晶体管的有源层 材质例如包括氧化物半导体。
在一个实施例中， 所述氧化物半导体可以为铟镓辞氧化物或铪铟辞氧化 物。
在一个实施例中， 所述第一薄膜晶体管的有源层的氧含量高于所述第二 薄膜晶体管的有源层的氧含量。
在一个实施例中， 所述第一薄膜晶体管的有源层为包括较高氧含量的 IGZO有源层， 且所述第二薄膜晶体管的有源层为包括较低氧含量的 IGZO 有源层。
在一个实施例中， 所述阵列基板可以为顶栅型或底栅型。
在一个实施例中， 所述阵列基板可以应用于 TFT-LCD面板或 AMOLED 面板。
本发明实施例的另一方面提供了一种阵列基板的制造方法， 包括： 在衬底板上的设定位置形成第一薄膜晶体管和第二薄膜晶体管， 其中， 第一薄膜晶体管为增强型， 第二薄膜晶体管为耗尽型。
所述在衬底板上的设定位置形成第一薄膜晶体管和第二薄膜晶体管可以 包括以下步骤：
A、 形成包括氧化物半导体的有源层图形；
B、 在形成有源层图形的基板上形成掩模图案， 通过利用该掩模图案调 整基板设定位置的有源层的氧含量， 形成具有较高氧含量的第一薄膜晶体管 的有源层和具有较低氧含量的第二薄膜晶体管的有源层。
例如 , 所述氧化物半导体为铟镓辞氧化物或铪铟辞氧化物。
在一个实施例中， 所述调整基板设定位置的有源层的氧含量可以包括气 体氛围处理，所述气体氛围处理所釆用的气体包括还原性气体或氧化性气体 , 处理方式包括热退火或等离子体轰击。
在一个实施例中， 所述调整基板设定位置的有源层的氧含量可以包括液 体氛围处理，所述液体氛围处理所釆用的液体包括还原性液体或氧化性液体， 处理方式包括化学反应或元素扩散。 例如， 所述液体氛围处理可以为釆用稀 盐酸或氢氟酸的化学反应腐蚀处理。 在一个示例中， 所述液体氛围处理为釆 用稀盐酸或氢氟酸的化学反应腐蚀处理。
在一个实施例中， 所述调整基板设定位置的有源层的氧含量可以包括固 体氛围处理，所述固体氛围处理所釆用的固体包括还原性固体或氧化性固体 , 处理方式包括化学反应或元素扩散。 例如， 所述固体氛围处理可以为利用与 有源层接触的部分栅极绝缘层或钝化层进行的热扩散处理。 在一个示例中， 所述固体氛围处理为利用与有源层接触的部分栅极绝缘层或钝化层进行的热 扩散处理。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例的阵列基板的结构示意图
图 2为本发明实施例的阵列基板的结构示意图
图 3为图 2所示的阵列基板的制造过程示意图； 以及
图 4为阵列基板上不同氧含量的薄膜晶体管的转移特性曲线图 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
为了解决现有技术中 IGZO半导体作为阵列基板的有源层沟道材料， 只 能单一利用其耗尽型或增强型的特性， 阵列基板的结构较为复杂， 稳定性较 差， 有效像素面积不能够进一步增加的技术问题， 本发明实施例提供了一种 阵列基板及其制造方法。
如图 1所示，根据本发明实施例的阵列基板， 包括： 衬底板 10和分别位 于衬底板 10上的第一薄膜晶体管 201a和第二薄膜晶体管 201b, 其中， 第一 薄膜晶体管 201a为增强型， 第二薄膜晶体管 201b为耗尽型。
第一薄膜晶体管 201a的有源层和第二薄膜晶体管 201b的有源层材质包 括氧化物半导体，例如铟镓辞氧化物（ InGaZn04 )或铪铟辞氧化物（ HflnZnO ) 等。 可对有源层进行掺杂， 以提高薄膜晶体管的性能。在本发明的实施例中， 例如， 氧化物半导体为铟镓辞氧化物， 其具有迁移率高、 均勾性好和可在室 温下制备等优点。
阵列基板可以为顶栅型结构或底栅型结构， 可以为交叠型或反交叠型结 构。 或者， 阵列基板又可以为共面型或反共面型结构。 此外， 阵列基板也可 以构造为在衬底板的背面制备高反射层， 从而制备成顶发射器件。
衬底板 10的材质可包括玻璃或者石英等，但不限于这些透明材质。也可 以由陶瓷、 金属等形成衬底板 10以用于制备顶发射器件。
本发明实施例阵列基板可应用于 TFT-LCD面板或 AMOLED面板。
本发明实施例阵列基板的制造方法， 包括：
在衬底板上的设定位置形成第一薄膜晶体管和第二薄膜晶体管， 其中， 第一薄膜晶体管为增强型， 第二薄膜晶体管为耗尽型。
形成第一薄膜晶体管和第二薄膜晶体管的设定位置可以根据各自的功 能、 结构需要进行设计。 例如， 当薄膜晶体管在像素区及亚像素区中用作驱 动晶体管时， 可起到控制发光亮度的作用， 但本发明绝不限于此。 例如， 第 一和第二薄膜晶体管还可以用于时序控制电路， 或者用于扫描驱动电路和数 据驱动电路， 或者用于阵列基板测试区， 或者用于阵列基板外围静电防治电 路等。
在衬底板上的设定位置形成第一薄膜晶体管和第二薄膜晶体管时， 形成 有源层可以包括：
步骤 101、 形成包括氧化物半导体的有源层图形；
步骤 102、 在形成有源层图形的基板上形成掩模图案， 通过利用该掩模 图案调整基板设定位置的有源层的氧含量， 形成具有较高氧含量的第一薄膜 晶体管的有源层和具有较低氧含量的第二薄膜晶体管的有源层。
在本实施例中， 通过例如构图工艺可以在形成有源层图形的基板上形成 掩模图案。 需要说明的是， 本发明的实施例中所称的构图工艺包括光刻胶涂 布、 掩模、 曝光、 显影、 刻蚀、 光刻胶剥离等工艺， 光刻胶以正性光刻胶为 例， 但是这并非对本发明的限制。
此外， 例如， 氧化物半导体为铟镓辞氧化物或铪铟辞氧化物。
调整基板设定位置的有源层的氧含量可以釆用气体氛围处理、 液体氛围 处理或固体氛围处理的方式。 气体氛围处理所釆用的气体包括还原性气体或 氧化性气体， 例如 ¾, 02, C¾等， 处理方式包括热退火或等离子体轰击等。 液体氛围处理所釆用的液体包括还原性液体或氧化性液体， 处理方式包括化 学反应或元素扩散， 例如， 通过稀盐酸或氢氟酸的化学反应腐蚀处理。 固体 氛围处理所釆用的固体包括还原性固体或氧化性固体， 处理方式包括化学反 应或元素扩散， 例如， 通过与有源层接触的部分栅极绝缘层或钝化层的热扩 散处理。
例如， 当釆用 02氛围处理调整基板设定位置的有源层的氧含量时，具体 步骤可以为： 将形成有掩模图案的基板在 02氛围中进行热退火处理，退火温 度为 130°C , 退火时间为 1小时， 最终在设定位置的有源层的氧含量提高以 形成较高氧含量有源层。当通过 ¾氛围处理来调整基板设定位置的有源层的 氧含量时，具体步骤可以为：将形成有掩模图案的基板送入 ¾氛围的反应离 子刻蚀设备中进行等离子体轰击处理，功率大小 2 ~ 8 kW,处理时间 180秒， 最终在设定位置的有源层的氧含量降低以形成较低氧含量有源层。 例如， 该 形成有掩模图案的基板可以通过构图工艺形成。
在步骤 101中，形成包括氧化物半导体的有源层图形的步骤可以具体为： 釆用溅射方法沉积有源层膜层（例如低氧含量有源层膜层或高氧含量有源层 膜层）， 溅射过程中气体氛围的氧含量为 10%~80%,有源层膜层的沉积厚度 为 50纳米， 然后通过掩模刻蚀工艺形成有源层图形。
图 2示出了根据本发明实施例的阵列基板。 在该实施例中， 阵列基板釆 用底栅型结构， 可用于制备 AMOLED面板或 TFT-LCD面板。 如图 3所示， 该阵列基板的形成过程包括： 在透明衬底板 10上依次形成： 绝缘緩冲层（图 中未示出 )、栅极 11、 栅极绝缘层 12、 经气体氛围处理后氧含量不同的两种 IGZO有源层 (即高氧含量有源层 13a和低氧含量有源层 13b )、 刻蚀阻挡层 14、 源极 15和漏极 16、 钝化层（图中未示出） 、 透明电极（图中未示出） 和像素界定层（图中未示出） 。
需要说明的是， 图 2和图 3仅是用于说明增强型 TFT和耗尽型 TFT的 结构， 并不用于限定增强型 TFT和耗尽型 TFT的位置关系。 在实际的阵列 基板上， 包含高氧含量有源层 13a的增强型 TFT和包含低氧含量有源层 13b 的耗尽型 TFT并不一定都是相邻设置。 比如， 在液晶显示装置的像素区域主 要使用耗尽型 TFT, 而在周边电路区域则是增强型 TFT和耗尽型 TFT搭配 使用。
在本发明实施例的阵列基板中，透明衬底板的材质可以为玻璃或石英等； 栅极可以由钼、铜等金属形成； 栅极绝缘层材质可以为二氧化硅、 氮化硅等； IGZO有源层包括高氧含量和低氧含量两种有源层区域； 刻蚀阻挡层可以由 二氧化硅等材质形成， 用于防止源极和漏极在湿法刻蚀时对已形成的用作沟 道的 IGZO有源层造成损伤； 源极和漏极可釆用同一材质， 例如钼、 铝、 钛、 铜等金属， 或这些金属的复合层， 或这些金属的合金等。
阵列基板上不同氧含量的薄膜晶体管的转移特性 (当薄膜晶体管的漏极 和源极之间的电压保持不变时， 栅极与源极之间的电压和漏极电流的关系称 为转移特性， 其描述的是栅极与源极之间的电压对漏极电流的控制作用）如 图 4所示， 其中， （a )图对应于包括较低氧含量的 IGZO有源层的薄膜晶体 管，该薄膜晶体管为耗尽型（在输入电压为零时，已有一定的漏极电流存在）； ( b )图对应于包括正常氧含量的 IGZO有源层的薄膜晶体管， 该薄膜晶体管 为弱耗尽型； （c ) 图对应于包括较高氧含量的 IGZO有源层的薄膜晶体管， 该薄膜晶体管为增强型 （当输入电压为零时， 漏极电流几乎为零， 需要输入 电压达到一定值才能产生一定的漏极电流） 。
通过本发明第一实施例的制造阵列基板的方法来制备图 2所示的阵列基 板， 具体方法 ^下：
透明衬底板釆用标准方法（例如 UV分解清洗法、 药液喷淋清洗法或超 声波清洗法等）清洗， 之后釆用化学气相沉积方法沉积二氧化硅薄膜作为绝 缘緩冲层， 沉积厚度为 200纳米；
之后釆用溅射方法在绝缘緩冲层上沉积栅极金属层， 材质为钼， 沉积厚 度为 200纳米， 并光刻刻蚀出所需栅极图形；
再釆用化学气相沉积方法在 370°C在栅金属层上沉积栅极绝缘层， 材质 为二氧化硅， 沉积厚度为 150纳米；
之后釆用溅射方法在栅绝缘层上沉积低氧含量 IGZO有源层膜层， 溅射 过程中气体氛围的氧含量为 10 %〜 30 %, 沉积厚度约为 50纳米， 并光刻刻 蚀出所需的有源层图形；
再次通过光刻工艺在基板上形成掩模图案， 将形成有掩模图案的基板在 02氛围中进行退火工艺以改变设定位置的 IGZO有源层的氧含量， 其中 02 氛围的氧含量为 60 % ~ 80 %, 退火温度为 130°C , 退火时间 1 小时， 最终在 设定位置形成高氧含量有源层；
进而在所需区域沉积、 光刻刻蚀出刻蚀阻挡层， 材质为二氧化硅， 厚度 约为 50 纳米；
之后釆用溅射方法在所得结构上沉积源、漏电极金属层，材质为钼或铝， 厚度为 200纳米， 并光刻刻蚀出所需源极、 漏极图形； 厚度约为 100〜 500纳米， 并进而光刻刻蚀出连接通孔；
再在钝化层上溅射沉积透明电极层， 并光刻刻蚀出像素区或亚像素区透 明电极图形；
最后在背板上旋涂沉积亚克力系材料并光刻、 固化以形成像素界定层， 厚度约为 1.5微米， 最终完成了同时包括增强型薄膜晶体管和耗尽型薄膜晶 体管的阵列基板。
阵列基板制备完成后，可用于继续制备 AMOLED面板或 TFT-LCD面板。 以制备 AMOLED面板为例， 后续具体过程可以为： 釆用 02等离子体处理阵 列基板表面， 进一步提升透明电极的表面功函数， 同时钝化基板表面层； 在 有机金属薄膜沉积高真空系统中将有机材料及阳极金属薄层热蒸发蒸镀到阵 列基板上； 在 lxl(T5 Pa 的真空下通过热蒸发蒸镀依次形成空穴传输层（约 170°C )、 有机发光层及电子传输层（约 190°C )和阴极（约 900°C ) , 其中， 空穴传输层可以为 50纳米厚的 ΝΡΒ(Ν, Ν'-二苯基 -N-N'二 (1-萘基) -1,1'二苯基 -4, 4'-二胺)；有机发光层可以通过分像素区掩模蒸镀工艺而形成，绿光、蓝光 和红光像素区分别包括掺杂磷光材料，该掺杂磷光材料的主体材料可以为 25 纳米厚的 CBP: (ppy)2Ir(acac) ( 4,4'-Ν,Ν'-二咔唑-联苯： 二 (2-苯基吡啶）乙酰 丙酮铱） 、 CBP: FIrpic ( 4,4'-Ν,Ν'-二咔唑-联苯： 双 (4,6-二氟苯基吡啶 -N,C2) 吡啶曱酰合铱）和 CBP: Btp2Ir(acac) ( 4,4'-Ν,Ν'-二咔唑-联苯： 二 (2-(2，-苯并 [4,5-a]噻吩基)吡啶 -N,C30)铱（乙酰丙酮）） 。 电子传输层可以为 25 纳米厚的 Bphen ( 4,7-二苯基 -1,10-菲啰啉） ； 阴极可以为约 200纳米厚的钐 /铝层。 该 AMOLED面板为全彩发光， 出光方式为底出光。 该 AMOLED面板 的阵列基板中， 外围电路及防静电电路等可设置有双型 (即包含增强型和耗 尽型）薄膜晶体管。在亚像素区中， 因红光、蓝光 OLED器件发光效率较低， 所对应的驱动薄膜晶体管釆用低氧含量 IGZO有源层； 因绿光 OLED器件发 光效率较高， 所对应的驱动薄膜晶体管釆用高氧含量 IGZO有源层。
与第一实施例类似， 通过本发明第二实施例的制造阵列基板的方法来制 备图 3所示的阵列基板， 具体方法如下：
透明衬底板釆用标准方法清洗， 之后釆用化学气相沉积方法沉积二氧化 硅薄膜作为绝缘緩冲层， 沉积厚度为 200纳米；
之后釆用溅射方法在绝缘緩冲层上沉积栅极金属层， 材质为钼， 沉积厚 度为 200 纳米， 并光刻刻蚀出所需栅极图形；
再釆用化学气相沉积方法在 370 °C下在栅极金属层上沉积栅极绝缘层， 材质为二氧化硅， 沉积厚度为 150纳米；
之后釆用溅射方法在栅极绝缘层上沉积高氧含量 IGZO有源层膜层， 溅 射过程中气体氛围的氧含量为 60 %〜 80 %, 沉积厚度约为 50纳米， 并光刻 刻蚀出所需的有源层图形；
再次通过光刻工艺在基板上形成掩模图案， 将形成有掩模图案的基板在 ¾氛围的反应离子刻蚀设备中进行等离子体处理工艺以改变设定位置的 IGZO有源层的氧含量， 功率大小 2 ~ 8 kW, 处理时间 180秒， 最终在设定 位置形成低氧含量有源层；
进而在所需区域沉积、 光刻刻蚀出刻蚀阻挡层， 材质为二氧化硅， 厚度 约为 50纳米；
之后釆用溅射方法沉积源、 漏电极金属层， 材质为钼或铝， 厚度为 200 纳米， 并光刻刻蚀出所需源极、 漏极图形；
再釆用化学气相沉积方法制备钝化层，材质为二氧化硅，厚度约为 100 ~ 500纳米， 并进而光刻刻蚀出连接孔；
再在钝化层上溅射沉积透明电极层， 并光刻刻蚀出像素区或亚像素区透 明电极图形， 最终形成同时包括增强型薄膜晶体管和耗尽型薄膜晶体管的阵 列基板。 上述过程与图 4中所示过程略有不同。 在该方法中， 先沉积形成高氧含 量有源层 13a, 之后再通过等离子体处理工艺将部分的高氧含量有源层转化 成低氧含量有源层 13b。
阵列基板制备完成后，可用于继续制备 AMOLED面板或 TFT-LCD面板。 以制备 TFT-LCD面板为例， 后续工艺为取向层涂布及压印取向工艺， 以及 隔物垫制备和对应的彩膜基板制备工艺， 并进行对盒、 切割、 灌晶和封胶工 艺
该 TFT-LCD面板为全彩发光。 像素区和外围电路部分可根据需要分别 设置为双型 （即包含增强型和耗尽型）薄膜晶体管。
在本发明技术方案中， 由于阵列基板同时具有增强型的第一薄膜晶体管 和耗尽型的第二薄膜晶体管， 将这两种类型的薄膜晶体管分别形成在阵列基 板的设定位置以发挥其功能特性， 对比于现有技术阵列基板的单一耗尽型薄 膜晶体管或单一增强型薄膜晶体管， 实施例的阵列基板可减少薄膜晶体管设 置数量， 简化电路走线， 使整个阵列基板的结构大为简化， 结构稳定性大大 提高， 阵列基板有效像素面积也得以进一步增加。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板， 包括： 衬底板和分别位于衬底板上的第一薄膜晶体管 和第二薄膜晶体管， 其中第一薄膜晶体管为增强型， 第二薄膜晶体管为耗尽 型。
2、如权利要求 1所述的阵列基板，其中第一薄膜晶体管的有源层和第二 薄膜晶体管的有源层的材质包括氧化物半导体。
3、如权利要求 2所述的阵列基板，其中所述氧化物半导体为铟镓辞氧化 物或铪铟辞氧化物。
4、如权利要求 2或 3所述的阵列基板，其中所述第一薄膜晶体管的有源 层的氧含量高于所述第二薄膜晶体管的有源层的氧含量。
5、如权利要求 4所述的阵列基板，其中所述第一薄膜晶体管的有源层为 包括较高氧含量的 IGZO的有源层， 且所述第二薄膜晶体管的有源层为包括 较低氧含量的 IGZO的有源层。
6、如权利要求 1-5中任一所述的阵列基板， 其中所述阵列基板为顶栅型 或底栅型。
7、 如权利要求 1-6 中任一所述的阵列基板， 其中所述阵列基板应用于 TFT-LCD面板或 AMOLED面板。
8、 一种阵列基板的制造方法， 其中包括：
在衬底板上的设定位置形成第一薄膜晶体管和第二薄膜晶体管， 其中第 一薄膜晶体管为增强型， 第二薄膜晶体管为耗尽型。
9、如权利要求 8所述的制造方法，其中所述在衬底板上的设定位置形成 第一薄膜晶体管和第二薄膜晶体管包括：
形成包括氧化物半导体的有源层图形；
在形成有源层图形的基板上形成掩模图案， 通过利用该掩模图案调整基 板设定位置的有源层的氧含量， 形成具有较高氧含量的第一薄膜晶体管的有 源层和具有较低氧含量的第二薄膜晶体管的有源层。
10、 如权利要求 9所述的制造方法， 其中所述氧化物半导体为铟镓辞氧 化物或铪铟辞氧化物。
11、如权利要求 9或 10所述的制造方法，其中所述调整基板设定位置的 有源层的氧含量包括气体氛围处理， 所述气体氛围处理所釆用的气体包括还 原性气体或氧化性气体， 处理方式包括热退火或等离子体轰击。
12、如权利要求 9或 10所述的制造方法，其中所述调整基板设定位置的 有源层的氧含量包括液体氛围处理， 所述液体氛围处理所釆用的液体包括还 原性液体或氧化性液体， 处理方式包括化学反应或元素扩散。
13、如权利要求 12所述的制造方法，其中所述液体氛围处理为釆用稀盐 酸或氢氟酸的化学反应腐蚀处理。
14、如权利要求 9或 10所述的制造方法，其中所述调整基板设定位置的 有源层的氧含量包括固体氛围处理， 所述固体氛围处理所釆用的固体包括还 原性固体或氧化性固体， 处理方式包括化学反应或元素扩散。
15、如权利要求 14所述的制造方法，其中所述固体氛围处理为利用与有 源层接触的部分栅极绝缘层或钝化层进行的热扩散处理。
PCT/CN2012/084880 2012-02-02 2012-11-20 阵列基板及其制造方法 Ceased WO2013113232A1 (zh)

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