WO2013101668A1 - Barrier tape for keep-out zone management - Google Patents
Barrier tape for keep-out zone management Download PDFInfo
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- WO2013101668A1 WO2013101668A1 PCT/US2012/070990 US2012070990W WO2013101668A1 WO 2013101668 A1 WO2013101668 A1 WO 2013101668A1 US 2012070990 W US2012070990 W US 2012070990W WO 2013101668 A1 WO2013101668 A1 WO 2013101668A1
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- Prior art keywords
- microelectronic
- microelectronic substrate
- microelectronic device
- substrate
- flowable material
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- H10W76/47—
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- H10W74/012—
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- H10W74/15—
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- H10W72/01308—
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- H10W72/072—
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- H10W72/073—
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- H10W72/07304—
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- H10W72/387—
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- H10W72/884—
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- H10W72/931—
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- H10W74/111—
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- H10W90/724—
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- H10W90/734—
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- H10W90/754—
Definitions
- microelectronic device packaging and, more particularly, to the management of flowable materials used in the packaging of microelectronic devices.
- FIG. 1 is a side cross-sectional view of a microelectronic assembly including a microelectronic device mounted on a microelectronic substrate.
- FIG. 2 is a side cross-sectional view of the microelectronic assembly of FIG. 1 wherein an underfill material is dispensed between the microelectronic device and the microelectronic substrate.
- FIG. 3 is a side cross-sectional view of a microelectronic assembly of FIG. 2 after the underfill material has been dispensed and cured.
- FIG. 4 is a top plan view of the microelectronic assembly of FIG. 3 along line 4-4.
- FIG. 5 is a side cross-sectional view of a microelectronic assembly including a trench formed in the microelectronic substrate for containment of underfill material.
- FIG. 6 is a side cross-sectional view of a microelectronic assembly including a dam formed on the microelectronic substrate for containment of underfill material.
- FIG. 7 is a side cross-sectional view of a microelectronic assembly including a barrier tape applied to the microelectronic substrate for containment of underfill material, according to an embodiment of the present description.
- FIG. 8 is a side cross-sectional view of a microelectronic assembly of FIG. 7 after the removal of the barrier tape to form a microelectronic device package, according to an embodiment of the present description.
- FIG. 9 is a top plan view of a microelectronic assembly including a barrier tape applied to the microelectronic substrate for containment of underfill material, according to one embodiment of the present description.
- FIG. 10 is a top plan view of a microelectronic assembly including a barrier tape applied to the microelectronic substrate for containment of underfill material, according to another embodiment of the present description.
- FIG. 11 is a side cross-sectional view of a microelectronic assembly a barrier tape is used to contain an encapsulant material dispensed on a microelectronic device, according to one embodiment of the present description.
- FIG. 12 is a side cross-sectional view of the microelectronic assembly of FIG. 11 after the removal of the barrier tape to form a microelectronic device package, according to one embodiment of the present description.
- FIG. 13 is a flow diagram of a process of utilizing a barrier tape in the fabrication of a microelectronic device package, according to an embodiment of the present description.
- FIG. 14 is a flow diagram of a process of utilizing a barrier tape in the fabrication of a microelectronic device package, according to another embodiment of the present description.
- Embodiments of the present description relate to the field of microelectronic device packaging and, more particularly, to the management of flowable materials used in the packaging of microelectronic devices, wherein a barrier tape may be positioned proximate a keep-out zone defined on a microelectronic substrate to arrest the
- a microelectronic assembly 100 may include a microelectronic device 102, such as a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit, or the like, electrically attached to a microelectronic substrate 112, such as an interposer, a printed circuit board, and the like, through a plurality of interconnects 122, such as refiowable solder bumps or balls, in a configuration generally known as a flip-chip or controlled collapse chip connection ("C4")
- the interconnects 122 may extend between bond pads 104 proximate a land surface 106 of the microelectronic device 102 and mirror-image bond pads 114 proximate an attachment surface 116 of the microelectronic substrate 112.
- microelectronic device bond pads 104 may be in electrical communication with integrated circuitry (not shown) within the microelectronic device 102.
- the microelectronic substrate bond pads 114 may be in electrical communication with a hierarchy of electrically conductive paths (illustrated as dashed lines 118) to provide electrical communication routes to external components (not shown).
- the microelectronic substrate 112 may be primarily composed of any appropriate material, including, but not limited to, dielectric materials, bismaleimine triazine resin, fire retardant grade 4 material, polyimide materials, glass reinforced epoxy matrix material, and the like, as well as combinations, laminates, and/or multiple layers thereof.
- the conductive paths 118 may be composed of any conductive material, including but not limited to metals, such as copper and aluminum, and alloys thereof.
- the interconnects 122 can be made any appropriate material, including, but not limited to, solders and conductive filled epoxies.
- Solder materials may include may be any appropriate material, including but not limited to, lead/tin alloys, such as 63% tin / 37%) lead solder, or lead-free solders, such a pure tin or high tin content alloys (e.g. 90% or more tin), such as tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, and similar alloys.
- the solder is reflowed, either by heat, pressure, and/or sonic energy to secure the solder between the microelectronic device bond pads 104 and the microelectronic substrate bond pads 114.
- an electrically-insulating flowable material such as an underfill material 124, may be disposed between the microelectronic device 102 and the microelectronic substrate 112, which substantially encapsulates the interconnects 122.
- the underfill material 124 may be used to reduce mechanical stress issues that can arise from thermal expansion mismatch between the microelectronic device 102 and the microelectronic substrate 1 12.
- the underfill material 124 may be an epoxy material, including, but not limited to epoxy, cyanoester, silicone, siloxane and phenolic based resins, that has sufficiently low viscosity to be wicked between the microelectronic device 102 and the microelectronic substrate 112 by capillary action when introduced by an underfill material dispenser 130 along at least one edge 120 of the microelectronic device 102 (e.g. the microelectronic device edge 120 extends between the microelectronic device land surface 106 and a microelectronic device back surface 108), which will be understood to those skilled in the art.
- the underfill material 124 may be subsequently cured (hardened), such as by heat or radiation, which forms the microelectronic device package 140 shown in FIG. 3.
- interconnect pitch 126 e.g. distance between the interconnects 122
- interconnect height 128 e.g. distance between microelectronic device land surface 106 and the microelectronic substrate attachment surface 116
- decreasing the viscosity and/or improving the wettability of the underfill material 124 results in the underfill material 124 bleeding out and substantially surrounding the microelectronic device 102, as shown in FIGs. 3 and 4.
- bleed-out tongue This bleed-out area beyond the microelectronic device edges 120 is generally referred to as a "bleed-out tongue" 132 having a varying width 134.
- the bleed-out tongue 132 may be a problem as it can cover and contaminate valuable surface area on the microelectronic substrate 112 within what is known as a "keep-out zone" (illustrated as the shaded area 136).
- the keep-out zone 136 may be an area where other components (not shown), such as other microelectronic devices, solder structures, bond pads, and the like, are mounted and/or positioned.
- a trench 142 may be formed in the microelectronic substrate, such as by etching into a solder resist layer and/or a dielectric layer which is a constituent of the microelectronic substrate 112, proximate the keep-out zone 136 to arrest encroachment of the underfill material 124.
- the formation of the trench 142 may be effective in stopping encroachment of the underfill material 124, it is limited by the routing of the conductive paths 118 on or in the microelectronic substrate 112 and it may require additional dielectric layers for proper conductive path 118 routing, as will be understood to those skilled in the art.
- the formation of the trench 142 may not be an effective way to contain a large quantity of underfill material 124. Furthermore, the trench 142 takes up valuable surface area on the microelectronic substrate 112. As shown in FIG. 6, a dam 144 may be formed proximate the keep-out zone 136 to arrest encroachment of the underfill material 124. The dam 144 may be formed by dispensing a bead of polymer material, such as an epoxy, onto the microelectronic substrate attachment surface 116. Although the formation of the dam 144 may also be effective in stopping encroachment of the underfill material 124, it also requires several addition processing steps and leaves a structure (i.e. the dam 144) that takes up valuable surface area on the microelectronic substrate 112.
- FIG. 7 illustrates one embodiment of the present description wherein a barrier tape 200 is positioned proximate the keep-out zone 136.
- the barrier tape 200 is directly adjacent the keep-out zone 136.
- the barrier tape 200 is closer to the microelectronic device 102 than the keep-out zone 136.
- the barrier tape 200 blocks any encroachment the underfill material 124 into the keep-out zone 136.
- the barrier tape 200 may comprise a base film 202 and an adhesive layer 204.
- the base film may be any appropriate material, such as a polymer material, including but not limited to polyester, polyethylene (“PPE”) and its high performance derivatives, polypropylene (“PPP”) and its high performance derivatives, polyvinyl acetate, poly vinyl chloride (“PVC”), poly vinyl fluoride, polytetrafluoroethylene (“PTFE”), polyamide and polyimide, as well as copolymers of any of these polymers, and multiple layers of any of these polymers.
- the adhesive layer 204 may be any appropriate adhesive, including but not limited to acrylic, acetate, styrene -butadiene, silicone, epoxy, ester, urethane and cyanoacrylate, as well as derivatives of any of these polymers.
- the underfill material 124 may then be cured (hardened) using heat or radiation to form a microelectronic device package 140.
- the barrier tape 200 may be optionally removed after curing, as shown in FIG. 8. If the barrier tape 200 is removed, the resulting cured underfill material 124 may have an edge surface 152 that is unsupported (e.g. does not abut any other structure) and is substantially perpendicular to the microelectronic substrate attachment surface 116.
- the barrier tape 200 may be positioned to substantially surround the microelectronic device 102. In other embodiment as shown in FIG. 10, the barrier tape 200 may extend along one (illustrated) or more microelectronic device edge 120. As illustrated in FIG. 10, the barrier tape 200 may be positioned proximate the microelectronic device edge 120 where the underfill material 124 is dispensed (FIG. 2), which is the most susceptible area for keep-out zone 136
- a microelectronic device 302 may be attached by its back surface 308 to an attachment surface 316 of a microelectronic substrate 312 with a layer of adhesive 324, including, but not limited to, epoxies, urethane, polyurethane, and silicone elastomers.
- a plurality of bond pads 304 may be disposed on a land surface 306 of the microelectronic device 302.
- the microelectronic device bond pads 304 may be near at least one edge 318 of the microelectronic device 302 (e.g.
- the microelectronic device edge 318 extends between the microelectronic device land surface 306 and a microelectronic device back surface 308) and may be electrically connected by bond wires 322 to corresponding bond pads 314 on the microelectronic substrate 312.
- a flowable material such as an encapsulant material 332 may be deposited thereon.
- the barrier tape 200 may be positioned proximate a keep-out zone (illustrated generally with arrows 334 and previously described) to substantially surround the microelectronic device 302, the bond wires 322, and the microelectronic substrate bond pads 314.
- the encapsulant material 332 may then be deposited to cover and protect the microelectronic device 302 and the bond wires 322, wherein the barrier tape 200 prevents the encapsulant material 332 from encroaching into the keep-out zone 334.
- the encapsulant material 332 may include, but is not limited to plastics, resins, epoxies, glob top materials, and the like.
- the encapsulant material 332 may then be cured (hardened) to form a
- the barrier tape 200 may be optionally removed, as shown in FIG. 12. If the barrier tape 200 is removed, the resulting cured encapsulant material 332 may have an edge surface 336 that is unsupported (e.g. does not abut any other structure) and is substantially perpendicular to the microelectronic substrate attachment surface 316.
- a process flow using a barrier tape for keep-out zone management is illustrated in the flow diagram of FIG. 13.
- a microelectronic device may be attached to a microelectronic substrate.
- a barrier tape may be applied on the
- microelectronic substrate proximate a keep-out zone defined on the microelectronic substrate, as defined in block 420.
- a flowable material may be applied adjacent the microelectronic device. The flowable material may then be cured, as defined in block 440. If the barrier tape is to remain on microelectronic substrate, the process is ended, as shown. However, if the barrier tape is not to remain on the microelectronic substrate, after curing the flowable material, the barrier tape may be removed, as defined in block 450.
- a barrier tape may be applied on the microelectronic substrate proximate a keep-out zone defined on the microelectronic substrate.
- a microelectronic device may be attached to a microelectronic substrate, as defined in block 520.
- a flowable material may be applied adjacent the microelectronic device. The flowable material may then be cured, as defined in block 540. If the barrier tape is to remain on microelectronic substrate, the process is ended, as shown. However, if the barrier tape is not to remain on the microelectronic substrate, after curing the flowable material, the barrier tape may be removed, as defined in block 550.
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The present description relates to the field of microelectronic device packaging, wherein flowable materials used in microelectronic device packaging may be managed with the use of a barrier tape positioned proximate a keep-out zone defined on a microelectronic substrate to arrest the encroachment of any flowable material into the keep-out zone.
Description
BARRIER TAPE FOR KEEP-OUT ZONE MANAGEMENT
BACKGROUND
Embodiments of the present description generally relate to the field of
microelectronic device packaging and, more particularly, to the management of flowable materials used in the packaging of microelectronic devices.
BRIEF DESCRIPTION OF THE DRAWINGS
The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which:
FIG. 1 is a side cross-sectional view of a microelectronic assembly including a microelectronic device mounted on a microelectronic substrate.
FIG. 2 is a side cross-sectional view of the microelectronic assembly of FIG. 1 wherein an underfill material is dispensed between the microelectronic device and the microelectronic substrate.
FIG. 3 is a side cross-sectional view of a microelectronic assembly of FIG. 2 after the underfill material has been dispensed and cured.
FIG. 4 is a top plan view of the microelectronic assembly of FIG. 3 along line 4-4. FIG. 5 is a side cross-sectional view of a microelectronic assembly including a trench formed in the microelectronic substrate for containment of underfill material.
FIG. 6 is a side cross-sectional view of a microelectronic assembly including a dam formed on the microelectronic substrate for containment of underfill material.
FIG. 7 is a side cross-sectional view of a microelectronic assembly including a barrier tape applied to the microelectronic substrate for containment of underfill material, according to an embodiment of the present description.
FIG. 8 is a side cross-sectional view of a microelectronic assembly of FIG. 7 after the removal of the barrier tape to form a microelectronic device package, according to an embodiment of the present description.
FIG. 9 is a top plan view of a microelectronic assembly including a barrier tape applied to the microelectronic substrate for containment of underfill material, according to one embodiment of the present description.
FIG. 10 is a top plan view of a microelectronic assembly including a barrier tape applied to the microelectronic substrate for containment of underfill material, according to another embodiment of the present description.
FIG. 11 is a side cross-sectional view of a microelectronic assembly a barrier tape is used to contain an encapsulant material dispensed on a microelectronic device, according to one embodiment of the present description.
FIG. 12 is a side cross-sectional view of the microelectronic assembly of FIG. 11 after the removal of the barrier tape to form a microelectronic device package, according to one embodiment of the present description.
FIG. 13 is a flow diagram of a process of utilizing a barrier tape in the fabrication of a microelectronic device package, according to an embodiment of the present description.
FIG. 14 is a flow diagram of a process of utilizing a barrier tape in the fabrication of a microelectronic device package, according to another embodiment of the present description.
DETAILED DESCRIPTION
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Therefore, the use of the phrase "one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing
from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.
Embodiments of the present description relate to the field of microelectronic device packaging and, more particularly, to the management of flowable materials used in the packaging of microelectronic devices, wherein a barrier tape may be positioned proximate a keep-out zone defined on a microelectronic substrate to arrest the
encroachment of any flowable material into the keep-out zone.
In the production of microelectronic packages, microelectronic devices are generally mounted on microelectronic substrates, which provide electrical communication routes between the microelectronic devices and external components. As shown in FIG. 1, a microelectronic assembly 100 may include a microelectronic device 102, such as a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit, or the like, electrically attached to a microelectronic substrate 112, such as an interposer, a printed circuit board, and the like, through a plurality of interconnects 122, such as refiowable solder bumps or balls, in a configuration generally known as a flip-chip or controlled collapse chip connection ("C4")
configuration. The interconnects 122 may extend between bond pads 104 proximate a land surface 106 of the microelectronic device 102 and mirror-image bond pads 114 proximate an attachment surface 116 of the microelectronic substrate 112. The
microelectronic device bond pads 104 may be in electrical communication with integrated circuitry (not shown) within the microelectronic device 102. The microelectronic substrate bond pads 114 may be in electrical communication with a hierarchy of electrically conductive paths (illustrated as dashed lines 118) to provide electrical communication routes to external components (not shown).
The microelectronic substrate 112 may be primarily composed of any appropriate material, including, but not limited to, dielectric materials, bismaleimine triazine resin, fire retardant grade 4 material, polyimide materials, glass reinforced epoxy matrix material,
and the like, as well as combinations, laminates, and/or multiple layers thereof. The conductive paths 118 may be composed of any conductive material, including but not limited to metals, such as copper and aluminum, and alloys thereof.
The interconnects 122 can be made any appropriate material, including, but not limited to, solders and conductive filled epoxies. Solder materials may include may be any appropriate material, including but not limited to, lead/tin alloys, such as 63% tin / 37%) lead solder, or lead-free solders, such a pure tin or high tin content alloys (e.g. 90% or more tin), such as tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, and similar alloys. When the microelectronic device 102 is attached to the microelectronic substrate 112 with interconnects 122 made of solder, the solder is reflowed, either by heat, pressure, and/or sonic energy to secure the solder between the microelectronic device bond pads 104 and the microelectronic substrate bond pads 114.
As shown in FIG. 2, an electrically-insulating flowable material, such as an underfill material 124, may be disposed between the microelectronic device 102 and the microelectronic substrate 112, which substantially encapsulates the interconnects 122. The underfill material 124 may be used to reduce mechanical stress issues that can arise from thermal expansion mismatch between the microelectronic device 102 and the microelectronic substrate 1 12. The underfill material 124 may be an epoxy material, including, but not limited to epoxy, cyanoester, silicone, siloxane and phenolic based resins, that has sufficiently low viscosity to be wicked between the microelectronic device 102 and the microelectronic substrate 112 by capillary action when introduced by an underfill material dispenser 130 along at least one edge 120 of the microelectronic device 102 (e.g. the microelectronic device edge 120 extends between the microelectronic device land surface 106 and a microelectronic device back surface 108), which will be understood to those skilled in the art. The underfill material 124 may be subsequently cured (hardened), such as by heat or radiation, which forms the microelectronic device package 140 shown in FIG. 3.
With the pressure to decrease the size of the microelectronic device packages 140, interconnect pitch 126 (e.g. distance between the interconnects 122) and interconnect height 128 (e.g. distance between microelectronic device land surface 106 and the microelectronic substrate attachment surface 116) has decreased. Thus, it has become successively more difficult to obtain adequate underfill material dispersion without continuously decreasing the viscosity of the underfill material 124 or improving its
wettability properties, as will be understood to those skilled in the art. However, decreasing the viscosity and/or improving the wettability of the underfill material 124 results in the underfill material 124 bleeding out and substantially surrounding the microelectronic device 102, as shown in FIGs. 3 and 4. This bleed-out area beyond the microelectronic device edges 120 is generally referred to as a "bleed-out tongue" 132 having a varying width 134. The bleed-out tongue 132 may be a problem as it can cover and contaminate valuable surface area on the microelectronic substrate 112 within what is known as a "keep-out zone" (illustrated as the shaded area 136). The keep-out zone 136 may be an area where other components (not shown), such as other microelectronic devices, solder structures, bond pads, and the like, are mounted and/or positioned.
Various methods may be used to prevent the flow of underfill materials into keep- out zones. As shown in FIG. 5, a trench 142 may be formed in the microelectronic substrate, such as by etching into a solder resist layer and/or a dielectric layer which is a constituent of the microelectronic substrate 112, proximate the keep-out zone 136 to arrest encroachment of the underfill material 124. Although the formation of the trench 142 may be effective in stopping encroachment of the underfill material 124, it is limited by the routing of the conductive paths 118 on or in the microelectronic substrate 112 and it may require additional dielectric layers for proper conductive path 118 routing, as will be understood to those skilled in the art. Additionally, the formation of the trench 142 may not be an effective way to contain a large quantity of underfill material 124. Furthermore, the trench 142 takes up valuable surface area on the microelectronic substrate 112. As shown in FIG. 6, a dam 144 may be formed proximate the keep-out zone 136 to arrest encroachment of the underfill material 124. The dam 144 may be formed by dispensing a bead of polymer material, such as an epoxy, onto the microelectronic substrate attachment surface 116. Although the formation of the dam 144 may also be effective in stopping encroachment of the underfill material 124, it also requires several addition processing steps and leaves a structure (i.e. the dam 144) that takes up valuable surface area on the microelectronic substrate 112.
FIG. 7 illustrates one embodiment of the present description wherein a barrier tape 200 is positioned proximate the keep-out zone 136. In one embodiment, the barrier tape 200 is directly adjacent the keep-out zone 136. In another embodiment, the barrier tape 200 is closer to the microelectronic device 102 than the keep-out zone 136. When the underfill material 124 is dispensed, such as illustrated in FIG. 2, the barrier tape 200
blocks any encroachment the underfill material 124 into the keep-out zone 136. The barrier tape 200 may comprise a base film 202 and an adhesive layer 204. The base film may be any appropriate material, such as a polymer material, including but not limited to polyester, polyethylene ("PPE") and its high performance derivatives, polypropylene ("PPP") and its high performance derivatives, polyvinyl acetate, poly vinyl chloride ("PVC"), poly vinyl fluoride, polytetrafluoroethylene ("PTFE"), polyamide and polyimide, as well as copolymers of any of these polymers, and multiple layers of any of these polymers. The adhesive layer 204 may be any appropriate adhesive, including but not limited to acrylic, acetate, styrene -butadiene, silicone, epoxy, ester, urethane and cyanoacrylate, as well as derivatives of any of these polymers.
The underfill material 124 may then be cured (hardened) using heat or radiation to form a microelectronic device package 140. The barrier tape 200 may be optionally removed after curing, as shown in FIG. 8. If the barrier tape 200 is removed, the resulting cured underfill material 124 may have an edge surface 152 that is unsupported (e.g. does not abut any other structure) and is substantially perpendicular to the microelectronic substrate attachment surface 116.
In one embodiment as shown in FIG. 9, the barrier tape 200 may be positioned to substantially surround the microelectronic device 102. In other embodiment as shown in FIG. 10, the barrier tape 200 may extend along one (illustrated) or more microelectronic device edge 120. As illustrated in FIG. 10, the barrier tape 200 may be positioned proximate the microelectronic device edge 120 where the underfill material 124 is dispensed (FIG. 2), which is the most susceptible area for keep-out zone 136
encroachment by the underfill material 124, as will be understood to those skilled in the art.
It is understood that the barrier tape 200 may be used with regard to other microelectronic device packaging processes. For example, as illustrated in FIG. 11, a microelectronic device 302 may be attached by its back surface 308 to an attachment surface 316 of a microelectronic substrate 312 with a layer of adhesive 324, including, but not limited to, epoxies, urethane, polyurethane, and silicone elastomers. A plurality of bond pads 304 may be disposed on a land surface 306 of the microelectronic device 302. The microelectronic device bond pads 304 may be near at least one edge 318 of the microelectronic device 302 (e.g. the microelectronic device edge 318 extends between the microelectronic device land surface 306 and a microelectronic device back surface 308)
and may be electrically connected by bond wires 322 to corresponding bond pads 314 on the microelectronic substrate 312. In order to protect the microelectronic device 302 and the bond wires 322, a flowable material, such as an encapsulant material 332, may be deposited thereon. As illustrate in FIG. 11, the barrier tape 200 may be positioned proximate a keep-out zone (illustrated generally with arrows 334 and previously described) to substantially surround the microelectronic device 302, the bond wires 322, and the microelectronic substrate bond pads 314. The encapsulant material 332 may then be deposited to cover and protect the microelectronic device 302 and the bond wires 322, wherein the barrier tape 200 prevents the encapsulant material 332 from encroaching into the keep-out zone 334. The encapsulant material 332 may include, but is not limited to plastics, resins, epoxies, glob top materials, and the like.
The encapsulant material 332 may then be cured (hardened) to form a
microelectronic device package 340. After curing, the barrier tape 200 may be optionally removed, as shown in FIG. 12. If the barrier tape 200 is removed, the resulting cured encapsulant material 332 may have an edge surface 336 that is unsupported (e.g. does not abut any other structure) and is substantially perpendicular to the microelectronic substrate attachment surface 316.
A process flow using a barrier tape for keep-out zone management is illustrated in the flow diagram of FIG. 13. As defined in block 410, a microelectronic device may be attached to a microelectronic substrate. A barrier tape may be applied on the
microelectronic substrate proximate a keep-out zone defined on the microelectronic substrate, as defined in block 420. As defined in block 430, a flowable material may be applied adjacent the microelectronic device. The flowable material may then be cured, as defined in block 440. If the barrier tape is to remain on microelectronic substrate, the process is ended, as shown. However, if the barrier tape is not to remain on the microelectronic substrate, after curing the flowable material, the barrier tape may be removed, as defined in block 450.
Another process flow using a barrier tape for keep-out zone management is illustrated in the flow diagram of FIG. 14. As defined in block 510, a barrier tape may be applied on the microelectronic substrate proximate a keep-out zone defined on the microelectronic substrate. A microelectronic device may be attached to a microelectronic substrate, as defined in block 520. As defined in block 530, a flowable material may be applied adjacent the microelectronic device. The flowable material may then be cured, as
defined in block 540. If the barrier tape is to remain on microelectronic substrate, the process is ended, as shown. However, if the barrier tape is not to remain on the microelectronic substrate, after curing the flowable material, the barrier tape may be removed, as defined in block 550.
It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in FIGs. 1-14. The subject matter may be applied to other microelectronic device fabrication applications which require the management of flowable material and is not limited to any technology or product, as will be understood to those skilled in the art. Furthermore, the subject matter may also be used in any appropriate application outside of the microelectronic device fabrication field.
Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.
Claims
1. A microelectronic package comprising:
a microelectronic substrate having an attachment surface;
a microelectronic device attached to the microelectronic substrate attachment surface; and
a cured flowable material adjacent the microelectronic device and the
microelectronic substrate attachment surface, wherein the cured flowable material includes an unsupported edge surface which is substantially perpendicular to the microelectronic substrate attachment surface.
2. The microelectronic package of claim 1, the unsupported edge surface is proximate a keep-out zone defined on the microelectronic substrate attachment surface.
3. The microelectronic package of claim 1, wherein the cured flowable material comprises an underfill material.
4. The microelectronic package of claim 1, wherein the cured flowable material comprises an encapsulant material.
5. The microelectronic package of claim 1, wherein the microelectronic device is attached to the microelectronic substrate attachment surface with a plurality of
interconnects extending between at plurality bond pads on a land surface of the microelectronic land surface and a corresponding plurality of bond pads on the
microelectronic substrate attachments surface.
6. The microelectronic package of claim 5, wherein the cured flowable material comprises an underfill material disposed between the microelectronic device land surface and the microelectronic substrate attachments surface to substantial encapsulate the plurality of interconnects, wherein at least a portion of the underfill material extends from between the microelectronic device and the microelectronic substrate, and wherein the unsupported edge surface is on the portion of the underfill material extending from between the microelectronic device and the microelectronic substrate.
7. The microelectronic package of claim 1 , wherein a back surface of the
microelectronic device is attached to the microelectronic substrate attachment surface and wherein a plurality bond pads on a land surface of the microelectronic land surface are connected by a plurality of bond wires to a corresponding plurality of bond pads on the microelectronic substrate attachments surface microelectronic device.
8. The microelectronic package of claim 7, wherein the cured flowable material comprises an encapsulant material disposed on the microelectronic device and the plurality of bond wires.
9. A microelectronic package comprising:
a microelectronic substrate having an attachment surface;
a microelectronic device attached to the microelectronic substrate attachment surface;
a barrier tape attached to the microelectronic substrate attachment surface; and a flowable material adjacent the microelectronic device and the microelectronic substrate attachment surface, wherein at least a portion of the cured flowable abuts the barrier tape.
10. The microelectronic package of claim 9, the barrier tape is proximate a keep-out zone defined on the microelectronic substrate attachment surface.
11. The microelectronic package of claim 9, wherein the flowable material comprises an underfill material.
12. The microelectronic package of claim 9, wherein the cured flowable material comprises an encapsulant material.
13. The microelectronic package of claim 9, wherein the microelectronic device is attached to the microelectronic substrate attachment surface with a plurality of
interconnects extending between at plurality bond pads on a land surface of the microelectronic land surface and a corresponding plurality of bond pads on the
microelectronic substrate attachments surface.
14. The microelectronic package of claim 13, wherein the cured flowable material comprises an underfill material disposed between the microelectronic device land surface and the microelectronic substrate attachments surface to substantial encapsulate the plurality of interconnects, wherein at least a portion of the underfill material extends from between the microelectronic device and the microelectronic substrate, and wherein the unsupported edge surface is on the portion of the underfill material extending from between the microelectronic device and the microelectronic substrate.
15. The microelectronic package of claim 9, wherein a back surface of the
microelectronic device is attached to the microelectronic substrate attachment surface and wherein a plurality bond pads on a land surface of the microelectronic land surface are connected by a plurality of bond wires to a corresponding plurality of bond pads on the microelectronic substrate attachments surface microelectronic device.
16. The microelectronic package of claim 9, wherein the cured flowable material comprises an encapsulant material disposed on the microelectronic device and the plurality of bond wires.
17. A method of fabricating a microelectronic package, comprising:
attaching a microelectronic device to an attachment surface of a microelectronic substrate;
applying a barrier tape on the microelectronic substrate attachment surface proximate a keep-out zone defined on the microelectronic substrate;
dispensing a flowable material adjacent the microelectronic device; and curing the flowable material
18. The method of claim 17, further comprising removing the barrier tape from the microelectronic substrate attachment surface, after curing the flowable material.
19. The method of claim 18, wherein removing the barrier tape forms an unsupported edge surface of the cured flowable material.
20. The method of claim 19, wherein removing the barrier tape to form the
unsupported edge surface of the cured flowable material comprises removing the barrier tape to form the unsupported edge surface of the cured flowable material which is substantially perpendicular to the microelectronic substrate attachment surface.
21. The method of claim 17, whether applying a barrier tape on the microelectronic substrate proximate a keep-out zone defined on the microelectronic substrate occurs prior to attaching a microelectronic device to a microelectronic substrate.
22. The method of claim 17, wherein dispensing a flowable material adjacent the microelectronic device comprises dispensing an underfill material between
microelectronic device and the microelectronic substrate.
23. The method of claim 17, wherein dispensing a flowable material adjacent the microelectronic device comprises dispensing an encapsulant material on the
microelectronic device.
24. The method of claim 17, wherein attaching a microelectronic device to a microelectronic substrate comprises attaching a microelectronic device to a
microelectronic substrate with a plurality of interconnects extending between at plurality bond pads on a land surface of the microelectronic land surface and a corresponding plurality of bond pads on the microelectronic substrate attachments surface.
25. The method of claim 24, wherein dispensing a flowable material adjacent the microelectronic device comprises dispensing an underfill material disposed between the microelectronic device land surface and the microelectronic substrate attachments surface to substantial encapsulate the plurality of interconnects, wherein at least a portion of the underfill material extends from between the microelectronic device and the
microelectronic substrate to abut the barrier tape.
26. The method of claim 17, wherein attaching a microelectronic device to a microelectronic substrate comprises attaching a back surface of the microelectronic device to the microelectronic substrate attachment surface and wherein attaching a plurality bond pads on a land surface of the microelectronic land surface by a plurality of bond wires to a corresponding plurality of bond pads on the microelectronic substrate attachment surface microelectronic device.
27. The method of claim 26, wherein dispensing a flowable material comprises dispensing an encapsulant material on the microelectronic device and the plurality of bond wires, wherein at least a portion of the encapsulant material abuts the barrier tape.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| MYPI2011006292A MY179499A (en) | 2011-12-27 | 2011-12-27 | Barrier tape for keep-out zone management |
| MYPI2011006292 | 2011-12-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2013101668A1 true WO2013101668A1 (en) | 2013-07-04 |
Family
ID=48698554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2012/070990 Ceased WO2013101668A1 (en) | 2011-12-27 | 2012-12-20 | Barrier tape for keep-out zone management |
Country Status (2)
| Country | Link |
|---|---|
| MY (1) | MY179499A (en) |
| WO (1) | WO2013101668A1 (en) |
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|---|---|---|---|---|
| WO2017172227A1 (en) * | 2016-04-01 | 2017-10-05 | Intel Corporation | Electronic device package |
| US20210335628A1 (en) * | 2020-04-28 | 2021-10-28 | Western Digital Technologies, Inc. | Flip-chip package with reduced underfill area |
| US12021060B2 (en) * | 2020-09-22 | 2024-06-25 | Western Digital Technologies, Inc. | Reducing keep-out-zone area for a semiconductor device |
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| US20020060368A1 (en) * | 2000-04-06 | 2002-05-23 | Tongbi Jiang | Underfile process |
| US20020060084A1 (en) * | 2001-12-11 | 2002-05-23 | Hilton Robert M. | Flip-chip package with underfill dam that controls stress at chip edges |
| KR20020063131A (en) * | 2001-01-26 | 2002-08-01 | 소니 가부시끼 가이샤 | Semiconductor device and fabrication method thereof |
| KR20050084487A (en) * | 2002-12-23 | 2005-08-26 | 프리스케일 세미컨덕터, 인크. | Selective underfill for flip chips and flip-chip assemblies |
| KR20080052482A (en) * | 2006-12-07 | 2008-06-11 | 스태츠 칩팩 아이엔씨. | Multilayer Semiconductor Package |
-
2011
- 2011-12-27 MY MYPI2011006292A patent/MY179499A/en unknown
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2012
- 2012-12-20 WO PCT/US2012/070990 patent/WO2013101668A1/en not_active Ceased
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020060368A1 (en) * | 2000-04-06 | 2002-05-23 | Tongbi Jiang | Underfile process |
| KR20020063131A (en) * | 2001-01-26 | 2002-08-01 | 소니 가부시끼 가이샤 | Semiconductor device and fabrication method thereof |
| US20020060084A1 (en) * | 2001-12-11 | 2002-05-23 | Hilton Robert M. | Flip-chip package with underfill dam that controls stress at chip edges |
| KR20050084487A (en) * | 2002-12-23 | 2005-08-26 | 프리스케일 세미컨덕터, 인크. | Selective underfill for flip chips and flip-chip assemblies |
| KR20080052482A (en) * | 2006-12-07 | 2008-06-11 | 스태츠 칩팩 아이엔씨. | Multilayer Semiconductor Package |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017172227A1 (en) * | 2016-04-01 | 2017-10-05 | Intel Corporation | Electronic device package |
| US10249515B2 (en) | 2016-04-01 | 2019-04-02 | Intel Corporation | Electronic device package |
| US20210335628A1 (en) * | 2020-04-28 | 2021-10-28 | Western Digital Technologies, Inc. | Flip-chip package with reduced underfill area |
| US11837476B2 (en) * | 2020-04-28 | 2023-12-05 | Western Digital Technologies, Inc. | Flip-chip package with reduced underfill area |
| US12021060B2 (en) * | 2020-09-22 | 2024-06-25 | Western Digital Technologies, Inc. | Reducing keep-out-zone area for a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| MY179499A (en) | 2020-11-09 |
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