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WO2013190812A1 - Procédé de production d'un dispositif à semiconducteur, dispositif à semiconducteur et système de production pour dispositif à semiconducteur - Google Patents

Procédé de production d'un dispositif à semiconducteur, dispositif à semiconducteur et système de production pour dispositif à semiconducteur Download PDF

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Publication number
WO2013190812A1
WO2013190812A1 PCT/JP2013/003734 JP2013003734W WO2013190812A1 WO 2013190812 A1 WO2013190812 A1 WO 2013190812A1 JP 2013003734 W JP2013003734 W JP 2013003734W WO 2013190812 A1 WO2013190812 A1 WO 2013190812A1
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WO
WIPO (PCT)
Prior art keywords
etching
heating
developing
substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2013/003734
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English (en)
Japanese (ja)
Inventor
実佳 福井
儀紀 小西
慶匡 本多
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
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Tokyo Electron Ltd
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Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of WO2013190812A1 publication Critical patent/WO2013190812A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/38—Treatment before imagewise removal, e.g. prebaking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32458—Vessel
    • H01J37/32522—Temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32733—Means for moving the material to be treated
    • H01J37/32752—Means for moving the material to be treated for moving the material across the discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32917—Plasma diagnostics
    • H01J37/32935—Monitoring and controlling tubes by information coming from the object and/or discharge
    • H10P50/268—
    • H10P72/0602—
    • H10P74/203—
    • H10P74/23—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device manufacturing method, a semiconductor device, and a semiconductor device manufacturing system.
  • a fine electronic circuit is formed on a substrate such as a semiconductor wafer by a photolithography process using a photoresist.
  • a coating and developing apparatus that applies and develops a photoresist, an exposure apparatus that exposes the photoresist, and a plasma etching apparatus that etches a layer to be etched using a photoresist patterned in a predetermined shape as a mask Etc. are used.
  • the exposed photoresist is subjected to heat treatment (post-exposure baking (PEB)) that promotes a chemical reaction in the photoresist before development.
  • PEB post-exposure baking
  • the heating temperature can be adjusted for each of a plurality of heating regions.
  • the in-plane uniformity of the pattern dimension of the formed resist mask can be improved.
  • etching apparatus in which one etching apparatus includes a plurality of etching chambers (etching mechanisms) is used.
  • Many production lines use multiple devices. Therefore, the semiconductor wafer after the development processing is transferred to any one of a plurality of etching chambers during the manufacturing process and subjected to the etching processing.
  • the etching apparatus there is a so-called chamber machine difference in which the etching processing state is slightly different for each etching chamber. Because of such chamber differences, even if the same etching process is performed with the same recipe, the pattern dimension (CD) of the layer to be etched (CD) and its surface are different for each etching chamber (etching mechanism). Internal uniformity is different. Therefore, even if the heating temperature in the post-exposure bake is adjusted, the CD of the pattern of the layer to be etched may not reach a desired value depending on the etching chamber that is subsequently transported and processed, and the surface of the CD There is a problem that the internal uniformity may not be sufficiently improved.
  • the present invention has been made in response to the above-described conventional circumstances, and is a semiconductor device capable of improving the dimensional accuracy of a pattern formed on a substrate and improving the in-plane uniformity as compared with the conventional case. It is an object to provide a manufacturing method, a semiconductor device, and a semiconductor device manufacturing system.
  • the exposed photoresist is developed to form a photoresist mask on the substrate, and the heating temperature can be changed for each of the plurality of heating regions.
  • the exposed photoresist is developed to form a photoresist mask on the substrate, and the heating temperature can be changed for each of the plurality of heating regions.
  • a plurality of etchings for etching a layer to be etched under the mask through the mask formed by the developing mechanism and a heating mechanism for heating the substrate after exposure of the photoresist and before development by the developing mechanism;
  • a semiconductor device manufacturing system comprising: a mechanism; and a transport mechanism that transports the substrate from the developing mechanism to the etching mechanism, wherein a heating process by the heating mechanism, a developing process by the developing mechanism, and the etching are performed in advance.
  • An etching process by a mechanism is performed on the substrate, and the substrate after the etching process by the etching mechanism is performed.
  • Heating condition data for measuring the etching layer pattern dimensions at a plurality of points and obtaining heating condition data relating to the heating conditions by the heating mechanism for minimizing variations in the pattern dimension for each etching mechanism and storing them in the data storage means
  • a process execution etching mechanism for acquiring a transfer schedule information by the transfer mechanism and specifying a process execution etching mechanism for etching the substrate in the etching mechanism when the substrate is heated by the heating mechanism.
  • the present invention it is possible to improve the dimensional accuracy of the pattern formed on the substrate and improve the in-plane uniformity as compared with the prior art.
  • Explanatory drawing which shows the general formula of a related system model.
  • FIG. 1 is a block diagram showing a configuration of a semiconductor device manufacturing system 100 that realizes a semiconductor device manufacturing method according to an embodiment of the present invention.
  • a semiconductor device manufacturing system 100 includes a control unit 101, a data storage unit 102, a coating and developing device 103, a plurality of etching devices 104 (only one is shown in FIG. 1), A transport mechanism 105 and a CD measuring device 106 are provided.
  • a control unit 101 as a host computer controls the coating and developing apparatus 103, the plurality of etching apparatuses 104, and the transport mechanism 105 in an integrated manner, and gives job generation, start commands, and the like thereto.
  • the data storage unit 102 stores data related to the etching process, for example, data related to the CD value of the pattern measured by the CD measuring device 106, and data related to etching such as a recipe for each chamber of each etching apparatus 103. Is done.
  • the coating and developing apparatus 103 applies a photoresist to a semiconductor wafer and performs post-bake processing and development processing on the exposed photoresist.
  • the etching apparatus 104 is a multi-chamber type apparatus having a plurality of etching chambers as will be described later, and a plurality of etching apparatuses are arranged.
  • the transfer mechanism 105 transfers the semiconductor wafer between the coating and developing apparatus 103 and each etching apparatus 104.
  • the CD measuring device 106 measures the CD of the etching pattern at a predetermined measurement point on the etched semiconductor wafer for each etching chamber of each etching apparatus 104.
  • the measurement result is stored in the data storage unit 102 as data for each etching chamber.
  • FIGS. 2 is a plan view
  • FIG. 3 is a front view
  • FIG. 4 is a rear view.
  • the coating and developing apparatus 103 transfers the semiconductor wafer W between the cassette station 111, the processing station 112 having a plurality of processing units, and the exposure apparatus 114 provided adjacent to the processing station 112 and the processing station 112. Interface station 113.
  • a wafer cassette (or hoop) (CR) in which a plurality of semiconductor wafers W to be processed in the coating and developing apparatus 103 are horizontally accommodated is carried from another system.
  • the wafer cassette (CR) containing the semiconductor wafer W that has been processed in the coating and developing apparatus 103 is unloaded from the cassette station 111 to another system.
  • the cassette station 111 carries the semiconductor wafer W between the wafer cassette (CR) and the processing station 112.
  • a cassette mounting table 120 extending along the X direction is provided at the inlet side end (Y direction end in FIG. 2) of the cassette station 111.
  • a plurality of (five in FIG. 2) positioning projections 120a are arranged in a row along the X direction on the cassette mounting table 120, and the wafer cassette (CR) faces the wafer loading / unloading port toward the processing station 112 side.
  • the lever is placed at the position of the protrusion 120a.
  • a wafer transfer mechanism 121 is provided so as to be positioned between the cassette mounting table 120 and the processing station 112.
  • the wafer transfer mechanism 121 includes a wafer transfer pick 121a that can move in the cassette arrangement direction (X direction) and the arrangement direction (Z direction) of the semiconductor wafers W in the wafer cassette (CR).
  • the pick 121a is rotatable in the ⁇ direction shown in FIG. Thereby, the wafer transfer pick 121a can access any wafer cassette (CR), and is provided with a transition unit (TRS-G 3) provided in a third processing unit group G 3 of the processing station 112 described later. ) Can be accessed.
  • TRS-G 3 transition unit
  • the processing station 112 the system front side, in order from the cassette station 111 side, the first processing unit group G 1 and the second processing unit group G 2 is arranged. Further, a third processing unit group G 3 , a fourth processing unit group G 4 and a fifth processing unit group G 5 are arranged on the system rear side in order from the cassette station 111 side.
  • the first main transfer section A 1 is disposed between the third processing unit group G 3 and the fourth processing unit group G 4, and the fourth processing unit group G 4 and the fifth processing unit group G 5 the second main transfer section a 2 is disposed between.
  • the first main rear side of the transport unit A 1 sixth processing unit group G 6 is provided, on the back side of the second main transfer section A 2 is disposed seventh processing unit group G 7 Yes.
  • the first processing unit group G 1, 5 spinner-type processing units as solution supplying unit for performing predetermined processing by placing the semiconductor wafer W on a spin chuck in a cup For example, three coating units (COT) and two coating units (BARC) for forming an antireflection film for preventing reflection of light during exposure are arranged in a total of five stages. Also in the second processing unit group G 2, five spinner-type processing units, for example, five of the developing unit (DEV) are stacked in disposed five stages.
  • COT coating units
  • BARC two coating units
  • DEV developing unit
  • the third processing unit group G 3 includes, from below, a temperature control unit (TCP), a transfer unit for the semiconductor wafer W between the cassette station 111 and the first main transfer unit A 1. Transition unit (TRS-G 3 ), a spare space V in which a desired oven-type processing unit and the like can be provided, and three high-precision temperature control units that heat-treat the semiconductor wafer W under accurate temperature control ( CPL-G 3 ) and four high-temperature heat treatment units (BAKE) for performing predetermined heat treatment on the semiconductor wafer W are arranged in a total of 10 stages.
  • TCP temperature control unit
  • TRS-G 3 transition unit
  • CPL-G 3 three high-precision temperature control units that heat-treat the semiconductor wafer W under accurate temperature control
  • BAKE high-temperature heat treatment units
  • the fourth processing unit group G 4 includes, from below, a high-precision temperature control unit (CPL-G 4 ), four pre-baking units (PAB) that heat-treat the semiconductor wafer W after resist coating, and development processing.
  • CPL-G 4 high-precision temperature control unit
  • PAB pre-baking units
  • POST post bake units
  • the fifth processing unit group G 5 includes four high-precision temperature control units (CPL-G 5 ) and six post-exposure baking units that heat-treat the semiconductor wafer W after exposure and before development, from the bottom. (PEB) are arranged in a total of 10 stages.
  • the post-exposure bake unit (PEB) As shown in FIG. 5, the post-exposure bake unit (PEB) is integrated into the casing 132 in the casing 132, which can be moved up and down, and the processing chamber that is integrated with the lid 130 in the lower side. And a hot plate housing part 131 for forming K.
  • the lid 130 has a substantially cylindrical shape with an open bottom surface.
  • An exhaust part 130 a is provided at the center of the upper surface of the lid 130.
  • the atmosphere in the processing chamber K is uniformly exhausted from the exhaust part 130a.
  • a hot plate 140 as a heat treatment plate is provided at the center of the hot plate housing portion 131.
  • the heat plate 140 is formed in a substantially disk shape, for example.
  • the hot plate 140 is divided into a plurality of, for example, five hot plate regions R 1 , R 2 , R 3 , R 4 , and R 5 . That is, for example, when viewed from the upper side, the hot plate 140 is divided into a circular hot plate region R 1 located in the center and hot plate regions R 2 to R 5 whose periphery is divided into four arcs. ing.
  • a heater 141 that generates heat by power feeding is individually incorporated so that each of the hot plate regions R 1 to R 5 can be heated.
  • the amount of heat generated by the heater 141 in each of the hot plate regions R 1 to R 5 is adjusted by the temperature controller 142.
  • the temperature control device 142 adjusts the amount of heat generated by each heater 141 to control the temperature of each of the hot plate regions R 1 to R 5 to a predetermined set temperature.
  • the temperature setting in the temperature control device 142 is performed by, for example, a temperature setting device 190 described later.
  • lift pins 150 are provided for supporting and lifting the semiconductor wafer W from below.
  • the lift pins 150 are moved up and down by a lift drive mechanism 151.
  • a through-hole 152 that penetrates the hot plate 140 in the thickness direction is formed in the vicinity of the center of the hot plate 140, and the lift pins 150 rise from below the hot plate 140, and the hot plate 140 extends from the through-hole 152. It can protrude upward.
  • the hot plate housing part 131 includes, for example, an annular support member 160 that houses the hot plate 140 and supports the outer periphery of the hot plate 140, and a substantially cylindrical support ring 161 that surrounds the outer periphery of the support member 160. .
  • the post-exposure bake unit (PEB) has a cooling plate (not shown) next to the hot plate 140, for example, and the semiconductor wafer W can be placed on the cooling plate and cooled. Therefore, the post-exposure bake unit (PEB) can perform both heating and cooling.
  • the number of stacked stages and the arrangement of units of the third to fifth processing unit groups G 3 to G 5 are not limited to those shown in the figure, and can be arbitrarily set.
  • the seventh processing unit group G 7 includes, from below, a film thickness measuring device (FTI) that measures the resist film thickness and a peripheral exposure device (WEE) that selectively exposes only the edge portion of the semiconductor wafer W. It is arranged on the steps.
  • FTI film thickness measuring device
  • WEE peripheral exposure device
  • the first main transfer section A 1 is provided first main wafer transfer device 116, the first main wafer transfer device 116, the first processing unit group G 1, the third processing unit group Each unit included in G 3 , the fourth processing unit group G 4 and the sixth processing unit group G 6 can be selectively accessed.
  • the second main transfer section A 2 is provided a second main wafer transfer device 117, the second main wafer transfer device 117, the second processing unit group G 2, the fourth processing unit group G 4, the fifth processing unit
  • Each unit provided in the group G 5 and the seventh processing unit group G 7 can be selectively accessed.
  • the semiconductor wafer W is held on these arms and is transported in each of the X direction, the Y direction, the Z direction, and the ⁇ direction.
  • a liquid temperature control pump 124 and a duct 128 are provided between the first processing unit group G 1 and the cassette station 111, and between the second processing unit group G 2 and the interface station 113.
  • a liquid temperature adjusting pump 125 and a duct 129 are provided. Liquid temperature adjusting pump 124 and 125, and supplies a predetermined processing liquid first processing unit group G 1 respectively to the second processing unit group G 2.
  • the ducts 128 and 129 are for supplying clean air from an air conditioner (not shown) provided outside the coating and developing apparatus 103 to the inside of each of the processing unit groups G 1 to G 5 .
  • the first processing unit group G 1 to the seventh processing unit group G 7 can be removed for maintenance, and the panel on the back side of the processing station 112 can be removed or opened / closed. Further, as shown in FIG. 3, the first processing unit group G 1 of the lower second processing unit group G 2, the first processing unit group G 1 and a predetermined process liquid to the second processing unit group G 2 Supplying chemical units (CHM) 126 and 127 are provided.
  • CHM chemical units
  • Interface station 113 includes a first interface station 113a of the processing station 112 side, and is composed of a second interface station 113b of the exposure apparatus 114 side, the first interface station 113a opening in the fifth processing unit group G 5
  • a first wafer transfer body 162 is disposed so as to face the part, and a second wafer transfer body 163 movable in the X direction is disposed at the second interface station 113b.
  • an out buffer cassette (OUTBR) for temporarily storing the semiconductor wafers W carried out from the exposure apparatus 114 is transferred to the exposure apparatus 114.
  • in buffer cassette for temporarily accommodating the semiconductor wafer W to be (INBR) eighth processing unit group G 8 to the edge exposure unit (WEE) is constituted by stacking is disposed.
  • the in buffer cassette (INBR) and the out buffer cassette (OUTBR) can accommodate a plurality of, for example, 25 semiconductor wafers W.
  • a two-stage high-precision temperature control unit (CPL-G 9 ), a transition unit (TRS-G 9 ), ninth processing unit group G 9 is arranged which is configured by stacking.
  • the first wafer transfer body 162 has a fork 162a for transferring the wafer, which is movable in the Z direction and rotatable in the ⁇ direction, and is movable back and forth in the XY plane. .
  • the fork 162a can selectively access each of the fifth processing unit group G 5 , the eighth processing unit group G 8 , and the ninth processing unit group G 9 .
  • the semiconductor wafer W can be transferred.
  • the second wafer transfer body 163 has a fork 163a for wafer transfer that can move in the X and Z directions, can rotate in the ⁇ direction, and can advance and retreat in the XY plane.
  • the fork 163a includes units of the ninth processing unit group G 9, being selectively accessible against incoming stage 114a and outgoing stage 114b of the exposure apparatus 114, the transfer of the semiconductor wafers W between these portions Can be done.
  • a central control unit 119 for controlling the entire coating and developing apparatus 103 is provided below the cassette station 111.
  • the resist coating and developing process for the semiconductor wafer W are performed as follows.
  • the semiconductor wafer W before processing from the wafer cassette (CR) is taken out by the wafer transfer mechanism 121 one by one, the semiconductor wafer W to the processing station 112 of the processing unit group G 3 in placed transit unit (TRS-G 3 ).
  • the baking process in the high temperature heat treatment unit (BAKE) is performed.
  • an adhesion process may be performed by the adhesion unit (AD).
  • the semiconductor wafer W is transferred to the resist coating unit (COT) belonging to the first processing unit group G 1 , and the resist A liquid coating process is performed.
  • COT resist coating unit
  • the semiconductor wafer W is transferred into the exposure apparatus 114 by the second wafer transfer body 163.
  • the semiconductor wafer W that has been subjected to the exposure process by the exposure apparatus 114 is carried into the transition unit (TRS-G 9 ) by the second wafer transfer body 163. Thereafter, the semiconductor the wafer W, post-exposure baking treatment by post-exposure baking unit (PEB) which belongs to the fifth processing unit group G 5, the developing process by the developing unit (DEV) belonging to the second processing unit group G 2, post-baking post-baking by the unit (pOST), control the temperature treatment by high-precision temperature regulating unit (CPL-G 3).
  • PEB post-exposure baking unit
  • DEV developing process by the developing unit
  • pOST post-baking post-baking by the unit
  • CPL-G 3 control the temperature treatment by high-precision temperature regulating unit
  • the photoresist (mask) is patterned by the above procedure.
  • the etching apparatus 104 is configured by connecting a plurality of (three in the example of FIG. 7) processing modules 300 to one transfer module 310 that transfers a semiconductor wafer in the atmosphere. Yes.
  • Each processing module 300 includes a processing unit 301 that accommodates a substrate in an etching chamber and performs a predetermined plasma etching process. These processing units 301 are transport modules via a load lock chamber 302, respectively. 310 is connected.
  • the transfer module 310 includes a transfer chamber 311 having an air atmosphere inside, and a transfer mechanism (not shown) for transferring the semiconductor wafer W is disposed in the transfer chamber 311.
  • the processing unit 301 includes an etching chamber 2 made of, for example, aluminum whose surface is anodized and formed into a cylindrical shape, and the etching chamber 2 is grounded.
  • a substantially cylindrical susceptor support 4 for mounting the semiconductor wafer W is provided on the bottom of the etching chamber 2 via an insulating plate 3 such as ceramics.
  • a susceptor (mounting table) 5 also serving as a lower electrode is provided on the susceptor support 4.
  • a high pass filter (HPF) 6 is connected to the susceptor 5.
  • a refrigerant chamber 7 is provided inside the susceptor support 4, and the refrigerant is introduced into the refrigerant chamber 7 through a refrigerant introduction pipe 8, circulated, and discharged from a refrigerant discharge pipe 9. Then, the cold heat is transferred to the semiconductor wafer W through the susceptor 5, whereby the semiconductor wafer W is controlled to a desired temperature.
  • the upper center portion of the susceptor 5 is formed into a convex disk shape, and an electrostatic chuck 11 having substantially the same shape as the semiconductor wafer W is provided thereon.
  • the electrostatic chuck 11 is configured by disposing an electrode 12 between insulating materials. Then, when a DC voltage of, for example, 1.5 kV is applied from the DC power source 13 connected to the electrode 12, the semiconductor wafer W is electrostatically attracted by, for example, Coulomb force.
  • the insulating plate 3, the susceptor support 4, the susceptor 5, and the electrostatic chuck 11 are formed with a gas passage 14 for supplying a heat transfer medium (for example, He gas) on the back surface of the semiconductor wafer W.
  • a heat transfer medium for example, He gas
  • An annular focus ring 15 is disposed around the upper peripheral edge of the susceptor 5 so as to surround the semiconductor wafer W placed on the electrostatic chuck 11.
  • the focus ring 15 is made of, for example, a conductive material such as silicon, and has an effect of improving etching uniformity.
  • the upper electrode 21 is provided above the susceptor 5 so as to face the susceptor 5 in parallel.
  • the upper electrode 21 is supported on the upper portion of the etching chamber 2 via an insulating material 22.
  • the upper electrode 21 includes an electrode plate 24 and an electrode support 25 made of a conductive material that supports the electrode plate 24.
  • the electrode plate 24 is made of, for example, a conductor such as Si or SiC, or a semiconductor, and has a large number of discharge holes 23.
  • the electrode plate 24 forms a surface facing the susceptor 5.
  • a gas inlet 26 is provided at the center of the electrode support 25 in the upper electrode 21, and a gas supply pipe 27 is connected to the gas inlet 26. Further, a processing gas supply source 30 is connected to the gas supply pipe 27 via a valve 28 and a mass flow controller 29. An etching gas for plasma etching processing is supplied from the processing gas supply source 30.
  • An exhaust pipe 31 is connected to the bottom of the etching chamber 2, and an exhaust device 35 is connected to the exhaust pipe 31.
  • the exhaust device 35 includes a vacuum pump such as a turbo molecular pump, and is configured to be able to evacuate the etching chamber 2 to a predetermined reduced pressure atmosphere, for example, a predetermined pressure of 1 Pa or less.
  • a gate valve 32 is provided on the side wall of the etching chamber 2. With the gate valve 32 opened, the semiconductor wafer W is connected to an adjacent load lock chamber (load lock chamber 302 shown in FIG. 7). Carry between.
  • a first high-frequency power source 40 is connected to the upper electrode 21, and a matching unit 41 is inserted in the feeder line. Further, a low pass filter (LPF) 42 is connected to the upper electrode 21.
  • the first high frequency power supply 40 has a frequency in the range of 27 to 150 MHz. By applying such a high frequency, it is possible to form a high-density plasma in a preferable dissociated state in the etching chamber 2.
  • a second high frequency power supply 50 is connected to the susceptor 5 as a lower electrode, and a matching unit 51 is inserted in the power supply line.
  • the second high-frequency power supply 50 has a lower frequency range than the first high-frequency power supply 40, and damage to the semiconductor wafer W, which is the substrate to be processed, by applying a frequency in such a range. Appropriate ion action can be given without giving.
  • the frequency of the second high frequency power supply 50 is preferably in the range of 1 to 20 MHz, for example.
  • control unit 60 includes a process controller 61 that includes a CPU and controls each unit of the etching apparatus 104 including the processing unit 301, a user interface unit 62, and a storage unit 63.
  • the user interface unit 62 includes a keyboard for inputting commands to allow the process manager to manage the etching apparatus 104 including the processing unit 301, a display for visualizing and displaying the operation status, and the like.
  • the storage unit 63 stores a recipe in which a control program (software) for realizing various processes executed by the processing unit 301 under the control of the process controller 61, processing condition data, and the like are stored. Then, if desired, an arbitrary recipe is called from the storage unit 63 by an instruction from the user interface unit 62 and is executed by the process controller 61, so that the desired processing in the processing unit 301 is performed under the control of the process controller 61. Is performed.
  • recipes such as control programs and processing condition data may be stored in a computer-readable storage medium (for example, a hard disk, CD, flexible disk, semiconductor memory, etc.) or other recipes. For example, it is possible to transmit the data from time to time via a dedicated line and use it online.
  • the processing unit 301 When plasma etching of the semiconductor wafer W is performed by the processing unit 301 having the above configuration, first, after the gate valve 32 is opened, the semiconductor wafer W is carried into the etching chamber 2 from the load lock chamber 302 shown in FIG. And placed on the electrostatic chuck 11. The semiconductor wafer W is electrostatically attracted onto the electrostatic chuck 11 by applying a DC voltage from the DC power source 13. Next, the gate valve 32 is closed, and the etching chamber 2 is evacuated to a predetermined degree of vacuum by the exhaust device 35.
  • valve 28 is opened, and the flow rate of a predetermined etching gas from the processing gas supply source 30 is adjusted by the mass flow controller 29 while passing through the processing gas supply pipe 27 and the gas inlet 26, so that the upper electrode 21 is hollow. Then, the liquid is uniformly discharged onto the semiconductor wafer W as shown by the arrows in FIG. 8 through the discharge holes 23 of the electrode plate 24.
  • the pressure in the etching chamber 2 is maintained at a predetermined pressure. Thereafter, high frequency power having a predetermined frequency is applied to the upper electrode 21 from the first high frequency power supply 40. As a result, a high-frequency electric field is generated between the upper electrode 21 and the susceptor 5 as the lower electrode, and the etching gas is dissociated into plasma.
  • high frequency power having a frequency lower than that of the first high frequency power supply 40 is applied from the second high frequency power supply 50 to the susceptor 5 serving as the lower electrode.
  • ions in the plasma are drawn to the susceptor 5 side, and the anisotropy of etching is enhanced by ion assist.
  • the plasma etching process is performed on the semiconductor wafer W by the above procedure, and the layer to be etched is patterned into a predetermined pattern via a photoresist mask.
  • the temperature setting device 190 is composed of, for example, a general-purpose computer including a CPU and a memory, and is provided in the cassette station 111 of the coating and developing device 103, for example, as shown in FIG.
  • the temperature setting device 190 includes, for example, a calculation unit 200 that executes various programs, an input unit 201 that inputs various information for temperature setting, and a function for calculating a temperature correction value, as shown in FIG.
  • a data storage unit 202 that stores various types of information such as a relational model F, a program storage unit 203 that stores various programs for temperature setting, and a temperature controller 142 to change the temperature setting of the heat plate 140
  • a communication unit 204 and the like are provided.
  • the data storage unit 202 stores, for example, a relationship model F that is a function of the correction amount of the etching pattern line width and the temperature correction value (temperature offset value) of the heat plate 140.
  • This relational model F is individually set for each etching chamber 2 of each of the etching apparatuses 104 described above, and therefore, x pieces of the relational model F correspond to the number x of the etching chambers 2 provided in the semiconductor device manufacturing system 100.
  • the relationship model F (F 1 to F x ) is set.
  • the relationship model F of each etching chamber 2 is set according to the number y of the recipes.
  • the relationship model F (F 1,1 to F x, y ) (hereinafter simply referred to as F) is set.
  • relational models F represent, for example, a correlation between a dimension of an etched pattern of a predetermined portion in the wafer surface, for example, a target correction amount ⁇ CD of a line width and a temperature correction value ⁇ T of each of the hot plate regions R 1 to R 5.
  • ⁇ CD F ⁇ ⁇ T (1)
  • the relational model F is an n-row ⁇ m-column matrix as shown in FIG. 10 expressed using a predetermined coefficient indicating, for example, in-plane variation in line width that fluctuates around 1 ° C. .
  • the relationship model F is set as follows, for example.
  • the semiconductor wafer is subjected to a photolithography process and an etching process in a state where the temperature setting of one hot plate region of the hot plate 140 is increased by 1 ° C. from the current setting, and the etching pattern in the wafer surface formed as a result is changed.
  • Dimensions, such as line width, are measured by the CD measuring device 106 shown in FIG.
  • the line width measurement is performed for each region of the semiconductor wafer corresponding to each of the hot plate regions R 1 to R 5, and is performed at a plurality of measurement points Q such as a total of 18 points as shown in FIG.
  • the line width fluctuation amount of the etching pattern in the wafer surface when the temperature setting of each hot plate region is raised by 1 ° C. is detected.
  • the line width variation amount in the wafer surface is regarded as a contour surface in the two-dimensional plane of x and y.
  • the curved surface is expressed by a polynomial function, and the coefficient fk of the polynomial function is expressed as follows. Let it be a matrix element of the relational model F.
  • the program storage unit 203 uses, for example, the relationship model F to calculate the temperature correction value ⁇ T for each of the hot plate regions R 1 to R 5 of the hot plate 140 from the line width measurement result of the etching pattern in the wafer surface.
  • the program P1, the setting change program P2 for changing the existing temperature setting of the temperature control device 142 based on the calculated temperature correction value ⁇ T, and the like are stored. Note that the various programs for realizing these temperature setting processes were recorded on a computer-readable recording medium such as a CD and installed in the temperature setting device 190 from the recording medium. May be.
  • the calculation program P1 obtains the necessary line width correction amount ⁇ CD from the line width measurement result.
  • the measurement line width in the wafer plane is expressed by a polynomial function, a coefficient fk of the polynomial function is obtained, and the coefficient fk multiplied by ⁇ 1 so that the coefficient fk becomes zero is used as the line width correction amount ⁇ CD.
  • the calculation program P1 calculates the corrected temperature value ⁇ T of each of the hot plate regions R 1 to R 5 using the relation model F from the line width correction amount ⁇ CD.
  • the corrected temperature value ⁇ T is expressed by the following equation (2) obtained by modifying the relational equation (1).
  • ⁇ T F ⁇ 1 ⁇ ⁇ CD (2) Is calculated from the line width correction amount ⁇ CD.
  • the optimum processing in the post-exposure bake unit is performed by actually performing the heat treatment, development processing, and etching processing of the semiconductor wafer and measuring the CD of the etching pattern. The correct heating conditions.
  • a series of photolithography processes are performed in the coating and developing apparatus 103, and then the semiconductor wafer subjected to the etching process in the etching apparatus 104 is carried into the CD measuring device 106.
  • the CD measuring device 106 measures the CD of the pattern formed on the etched layer of the semiconductor wafer (step S1 in FIG. 12). At this time, for example, as shown in FIG. 13, CDs at a plurality of measurement points Q in the wafer surface are measured. For example, CDs over the entire surface of the wafer W corresponding to the respective hot plate regions R 1 to R 5 of the hot plate 140 are obtained. Desired. This measurement result is stored in the data storage unit 102.
  • Step S2 in FIG. 12 the measurement result of CD in the wafer surface of the etching pattern is read by the temperature setting device 190, and the coefficient fk when the variation in line width in the wafer surface is expressed by a polynomial function is calculated from the measurement result.
  • a line width correction amount ⁇ CD is calculated from the coefficient fk. Then, these line width correction amounts ⁇ CD are substituted into the relational expression (2), and the temperature correction values ⁇ T ( ⁇ T 1 to ⁇ T 5 ) of the respective hot plate regions R 1 to R 5 are calculated using the relational model F. (Step S3 in FIG. 12).
  • temperature correction values ⁇ T 1 to ⁇ T 5 are calculated so that the coefficient fk in the measurement line width becomes zero and the in-plane variation of the line width is eliminated.
  • an optimized post-exposure bake unit that can accurately form an etching pattern that matches the target CD value and has good in-plane uniformity ( The heating conditions in PEB) can be obtained.
  • Such a heating condition data collection step is performed for each etching chamber 2 and for each recipe performed in the etching chamber 2, and the acquired heating condition data is stored in the data storage unit 102 shown in FIG. Be contained.
  • the above process is an example of the heating condition data collection process (S11) in the flowchart shown in FIG.
  • the temperature setting device 190 receives the heat treatment from the control unit 101 shown in FIG. After that, the transfer mechanism 105 is transferred to which etching apparatus 104 and the transfer schedule information about which etching chamber 2 of the transferred etching apparatus 104 is subjected to the etching process is acquired, and the semiconductor wafer is etched.
  • the process execution etching chamber 2 is specified (step S12 in FIG. 14).
  • the temperature setting device 190 reads the recipe executed in the process execution etching chamber from the data storage unit 102 shown in FIG.
  • the optimized heating condition data at is acquired (step S13 in FIG. 14).
  • the temperature of each of the hot plate regions R 1 to R 5 in the post-exposure bake unit (PEB) is set, and the semiconductor wafer is heated (step S14 in FIG. 14).
  • the semiconductor wafer is transferred to a development unit (DEV) and developed (step S15 in FIG. 14).
  • DEV development unit
  • the semiconductor wafer is transferred to the process execution etching chamber 2 described above, and is etched by the process execution etching chamber 2 (step S16 in FIG. 14).
  • the CD of the photoresist mask pattern after the development process is not necessarily uniform. This is because when a photoresist mask having a uniform CD is used, the etching pattern CD may be uneven at the center and the outer periphery of the semiconductor wafer, for example. In order to eliminate such in-plane non-uniformity of the etching process, the CD of the photoresist mask pattern is not uniform but biased.
  • the CD (line width) of the etching pattern tends to be thin at the center of the semiconductor wafer and thick at the periphery.
  • the line width of the photoresist mask is previously made thick at the center and thin at the periphery.
  • the temperature control is performed so that the heating temperature is lower in the central portion and higher in the peripheral portion.
  • the CD of the etching pattern after the etching process The inside uniformity is in a good state.
  • the CD of the etching pattern is measured by the CD measuring device 106.
  • the data of the measured CD is the data storage unit 102 together with the data related to the etching chamber 2 that has performed the etching process and the recipe that has been performed. Is housed in. If the CD measurement result (dimensional accuracy and in-plane uniformity) does not satisfy the required conditions, the temperature correction value is recalculated as described above, and the heating condition data is reset.
  • the temperature control (temperature offset) in the post-exposure bake (PEB) is performed in consideration of the machine difference of the etching chamber 2, so that the dimensional accuracy of the pattern formed on the substrate can be improved as compared with the conventional case. Improvement and improvement of in-plane uniformity can be achieved.
  • the temperature setting device 190 calculates the line width correction amount ⁇ CD from the line width measurement result of the etching pattern.
  • the calculation is performed by another computer, for example, the control unit 101.
  • the calculation result of the line width correction amount ⁇ CD may be input to the temperature setting device 190.
  • the temperature setting device 190 calculates the temperature correction value ⁇ T from the line width correction amount ⁇ CD, and sets the new temperature correction value ⁇ T.
  • the temperature correction value ⁇ T is calculated by using the function of the relational model F.
  • the function is a function of the line width correction amount ⁇ CD of the etching pattern and the temperature correction value ⁇ T of the hot plate 140.
  • Other functions may be used.
  • the temperature-set hot plate 140 is divided into five regions, but the number can be arbitrarily selected. Further, the shape of the divided region of the hot plate 140 can be arbitrarily selected.
  • the present invention can be used in the field of manufacturing semiconductor devices. Therefore, it has industrial applicability.
  • DESCRIPTION OF SYMBOLS 100 Semiconductor device manufacturing system, 101 ... Control part, 102 ... Data accommodating part, 103 ... Coating and developing apparatus, 104 ... Etching apparatus, 105 ... Conveyance mechanism, 106 ... CD measuring device.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

L'invention concerne un procédé de production d'un dispositif à semiconducteur, le procédé employant un mécanisme de développement, un mécanisme de chauffage servant à réaliser un processus de chauffage d'un substrat à la suite d'une exposition mais avant un développement, une pluralité de mécanismes de gravure et un mécanisme de transport, le procédé comportant : une étape lors de laquelle, à la suite d'un processus de gravure, les dimensions de motif d'une couche gravée sont mesurées en des points multiples et des données de paramètres de chauffage destinées à minimiser les écarts de dimensions de motif sont élaborées pour chacun des mécanismes de gravure et stockées dans un moyen de stockage de données ; une étape lors de laquelle, pendant le processus de chauffage d'un substrat par le mécanisme de chauffage, des informations de programmation de transport sont acquises, et un mécanisme de gravure d'exécution de processus destiné à réaliser le processus de gravure sur le substrat en question est désigné parmi les mécanismes de gravure ; une étape lors de laquelle des données de paramètres de chauffage destinées au mécanisme de gravure d'exécution de processus sont acquises à partir du moyen de stockage de données ; et une étape lors de laquelle la température de chauffage dans chacune des zones de chauffage est régulée sur la base des données acquises de paramètres de chauffage.
PCT/JP2013/003734 2012-06-19 2013-06-13 Procédé de production d'un dispositif à semiconducteur, dispositif à semiconducteur et système de production pour dispositif à semiconducteur Ceased WO2013190812A1 (fr)

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JP2012137591A JP2014003164A (ja) 2012-06-19 2012-06-19 半導体装置の製造方法及び半導体装置並びに半導体装置の製造システム

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112114498A (zh) * 2020-09-12 2020-12-22 刘晟麟 一种匀胶显影均温加热装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6706696B2 (ja) * 2017-02-01 2020-06-10 東京エレクトロン株式会社 基板処理方法、コンピュータ記憶媒体及び基板処理システム
JP7114456B2 (ja) * 2018-12-28 2022-08-08 株式会社Ｓｃｒｅｅｎホールディングス 基板処理装置および基板搬送方法
US12438051B2 (en) * 2019-09-27 2025-10-07 Panasonic Intellectual Property Management Co., Ltd. Dicing system and dicing method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310698A (ja) * 2005-05-02 2006-11-09 Dainippon Screen Mfg Co Ltd 基板処理装置
WO2007032372A1 (fr) * 2005-09-15 2007-03-22 Tokyo Electron Limited Appareil, procede, programme de traitement de substrat et support d'enregistrement lisible par ordinateur enregistre avec ce programme
WO2007032370A1 (fr) * 2005-09-15 2007-03-22 Tokyo Electron Limited Appareil, procede, programme de traitement de substrat et support d'enregistrement lisible par ordinateur enregistre avec ce programme
JP2009021443A (ja) * 2007-07-12 2009-01-29 Tokyo Electron Ltd 基板処理装置及び基板処理方法
JP2011003819A (ja) * 2009-06-22 2011-01-06 Tokyo Electron Ltd 基板の処理方法、プログラム、コンピュータ記憶媒体及び基板処理システム

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310698A (ja) * 2005-05-02 2006-11-09 Dainippon Screen Mfg Co Ltd 基板処理装置
WO2007032372A1 (fr) * 2005-09-15 2007-03-22 Tokyo Electron Limited Appareil, procede, programme de traitement de substrat et support d'enregistrement lisible par ordinateur enregistre avec ce programme
WO2007032370A1 (fr) * 2005-09-15 2007-03-22 Tokyo Electron Limited Appareil, procede, programme de traitement de substrat et support d'enregistrement lisible par ordinateur enregistre avec ce programme
JP2009021443A (ja) * 2007-07-12 2009-01-29 Tokyo Electron Ltd 基板処理装置及び基板処理方法
JP2011003819A (ja) * 2009-06-22 2011-01-06 Tokyo Electron Ltd 基板の処理方法、プログラム、コンピュータ記憶媒体及び基板処理システム

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112114498A (zh) * 2020-09-12 2020-12-22 刘晟麟 一种匀胶显影均温加热装置

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