WO2013175618A1 - Information processing device and information processing method - Google Patents

Abstract

An information processing device having: a port that is shared by a plurality of devices; a switch for switching the port connection destination among the plurality of devices; and a control unit for switching the switch on the basis of the communication cycles of the plurality of devices from a device with a short communication cycle to a device with a long communication cycle in synchronization with the long-communication-cycle device.

Description

Information processing apparatus and information processing method

The present invention relates to a communication system.

Vehicles are often configured with an in-vehicle network to perform various controls within the vehicle. The in-vehicle network is realized by connecting many electronic control units (ECU: “Electronic Control Unit”), sensors, actuators, and the like to the LAN. Electronic control units, sensors, actuators, and the like connected to the in-vehicle network are sometimes called communication nodes or devices. Communication nodes are arranged at various positions in the vehicle. Communication nodes are connected by communication lines or electric wires.

For example, an in-vehicle network is configured by connecting a plurality of communication nodes to a data bus. The in-vehicle network includes CAN (Controller Area Network) and LIN (Local Interconnect Network). The vehicle-mounted network may include a device that performs communication according to FlexRay (registered trademark).

Tasks processed by multiple communication nodes are controlled by executing time synchronization. For example, in powertrain control executed by an engine control electronic control unit, an HV control electronic control unit, or the like, the tasks of both electronic control units are controlled by executing time synchronization.

It is known that a device that communicates with a different bus protocol is connected to a shared IO pin and the communication bus protocol is switched via the shared IO pin in a time-sharing manner (see, for example, Patent Document 1).

JP 2007-108858 A

It is being studied to reduce the number of communication nodes by integrating functions executed by multiple communication nodes. For example, a function executed by two communication nodes can be executed by one communication node. By doing so, one communication node can be reduced.

When integrating the functions executed by multiple communication nodes, it is desirable to have a configuration that can divert existing systems.

However, if an existing system can be used, the function may be redundant. Moreover, there is a possibility that the number of ports increases and the chip area of the microcomputer increases.

In order to reduce the number of ports, a method of connecting a plurality of communication nodes to one port and switching the communication nodes connected to the ports by switching is conceivable. However, since switching is performed according to the task of the communication node, the number of times of switching may increase. When the number of times of switching increases, power consumption increases. Due to the increase in power consumption, for example, in powertrain control executed by an engine control electronic control unit, an HV control electronic control unit, or the like, there is a possibility that the fuel consumption is reduced or the time until the battery is raised may be shortened. is there.

The present invention has been made in view of the above points, and an object thereof is to reduce power consumption when integrating functions executed by a plurality of communication nodes and reducing the number of communication nodes.

An information processing apparatus according to an embodiment of the disclosure
Ports shared between multiple devices,
A switch for switching the connection destination of the port between the plurality of devices;
And a control unit that switches the switch from a device having a short communication cycle to a device having a long communication cycle at a timing synchronized with a device having a long communication cycle based on the communication cycle of the plurality of devices.

An information processing method in an information processing apparatus according to an embodiment of the disclosure is
Information indicating a communication cycle is obtained from a plurality of devices, and the plurality of devices are transmitted from a device having a short communication cycle to a device having a long communication cycle at a timing synchronized with the device having a long communication cycle based on the information indicating the communication cycle Change the switch that switches the connection destination of the port shared between the devices.

According to the disclosed embodiment, it is possible to reduce power consumption when integrating functions executed by a plurality of communication nodes and reducing the number of communication nodes.

It is a figure which shows one Example of a communication system. It is a figure which shows one Example of a communication node. It is a functional block diagram which shows one Example of a communication node. It is a figure which shows one Example of data output timing information. It is a figure which shows one Example of a data output timing. It is a figure which shows one Example of a microcomputer. It is a functional block diagram which shows one Example of a microcomputer. It is a figure which shows one Example of data output timing information. It is a figure which shows one Example of a receiver. It is a functional block diagram which shows one Example of a receiver. It is a flowchart which shows one Example of operation | movement of a communication system. It is a figure which shows one modification of data output timing. It is a figure which shows the modification of data output timing information.

Next, the form for implementing this invention is demonstrated, referring drawings based on the following Examples.
In all the drawings for explaining the embodiments, the same reference numerals are used for those having the same function, and repeated explanation is omitted.

<Example>
<Communication system>
FIG. 1 shows an embodiment of a communication system.

The communication system includes a communication node 100 _n (n is an integer of n> 0), a microcomputer 200, and a receiving device 300. FIG. 1 shows an example where n = 2. n may be 3 or more. The communication system is mounted on a moving body such as a vehicle, for example.

The communication node 100 _n may be realized by an electronic control unit or the like. The electronic control unit may execute system control. The communication node 100 _n may be realized by a sensor or the like. The communication node 100 _n may be referred to as a device.

The communication node 100 _n may input / output digital signals or input / output analog signals. For example, when the communication node 100 _n is realized by an electronic control unit or the like, a digital signal may be used for input / output with the display device. Display devices include liquid crystal displays (LCD), cathode ray tube (CRT) displays, and plasma displays (PDP).
Plasma display panel), organic EL (Electro-Luminescence) display, etc. are included. Further, for example, when the communication node 100 _n is configured by a sensor, an analog signal may be output. The sensor may include a sensor that detects acceleration, a sensor that detects temperature, a sensor that detects humidity, and the like.

In one embodiment of the communication system, the communication node 100 ₁ includes the hybrid electronic control unit, the communication node 100 ₂ will be described that includes an engine electronic control unit. The communication nodes 100 ₁ and 100 ₂ may include electronic control units having other functions.

Furthermore, in one embodiment of a communications system, the function of the communication node 100 _1, and the communication node 100 ₂ functions are integrated. For example, the functions performed by the communication node 100 _1, functions performed by the communication node 100 ₂ and may also be executed by a single communication node. In this case, in order to configure that can use the existing systems, and an output terminal corresponding to the communication node 100 _1, and an output terminal corresponding to the communication node 100 ₂ is prepared. The communication node 100 _1, and the communication node 100 ₂ is exclusively controlled. 1 shows a communication node 100 _1, although the communication node 100 ₂ is depicted separately, it may be one of the communication nodes. In this embodiment, for convenience of explanation, the communication node 100 _1, it will be described separately and the communication node 100 _2.

The communication node 100 ₁ is connected to the system bus 150. The communication node 100 ₁ controls the engine output, the distribution between the motor output. For example, the communication node 100 _1, the load or the vehicle, in accordance with the running state or the like, and controls the engine output, the distribution between the motor output. In this case, information indicating the load of the vehicle, information indicating the traveling state is input from the system bus 150, to the communication node 100 _1. Furthermore, the communication node 100 _1, when the deceleration of the vehicle, to perform the control for storing travel energy as electricity. In this case, information indicating the speed of the vehicle is inputted from the system bus 150, to the communication node 100 _1.

The communication node 100 ₂ is connected to the system bus 150. The communication node 100 _2, fuel injection amount, ignition timing, and controls the throttle opening or the like. The communication node 100 ₂ can be included EFI (Electronic Fuel Injection) electronic control unit. For example, the communication node 100 _2, based on information from various sensors indicating the condition of the engine and vehicle controls. By doing in this way, engine output, fuel consumption, and exhaust gas cleanliness can be improved.

The microcomputer 200 is connected to the communication node 100 ₁ and 100 _2. The microcomputer 200 outputs data from the communication nodes 100 ₁ and 100 ₂ to the receiving device 300. When outputting data from the communication nodes 100 ₁ and 100 ₂ , the microcomputer 200 executes control to switch switches so that one of the plurality of latch circuits is connected to the output port.

The receiving device 300 is connected to the microcomputer 200. The receiving device 300 receives an output signal from the microcomputer 200. The receiving apparatus 300 may be realized by, for example, ASIC (Application Specific Integrated Circuit) or the like.

<Communication node 100 _n >
Figure 2 shows an embodiment of the communication node 100 _n. FIG. 2 mainly shows a hardware configuration.

The communication node 100 _n includes an MPU (Micro-Processing Unit) 102, a communication module 104, and a storage unit 106. The MPU 102, the communication module 104, and the storage unit 106 are connected to the bus 160.

MPU102 communicates node 100 _n overall control.

The communication module 104 communicates with the microcomputer 200. For example, the communication module 104 performs communication according to a predetermined communication protocol. The communication module 104 may perform transmission / reception of digital signals or may perform transmission / reception of analog signals. For example, when transmitting the digital signal, the communication module 104 transmits a tag, transmits the tag, and then transmits the digital signal. By transmitting the tag, the receiving side can be notified of the start of data. For example, the communication module 104 changes the voltage when transmitting an analog signal. The receiving side samples the voltage, and determines the presence or absence of a change in the sampled voltage based on a preset threshold. In addition, the communication module 104 outputs data to the system bus 150 and receives data from the system bus 150. Further, the communication module 104 inputs a clock signal (hereinafter referred to as “base clock signal”) serving as a reference used for controlling the communication node 100 _n to the microcomputer 200.

The storage unit 106 stores a program for causing the MPU 102 to function as the communication node 100 _n .

<Function of the communication node 100 _n>
FIG. 3 shows an example of the function of the communication node 100 _n . FIG. 3 mainly shows functions executed by the MPU 102. That is, the function shown in FIG. 3 is executed by the MPU 102 functioning in accordance with the software (program) stored in the storage unit 106. Further, the functions shown in FIG. 3 may be executed by the MPU 102 functioning in accordance with software (firmware) stored in the MPU 102.

The MPU 102 functions as a timing control unit 1022 and a data output control unit 1024.

The timing control unit 1022 controls the data output timing. Specifically, the timing control unit 1022 controls the output timing of data from the communication module 104 of the communication node 100 _n to the latch circuit of the microcomputer 200. The output timing may be scheduled in advance. The communication module 104 of the communication node 100 _n and the latch circuit of the microcomputer 200 are connected by wire.

When the information indicating the data output timing (hereinafter referred to as “data output timing information”) is requested from the microcomputer 200, the timing control unit 1022 inputs the information indicating the output timing to the communication module 104. The communication module 104 transmits data output timing information from the timing control unit 1022 to the microcomputer 200.

FIG. 4 shows an example of data output timing information.

The data output timing information includes a latch circuit identifier and data output timing.

Latch circuit identifier is an identifier of a latch circuit connected to the communication node 100 _n.

The data output timing indicates a timing at which data is output from the communication node 100 _{n with} respect to a base axis clock signal that is a reference used when the communication nodes 100 ₁ and 100 ₂ are controlled. The timing of outputting data from the communication node 100 _n may be referred to as a communication cycle. The communication nodes 100 ₁ and 100 ₂ are controlled in synchronization with the base axis clock signal. Specifically, the data output timing may be represented by a frequency division number for the base clock signal. In one embodiment of the communication system, a case will be described in which the data output timing is represented by the frequency division number for the base clock signal. The data output timing may be represented by other information. For example, the data output timing may be represented by scheduling information of the communication node 100 _n .

FIG. 5 shows an example of data output timing.

FIG. 5 shows a base clock signal, a clock signal represented by a waveform obtained by dividing the base clock signal by 3, and a clock signal represented by a waveform obtained by dividing the base clock signal by two. When the timing at which data is output from the communication node 100 _n corresponds to the clock signal represented by the waveform divided by 3, “3” is included as the data output timing. When the timing at which data is output from the communication node 100 _n corresponds to the clock signal represented by the waveform divided by 2, “2” is included as the data output timing information. “2” and “3” are examples, and are appropriately set according to the timing of outputting data from the communication node 100 _n .

The data output control unit 1024 controls the timing for outputting data from the communication module 104 in accordance with the timing controlled by the timing control unit 1022.

<Microcomputer 200>
FIG. 6 shows an embodiment of the microcomputer 200. The microcomputer 200 functions as an information processing device. FIG. 6 mainly shows a hardware configuration.

The microcomputer 200 includes a MPU 202, (is m, m> 0 integer) latch circuit ₂₀₄ m and, a switch 206, and IF208, the cornerstone timer 210, a switch timing port 212, a base shaft timer port 214, port 216 and And a storage unit 218. The MPU 202, the switch 206, the base axis timer 210, the switch timing port 212, the base axis timer port 214, the port 216, and the storage unit 218 are connected by a bus 250.

The MPU 202 controls the entire microcomputer 200.

The latch circuit 204 _m is connected to the communication node 100 _n . FIG. 6 shows a case where m = 2 as an example. m> 2 may be sufficient. The value of m is set according to the number of communication nodes to be integrated. The latch circuit 204 _m temporarily holds data from the communication node 100 _n .

The switch 206 switches the latch circuit connected to the bus 250 between the latch circuits 204 ₁ and 204 _{2 in} accordance with control by the MPU 202.

If is switched to the latch circuit 204 ₁ side by the switch 206, the data held in the latch circuit 204 ₁ is input to the port 216 through the bus 250. If is switched to the latch circuit 204 ₂ side by the switch 206, the data held in the latch circuit 204 ₂ is supplied to the port 216 through the bus 250. That is, by switching the latch circuit connected to the bus 250 by the switch 206, it is possible to share a port to which output data from a plurality of latch circuits is input.

By having the latch circuit 204 _m , for example, even when the communication nodes 100 ₁ and 100 ₂ output data at substantially the same timing, the data is held in the latch circuit 204 _m . The microcomputer 200, it is possible to shift the timing to switch between the latch circuit 204 ₁ and the latch circuit 204 ₂ by the switch 206 in time, it is possible to acquire the data from the communication node ₁₀₀ 1, 100 ₂ both.

The IF 208 is an interface between the communication nodes 100 ₁ and 100 ₂ . Data output timing information from the communication nodes 100 ₁ and 100 ₂ is input to the IF 208. The data output timing information input to the IF 208 is input to the base axis timer 210. The data output timing information input to the IF 208 is input to the MPU 202 via the bus 250. Further, in the IF208, from the communication node 100 ₁ and 100 _2, the base shaft clock signal. The base axis clock signal input to the IF 208 is input to the base axis timer 210.

The base axis timer 210 performs processing synchronized with the base axis clock signal from the IF 208. For example, the base axis timer 210 may divide the base axis clock signal to generate a reference clock. The base axis timer 210 inputs a base axis clock signal to the MPU 202 and the base axis timer port 214.

The switch timing port 212 notifies the receiving apparatus 300 of the timing (hereinafter referred to as “switching timing”) for switching the switch 206 between the latch circuits 204 ₁ and 204 ₂ , which is notified from the MPU 202.

The base axis timer port 214 inputs the base axis clock signal from the base axis timer 210 to the receiving device 300.

Port 216 outputs a signal from the latch circuit 204 ₁ or latch circuit 204 _2.

The storage unit 218 stores a program that causes the MPU 202 to function as the microcomputer 200.

<Function of microcomputer 200>
FIG. 7 shows an embodiment of the function of the microcomputer 200. FIG. 7 mainly shows functions executed by the MPU 202. That is, when the MPU 202 functions according to software (program) stored in the storage unit 218, the function shown in FIG. 7 is executed. Further, the functions shown in FIG. 7 may be executed when the MPU 202 functions according to software (firmware) stored in the MPU 202.

The MPU 202 functions as a switch timing arbitration unit 2022 and a switch control unit 2024.

The switch timing arbitration unit 2022 acquires data output timing information from the communication nodes 100 ₁ and 100 ₂ . The switch timing arbitration unit 2022 may acquire data output timing information at a predetermined cycle, or may acquire data output timing information irregularly. A base axis clock signal is input from the base axis timer 210 to the switch timing arbitration unit 2022. The switch timing arbitration unit 2022 arbitrates the timing for switching the switch 206 to the latch circuit 204 ₁ or 204 ₂ based on the base clock signal and the data output timing information.

Specifically, the switch timing arbitration unit 2022 determines whether the frequency output frequency division numbers included in the data output timing information from the communication nodes 100 ₁ and 100 ₂ have the same value. When it is determined that the frequency division number of the data output timing is the same value, the switch timing arbitration unit 2022 switches the switch 206 so that different latch circuits are connected to the bus 250 at the rising edge and the falling edge of the clock signal. Mediate.

When it is determined that the frequency division number of the data output timing is different, the switch timing arbitration unit 2022 performs arbitration so as to switch the switch 206 so as to be connected to the latch circuit connected to the communication node having a small frequency division number. The switch timing arbitration unit 2022 performs arbitration so as to switch the switch 206 so as to connect to a latch circuit connected to a communication node having a large frequency division number at the timing of the communication node having a large frequency division number.

After arbitrating to connect to a latch circuit connected to a communication node having a large frequency division number, the switch timing arbitration unit 2022 is connected to a latch circuit connected to a communication node having a small frequency division number. Then, arbitrate to switch.

FIG. 8 shows an example of processing performed by the switch timing arbitration unit 2022.

For example, data output timing information is input to the switch timing arbitration unit 2022 from the communication node 100 _n . The data output timing information from the communication node 100 _1, includes a "latch circuit 204 _1" as the latch circuit identifier includes "3" as the data output timing. Further, the data output timing information from the communication node 100 _2, include "latch circuit 204 _2" as the latch circuit identifier includes "2" as the data output timing.

In this case, the switch timing arbitration unit 2022, so as to be connected to the latch circuit 204 ₂ connected small communication node 100 ₂ of the frequency dividing number, arbitrates to switch the switch 206. Switching timing arbitration unit 2022, minutes at a circumferential speed of greater communication node 100 ₁ timing, so as to be connected to the latch circuit 204 ₁ connected to the larger communication node 100 ₁ in the frequency division number, the arbitration to switch the switch 206 To do.

After switching the switch 206 to connect frequency division number larger communication nodes connected to 100 ₁ and the latch circuit 204 _1, the switch timing arbitration unit 2022, connected small communication node 100 ₂ of the frequency dividing number latch so as to be connected to the circuit ₂₀₄₂ arbitrates to switch the switch 206. That is, the switch timing arbitration unit 2022, minutes at a circumferential speed of greater communication node 100 ₁ synchronized timing, and switches the switch 206 so as to be connected to the latch circuit 204 ₁ connected to the larger communication node 100 ₁ in the frequency division number To mediate. Thus, primarily, by switching the switch 206 to connect the dividing number of small connected to the communication node 100 ₂ a latch circuit 204 _2, it can reduce the number changeover switch 206. Since the number of times of switching of the switch 206 can be reduced, the power consumed during switching can be reduced.

The switch timing arbitration unit 2022 notifies the switch control unit 2024 and the switch timing port 212 of the switching timing.

The switch control unit 2024 is connected to the switch timing arbitration unit 2022. The switching timing from the switch timing arbitration unit 2022 is input to the switch control unit 2024. The switch control unit 2024 controls the switch 206 based on the switching timing.

The switch timing port 212 outputs the switch switching timing from the switch timing arbitration unit 2022.

<Receiving device 300>
FIG. 9 shows an embodiment of the receiving device 300. FIG. 9 mainly shows the hardware configuration.

The receiving apparatus 300 includes an MPU 302, a latch circuit 304 _k (k is an integer of k> 0), a switch 306, a switch timing port 312, a base timer port 314, a port 316, and a storage unit 318. . The MPU 302, the switch 306, the switch timing port 312, the base timer port 314, the port 316, and the storage unit 318 are connected by a bus 350.

The MPU 302 controls the entire receiving device 300.

The latch circuit 304 _k temporarily holds data from the microcomputer 200. FIG. 9 shows a case where k = 2 as an example. k> 2 may be sufficient.

The switch 306 switches a latch circuit connected to the bus 350 between the latch circuits 304 ₁ and 304 _{2 in} accordance with control by the MPU 302. If is switched to the latch circuit 304 ₁ side by the switch 306, data from port 316 is input to the latch circuit 304 _1. If is switched to the latch circuit 304 ₂ side by the switch 306, data from port 316 is input to the latch circuit 304 _2. That is, by switching the latch circuit connected to the bus 350 by the switch 306, a port for inputting data to a plurality of latch circuits can be shared.

Switch timing is input from the microcomputer 200 to the switch timing port 312. The switch timing port 312 inputs the switching timing to the MPU 302.

The base axis timer port 314 receives a base axis clock signal from the microcomputer 200. The base axis timer port 314 inputs a base axis clock signal to the MPU 302.

A signal from the microcomputer 200 is input to the port 316.

The storage unit 318 stores a program that causes the MPU 302 to function as the receiving device 300.

<Function of Receiving Device 300>
FIG. 10 shows an embodiment of the function of the receiving device 300. FIG. 10 mainly shows functions executed by the MPU 302. That is, when the MPU 302 functions according to software (program) stored in the storage unit 318, the function shown in FIG. 10 is executed. Further, the functions shown in FIG. 10 may be executed when the MPU 302 functions according to software (firmware) stored in the MPU 302.

The MPU 302 functions as the switch control unit 3024.

The switch control unit 3024 receives the switching timing from the switch timing port 312 and receives the base clock signal from the base timer port 314. The switch control unit 3024 controls the switch 306 based on the switching timing and the base clock signal.

Specifically, the switch control unit 3024 executes control synchronized with the base clock signal. After synchronizing the cornerstone clock signal, the switch control unit 3024 in accordance with the switching timing, is connected to port 316, a latch circuit 304 ₂ the data from the frequency division number of small communication node 100 ₂ in the data output timing is input As described above, control for switching the switch 306 is executed.

The switch control section 3024, a large communication node 100 ₁ in the timing of the frequency division number of the data output timing, and port 316, so as to connect the latch circuits 304 _1, control for switching the switch 306. That is, the switch control unit 3024, at the timing when the data held in the latch circuit 204 ₁ is input to the port 316, so as to be connected to the latch circuit 304 _1, control for switching the switch 306.

After executing the control for switching the switch 306 so as to be connected to the latch circuit 304 _1, the switch control section 3024, so as to be connected to the latch circuit 304 _2, control for switching the switch 306. That is, the switch control unit 3024 in accordance with the switching timing, frequency at a circumferential speed of greater communication node 100 ₁ synchronized timing, a latch circuit 204 ₁ connected to the larger communication node 100 ₁ in the frequency division number, the latch circuit 304 ₁ So that the switch 306 is switched so as to be connected to each other.

<Operation of communication system>
FIG. 11 is a flowchart showing an embodiment of the operation of the communication system. FIG. 11 mainly shows the operation of the microcomputer 200.

In step S1102, the switch timing arbitration unit 2022, from the communication node 100 _n, obtains the data output timing information.

In step S1104, the switch timing arbitration unit 2022 arranges the data output timing information. Specifically, the switch timing arbitration unit 2022 arranges the data output timing information as shown in FIG.

In step S1106, the switch timing arbitration unit 2022 notifies the switch timing port 212 of the switching timing.

In step S <b> 1108, the switch timing arbitration unit 2022 acquires a base axis clock signal from the base axis timer 210.

In step S1110, the switch timing arbitration unit 2022 acquires data output timing information of the latch circuit to be arbitrated.

In step S1112, the switch timing arbitration unit 2022 determines whether or not the data output timings included in the data output timing information are the same.

In step S1114, if the data output timing in the data output timing information are the same, the switch control section 2024, the rising of the data output timing switch to the latch circuit 204 _1, the control for switching on the falling to the latch circuit 204 ₂ Execute. The switch control unit 2024, on the contrary, at the rising edge of the data output timing switch to the latch circuit 204 _2, may be executed a control for switching the falling to the latch circuit 204 _1.

In step S1116, if the data output timing in the data output timing information are different, the switch control section 2024 determines whether or not a great timing of the communication node 100 ₁ in the frequency division number.

In step S1118, if it is larger timing of the communication node 100 ₁ of the dividing number, the switch controller 2024 switches to the latch circuit 204 ₁ connected to the larger communication node 100 ₁ in the frequency division number.

In step S1120, if a small timing of the communication node 100 ₂ of division number, the switch controller 2024 switches to the latch circuit 204 ₂ connected small communication node 100 ₂ of the frequency dividing number.

According to the present embodiment, a plurality of communication nodes are connected to one switch. Based on the communication cycle of each communication node, the communication node connected to the switch 206 is switched. Specifically, at a timing synchronized with a long communication node 100 ₁ of communication cycle, a short from the communication node 100 ₂ of the communication cycle is switched to the long communication node 100 ₁ of communication cycle. By doing so, the number of times the switch 206 is switched can be reduced, so that power consumption can be reduced.

When three or more communication nodes are connected to one switch, the three or more synchronization timings are set in advance so as not to overlap. By doing in this way, the communication node connected to the switch 206 is switched based on the communication period of each of the three or more communication nodes. Specifically, at a timing synchronized with a long communication node 100 ₁ of communication cycle, a short from the communication node 100 ₂ of the communication cycle is switched to the long communication node 100 ₁ of communication cycle. By doing so, the number of times the switch 206 is switched can be reduced, so that power consumption can be reduced.

<Modification>
FIG. 12 shows an embodiment of data output timing.

FIG. 12 shows a base clock signal, a clock signal represented by a waveform obtained by dividing the base clock signal by 3, and a waveform indicating a no-signal state from a clock signal represented by a waveform obtained by dividing the base clock signal by two. It is shown that the clock signal is changed.

When the timing at which data is output from the communication node 100 _n corresponds to the clock signal represented by the waveform divided by 3, “3” is included as the data output timing of the data output timing information.

When the timing for outputting data from the communication node 100 _n corresponds to the clock signal represented by the waveform divided by 2, “2” is included as the data output timing of the data output timing information. “2” and “3” are examples, and are appropriately set according to the timing of outputting data from the communication node 100 _n .

When the timing for outputting data from the communication node 100 _n corresponds to the clock signal represented by the waveform indicating the no-signal state, “∞ (infinity)” is included as the data output timing of the data output timing information. The case where the clock signal is represented by the waveform indicating the no-signal state includes, for example, the case where the communication node 100 _n is in the sleep state.

FIG. 13 shows an example of processing by the switch timing arbitration unit 2022. 13, the data output timing information communication node 100 ₂ is acquired after the transition to the sleep condition is indicated.

For example, data output timing information is input to the switch timing arbitration unit 2022 from the communication node 100 _n . The data output timing information from the communication node 100 _1, includes a "latch circuit 204 _1" as the latch circuit identifier includes "3" as the data output timing. Further, the data output timing information from the communication node 100 _2, include "latch circuit 204 _2" as the latch circuit identifier includes "∞" as the data output timing.

In this case, the switch timing arbitration unit 2022, so as to be connected to the latch circuit 204 ₁ connected to a small communication node 100 ₁ of the frequency division number, arbitrates to switch the switch 206. Switching timing arbitration unit 2022, minutes at a peripheral speed of the larger of the communication node 100 _second timing, so as to be connected to the latch circuit connected to a large communication node dividing number, arbitrates to switch the switch. However, the communication node 100 ₂ is for a sleep state, is not performed by switching the switch 206 to connect with the frequency division number larger communication node 100 ₂ connected to the latch circuit. The communication node 100 ₂ in the sleep state in order to not be synchronized.

According to the modification of the communication system, the data output timing information is acquired at a predetermined cycle, so that the switch can be switched following the state even when the communication node is in the sleep state. For this reason, power consumption can be reduced.

Although the present invention has been described above with reference to specific embodiments and modifications, each embodiment and modification is merely illustrative, and those skilled in the art will recognize various modifications, modifications, alternatives, and substitutions. You will understand examples. For convenience of explanation, an apparatus according to an embodiment of the present invention has been described using a functional block diagram, but such an apparatus may be implemented in hardware, software, or a combination thereof. The present invention is not limited to the above-described embodiments, and various variations, modifications, alternatives, substitutions, and the like are included without departing from the spirit of the present invention.

100 _n (n is an integer of n> 0) Communication node 102 MPU
104 Communication Module 106 Storage Unit 160 Bus 200 Microcomputer 202 MPU
204 _m (m is an integer of m> 0) Latch circuit 206 Switch 208 IF
210 Base axis timer 212 Switch timing port 214 Base axis timer port 216 Port 218 Storage unit 300 Receiver 302 MPU
304 _k (k is an integer of k> 0) Latch circuit 306 Switch 312 Switch timing port 314 Base axis timer port 316 Port 318 Storage unit 1022 Timing control unit 1024 Data output control unit 2022 Switch timing arbitration unit 2024 Switch control unit 3024 Switch control Part

Claims (6)

Ports shared between multiple devices,
A switch for switching the connection destination of the port between the plurality of devices;
An information processing apparatus comprising: a control unit configured to switch the switch from a device having a short communication cycle to a device having a long communication cycle at a timing synchronized with a device having a long communication cycle based on a communication cycle of the plurality of devices. The data output from the port is input to a receiving device connected to the information processing device, and the receiving device receives data from the port in synchronization with the information processing device. The information processing apparatus described. The control unit switches the switch from a device having a small frequency division number for a reference clock signal to a device having a large frequency division number for a reference clock signal at a timing synchronized with a device having a long communication cycle. Item 4. The information processing apparatus according to Item 1. The information processing apparatus according to claim 1, wherein the control unit switches the switch at a rising edge and a falling edge of a clock signal between devices having the same communication cycle. A plurality of latch circuits for holding data from the plurality of devices;
The information processing apparatus according to claim 1, wherein the switch switches a connection destination of the port between a plurality of latch circuits that hold data from the plurality of devices. Information indicating a communication cycle is obtained from a plurality of devices, and the plurality of devices are transmitted from a device having a short communication cycle to a device having a long communication cycle at a timing synchronized with the device having a long communication cycle based on the information indicating the communication cycle. Processing method for switching a switch for switching a connection destination of a port shared between devices.

Images