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WO2013037100A1 - Synthétiseur radiofréquence et émetteur/récepteur - Google Patents

Synthétiseur radiofréquence et émetteur/récepteur Download PDF

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Publication number
WO2013037100A1
WO2013037100A1 PCT/CN2011/079572 CN2011079572W WO2013037100A1 WO 2013037100 A1 WO2013037100 A1 WO 2013037100A1 CN 2011079572 W CN2011079572 W CN 2011079572W WO 2013037100 A1 WO2013037100 A1 WO 2013037100A1
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WO
WIPO (PCT)
Prior art keywords
frequency
signal
mhz
mixer
transceiver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2011/079572
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English (en)
Chinese (zh)
Inventor
魏学旺
傅博
覃志华
李克季
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hytera Communications Corp Ltd
Original Assignee
Hytera Communications Corp Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hytera Communications Corp Ltd filed Critical Hytera Communications Corp Ltd
Priority to PCT/CN2011/079572 priority Critical patent/WO2013037100A1/fr
Publication of WO2013037100A1 publication Critical patent/WO2013037100A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a radio frequency synthesizer and a transceiver. Background technique
  • the carrier signal in the transceiver is usually generated by a radio frequency synthesizer in the transceiver.
  • 1 and 2 respectively show a structural diagram of a prior art radio frequency synthesizer.
  • the phase-locked loop outputs a current pulse to the low-pass filter LPF1, and the LPF1 filters out the high-frequency signal in the current pulse, and outputs different control at different times.
  • the voltage is applied to the voltage controlled oscillator VC01 and the voltage controlled oscillator VC03, and the voltage controlled oscillator VC03 generates a signal with a frequency of 380-430 MHz under the control of the control voltage, and the buffer debounces the signal outputted by the VC03 to obtain a debounce processing.
  • VC01 After the signal of 380-430MHZ is used as the transmitting local oscillator, VC01 generates the signal with the frequency of 453.35-503.35MHZ under the control of the control voltage, and part of the signals output by VC01 and VC03 are fed back to the first frequency divider, the first frequency divider pair The signal is divided and output to a phase-locked loop.
  • the phase-locked loop compares the reference frequency with the frequency of the output signal after the first frequency divider is divided. According to the comparison result, the current pulse is adjusted and output to the low-pass filter LPF1 for control.
  • the control voltage output from LPF1 is constant at a predetermined value, causing VC01 and VC03 to generate a signal of constant frequency.
  • the phase-locked loop outputs a current pulse to the low-pass filter LPF2, LPF2 filters out the high-frequency signal in the current pulse, and outputs the control voltage to the voltage-controlled oscillator VC02, which generates a 146.7 MHz signal under the control of the control voltage.
  • Output, VC02 output signal is divided into two ways, one is used as the second receiving local oscillator, the other is output to the second frequency divider, and the second frequency divider divides the 453.35MHz and outputs it to the phase-locked loop.
  • the phase-locked loop is compared.
  • the frequency of the output signal after the reference frequency is divided by the second frequency divider, according to the comparison result, the current pulse is adjusted and output to the low pass filter LPF2, so as to control the control voltage outputted by the LPF2 to be constant at a predetermined value, so that the VC02 is made constant.
  • the signal of the frequency is.
  • the first receiving local oscillator and the second receiving local oscillator are receiving local oscillators of the transceiver, that is, two local oscillators used by the transceiver to perform down-conversion processing on the received signals.
  • FIG. 2 shows another structure of a radio frequency synthesizer provided by the prior art, which is different from FIG. 1 in that: the voltage controlled oscillator VC03 generates a signal with a frequency of (380-430 MHz) x 2 MHz, and then uses one. A divide-by-two divideter obtains a signal of 380-430 MHz as the transmitted local oscillator.
  • the transmission frequency in Figure 1 is the same as the oscillation frequency of VC03 (the frequency of the output signal of VC03)
  • the second harmonic of the transmission frequency in Figure 2 is the same as the oscillation frequency of VC03 (the frequency of the output signal of VC03), resulting in The transmitted signal interferes with VC03, making the operating state of VC03 unstable, and thus unable to provide a stable transmitting local oscillator.
  • Embodiments of the present invention provide a radio frequency synthesizer capable of preventing a transmission signal of a transceiver from causing interference to a voltage controlled oscillator in a phase locked loop system.
  • An RF synthesizer comprising:
  • phase-locked loop system configured to output a signal of a first frequency and a signal of a second frequency; wherein, the signal of the second frequency is a second receiving local oscillator;
  • a frequency synthesizing circuit configured to perform frequency synthesis on the signal of the first frequency and the signal of the second frequency to obtain a signal of a predetermined frequency y, the predetermined frequency y rnxf ⁇ nxf ⁇ , where f is the first frequency, f 2 is the second frequency, m, n is not 0; the predetermined frequency is a transmission frequency of a transceiver where the radio frequency synthesizer is located or a multiple of a transmission frequency of the transceiver.
  • a transceiver includes the above RF synthesizer.
  • the RF synthesizer performs frequency synthesis on the first frequency signal and the second frequency signal locked by the phase locked loop system to obtain a signal of a predetermined frequency y, wherein the predetermined frequency is the transmitting frequency of the transceiver where the radio frequency synthesizer is located. Or a multiple of the transmitting frequency of the transceiver, and the second frequency signal is the second receiving local oscillator, so that the carrier of the transmitted signal (ie, the signal of the predetermined frequency y) can be obtained by using the signal of the first frequency and the second receiving local oscillator.
  • the carrier rate of the transceiver transmitting signal is different from the frequency locked by the phase locked loop system, and is not the frequency division or frequency multiplication of the locked phase of the phase locked loop system, so that the transmitted signal does not interfere with the phase locked loop system.
  • the voltage controlled oscillator enables the voltage controlled oscillator in the phase locked loop system to work stably, thereby enabling the phase locked loop system to stably output the signal of the first frequency and the second receiving local oscillator.
  • FIG. 1 is a structural diagram of a radio frequency synthesizer provided by the prior art
  • FIG. 2 is a structural diagram of another RF synthesizer provided by the prior art
  • FIG. 3 is a structural diagram of a radio frequency synthesizer according to an embodiment of the present invention.
  • FIG. 4 is a specific structural diagram of a radio frequency synthesizer according to an embodiment of the present invention.
  • FIG. 5 is a structural diagram of a phase locked loop in a radio frequency synthesizer according to an embodiment of the present invention.
  • FIG. 6 is a specific structural diagram of another radio frequency synthesizer according to an embodiment of the present invention.
  • FIG. 7 is a detailed structural diagram of still another radio frequency synthesizer according to an embodiment of the present invention. Detailed ways
  • an embodiment of the present invention provides a radio frequency synthesizer, including: a phase locked loop system 10 and a frequency synthesizing circuit 20,
  • phase-locked loop system 10 configured to output a signal of a first frequency and a signal of a second frequency; wherein, the signal of the second frequency is a second receiving local oscillator;
  • the transmitting frequency of the transceiver is the same as the receiving frequency.
  • the signal of the first frequency is the first receiving local oscillator of the transceiver.
  • the phase locked loop system includes: a first voltage controlled oscillator And a second voltage controlled oscillator; wherein, the first voltage controlled oscillator is configured to output a signal of a first frequency, and the second voltage controlled oscillator is configured to output a signal of the second frequency, wherein the signal of the first frequency and the first The signals of the two frequencies are respectively the first receiving local oscillator and the second receiving local oscillator of the transceiver, wherein the first receiving local oscillator and the second receiving local oscillator are local oscillators used when the received signal is down-converted.
  • the transceiver transmits a frequency different from the receiving frequency, and the difference between the two is called The duplex phase interval; at this time, the phase locked loop system is further configured to output a signal of the third frequency; wherein, the signal of the third frequency is the first receiving local oscillator of the transceiver; the difference between the first frequency and the third frequency is Duplex interval; the signal of the third frequency and the signal of the first frequency are outputted by the same voltage controlled oscillator in the phase locked loop system at different times.
  • the phase locked loop system includes: a first voltage controlled oscillator and a second voltage controlled oscillator; wherein, the first voltage controlled oscillator is configured to output a signal of the first frequency at the first moment, and output the second time a signal of the third frequency; wherein, the signal of the third frequency is the first receiving local oscillator of the transceiver; the difference between the first frequency and the third frequency is a duplex interval, and the duplex interval is the difference between the transmitting frequency and the receiving frequency, that is, The difference obtained by subtracting the third frequency from the first frequency is equal to the difference obtained by subtracting the receiving frequency from the transmitting frequency; the second voltage controlled oscillator is configured to output a signal of the second frequency; wherein the signal of the second frequency is a transceiver The second receiving local oscillator.
  • the frequency synthesizing circuit 20 is configured to perform frequency synthesis on the signal of the first frequency and the signal of the second frequency to obtain a signal of a predetermined frequency, Where f is the first frequency, f 2 is the second frequency, m, n is not 0; the predetermined frequency is a transmission frequency of the transceiver or a multiple of a transmission frequency of the transceiver, the predetermined frequency
  • the signal is the carrier of the transmitted signal, which may also be referred to as the transmitting local oscillator.
  • the predetermined frequency is the carrier rate of the transmitted signal, that is, the transmitting frequency.
  • the frequency synthesizing circuit may adopt the first frequency synthesizing circuit and the second frequency of the subsequent embodiments. The synthesis circuit, the third frequency synthesis circuit or the fourth frequency synthesis circuit are described in detail in the following embodiments.
  • the transceiver operating frequency can be 380MHz - 430MHz, that is, the receiving frequency and transmitting frequency of the transceiver are between 380MHz and 430MHz.
  • the receiving frequency and the transmitting frequency of the transceiver can be the same or different.
  • the RF synthesizer performs frequency synthesis on the first frequency signal and the second frequency signal locked by the phase locked loop system to obtain a signal of a predetermined frequency y, wherein the predetermined frequency is the transmitting frequency of the transceiver where the radio frequency synthesizer is located. Or a multiple of the transmitting frequency of the transceiver, and the second frequency signal is the second receiving local oscillator, so that the carrier of the transmitted signal (ie, the signal of the predetermined frequency y) can be obtained by using the signal of the first frequency and the second receiving local oscillator.
  • the carrier rate of the transceiver transmitting signal is different from the frequency locked by the phase locked loop system, and is not the frequency division or frequency multiplication of the locked phase of the phase locked loop system, so that the transmitted signal does not interfere with the phase locked loop system.
  • the voltage controlled oscillator enables the voltage controlled oscillator in the phase locked loop system to work stably, thereby enabling the phase locked loop system to stably output the signal of the first frequency and the second receiving local oscillator. Further, since only a phase-locked loop system with two voltage-controlled oscillators is used, two carriers for receiving the local oscillator and the transmitted signal can be provided, and there is no need to use three voltage-controlled oscillators as in the prior art, saving The cost.
  • the following embodiments are described by taking the receiving frequency and the transmitting frequency as 380 MHz as an example. However, those skilled in the art can understand that the receiving frequency and the transmitting frequency are not 380 MHz, but other arbitrary frequencies. The technical solutions provided by the following embodiments of the present invention can also be used.
  • a radio frequency synthesizer comprising: a phase locked loop system 100 and a first frequency synthesizing circuit 200.
  • the receiving frequency and the transmitting frequency of the transceiver are equal, and the phase of the phase locked loop system is output.
  • the phase locked loop system 100 includes: a phase locked loop 101, a first low pass filter 102, a first voltage controlled oscillator 103, a first buffer 104, a first frequency divider 105, a second low pass filter 106, Two voltage controlled oscillator 107, a second buffer 108, and a second frequency divider 109.
  • the first frequency synthesizing circuit 200 includes at least: a first mixer 201 and a second mixer 203.
  • the phase-locked loop 101 specifically includes: a first phase frequency detector 1011, a second phase frequency detector 1012, a first charge pump 1013, a second charge pump 1014, and a configuration unit 1015.
  • the structure of the phase locked loop is as shown in FIG.
  • the first phase frequency detector 1011 is configured to compare the frequency division of the first reference frequency with the output signal of the first voltage controlled oscillator to obtain a first comparison result, where the second phase frequency detector 1012 is used.
  • the configuration unit 1015 is configured to receive a Field-Programmable Gate Array (FPGA) Sending configuration parameters, initializing and registering configuration data of the first phase frequency detector 1011, the second phase frequency detector 1012, the first charge pump 1013, and the second charge pump 1014 according to the configuration parameter, and Said FPGA sends a notification message, the notification message is used to lock the phase locked loop 100 to the system is a first and second frequencies, i.e., whether the stability has provided a first receiving local oscillator and a second receiving local oscillator.
  • FPGA Field-Programmable Gate Array
  • a first low-pass filter 102 configured to filter the first current pulse, and output a first control voltage to the first voltage-controlled oscillator; specifically, filtering out the signal of the first current pulse that is greater than the first predetermined frequency And outputting the first control voltage to the first voltage controlled oscillator, wherein the filter bandwidth of the first low pass filter 102 is 0-5 kHz, and at this time, the first predetermined frequency is 5 kHz, specifically, the bandwidth of the low pass filter
  • the design is designed according to actual needs, and can be 2 kHz-6 kHz without affecting the implementation of the present invention.
  • a first voltage controlled oscillator 103 configured to output a frequency f under the control of the first control voltage (ie
  • a first buffer 104 configured to perform debounce processing on the signal output by the first voltage controlled oscillator 103; wherein, one of the signals of the frequency f after the debounce processing is output to the first mixer 201; The other of the signals of the frequency f after de-jitter processing is output to the first frequency divider 105;
  • a first frequency divider 105 configured to perform N1 frequency division on one of the de-jitter processed signals of the frequency f, and feed back the N1 frequency-divided signal to the first phase frequency detector 1011, so that
  • the phase frequency detector 1011 compares the first reference frequency with a signal obtained by dividing the first frequency divider 105, and the first charge pump 1013 adjusts the first current pulse based on the comparison result.
  • the first reference frequency is obtained by dividing M1 by 12 MHz.
  • the first reference frequency is 3 MHz
  • the value of N1 is approximately equal to 151.12.
  • a second low pass filter 106 configured to filter the second current pulse, and output a second control voltage to the second voltage controlled oscillator, specifically for filtering out the signal of the second current pulse that is greater than the second predetermined frequency And outputting a second control voltage to the second voltage controlled oscillator; wherein, the second low pass filter 106 has a filtering bandwidth of 0-5 kHz, and at this time, the second predetermined frequency is 5 kHz, generally, the low pass filter
  • the bandwidth design is designed according to actual needs, and can be 2 kHz-6 kHz without affecting the implementation of the present invention.
  • a second voltage controlled oscillator 107 configured to output a signal having a frequency of f 2 (ie, 146. MHz) under the control of the second control voltage, wherein the signal of the frequency f 2 is a second receiving local oscillator;
  • a second buffer 108 configured to perform debounce processing on the signal output by the second voltage controlled oscillator; one of the signals of the frequency f 2 after the debounce processing is output to the first mixer 201; The other of the processed signals of frequency f 2 is output to the second frequency divider 109;
  • the second frequency divider 109 is configured to perform N2 frequency division on the other one of the signals of the frequency f 2 after the debounce processing, and feed back the signal obtained by dividing the N2 frequency to the second phase frequency detector 1012
  • the second phase frequency detector 1012 compares the second reference frequency with the signal obtained by dividing the second frequency divider 109, and the second charge pump 1014 adjusts the second current pulse based on the comparison result.
  • the second reference frequency is generally obtained by dividing the M2 by 12 MHz, and may be 1.2 MHz, and the value of N2 is equal to 122.25.
  • the first frequency synthesizing circuit 200 includes:
  • the first mixer 201 is configured to mix the signal of the frequency f outputted by the first voltage controlled oscillator 103 and the signal of the frequency of the second voltage controlled oscillator 107 by f 2 to generate a frequency of f r f
  • the second mixer 203 is configured to mix the signal of the frequency f outputted by the first voltage controlled oscillator 103 and the signal of the frequency of the fr f 2 output by the first mixer 201 to generate a frequency of f +
  • the signal of ( ff 2 ) is output; where the frequency + ( ff 2 ) is twice the carrier frequency of the transmitted signal.
  • f + ( ff 2 ) 760 MHz.
  • the method further includes: a first band pass filter 202, configured to output the frequency of the first mixer 201 to f r f 2 The signal is filtered, and the filtered signal having the frequency f r f 2 is outputted to the second mixer 203; in this embodiment, the filter bandwidth of the first band pass filter 202 is 306.65 MHz ⁇ ⁇ , where ⁇ is an experience value;
  • the pass filter 202 filters the mixing result of the first mixer 201 to filter out multiple harmonics of 306.65 MHz.
  • the method further includes: a second band pass filter 204, configured to filter a signal output by the second mixer 203, and output a filtered signal having a frequency of f + (f r f 2 ); 760 ⁇ ⁇ ⁇ of the filter bandwidth of the band pass filter 204, where ⁇ is an empirical value;
  • the second mixer 203 As a result of the mixing by the second mixer 203, not only the 760 MHz signal but also the 760 MHz multiple harmonics, for example, the 1520 MHz signal, is required, so the second band pass filter 204 is required for the second mix.
  • the mixing result of the frequency band 203 is filtered to filter out multiple harmonics of 760 MHz.
  • the buffer one 205 is configured to remove the jitter in the signal of the frequency outputted by the second band pass filter 204 and output the de-jitter processed signal to the transmitting chip of the transceiver, and the transmitting chip of the subsequent transceiver is the frequency
  • the signal of f + ( f r f 2 ) is divided by two to obtain a 380 MHz signal, wherein the 380 MHz signal is the carrier of the transmitted signal, that is, the transmitted local oscillator, and 380 MHz is the carrier rate of the transmitted signal, that is, the transmitting frequency.
  • Signal f 2 (i.e., 306.65 MHz) is utilized in the first mixer and the frequency of the signal (i.e. 453.35MHz) of the signal f 2 (i.e., 146.7MHz) were mixed, embodiments of the present invention produced at a frequency,
  • the signal of frequency f (ie 453.35 MHz) and the signal of frequency f - f 2 (ie 306.65 MHz) are then mixed by the second mixer frequency to generate a 760 MHz signal and output to the transmitting chip of the transceiver, followed by
  • the transceiver chip of the transceiver divides the 760MHz signal by two to obtain a 380MHz signal, so that the carrier frequency of the transmitted signal (ie 380MHz) is different from the output frequency of the phase-locked loop system (ie 453.35MHz and 146.7MHz), and is not a lock.
  • the frequency division or multiplication of the output frequency of the phase loop system makes the transmitted signal not interfere with the voltage controlled oscillator in the phase locked loop system, so that the voltage controlled oscillator in the phase locked loop system can work stably, thereby making the phase lock
  • the ring system provides a stable first receive local oscillator and a second receive local oscillator. Further, since only the phase-locked loop system with two voltage-controlled oscillators is used, two receiving local oscillators and a transmitting local oscillator (ie, the above-mentioned 380 MHz signal) can be provided, and it is not necessary to use three voltages as in the prior art. Controlled oscillators save costs.
  • the above embodiment is described by taking the frequency of the first receiving local oscillator outputted by the phase locked loop system as the sum of the receiving frequency and the intermediate frequency of the transceiver.
  • the first receiving of the phase locked loop system output
  • the frequency of the local oscillator ⁇ can be the difference between the receiving frequency of the transceiver and the intermediate frequency.
  • the transmitting frequency and the receiving frequency in this embodiment are 380 MHz, which is merely an illustrative description, and those skilled in the art can understand that
  • the transmit and receive frequencies can be any of 380 MHz to 430 MHz.
  • the circuit structure used in this example is similar to that shown in Figure 4, except that:
  • a first voltage controlled oscillator 103 configured to output a signal having a frequency f (ie, 306.65 MHz) under the control of the first control voltage;
  • a second voltage controlled oscillator 107 for outputting a signal having a frequency of f 2 (ie, 146.7 MHz) under the control of the second control voltage;
  • the second mixer 203 is configured to mix the signal of the frequency f output by the first voltage controlled oscillator 103 and the signal of the frequency output by the first mixer 201 to generate a frequency of f + (f + f 2 ) The signal is output.
  • the first mixer 201 and the second mixer 203 may further include: a first band pass filter 202, configured to filter a signal of a frequency output by the first mixer 201, and output filtering The subsequent frequency is a signal of fi + fs to the second mixer 203; in this embodiment, the filter bandwidth of the first band pass filter 202 is 453.35 ⁇ ⁇ ⁇ , where ⁇ is an empirical value.
  • the second band pass filter 204 and the buffer one 205 are further included, and the specific functions of the second band pass filter 204 and the buffer one 205 are the same as those in the foregoing embodiment, and details are not described herein again.
  • FIG. 6 shows another RF synthesizer, comprising: a phase locked loop system 100 and a second frequency synthesizing circuit 300.
  • the receiving transceiver has the same receiving frequency and transmitting frequency
  • the phase locked loop system outputs
  • the frequency of the first receiving local oscillator is the sum of the receiving frequency of the transceiver and the intermediate frequency
  • the frequency f 2 of the second receiving local oscillator is twice the intermediate frequency
  • it is assumed that the receiving frequency and the transmitting frequency of the transceiver are both 380 MHz, and the intermediate frequency is 73.35 MHz.
  • the transmitting frequency and the receiving frequency in this embodiment
  • the rate of 380 MHz is merely an illustrative description, and those skilled in the art can understand that the transmitting frequency and the receiving frequency may be any one of 380 MHz-430 MHz.
  • the structure of the phase locked loop system 100 and the lock of FIG. The structure of the phase ring system 100 is the same and will not be described here.
  • the second frequency synthesizing circuit 300 specifically includes:
  • a signal for frequency f 2 outputted by the second voltage controlled oscillator 107 in the phase locked loop system 100 is divided by two to generate a signal having a frequency of f 2 /2.
  • the mixer 302 is configured to mix a signal of a frequency fi output by the first voltage controlled oscillator 103 in the phase locked loop system 100 and a signal of a frequency of f 2 /2 output by the second frequency divider 301, Generating a signal having a frequency of f r f 2 /2 and outputting; wherein, the frequency f r f 2 /2 is a carrier frequency of the transmitted signal, in this embodiment,
  • the signal received by the transceiver chip of the transceiver is the carrier of the transmitted signal.
  • the mixer 302 can have a frequency of f r f 2 /2 (ie, 380 MHz).
  • the signal is directly output to the transmitting chip; if there is a divide-by-two frequency divider in the transmitting chip of the transceiver, the frequency of the signal received by the transmitting chip of the transceiver should be twice the carrier frequency of the transmitting signal, so the second frequency synthesizing circuit 300 also includes:
  • a band pass filter 303 is provided for filtering a signal of the frequency f r f 2 /2 output from the mixer 302, and outputting the filtered signal having a frequency of f r f 2 /2.
  • the filter bandwidth of the band pass filter 303 is 380 ⁇ ⁇ ⁇ , where ⁇ is an empirical value;
  • the 380MHz multiple harmonics for example, the 760MHz signal, require a bandpass filter-303 to filter the mixing result of the mixer 302 to filter out multiple harmonics of 380MHz.
  • a band pass filter 305 for filtering a signal of the frequency multiplier 304 output frequency of 2 ⁇ ( ff 2 /2 ), and outputting the filtered signal having a frequency of 2 ⁇ ( ff 2 /2 );
  • the buffer two 306 is configured to remove the jitter in the signal of the frequency band 2 ⁇ ( ff 2 /2 ) outputted by the band pass filter two 304 and output the debounced signal to the transmitting chip of the transceiver, and the subsequent transceiver sends the signal
  • the shooter divides the 760MHz signal by two to obtain a 380MHz signal, and the transceiver uses the 380MHz signal as the carrier of the transmitted signal.
  • a signal with a frequency of f 2 (ie, 146.7 MHz) is divided by two by a divide-by-2 frequency divider, and a signal with a frequency of f 2 /2 (ie, 73.35 MHz) is generated and sent to the mixer.
  • the mixer then mixes the signal at frequency f (ie 453.35 MHz) with the signal at frequency f 2 /2 (ie 73.35 MHz) to produce a 380 MHz signal, which is then doubled by a frequency multiplier to the 380 MHz signal.
  • a 760 MHz signal is generated and output to a transceiver chip of the transceiver, and the transmitting chip of the subsequent transceiver divides the 760 MHz signal by two to obtain a 380 MHz signal, so that the carrier frequency of the transmitted signal (ie, the transmitting frequency is 380 MHz) and the phase locked loop system
  • the output frequency ie 453.35MHz and 146.7MHz
  • the voltage controlled oscillator in the system can work stably, thereby enabling the phase locked loop system to provide a stable first receiving local oscillator and a second receiving local oscillator.
  • phase-locked loop system with two voltage-controlled oscillators since only the phase-locked loop system with two voltage-controlled oscillators is used, it is possible to provide two carriers that receive the local oscillator and the transmitted signal (ie, the above-mentioned 380 MHz signal), without using three as in the prior art. Voltage controlled oscillators save costs.
  • the above embodiment is described by taking the frequency f of the first receiving local oscillator outputted by the phase locked loop system as the sum of the receiving frequency and the intermediate frequency of the transceiver.
  • the first output of the phase locked loop system is The frequency ⁇ of the receiving local oscillator may be the difference between the receiving frequency of the transceiver and the intermediate frequency.
  • the transmission frequency and the reception frequency in this embodiment are only 380 MHz. It will be understood by those skilled in the art that the transmission frequency and the reception frequency may be any of 380 MHz to 430 MHz.
  • the circuit structure used at this time is similar to that shown in Figure 6, except that:
  • a first voltage controlled oscillator 103 configured to output a signal having a frequency f (ie, 306.65 MHz) under the control of the first control voltage;
  • a second voltage controlled oscillator 107 for outputting a signal having a frequency of f 2 (ie, 146.7 MHz) under the control of the second control voltage;
  • a signal for frequency f 2 outputted from the second voltage controlled oscillator 107 is divided by two, and a signal having a frequency of f 2 /2 (ie, 73.35 MHz) is generated and output.
  • the mixer 302 is configured to mix the signal of the frequency f 2 /2 output by the second frequency divider 301 and the signal of the frequency f output by the first voltage controlled oscillator 103 to generate a frequency of /2+.
  • FIG. 7 shows another RF synthesizer, comprising: a phase locked loop system 100 and a third frequency synthesizing circuit 400.
  • the frequency f of the first receiving local oscillator output by the phase locked loop system is the receiving frequency and the intermediate frequency of the transceiver.
  • the frequency f 2 of the second receiving local oscillator is twice the intermediate frequency.
  • the structure of the phase-locked loop system 100 is the same as that of the phase-locked loop 100 of FIG. 5, and details are not described herein again.
  • the third frequency synthesizing circuit 400 specifically includes:
  • the frequency multiplier 401 is configured to double-double the signal of the frequency output by the first voltage controlled oscillator 103 in the phase locked loop system 100 to obtain a signal of a frequency 2xf (ie, 906.7 MHz) and output the signal;
  • the mixer 403 is configured to mix the signal of the frequency 2 xf output by the frequency multiplier 401 and the signal of the frequency f 2 output by the second voltage controlled oscillator 107 in the phase locked loop system 100 to obtain a frequency of 2xf r
  • the signal of f 2 is output, wherein This frequency is twice the carrier frequency of the transmitted signal, that is, twice the transmission frequency.
  • the method further includes: a filter one 402, configured to filter the signal of the output frequency 2 ⁇ (ie, 906.7 MHz) of the frequency multiplier 401 And outputting the filtered signal of frequency 2 ⁇ (ie, 906.7 MHz) to the mixer 403; the filter bandwidth of the filter one 402 is 906.7 MHz ⁇ , where ⁇ is a small value.
  • the frequency multiplier 401 doubles the 453.35 MHz outputted by the phase locked loop system 100, not only the 906.7 MHz signal but also the multiple harmonics of 906.7 MHz are obtained, so the filter-402 output of the frequency multiplier 401 is required. The signal is filtered.
  • the method further includes: a filter 404, configured to filter a signal with a frequency of 2 ⁇ f r f 2 output by the mixer 403, and output a filtered signal with a frequency of 2 ⁇ f r f 2 To buffer three 405.
  • the filter bandwidth of filter two 404 is 760 MHz ⁇ ⁇ , where ⁇ is a small value. Since the mixer 403 mixes the 906.7 MHz signal output from the filter one 402 and the 146.7 MHz signal output from the phase locked loop system 100, not only the 760 MHz signal but also the 760 MHz multiple harmonics are obtained, so the filter is required.
  • the second 404 filters the signal output by the mixer 403.
  • the buffer three 405 is configured to perform debounce processing on the signal of the 2ndf r f 2 (ie, 760MHz ) output of the filter 404, and send the de-jitter processed signal to the transmitting chip of the transceiver, and subsequently the transceiver
  • the transmitting chip divides the 760 MHz signal by two to obtain a 380 MHz signal, and the transceiver uses the 380 MHz signal as the carrier frequency of the transmitted signal.
  • the frequency of the signal (ie, 453.35 MHz) is doubled by using a frequency multiplier, and a signal with a frequency of 2 ⁇ f (ie, 906.7 MHz) is generated and sent to the mixer, and then the frequency is matched by the mixer.
  • a signal of 2 ⁇ (ie 906.7 MHz) and a signal of frequency f 2 (146.7 MHz) are mixed to generate a 760 MHz signal, and the transmitting chip of the subsequent transceiver divides the 760 MHz signal by two to obtain a 380 MHz signal, so that the signal is transmitted.
  • the carrier frequency (ie 380MHz) is different from the output frequency of the phase-locked loop system (ie 453.35MHz and 146.7MHz), and is not the frequency division or multiplication of the output frequency of the phase-locked loop system, so that the transmitted signal does not interfere with the phase-locked phase.
  • the voltage controlled oscillator in the ring system enables the voltage controlled oscillator in the phase locked loop system to operate stably, thereby enabling the phase locked loop system to provide a stable first receiving local oscillator and a second receiving local oscillator.
  • phase-locked loop system with two voltage-controlled oscillators since only the phase-locked loop system with two voltage-controlled oscillators is used, it is possible to provide two carriers that receive the local oscillator and the transmitted signal (ie, the above-mentioned 380 MHz signal), and do not need to use three as in the prior art. Voltage controlled oscillators save costs.
  • the above embodiment is described by taking the frequency of the first receiving local oscillator outputted by the phase locked loop system as the sum of the receiving frequency and the intermediate frequency of the transceiver.
  • the first receiving of the phase locked loop system output
  • the frequency f of the local oscillator can be the difference between the receiving frequency and the intermediate frequency of the transceiver.
  • the circuit structure used at this time is similar to that shown in Figure 4, except that: a first voltage controlled oscillator 103, configured to output a signal having a frequency of f (ie, 306.65 MHz) under the control of the first control voltage;
  • a second voltage controlled oscillator 107 for outputting a signal having a frequency of f 2 (ie, 146.7 MHz) under the control of the second control voltage;
  • the frequency multiplier 401 is configured to double-double the signal of the frequency outputted by the first voltage controlled oscillator 103 to obtain a signal with a frequency of 2 ⁇ (ie, 613.3 MHz) and output the signal;
  • the method further includes: a filter one 402, configured to filter a signal with a frequency of 2 ⁇ f (ie, 613.3 MHz) output by the frequency multiplier 401, and output the filtered signal.
  • the frequency of the signal is 2xf (ie, 613.3MHz) to the mixer 403; the filter bandwidth of the filter one 402 is 613.3MHz ⁇ ⁇ , where ⁇ is a small value.
  • the present invention provides a radio frequency synthesizer, comprising: a phase locked loop system and a fourth frequency synthesizing circuit.
  • the receiving transceiver has a receiving frequency and a transmitting frequency equal to each other, and the intermediate frequency is 73.35 MHz, and the foregoing embodiments The difference is that the frequency f 2 of the second receiving local oscillator is the intermediate frequency.
  • the frequency of the first receiving local oscillator output by the phase locked loop system is the sum of the receiving frequency and the intermediate frequency of the transceiver, and the receiving frequency and the transmitting frequency of the transceiver are both 380 MHz, and the intermediate frequency is 73.35.
  • the transmission frequency and the reception frequency of 380 MHz are merely illustrative, and those skilled in the art will appreciate that the transmission frequency and the reception frequency may be any of 380 MHz to 430 MHz.
  • the structure of the phase-locked loop system in this embodiment is similar to that of FIG. 5, and the difference is that: the first voltage-controlled oscillator is configured to output the frequency f under the control of the first control voltage (ie,
  • a second voltage controlled oscillator for outputting a frequency of f 2 under control of the second control voltage (ie, 73.35
  • the fourth frequency synthesizing circuit comprises: a mixer for outputting the frequency of the first voltage controlled oscillator to be (ie, 453.35 MHz) and the frequency of the second voltage controlled oscillator output being f 2 (ie, 73.35 MHz)
  • the frequency f of the first receiving local oscillator output by the phase locked loop system is the difference between the receiving frequency and the intermediate frequency of the transceiver, and the receiving frequency and the transmitting frequency of the transceiver are both 380 MHz.
  • the intermediate frequency is 73.35MHz.
  • the transmitting frequency and the receiving frequency in this embodiment are only 380 MHz, and those skilled in the art can understand that the transmitting frequency is And the receiving frequency can be any of 380 MHz-430 MHz.
  • a first voltage controlled oscillator for outputting a frequency f under the control of the first control voltage
  • a second voltage controlled oscillator for outputting a signal having a frequency of f 2 (ie, 73.35 MHz) under control of the second control voltage;
  • the fourth frequency synthesizing circuit includes: a first frequency multiplier for performing twice frequency on the signal outputted by the first voltage controlled oscillator, that is, 306.75 MHz, to obtain a frequency of 2 ⁇ (ie, 613.5 MHz).
  • a second frequency multiplier for multiplexing a signal of a frequency of f 2 (ie, 73.35 MHz) outputted by the second voltage controlled oscillator to obtain a signal having a frequency of 2 ⁇ f 2 (ie, 146.7 MHz);
  • the frequency is 2x +2x (ie 613.
  • the fourth frequency synthesizing circuit comprises: a mixer, the signal for outputting the frequency of the first voltage controlled oscillator to be (ie, 307.65 MHz) and the frequency of the output of the second voltage controlled oscillator being f 2 (ie, 73.35 MHz)
  • the transceiver in which the RF synthesizer is located is time-sharing.
  • the phase-locked loop system in the RF synthesizer can output the first receiving local oscillator and the second receiving local oscillator, and the transceiver.
  • the first received local oscillator and the second received local oscillator may be used to demodulate the received radio frequency signal in the first time slot, and the signal of the predetermined frequency y (ie, the carrier of the transmitted signal) generated by the frequency synthesizing circuit is used to transmit the radio frequency in the third time slot. signal.
  • the transmission frequency and the reception frequency may also be different.
  • the difference between the RF combiner and the RF combiner provided by the above embodiments is different. It is:
  • the first voltage controlled oscillator is configured to output a signal of the first frequency at a first time and a signal of the third frequency at a second time.
  • the difference between the first frequency and the third frequency is a duplex interval;
  • the signal of the third frequency is the first receiving local oscillator of the transceiver; for example, the first voltage controlled oscillator outputs the first receiving local oscillator in the first time slot , so that the transceiver uses the first receiving local oscillator to perform down-conversion processing on the received radio frequency signal, and the first voltage-controlled oscillator outputs a signal of the first frequency in the third time slot, so that the frequency synthesizing circuit generates the signal by using the first frequency.
  • the carrier of the transmitted signal is used by the transceiver to transmit the RF signal using the carrier.
  • the second voltage controlled oscillator is configured to output a signal of the second frequency; wherein the signal of the second frequency is the second receiving local oscillator of the transceiver.
  • the first frequency is f
  • the second frequency is f 2
  • the structure of the frequency synthesizing circuit is the same as the corresponding structure in the above embodiment, and will not be described again herein;
  • the first voltage controlled oscillator outputs signals of different frequencies at different times, one for the first receiving local oscillator and the other for the subsequent frequency synthesizing circuit for frequency synthesis.
  • the transceiver's transmit frequency is 380MHz
  • the receive frequency is 390MHz
  • the duplex interval is 10MHz.
  • the first voltage controlled oscillator is in the first
  • the signal of 453.35MHz ie 463.35MHz-10MHz
  • the first voltage controlled oscillator outputs the 463.35MHz signal as the first receiving local oscillator at the second moment, and the subsequent frequency synthesis
  • the structure and function of the device are similar to those of the above embodiments, and are not described herein again.
  • the embodiment of the invention further provides a transceiver comprising any of the above radio frequency synthesizers.
  • the transceiver is capable of frequency synthesizing the first frequency signal and the second frequency signal locked by the phase locked loop system to obtain a signal of a predetermined frequency y, wherein the predetermined frequency is a transmitting frequency of the transceiver or a multiple of a transmitting frequency of the transceiver
  • the second frequency signal is the second receiving local oscillator, so that the carrier of the transmitting signal can be obtained by using the signal of the first frequency and the second receiving local oscillator, and the carrier rate of the transmitting signal of the transceiver is locked with the phase locked loop system.
  • the frequency is different, and it is not the frequency division or multiplication of the frequency locked by the phase-locked loop system, so that the transmitted signal does not interfere with the voltage-controlled oscillator in the phase-locked loop system, so that the voltage-controlled oscillator in the phase-locked loop system can Stable operation, in turn, enables the phase-locked loop system to stably output a signal having a first frequency and a second receiving local oscillator. Further, since only a phase-locked loop system with two voltage-controlled oscillators is used, two carriers for receiving the local oscillator and the transmitted signal can be provided, and there is no need to use three voltage-controlled oscillators as in the prior art, saving The cost.
  • the medium can be a read only memory, a magnetic disk or a compact disk or the like.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Transceivers (AREA)

Abstract

L'invention concerne un synthétiseur radiofréquence comprenant un système de boucle à verrouillage de phase utilisé pour délivrer un signal à une première fréquence et un signal à une seconde fréquence, le signal à la seconde fréquence étant un second signal d'oscillateur local de réception et un circuit de synthèse de fréquence utilisé pour synthétiser la fréquence du signal à la première fréquence et du signal à la seconde fréquence et obtenir un signal à une fréquence prédéterminée y. La fréquence prédéterminée est égale à y=m×f1±n×f2, f1 étant la première fréquence, f2 étant la seconde fréquence et m et n n'étant pas égaux à zéro. La fréquence prédéterminée est une ou plusieurs fois supérieure à la fréquence d'émission de l'émetteur/récepteur où se trouve le synthétiseur radiofréquence. Un émetteur/récepteur comprend ledit synthétiseur radiofréquence.
PCT/CN2011/079572 2011-09-13 2011-09-13 Synthétiseur radiofréquence et émetteur/récepteur Ceased WO2013037100A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353311A (en) * 1992-01-09 1994-10-04 Nec Corporation Radio transmitter
CN1236502A (zh) * 1996-11-06 1999-11-24 艾利森公司 用于移动台的频率合成器电路
CN101471662A (zh) * 2007-12-26 2009-07-01 中国科学院微电子研究所 用于OFDM UWB的6至8.2GHz五频带频率综合器
CN201774528U (zh) * 2010-01-22 2011-03-23 南京誉葆科技有限公司 一体化Ku波段综合数字编码收发指令装置
CN102324932A (zh) * 2011-09-13 2012-01-18 海能达通信股份有限公司 射频合成器和收发机

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353311A (en) * 1992-01-09 1994-10-04 Nec Corporation Radio transmitter
CN1236502A (zh) * 1996-11-06 1999-11-24 艾利森公司 用于移动台的频率合成器电路
CN101471662A (zh) * 2007-12-26 2009-07-01 中国科学院微电子研究所 用于OFDM UWB的6至8.2GHz五频带频率综合器
CN201774528U (zh) * 2010-01-22 2011-03-23 南京誉葆科技有限公司 一体化Ku波段综合数字编码收发指令装置
CN102324932A (zh) * 2011-09-13 2012-01-18 海能达通信股份有限公司 射频合成器和收发机

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