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WO2013031552A1 - Dispositif d'affichage à cristaux liquides et procédé de commande associé - Google Patents

Dispositif d'affichage à cristaux liquides et procédé de commande associé Download PDF

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Publication number
WO2013031552A1
WO2013031552A1 PCT/JP2012/070883 JP2012070883W WO2013031552A1 WO 2013031552 A1 WO2013031552 A1 WO 2013031552A1 JP 2012070883 W JP2012070883 W JP 2012070883W WO 2013031552 A1 WO2013031552 A1 WO 2013031552A1
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WIPO (PCT)
Prior art keywords
line
video signal
scanning
auxiliary capacitance
pixel
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Ceased
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PCT/JP2012/070883
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English (en)
Japanese (ja)
Inventor
耕平 田中
誠二 金子
小川　康行
山本　薫
誠一 内田
泰 高丸
森　重恭
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Sharp Corp
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Sharp Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general

Definitions

  • the present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device that changes the potential of an auxiliary capacitance line in a liquid crystal display device at a predetermined timing and a driving method thereof.
  • a driving method in which the potential of the corresponding auxiliary capacitance line is changed after the selection period of each gate line (scanning signal line) is completed.
  • a driving method is referred to as a “CS driving method”.
  • This CS driving method generally includes a CS driver (auxiliary capacitance line driving circuit) for sequentially changing the potential of each CS line (the auxiliary capacitance line) in a liquid crystal display device. It is realized by providing it.
  • the CS driver is configured using, for example, a shift register. According to such a CS driving method, a large voltage can be applied to the liquid crystal layer with a small video signal amplitude, so that power consumption can be reduced.
  • Patent Document 1 for example.
  • Patent Document 2 discloses a liquid crystal display device in which a plurality of CS lines (auxiliary capacitance lines) are grouped into a plurality (for example, four) groups, and a plurality of CS lines included in each group are collectively driven. It is disclosed. With this configuration, the CS driver (auxiliary capacitor driver) can be simplified.
  • Japanese Unexamined Patent Publication No. 5-143021 Japanese Unexamined Patent Publication No. 2009-75418 Japanese Unexamined Patent Publication No. 2001-31253
  • an object of the present invention is to provide a CS driving type liquid crystal display device that reduces power consumption while reducing the frame area, and a driving method thereof.
  • a first aspect of the present invention is a liquid crystal display device, A plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and a plurality of pixel electrodes arranged in a matrix corresponding to the plurality of video signal lines and the plurality of scanning signal lines, A plurality of auxiliary capacitance lines arranged along a plurality of predetermined signal lines which are either the plurality of video signal lines or the plurality of scanning signal lines, and each pixel electrode and the plurality of auxiliary capacitance lines.
  • a display unit including an auxiliary capacitor formed between the two, A scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are in a non-selected state are alternately set with a frame period including the scanning period and the pause period as a cycle.
  • a scanning signal line driving circuit for driving the plurality of scanning signal lines as shown in FIG.
  • a video signal line drive that applies a video signal to the plurality of pixel electrodes via the plurality of video signal lines and sets the video signal to have a first polarity or a second polarity different from each other in the scanning period.
  • a storage capacitor signal to be applied to each storage capacitor line is generated, and a potential of the storage capacitor signal to be applied to the storage capacitor line in which the storage capacitor is formed between the pixel electrode to which the first polarity video signal is applied. And the potential of the storage capacitor signal to be applied to the storage capacitor line in which the storage capacitor is formed between the pixel electrode to which the video signal of the second polarity is applied and
  • An auxiliary capacitance signal generation circuit is provided that makes the potential of the auxiliary capacitance signal to be given to the auxiliary capacitance line different from the potential of the auxiliary capacitance signal to be given to the auxiliary capacitance line in the scanning period immediately before the pause period. .
  • the pause period is longer than the scanning period.
  • the predetermined signal line is the scanning signal line;
  • the auxiliary capacitance is formed between a pixel electrode corresponding to each scanning signal line and an auxiliary capacitance line along the scanning signal line,
  • the video signal line driving circuit selects the predetermined number of the scanning signal lines to select the polarity of the plurality of video signals to be applied to the plurality of video signal lines, respectively. It is characterized by inversion every period.
  • the predetermined signal line is the video signal line;
  • the auxiliary capacitance is formed between a pixel electrode corresponding to each video signal line and an auxiliary capacitance line along the video signal line,
  • the video signal line driving circuit reverses the polarity of the plurality of video signals to be given to the plurality of video signal lines for each of a predetermined number of the video signal lines in the scanning period.
  • a pixel electrode corresponding to an odd-numbered scanning signal line counted from the arrangement position side of the video signal line driving circuit, arranged in the direction in which the video signal line extends to the pixel electrode, and of the video signal line driving circuit The pixel electrodes corresponding to the even-numbered scanning signal lines counted from the arrangement position side correspond to the video signal lines adjacent to each other.
  • the predetermined signal line is the scanning signal line;
  • the auxiliary capacitor includes a pixel electrode corresponding to an odd-numbered video signal line counted from an arrangement position side of the scanning signal line driving circuit among pixel electrodes corresponding to each scanning signal line, and along the scanning signal line.
  • the video signal line driving circuit inverts the polarities of the plurality of video signals to be respectively applied to the plurality of video signal lines in the scanning period for each selection period in which each scanning signal line is in a selected state. It is characterized in that each signal line is inverted.
  • the predetermined signal line is the video signal line;
  • the auxiliary capacitor includes pixel electrodes corresponding to odd-numbered scanning signal lines counted from the arrangement position side of the video signal line driving circuit among pixel electrodes corresponding to the video signal lines, and along the video signal lines.
  • the video signal line driving circuit inverts the polarities of the plurality of video signals to be respectively applied to the plurality of video signal lines in the scanning period for each selection period in which each scanning signal line is in a selected state. It is characterized in that each signal line is inverted.
  • the video signal line driving circuit is characterized in that the amplitude of the plurality of video signals in a selection period in which each scanning signal line is in a selected state is reduced from the start time to the end time of the scanning period.
  • Each auxiliary capacitance line is formed as a transparent electrode.
  • Each auxiliary capacitance line is formed as an electrode of the same material as the predetermined signal line along the auxiliary capacitance line.
  • An eleventh aspect of the present invention is any one of the first to tenth aspects of the present invention,
  • the display unit further includes a thin film transistor in which the scanning signal line corresponding to each pixel electrode is connected to a gate terminal, and a semiconductor layer is formed of an oxide semiconductor,
  • the video signal line and the pixel electrode corresponding to the video signal line are connected via the thin film transistor in which the scanning signal line corresponding to the pixel electrode is connected to the gate terminal.
  • a plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines, and the plurality of scanning signal lines are arranged in a matrix.
  • a driving method for a display device comprising: a video signal line driving circuit for supplying video signals to a plurality of pixel electrodes; and an auxiliary capacitance signal generating circuit for generating an auxiliary capacitance signal to be given to each auxiliary capacitance line,
  • a scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are in a non-selected state are alternately set with a frame period including the scanning period and the pause period as a cycle.
  • the video signal has a polarity that is either a first polarity or a second polarity different from each other;
  • the storage capacitor signal potential to be applied to the storage capacitor line in which the storage capacitor is formed between the electrodes is different from each other, and the storage capacitor signal potential to be applied to each storage capacitor line in the pause period is And a step of making the potential different from the potential of the auxiliary capacitance signal to be applied to the auxiliary capacitance line in the scanning period immediately before the pause period.
  • a thirteenth aspect of the present invention is the twelfth aspect of the present invention, wherein the pause period is longer than the scanning period.
  • the amplitude of the plurality of video signals in the selection period in which each scanning signal line is in a selected state is reduced from the start point to the end point of the scanning period.
  • the method further comprises the step of:
  • CS driving is performed in a liquid crystal display device that performs so-called low-frequency refresh driving in which a rest period is provided after the scanning period.
  • the potential of the auxiliary capacitance signal to be given to each auxiliary capacitance line in the pause period is made different from the potential of the auxiliary capacitance signal to be given to the auxiliary capacitance line in the scanning period immediately before the pause period.
  • This is performed by an auxiliary capacitance signal generation circuit.
  • This auxiliary capacitance signal generation circuit changes the potential of each auxiliary capacitance line (auxiliary capacitance signal) in a pause period without sequentially changing the potential of each auxiliary capacitance line unlike the conventional CS driver.
  • the circuit scale is smaller than that of a conventional CS driver. For this reason, power consumption can be reduced while reducing the frame area. Further, since low frequency refresh driving is performed, further reduction in power consumption can be achieved.
  • the pause period is longer than the scanning period, further power consumption can be achieved.
  • the storage capacitor is formed between the pixel electrode corresponding to each scanning signal line and the storage capacitor line along the scanning signal line.
  • the polarities of the plurality of video signals to be applied to the plurality of video signal lines are inverted every predetermined number of selection periods in which the predetermined number of scanning signal lines are selected. Therefore, line inversion driving can be performed in units of a predetermined number of scanning signal lines.
  • the storage capacitor is formed between the pixel electrode corresponding to each video signal line and the storage capacitor line along the video signal line. Further, in the scanning period, the polarities of the plurality of video signals to be given to the plurality of video signal lines are inverted every predetermined number of video signal lines. Therefore, line inversion driving can be performed in units of a predetermined number of video signal lines.
  • the pixel electrodes corresponding to the odd-numbered pixels counted from the arrangement position side of the video signal line driving circuit, arranged in the extending direction of the video signal line, and the arrangement of the video signal line driving circuit correspond to the video signal lines adjacent to each other. For this reason, the polarities of the plurality of video signals to be given to the plurality of video signal lines are inverted every selection period in which each scanning signal line is selected. Thereby, so-called dot inversion driving can be performed.
  • the auxiliary capacitor is a pixel corresponding to an odd-numbered video signal line counted from the arrangement position side of the scanning signal line driving circuit among the pixel electrodes corresponding to each scanning signal line.
  • An even-numbered image that is formed between the electrode and the auxiliary capacitance line along the scanning signal line and counted from the arrangement position side of the scanning signal line driving circuit among the pixel electrodes corresponding to each scanning signal line It is formed between the pixel electrode corresponding to the signal line and the auxiliary capacitance line along the scanning signal line preceding the scanning signal line.
  • the polarities of the plurality of video signals to be given to the plurality of video signal lines are inverted for each selection period in which each scanning signal line is selected, and are inverted for each video signal line. For this reason, so-called dot inversion driving can be performed.
  • the auxiliary capacitors correspond to the odd-numbered scanning signal lines counted from the arrangement position side of the video signal line driving circuit.
  • the polarities of the plurality of video signals to be given to the plurality of video signal lines are inverted for each selection period in which each scanning signal line is selected, and are inverted for each video signal line. For this reason, so-called dot inversion driving can be performed.
  • the amplitude of the plurality of video signals in each selection period decreases from the start point to the end point of the scanning period.
  • the amplitude of the video signal decreases from the first selection period to the last selection period.
  • the scanning signal line that is earlier in the selection state in the scanning period has a higher pixel potential in the pixel formation portion corresponding to the scanning signal line, and the scanning signal line that has the later timing in the selection period in the scanning period.
  • each auxiliary capacitance line is formed as a transparent electrode. For this reason, the fall of an aperture ratio can be suppressed.
  • each auxiliary capacitance line is formed as an electrode made of the same material as a predetermined signal line. For this reason, since the auxiliary capacitance line and the predetermined signal line can be formed in the same process, the cost can be reduced.
  • a thin film transistor in which a semiconductor layer is formed of an oxide semiconductor is provided corresponding to each pixel electrode. For this reason, since the pixel potential can be held for a long time, the pause period can be made sufficiently long. In addition, since the writing of the video signal to the pixel electrode can be speeded up, the scanning period can be sufficiently shortened. Thereby, it is possible to suppress a decrease in the frame frequency (driving frequency in one frame period) while performing the low-frequency refresh driving.
  • the driving method of the liquid crystal display device has the same effects as the first aspect, the second aspect, and the eighth aspect of the present invention, respectively. be able to.
  • FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention.
  • FIG. 3 is a circuit diagram illustrating a configuration of a pixel formation unit in the first embodiment. It is a circuit diagram which shows the structure of the display part in the said 1st Embodiment. It is a signal waveform diagram which shows operation
  • FIG. 6 is a cross-sectional view taken along line A-A ′ in FIG. 5.
  • FIG. 8 is a sectional view taken along line B-B ′ in FIG. 7. It is a figure which shows the drain current-gate voltage characteristic of a-SiTFT and IGZOTFT. It is a circuit diagram which shows the structure of the display part in the 2nd Embodiment of this invention. It is a signal waveform diagram which shows operation
  • FIG. 15 is a sectional view taken along line D-D ′ in FIG. 14.
  • It is a circuit diagram which shows the structure of the display part in the 3rd Embodiment of this invention. It is a signal waveform diagram which shows operation
  • It is a top view which shows the implementation example of the pixel layout in the said 3rd Embodiment. It is a circuit diagram which shows the structure of the display part in the 1st modification of the said 3rd Embodiment.
  • FIG. 1 is a block diagram showing an overall configuration of an active matrix type liquid crystal display device adopting a CS driving method according to a first embodiment of the present invention.
  • the liquid crystal display device includes a power supply 100, a DC / DC converter 110, a display control circuit 200, a source driver (video signal line driving circuit) 300, a gate driver (scanning signal line driving circuit) 400, a display. Part 500 and common electrode driving circuit 600.
  • the liquid crystal display device according to this embodiment does not include a CS driver in the frame portion of the display unit 500 (panel).
  • the display unit 500 includes m source lines (video signal lines) SL1 to SLn, m gate lines (scanning signal lines) GL1 to GLm, and m gate lines GL1 to GLm.
  • a plurality of (m ⁇ n) pixel formation portions provided corresponding to the intersections of the CS lines (auxiliary capacitance lines) CL1 to CLm and the source lines SL1 to SLn and the gate lines GL1 to GLm, respectively. Is formed.
  • m and n are assumed to be even numbers, but the present invention is not limited to this.
  • These m ⁇ n pixel forming portions are arranged in a matrix to form a pixel array.
  • FIG. 2 is a circuit diagram showing a configuration of each pixel forming portion in the present embodiment.
  • the symbol P (i, j) is given to the pixel formation portion in the i-th row and j-th column.
  • the constituent elements other than the pixel formation portion the constituent elements in the i-th row, the j-th column, and the i-th row and j-th column are respectively referred to as “i-th row”, “j-th column”, and “i-row j” The description may be made using the continuation modifier of the “column”.
  • the pixel forming portion P (i, j) in the i-th row and j-th column has a gate terminal connected to the i-th gate line GLi passing through the corresponding intersection and the j-th source line SLj passing through the intersection.
  • a thin film transistor 50 having a source terminal connected thereto, a pixel electrode Ep connected to a drain terminal of the thin film transistor 50, a common electrode Ec commonly provided in the m ⁇ n pixel forming portions, and the m ⁇ n number
  • the liquid crystal layer is provided between the pixel electrode Ep and the common electrode Ec.
  • the symbol Ep (i, j) is attached to the pixel electrode in the pixel formation portion P (i, j) in the i-th row and j-th column. Further, the potential of the pixel electrode Ep (i, j) is referred to as a pixel potential, and is denoted by a reference symbol Vp (i, j).
  • a liquid crystal capacitance Clc is formed by the pixel electrode Ep and the common electrode Ec. Further, an auxiliary capacitor Ccs is formed by the CS line and the pixel electrode Ep. A pixel capacitor Cp is formed by the liquid crystal capacitor Clc and the auxiliary capacitor Ccs.
  • the semiconductor layer of the thin film transistor 50 in this embodiment is formed of, for example, an oxide semiconductor.
  • the present invention is not limited to this, and the semiconductor layer may be formed of, for example, amorphous silicon, polycrystalline silicon, or microcrystalline silicon. Note that an example in which an oxide semiconductor is used for a semiconductor layer will be described later.
  • the power supply 100 supplies a predetermined power supply voltage to the DC / DC converter 110, the display control circuit 200, and the common electrode drive circuit 600.
  • the DC / DC converter 110 generates a predetermined DC voltage for operating the source driver 300 and the gate driver 400 from the power supply voltage, and supplies it to the source driver 300 and the gate driver 400.
  • the common electrode drive circuit 600 applies a predetermined potential Vcom to the common electrode Ec. This potential Vcom is typically a fixed potential.
  • the display control circuit 200 receives an image signal DAT and a timing signal group TG such as a horizontal synchronization signal and a vertical synchronization signal sent from the outside, and controls a digital video signal DV and a source start pulse signal for controlling image display on the display unit 500.
  • SSP, source clock signal SCK, latch strobe signal LS, gate start pulse signal GSP, and gate clock signal GCK are output.
  • the display control circuit 200 in this embodiment is provided with an auxiliary capacitance signal generation circuit 201.
  • the display control circuit 200 generates and outputs an auxiliary capacitance signal CS for applying a bias to the pixel potential in each pixel formation unit by the auxiliary capacitance signal generation circuit 201.
  • This auxiliary capacitance signal CS is composed of two-phase auxiliary capacitance signals CSa and CSb.
  • the auxiliary capacitance signal CSa is referred to as a “first auxiliary capacitance signal”
  • the auxiliary capacitance signal CSb is referred to as a “second auxiliary capacitance signal”.
  • the first auxiliary capacitance signal CSa is applied to the odd-numbered CS lines
  • the second auxiliary capacitance signal CSb is applied to the even-numbered CS lines.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb are respectively sent to two power supply circuits (not shown) provided in the auxiliary capacitance signal generation circuit 201, for example, according to the timing signal group TG described above. Is generated.
  • the present invention is not limited to this, and the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb may be generated using three or more power supply circuits. In this case, the addition per power supply circuit is reduced.
  • the source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and receives the video signal SS (1) on the source lines SL1 to SLn, respectively. Apply ⁇ SS (n).
  • the gate driver 400 Based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200, the gate driver 400 scans signals GS (1) to GS at a high level potential (potential at which each gate line is selected). The application of (m) to each of the gate lines GL1 to GLm is repeated with one frame period as a cycle. A detailed description of the operation of the gate driver 400 will be given later.
  • the video signals SS (1) to SS (n) are applied to the source lines SL1 to SLn, respectively, and the scanning signals GOUT (1) to GOUT (m) are applied to the gate lines GL1 to GLm, respectively.
  • the display unit 500 an image based on the image signal DAT sent from the outside is displayed on the display unit 500.
  • FIG. 3 is a circuit diagram showing a configuration of the display unit 500 in the present embodiment.
  • the CS lines CL1 to CLm in this embodiment are arranged along the gate lines GL1 to GLm, respectively.
  • the auxiliary capacitance Ccs in each pixel formation portion is formed between the CS line arranged along the gate line to which the gate terminal of the thin film transistor 50 in the pixel formation portion is connected and the pixel electrode Ep in the pixel formation portion. ing.
  • the first auxiliary capacitance signal CSa is applied to the CS lines CL1, CL3,... CLm ⁇ 1 in the odd-numbered rows (hereinafter simply referred to as “odd-numbered rows”) counted from the side where the source driver 300 is arranged.
  • the second auxiliary capacitance signal CSb is applied to the CS lines CL2, CL4,... CLm of even-numbered rows (hereinafter simply referred to as “even-numbered rows”) counted from the side where the source driver 300 is disposed.
  • FIG. 4 is a signal waveform diagram for explaining the operation of the liquid crystal display device according to the present embodiment.
  • the pixel potential Vp (1,1) in the first row and the first column the pixel potential Vp (1 in the first row and the second column).
  • the pixel potential Vp (2,1) in the second row and the first column and the pixel potential Vp (m, 1) in the mth row and the first column are illustrated (in FIG. 23, however, Vp (1,1) ) And Vp (m, 1) only).
  • Vp (1,1) the pixel potential in the second row and the first column
  • Vp (m, 1) the pixel potential Vp (m, 1) in the mth row and the first column
  • one frame period is composed of a scanning period T1 and a pause period T2 provided after the scanning period T1. That is, the gate driver 400 drives the m gate lines GL1 to GLm so that the scanning period T1 and the scanning period T2 appear alternately with one frame period as a cycle.
  • the scanning period T1 the scanning signals GS (1) to GS (m) are sequentially set to the high level potential based on the gate clock signal GCK.
  • the suspension period T2 all of the m gate lines GL1 to GLm (scanning signals GS (1) to GS (m)) are in a non-selected state (low level potential).
  • the driving performed by providing the pause period T2 after the scanning period T1 is called “low frequency refresh driving”, and is disclosed in, for example, Patent Document 3.
  • the length of the scanning period T1 is 8.3 msec
  • the length of the pause period T2 is 991.7 msec. That is, the pause period T2 is longer than the scanning period T1.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb in the scanning period T1 are at a low potential Vl and a high potential Vh, which are different from each other. That is, the odd-numbered CS lines are at the low potential Vl, and the even-numbered CS lines are at the high potential Vh.
  • the video signals SS (1) to SS (n) repeat positive polarity (first polarity) and negative polarity (second polarity) every horizontal scanning period, and have the same polarity in each horizontal scanning period. .
  • the polarities of these video signals SS (1) to SS (n) are inverted every frame period.
  • the polarity inversion of the video signals SS (1) to SS (n) for each frame period is similarly performed in the following embodiments and modifications.
  • the horizontal scanning periods in which the gate lines GL1 to GLm in the 1st to mth rows are selected are referred to as “first to m selection periods”, respectively.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GL1 is turned on.
  • the pixel capacitor Cp is charged by the video signal that is output.
  • the pixel potential Vp (1,1) in the first row and the first column which is the pixel potential in the first row
  • the pixel potential Vp (1,2) in the first row and the second column become the write potential Vsig.
  • the pixel potential in the first row has a positive polarity.
  • the pixel potentials in the pixel forming portions adjacent to the extending direction of the gate line have the same polarity.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GL2 is turned on, so that the pixel capacitor Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potential Vp (2, 1) in the second row and the first column which is the pixel potential in the second row, becomes the write potential Vsig.
  • the pixel potential in the second row has a negative polarity.
  • the pixel potential after the second-row gate line GL2 is not selected is the same as that for the first row.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GLm is turned on, so that the pixel capacitance Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potential Vp (m, 1) in the m-th row and the first column which is the pixel potential in the m-th row, becomes the write potential Vsig.
  • the pixel potential in the m-th row has a negative polarity.
  • the pixel potential after the m-th gate line GLm is not selected is the same as that for the first row.
  • pixel potentials in pixel forming portions adjacent to the extending direction of the source line (hereinafter referred to as “Y direction”) have different polarities.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb respectively applied to the even-numbered CS lines forming the auxiliary capacitance Ccs therebetween have different potentials.
  • the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb are maintained until the end of the scanning period T1 in the subsequent frame period. Further, as described above, all of the gate lines GL1 to GLm are in a non-selected state during the suspension period T2, and each video signal is at a Vcom potential (not limited to this, but may be another fixed potential). Yes. Note that this video signal is not applied to the pixel electrode because the gate lines GL1 to GLm are all in a non-selected state.
  • the pixel potential Vp (1, 1) in the first row and first column is changed to the first potential.
  • the bias voltage ⁇ Vcs corresponding to the change in the one auxiliary capacitance signal CSa is applied.
  • the pixel potential Vp (1, 1) in the first row and the first column is expressed by the following formula (1) (however, the left side is shown as each pixel potential Vp).
  • Cpa represents a parasitic capacitance in the pixel.
  • the pixel potential Vp (1, 1) in the first row and the first column is larger than the write potential Vsig corresponding to the amplitude of the video signal by (Ccs / (Clc + Ccs + Cpa)) ⁇ (Vh ⁇ Vl).
  • the pixel potential Vp (1, 1) in the first row and first column is held until the thin film transistor 50 is turned on again in the scanning period T1 of the frame period subsequent to the present frame period.
  • the timing at which the video signal is written in the scanning period T1 is different in the 1st to mth rows, while the auxiliary capacitance signal is simultaneously changed in the 1st to mth rows in the rest period T2. For this reason, wrinkles may occur in the effective voltage for one frame in the first to mth rows.
  • each row has a different period from when the bias voltage ⁇ Vcs is added to the pixel potential Vp in the pause period T2 until the video signal is written in the immediately following scanning period T1. Because of.
  • “effective voltage for one frame” refers to a scanning period in a frame period subsequent to a video signal writing point (hereinafter simply referred to as “writing point”) in a scanning period T1 in an arbitrary frame period.
  • the effective voltage applied to the pixel capacitor Cp in the period up to the writing time at T1 (hereinafter referred to as “one frame holding period”).
  • the voltage applied to the pixel capacitor Cp of the pixel formation portion P (1,1) in the first row and first column corresponds to the difference between the pixel potential Vp (1,1) and the Vcom potential shown in FIG.
  • Such a difference in effective voltage for one frame is particularly large in a difference in period from when the bias voltage ⁇ Vcs is added to the pixel potential Vp in the pause period T2 to when the video signal is written in the immediately following scanning period T1. It becomes large between the 1st line and the m-th line.
  • the pause period T2 (991.7 msec) is set longer than the scanning period T1 (8.3 msec).
  • the pause period T2 is sufficiently longer than the scanning period T1
  • the influence of the difference in the 1st to mth rows of the timing at which the video signal is written in the scanning period T1 with respect to the one frame holding period is reduced. Therefore, the effective voltage drop for one frame in the 1st to mth rows is reduced.
  • FIG. 5 is a plan view showing a first implementation example of the pixel layout in the present embodiment.
  • 6 is a cross-sectional view taken along line AA ′ in FIG. 5 and 6 and the subsequent drawings relating to the pixel layout, the portion corresponding to the pixel formation portion P (i, j) is mainly shown.
  • the source line, the gate line, and the CS line are hatched, but the transparent electrode is not hatched.
  • illustration of an insulating substrate etc. is omitted.
  • the source line and the gate line are provided so as to cross each other, and the CS line is provided along the gate line.
  • the thin film transistor 50 is connected to a source line (more specifically, a part of the source line is a source electrode), is connected to a gate line (more specifically, a part of the gate line is a gate electrode), and is connected to a drain electrode. Connected to Ed.
  • the drain electrode Ed and the pixel electrode Ep are connected to each other through a contact hole CH.
  • the source line and the gate line are formed by a laminated film of an Al film and a Ti film, for example.
  • the CS line is also formed by a laminated film of an Al film and a Ti film.
  • a first insulating layer 51 is formed on the CS line (and the gate line).
  • the first insulating layer 51 is made of, for example, SiN x .
  • a source line and drain electrode Ed are formed on the first insulating layer 51.
  • the first insulating layer 51 forms an auxiliary capacitor Ccs between the CS line and the drain electrode Ed (that is, the pixel electrode Ep).
  • a second insulating layer 52 is formed on the source line and drain electrode Ed.
  • the second insulating layer 52 is made of, for example, SiN x . In the second insulating layer 52, the contact hole CH described above for connecting the drain electrode Ed and the pixel electrode Ep to each other is formed.
  • the pixel electrode Ep is formed so as to cover the contact hole CH. For this reason, the drain electrode Ed and the pixel electrode Ep are connected to each other.
  • the pixel electrode Ep is a transparent electrode made of ITO (Indium Tin Oxide) or the like.
  • a liquid crystal layer 60 is formed by filling liquid crystal between the pixel electrode Ep and the common electrode Ec which is a transparent electrode made of ITO or the like facing the pixel electrode Ep.
  • the liquid crystal layer 60 forms a liquid crystal capacitance Clc (not shown) between the pixel electrode Ep and the common electrode Ec.
  • the CS line is made of the same material as the gate line, these can be formed in the same process.
  • FIG. 7 is a plan view showing a second implementation example of the pixel layout in the present embodiment.
  • 8 is a cross-sectional view taken along the line BB ′ in FIG. Note that description of portions common to the first implementation example is omitted.
  • the CS line is formed as a transparent electrode made of ITO or the like.
  • the CS line in this implementation example is continuously formed across pixel forming portions adjacent in the X direction.
  • the drain electrode Ed is connected only to the pixel electrode Ep via the contact hole CH, and is not connected to the CS line.
  • the CS line does not cover the thin film transistor 50, but the present invention is not limited to this.
  • a first insulating layer 51 is formed on the source line.
  • a CS line which is a transparent electrode made of ITO or the like, is formed on the first insulating layer 51.
  • a second insulating layer 52 is formed on the CS line.
  • a pixel electrode Ep is formed on the second insulating layer 52. The second insulating layer 52 forms an auxiliary capacitor Ccs between the CS line and the pixel electrode Ep.
  • the CS line is formed as a transparent electrode, the CS line can be formed without reducing the aperture ratio.
  • a-Si TFT a thin film transistor
  • a-Si TFT a thin film transistor
  • a-Si amorphous silicon
  • an oxide semiconductor is used for the semiconductor layer of the thin film transistor 50 in each pixel formation portion in this embodiment.
  • the oxide semiconductor typically, InGaZnO x (hereinafter referred to as “IGZO”), which is an oxide semiconductor mainly containing indium, gallium, zinc, and oxygen, is used. It is not limited. For example, any oxide semiconductor containing at least one of indium, gallium, zinc, copper, silicon, tin, aluminum, calcium, germanium, and lead may be used.
  • FIG. 9 is a diagram showing drain current-gate voltage characteristics of a TFT using a-Si TFT and IGZO as a semiconductor layer (hereinafter referred to as “IGZOTFT”).
  • the horizontal axis represents the gate voltage Vg
  • the vertical axis represents the drain current Ids.
  • the leakage current of the IGZOTFT is 1/1000 or less of the leakage current of the a-Si TFT
  • the on-current of the IGZOTFT is about 20 times the on-current of the a-Si TFT.
  • the IGZOTFT has a small off-leakage current as described above, when the IGZOTFT is used as the thin film transistor 50 in this embodiment, the pixel potential can be maintained for a longer time than when the a-Si TFT is used as the thin film transistor 50. For this reason, when the IGZOTFT is used as the thin film transistor 50 in the present embodiment, the idle period T2 can be sufficiently provided.
  • the IGZOTFT has a large on-state current as described above, when the IGZOTFT is used as the thin film transistor 50 in this embodiment, the video signal is written to the pixel formation portion more than when the a-Si TFT is used as the thin film transistor 50. Can be speeded up. That is, the scanning period T1 can be shortened.
  • CS driving is performed in a liquid crystal display device that performs so-called low-frequency refresh driving in which a pause period T2 is provided after the scanning period T1.
  • a CS driver for driving a CS line is not provided in the frame portion of the display unit 500 (panel).
  • the display control circuit 200 is provided with an auxiliary capacitance signal generation circuit 201 that collectively changes the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb applied to the respective CS lines in the idle period T2.
  • this auxiliary capacitance signal generation circuit 201 changes the potential of each CS line at once without sequentially changing the potential of each CS line unlike the conventional CS driver, the circuit scale is larger than that of the conventional CS driver. Is small. For this reason, power consumption can be reduced while reducing the frame area. Further, since low frequency refresh driving is performed, further reduction in power consumption can be achieved. Further, since the potentials of all the CS lines (auxiliary capacitance signals) change simultaneously, the scanning order of the gate lines is ascending (GL1 ⁇ GL2 ⁇ ... ⁇ GLm) or descending (GLm ⁇ ... ⁇ GL2 ⁇ GL1). ) CS driving can be performed regardless of whether or not.
  • the pause period T2 is provided longer than the scanning period T1, further power consumption can be achieved.
  • the pause period T2 is sufficiently provided, the influence of the difference in the 1st to mth rows of the timing at which the video signal is written in the scanning period T1 with respect to the 1 frame holding period is reduced. Therefore, the effective voltage drop for one frame in the 1st to m-th rows is sufficiently reduced.
  • the CS lines CL1 to CLm are provided along the gate lines GL1 to GLm, respectively, and the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb having different potentials are respectively connected to the odd-numbered rows and It is given to the CS line of the even row.
  • the scanning period T1 the polarity of each video signal is inverted every horizontal scanning period, and the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb change simultaneously in the pause period T2.
  • line inversion driving (“gate line inversion driving”) that inverts the polarity of the video signal every predetermined number of gate lines (in this embodiment, one) and every frame period. Say).
  • the cost can be reduced because the CS line can be formed in the same process as the gate line.
  • the CS line is formed as a transparent electrode, it is possible to suppress a decrease in the aperture ratio due to the formation of the CS line.
  • the pixel potential can be held for a long time, so that the pause period T2 can be made sufficiently long.
  • the scanning period T1 can be sufficiently shortened. In this case, it is possible to suppress a decrease in the frame frequency (drive frequency in one frame period) while performing the low frequency refresh drive.
  • FIG. 10 is a circuit diagram showing a configuration of the display unit 500 according to the second embodiment of the present invention. Note that this embodiment is the same as the first embodiment except for the configuration of the display unit 500, the operation of the liquid crystal display device, and an implementation example of the pixel layout, and thus description of the same parts is omitted. .
  • the number of CS lines is n.
  • the n CS lines CL1 to CLn are arranged along the source lines SL1 to SLn, respectively.
  • the auxiliary capacitance Ccs in each pixel formation portion is formed between the CS line arranged along the source line to which the source terminal of the thin film transistor in the pixel formation portion is connected and the pixel electrode Ep in the pixel formation portion. Yes.
  • the first auxiliary capacitance signal CSa is applied to the CS lines CL1, CL3,..., CLn ⁇ 1 of the odd-numbered columns (hereinafter simply referred to as “odd-numbered columns”) counted from the side where the gate driver 400 is disposed.
  • the second auxiliary capacitance signal CSb is applied to the CS lines CL2, CL4,... CLn of even-numbered columns (hereinafter simply referred to as “even-numbered columns”) counted from the side where the gate driver 400 is disposed.
  • FIG. 11 is a signal waveform diagram for explaining the operation of the liquid crystal display device according to the present embodiment.
  • the description of the same parts as those in the first embodiment will be omitted as appropriate.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb in the scanning period T1 are at a low potential Vl and a high potential Vh, which are different from each other, respectively. That is, the odd-numbered CS lines are at the low potential Vl, and the even-numbered CS lines are at the high potential Vh.
  • the video signals applied to the odd-numbered and even-numbered source lines are positive and negative in the scanning period T1 (in the scanning period T1 in the subsequent frame period), respectively. Negative polarity and positive polarity).
  • the thin film transistor 50 whose gate terminal is connected to the gate line GL1 is turned on, so that the pixel capacitance Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potential Vp (1,1) in the first row and the first column which is the pixel potential in the first row
  • the pixel potential Vp (1,2) in the first row and the second column become the write potential Vsig.
  • the pixel potentials of the odd-numbered and even-numbered columns in the first row are positive and negative, respectively. Become sex.
  • the pixel potentials in the pixel formation portions adjacent in the X direction have different polarities.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GL2 is turned on, so that the pixel capacitance Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potential Vp (2, 1) in the second row and the first column which is the pixel potential in the second row, becomes the write potential Vsig.
  • the odd-numbered and even-numbered video signals are positive and negative, respectively, the odd-numbered and even-numbered pixels in the second row are the same as in the first row. The potential becomes positive and negative, respectively.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GLm is turned on, so that the pixel capacitor Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potential Vp (m, 1) in the m-th row and the first column which is the pixel potential in the m-th row, becomes the write potential Vsig.
  • the odd-numbered and even-numbered video signals are positive and negative, respectively, the odd-numbered and even-numbered pixels in the m-th row are the same as the first row. The potential becomes positive and negative, respectively.
  • the pixel potentials in the pixel forming portions adjacent in the Y direction have the same polarity.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb respectively applied to the even-numbered CS lines forming the auxiliary capacitance Ccs therebetween have different potentials.
  • FIG. 12 is a plan view showing a first implementation example of the pixel layout in the present embodiment.
  • 13 is a cross-sectional view taken along the line CC ′ in FIG. Note that description of parts similar to those of the implementation examples in the first embodiment is omitted as appropriate.
  • the source line and the gate line are provided so as to cross each other, and the CS line is provided along the source line.
  • the CS line in this implementation example is a CS bus line Bcs along the source line and a narrow CS line Ecs along the gate line and having a width in the X direction smaller than the distance between adjacent source lines. (Hereinafter simply referred to as “CS line Ecs”).
  • the material of each component in this implementation example is the same as that in the first implementation example of the first embodiment.
  • the CS bus line Bcs and the CS line Ecs are formed of the same material (for example, a laminated film of an Al film and a Ti film).
  • a first insulating layer 51 is formed on the CS line Ecs (and the gate line).
  • a first contact hole CHa for connecting the CS line Ecs and the CS bus line Bcs to each other is formed.
  • a source line, a drain electrode Ed, and a CS bus line Bcs are formed on the first insulating layer 51.
  • the CS bus line Bcs is formed so as to cover the first contact hole CHa. For this reason, the CS line electrode Ecs and the CS bus line Bcs are connected to each other.
  • the first insulating layer 51 forms an auxiliary capacitor Ccs between the CS line Ecs and the drain electrode Ed (that is, the pixel electrode Ep).
  • a second insulating layer 52 is formed on the source line, the drain electrode Ed, and the CS bus line Bcs.
  • the contact hole CH described above for connecting the drain electrode Ed and the pixel electrode Ep to each other is formed.
  • the pixel electrode Ep is formed so as to cover the contact hole CH. For this reason, the drain electrode Ed and the pixel electrode Ep are connected to each other.
  • the CS line Ecs is made of the same material as the gate line, they can be formed in the same process. Further, since the CS bus line Bcs is made of the same material as the source line and the drain electrode Ed, they can be formed in the same process.
  • FIG. 14 is a plan view showing a second implementation example of the pixel layout in the present embodiment.
  • 15 is a cross-sectional view taken along the line DD ′ in FIG. Note that description of portions common to the first implementation example is omitted. Further, FIG. 15 (layer structure) is the same as that of the second example of realization in the first embodiment, and the description thereof is omitted.
  • the CS line is formed as a transparent electrode made of ITO or the like.
  • the CS line in this implementation example is continuously formed across pixel forming portions adjacent in the Y direction. In FIG. 14, the CS line does not cover the thin film transistor 50, but the present invention is not limited to this.
  • the CS line is formed as a transparent electrode, the CS line can be formed without reducing the aperture ratio.
  • the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb applied to the odd-numbered and even-numbered CS lines are applied during the idle period T2.
  • An auxiliary capacitance signal generation circuit 201 that changes all at once is provided in the display control circuit 200. Since this auxiliary capacitance signal generation circuit 201 changes the potential of each CS line at once without sequentially changing the potential of each CS line unlike the conventional CS driver, the circuit scale is larger than that of the conventional CS driver. Is small. For this reason, power consumption can be reduced while reducing the frame area. Further, since low frequency refresh driving is performed, further reduction in power consumption can be achieved.
  • CS driving can be performed regardless of whether or not.
  • the CS lines CL1 to CLn are provided along the source lines SL1 to SLn, respectively, and the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb having different potentials are respectively connected to the odd-numbered columns and It is given to the CS line of the even column.
  • the odd-numbered and even-numbered video signals have different polarities, and the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb change simultaneously in the pause period T2.
  • line inversion driving (“source line inversion driving") that changes the polarity of the video signal for each predetermined number of source lines (one in this embodiment) and for each frame period while performing CS driving. Say).
  • the CS line Ecs can be formed in the same process as the gate line, and the CS bus line Bcs is set as the source line and the drain line. It can be formed by the same process. For this reason, cost can be reduced.
  • the CS line is formed as a transparent electrode, it is possible to suppress a decrease in the aperture ratio due to the formation of the CS line.
  • FIG. 16 is a circuit diagram showing a configuration of the display unit 500 according to the third embodiment of the present invention. Note that this embodiment is the same as the first embodiment except for the configuration of the display unit 500, the operation of the liquid crystal display device, and an implementation example of the pixel layout, and thus description of the same parts is omitted. .
  • CS lines CL1 to CLm are arranged along the gate lines GL1 to GLm, respectively, as in the first embodiment, while one CS line CL0 is further provided. It is provided as a CS line preceding the CS line CL1 in the first row.
  • the CS line CL0 may be referred to as a “0th CS line”.
  • the CS line CL0 is assumed to belong to the even-numbered CS line.
  • the auxiliary capacitance Ccs in the pixel formation portion in the odd-numbered column is between the CS line arranged along the gate line to which the gate terminal of the thin film transistor 50 in the pixel formation portion is connected and the pixel electrode Ep in the pixel formation portion. Is formed.
  • the auxiliary capacitance Ccs in the pixel formation portion in the even-numbered column includes the CS line preceding the CS line arranged along the gate line to which the gate terminal of the thin film transistor 50 in the pixel formation portion is connected, and It is formed between the pixel electrode Ep in the pixel formation portion.
  • the first auxiliary capacitance signal CSa is supplied to the odd-numbered CS lines CL1, CL3,... CLm-1.
  • the second auxiliary capacitance signal CSb is supplied to CL0, CL2, CL4,.
  • FIG. 17 is a signal waveform diagram for explaining the operation of the liquid crystal display device according to the present embodiment.
  • the description of the same parts as those in the first embodiment will be omitted as appropriate.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb in the scanning period T1 are at a low potential Vl and a high potential Vh, which are different from each other, respectively. That is, the odd-numbered CS lines are at the low potential Vl, and the even-numbered CS lines are at the high potential Vh.
  • the video signals SS (1) to SS (n) repeat the positive polarity and the negative polarity every horizontal scanning period, and the odd-numbered and even-numbered video signals have different polarities.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GL1 is turned on, so that the pixel capacitor Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potential Vp (1,1) in the first row and the first column which is the pixel potential in the first row
  • the pixel potential Vp (1,2) in the first row and the second column become the write potential Vsig.
  • the pixel potentials in the odd-numbered columns and the even-numbered columns in the first row Respectively have a positive polarity and a negative polarity.
  • the pixel potentials in the pixel formation portions adjacent in the X direction have different polarities.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GL2 is turned on, so that the pixel capacitance Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potentials of the odd-numbered and even-numbered columns in the second row Respectively have negative polarity and positive polarity.
  • the thin film transistor 50 whose gate terminal is connected to the gate line GLm is turned on, so that the pixel capacitor Cp is charged by the video signal supplied through the thin film transistor 50.
  • the pixel potential Vp (m, 1) in the m-th row and the first column which is the pixel potential in the m-th row, becomes the write potential Vsig.
  • the pixel potentials of the odd-numbered and even-numbered columns in the m-th row Respectively have negative polarity and positive polarity.
  • the pixel potentials have different polarities not only in the pixel forming portion adjacent in the X direction but also in the pixel forming portion adjacent in the Y direction.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb respectively applied to the even-numbered CS lines forming the auxiliary capacitance Ccs therebetween have different potentials.
  • the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb change in the same manner as in the first embodiment. Therefore, the odd-numbered CS lines change from the low potential Vl to the high potential Vh, and the even-numbered CS lines change from the high potential Vh to the low potential Vl at the same timing.
  • the pixel potential (pixel potential of the odd-numbered column) of the pixel electrode Ep of the odd-numbered column connected to the CS line of the odd-numbered row via the auxiliary capacitor Ccs has a positive polarity, and the pixel electrode of the even-numbered column The pixel potential of Ep (pixel potential in even-numbered columns) is negative.
  • the pixel potential of the odd-numbered pixel electrode Ep (pixel potential of the odd-numbered column) connected to the even-numbered CS line via the auxiliary capacitor Ccs has a negative polarity, and the pixels of the even-numbered pixel electrode Ep.
  • the potential (pixel potential in even-numbered columns) is positive. Note that the basic operation in the suspension period T2 is the same as that in the first embodiment, and a description thereof will be omitted.
  • FIG. 18 is a plan view showing an implementation example of the pixel layout in the present embodiment. Note that description of parts similar to those of the implementation examples in the first embodiment is omitted as appropriate. Further, the basic layer structure and the material of each component in the present implementation example are the same as those in the second implementation example (see FIG. 8) in the first embodiment. As shown in FIG. 18, in this implementation example, the source line and the gate line are provided so as to cross each other, and the CS line is provided along the gate line.
  • the CS line is formed as a transparent electrode made of ITO or the like.
  • the CS line is continuously formed over pixel forming portions adjacent in the X direction. In FIG. 18, the CS line does not cover the thin film transistor 50, but the present invention is not limited to this.
  • Each CS line in this implementation example is composed of two CS lines.
  • one of these two CS lines is referred to as a “first CS line”, and is denoted by a symbol CLa.
  • the other of these two CS lines is referred to as a “second CS line”, and is denoted by reference symbol CLb.
  • CLa potentials having the same polarity are applied to the first CS line and the second CS line (however, the polarity is inverted for each CS line).
  • the first CS line CLa and the second CS line constituting each CS line are arranged on both sides of the gate line along the CS line. In FIG.
  • the first CS line is opposed to the pixel electrode Ep of the pixel formation portion in the odd-numbered column (hereinafter simply referred to as “in the pixel formation portion” in the description of the pixel layout according to the present implementation example).
  • the area of CLa (the width in the Y direction) is larger than the area of the first CS line CLa in the pixel formation portion in the even-numbered column.
  • the area (width in the Y direction) of the second CS line CLb in the pixel formation portion in the odd-numbered column is smaller than the area of the second CS line CLb in the pixel formation portion in the even-numbered column. Note that the sum of the area of the first CS line CLa and the area of the second CS line CLb in each pixel formation portion is substantially equal.
  • the auxiliary capacitance Ccs of each pixel formation portion in this implementation example is specifically referred to as an auxiliary capacitance (hereinafter referred to as “first auxiliary capacitance”) formed between the first CS line CLa and the pixel electrode Ep in the pixel formation portion.
  • first auxiliary capacitance an auxiliary capacitance formed between the second CS line CLb and the pixel electrode Ep in the pixel formation portion.
  • second auxiliary capacitor an auxiliary capacitor formed between the second CS line CLb and the pixel electrode Ep in the pixel formation portion
  • the auxiliary capacitance Ccs in the pixel formation portion is substantially equal to the first auxiliary capacitance Ccsa. It is configured.
  • the second CS line CLb in the pixel formation portion in the even-numbered row is larger than the first CS line CLa in the pixel formation portion, the auxiliary capacitance Ccs in the pixel formation portion is substantially constituted by the second auxiliary capacitance Ccsb. ing.
  • the first CS line CLa and the second CS line CLb in each pixel forming portion constitute adjacent CS lines.
  • the first CS line CLa in the pixel formation portion in the i-th row and j-th column constitutes the i-th row CS line CLi
  • the second CS line CLb constitutes the i-th row CS line CLi-1.
  • different potentials are applied to the odd-numbered and even-numbered CS lines, that is, the first CS line CLa and the second CS line CLb in each pixel formation portion have different potentials (high potential Vh or A low potential Vl) is applied.
  • each pixel potential Vp after the potentials of all the CS lines simultaneously change in the rest period T2 is expressed by the following formula (2) obtained by modifying the above formula (1).
  • the CS line is formed as a transparent electrode, the CS line can be formed without reducing the aperture ratio.
  • the potentials of the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb applied to the odd-numbered and even-numbered CS lines, respectively, are applied in the idle period T2.
  • An auxiliary capacitance signal generation circuit 201 that changes all at once is provided in the display control circuit 200. Since this auxiliary capacitance signal generation circuit 201 changes the potential of each CS line at once without sequentially changing the potential of each CS line unlike the conventional CS driver, the circuit scale is larger than that of the conventional CS driver. Is small. For this reason, power consumption can be reduced while reducing the frame area. Further, since low frequency refresh driving is performed, further reduction in power consumption can be achieved.
  • CS driving can be performed regardless of whether or not.
  • the CS lines CL1 to CLm are provided along the gate lines GL1 to GLm, respectively, and the first auxiliary capacitance signal CSa and the second auxiliary capacitance signal CSb having different potentials are respectively connected to the odd-numbered rows and It is given to the CS line of the even column.
  • the scanning period T1 the polarity of each video signal is inverted every horizontal scanning period and every frame period, the video signals in the odd-numbered columns and the even-numbered columns have different polarities, and the first auxiliary The potentials of the capacitance signal CSa and the second auxiliary capacitance signal CSb change simultaneously in the pause period T2. For this reason, while performing CS driving, it is possible to perform dot inversion driving that changes the polarity of the video signal for each pixel forming portion adjacent in the X direction and the Y direction and for each frame period.
  • the CS line is formed as a transparent electrode, it is possible to suppress a decrease in the aperture ratio due to the formation of the CS line.
  • FIG. 19 is a circuit diagram showing a configuration of the display unit 500 in the first modification of the third embodiment of the present invention. Since the present modification is the same as the first embodiment and the third embodiment except for the configuration of the display unit 500 and the pixel layout implementation example, the description of the same parts is omitted. .
  • CS lines CL1 to CLn are arranged along the source lines SL1 to SLn, respectively, as in the second embodiment, while one CS line CL0 is further provided. It is provided as a CS line preceding the CS line CL1 in the first column.
  • the CS line CL0 may be referred to as a “0th column CS line”.
  • the CS line CL0 is assumed to belong to the even-numbered CS line.
  • Each CS line corresponds to a source line along the CS line and a source line subsequent to the source line.
  • the auxiliary capacitance Ccs in the pixel formation portion in the odd-numbered rows includes a CS line (that is, a CS line corresponding to the source line) arranged along the source line to which the source terminal of the thin film transistor in the pixel formation portion is connected, and It is formed between the pixel electrode Ep in the pixel formation portion.
  • the auxiliary capacitance Ccs in the pixel formation portion in the even-numbered row is the CS line preceding the CS line (that is, the source) arranged along the source line to which the source terminal of the thin film transistor in the pixel formation portion is connected. The line is formed between the corresponding CS line) and the pixel electrode Ep in the pixel formation portion.
  • the first auxiliary capacitance signal CSa is supplied to the odd-numbered CS lines CL1, CL3,... CLn-1.
  • the second auxiliary capacitance signal CSb is applied to the CS lines CL0, CL2, CL4,. Since the operation of the liquid crystal display device is the same as that of the third embodiment, description thereof is omitted (see FIG. 17).
  • FIG. 20 is a plan view showing an implementation example of the pixel layout in this modification.
  • description is abbreviate
  • the basic layer structure and the material of each component in the present implementation example are the same as those in the second implementation example (see FIG. 15) in the second embodiment.
  • the source line and the gate line are provided so as to cross each other, and the CS line is provided along the source line (more specifically, so as to cover the source line).
  • the CS line is formed as a transparent electrode made of ITO or the like.
  • the CS line is continuously formed over pixel forming portions adjacent in the Y direction. Although the CS line does not cover the thin film transistor 50 in FIG. 20, the present invention is not limited to this.
  • each CS line protrudes toward the pixel forming portion on the odd-numbered row corresponding to the source line covered by the CS line (the width in the X direction increases), and the pixel Opposite the pixel electrode Ep of the formation part.
  • each CS line protrudes to the pixel formation part side of the even-numbered row corresponding to the source line preceding the source line covered by the CS line, and faces the pixel electrode Ep of the pixel formation part.
  • the portion of the CS line that protrudes toward the pixel formation portion and faces the pixel electrode Ep of the pixel formation portion is referred to as a “main CS line”.
  • the opposite side of the main CS line of each CS line in the X direction also slightly faces the pixel forming portion as shown in FIG.
  • the portion of the CS line slightly facing the pixel forming portion is referred to as a “sub CS line”.
  • the main CS line (in each pixel formation portion) facing the pixel electrode Ep in each pixel formation portion has a larger area than the sub CS line in the pixel formation portion. Further, the sum of the area of the main CS line and the area of the sub CS line in each pixel forming portion is substantially equal.
  • the auxiliary capacitance Ccs of each pixel formation portion in this implementation example is more specifically the auxiliary capacitance formed between the main CS line and the pixel electrode Ep in the pixel formation portion (the implementation example of the third embodiment).
  • first auxiliary capacitor and is denoted by Ccsa
  • second auxiliary capacity and is denoted by a symbol Ccsb).
  • the auxiliary capacitance Ccs in the pixel formation portion is substantially equal to the first auxiliary capacitance Ccsa. It is configured.
  • each pixel potential Vp after the potentials of all the CS lines simultaneously change in the rest period T2 is expressed by the above equation (2) as in the implementation example of the third embodiment.
  • FIG. 21 is a circuit diagram showing a configuration of the display unit 500 in the second modification example of the third embodiment of the present invention.
  • description is abbreviate
  • CS lines CL1 to CLn are arranged along the source lines SL1 to SLn, respectively, as in the second embodiment, while one more source line SLn + 1 is provided. It is provided as a source line subsequent to the n-th source line SLn. This source line SLn + 1 belongs to the odd-numbered source line.
  • one CS line CLn + 1 is further provided as a CS line subsequent to the CS line CLn + 1 in the nth column. It is assumed that the CS line CLn + 1 belongs to the odd-numbered CS line.
  • the pixel forming portion (pixel electrode Ep) in the odd-numbered row and the pixel forming portion in the same column (aligned in the Y direction) and the even-numbered row as the pixel forming portion are respectively connected to the adjacent source lines. It corresponds. That is, the odd-numbered pixel forming portions and the even-numbered pixel forming portions in the same column respectively correspond to the adjacent source lines. More specifically, as shown in FIG. 21, the source terminal of the thin film transistor in the pixel formation portion in the odd-numbered rows is connected to the source line in the same column as the pixel formation portion. On the other hand, the source terminal of the thin film transistor in the pixel formation portion in the odd-numbered row is connected to the source line of the column immediately after the pixel formation portion.
  • auxiliary capacitance Ccs in each pixel formation portion is formed between the CS line arranged along the source line to which the source terminal of the thin film transistor in the pixel formation portion is connected and the pixel electrode Ep in the pixel formation portion.
  • the video signal applied to the source line and the auxiliary capacitance signal applied to the CS line are the same as those in the second embodiment.
  • the operation is performed by the same video signal and auxiliary capacitance signal as in the second embodiment.
  • the pixel potentials in the pixel formation portions adjacent in the X direction have different polarities
  • the pixel potentials in the pixel formation portions adjacent in the Y direction have different polarities. That is, dot inversion driving is performed as in the third embodiment and the first modification thereof.
  • FIG. 22 is a plan view showing an implementation example of the pixel layout in the present modification.
  • the pixel layout in this modification is basically the same as that in the first modification of the third embodiment except for the location of the thin film transistor (see FIG. 20).
  • the auxiliary capacitance Ccs of each pixel forming unit is configured by the first auxiliary capacitance Ccsa and the second auxiliary capacitance Ccsb described above.
  • the main CS line in each pixel formation portion has a larger area than the sub CS line in the pixel formation portion, the auxiliary capacitance Ccs in the pixel formation portion is substantially equal to the first auxiliary capacitance Ccsa. It is configured.
  • FIG. 23 is a signal waveform diagram for explaining the operation of the liquid crystal display device according to the fourth embodiment of the present invention. Since this embodiment is the same as the first embodiment except for the operation of the liquid crystal display device, the description of the same portion is omitted. Of the operation of the liquid crystal display device, the description of the same parts as those in the first embodiment will be omitted as appropriate.
  • the length of the scanning period T1 is 8.3 msec, which is the same as that in the first embodiment, whereas the length of the pause period T2 is different from that in the first embodiment. It is 8.3 msec. That is, a pause period T2 having the same length as the scanning period T1 is provided.
  • the effective voltage for one frame can be wrinkled in the 1st to mth rows.
  • the amplitude of each video signal decreases from the first selection period to the mth selection period.
  • the write potential Vsig increases as the line is on the scanning start side (side with the smaller gate line code number), and the write potential Vsig becomes closer toward the scanning end side (side with the larger gate line code number). Get smaller.
  • the pixel potential Vp increases as the scanning start side row, and the pixel potential Vp decreases as the scanning end side row.
  • wrinkles are reduced in the effective voltage for one frame in the 1st to mth rows.
  • the auxiliary capacitance signal generation circuit 201 is provided in the display control circuit 200, but the present invention is not limited to this.
  • the auxiliary capacitance signal generation circuit 201 may be provided outside the display control circuit 200.
  • the polarity of the video signal is inverted for each gate line.
  • the polarity of the video signal may be inverted for a plurality of gate lines.
  • the polarity of the video signal is inverted for each source line.
  • the polarity of the video signal may be inverted for each of a plurality of source lines.
  • the CS line is formed as a transparent electrode.
  • the present invention is not limited to this.
  • the CS line is replaced with a gate line or the like, similar to the second implementation example in the first embodiment and the second implementation example in the second embodiment.
  • the same material may be used. However, in this case, it is desirable to pay sufficient attention to the decrease in aperture ratio.
  • the rest period T2 is the same as the scanning period T1, but may be shorter than the scanning period T1.
  • CS driving type liquid crystal display device that reduces power consumption while reducing the frame area, and a driving method thereof.
  • the present invention can be applied to a CS drive type liquid crystal display device.
  • Source driver (video signal line drive circuit) 400 Gate driver (scanning signal line driving circuit) P (i, j) ... pixel formation part Ep (i, j) ... pixel electrode Vp (i, j) ... pixel potential GLi ... gate line (scanning signal line) SLj ... Source line (video signal line) Ccs ... auxiliary capacitors CSa, CSb ... first and second auxiliary capacitance signals SS (j) ... video signal T1 ... scanning period T2 ... rest period

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  • General Physics & Mathematics (AREA)
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  • Computer Hardware Design (AREA)
  • Optics & Photonics (AREA)
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  • Liquid Crystal Display Device Control (AREA)

Abstract

L'invention concerne un dispositif d'affichage à cristaux liquides qui utilise un procédé de commande de capacité de stockage, et qui possède une zone périphérique ainsi qu'une consommation d'énergie réduites. Ledit dispositif d'affichage à cristaux liquides utilise un rafraîchissement à basse fréquence avec une période d'inactivité après chaque période de balayage, et une ligne de capacité de stockage (CL1-CLm) est disposée le long de chaque ligne de grille (GL1-GLm). Dans chaque unité de formation de pixels, une capacité de stockage (Ccs) est formée entre l'électrode de pixel de ladite unité de formation de pixels et la ligne de capacité de stockage disposée le long de la ligne de grille connectée à la borne de grille du transistor à film mince (50) de ladite unité de formation de pixels. Un circuit de commande d'affichage fournit un premier signal de capacité de stockage (CSa) et un second signal de capacité de stockage (CSb) respectivement aux lignes de capacités de stockage impaires et paires. Lorsqu'une période d'inactivité débute, le premier signal de capacité de stockage (CSa) passe à un potentiel élevé à partir du potentiel bas présenté par ledit signal pendant les périodes de balayage (T1), et le second signal de capacité de stockage (CSb) passe à un potentiel bas à partir du potentiel élevé présenté par ledit signal pendant les périodes de balayage (T1).
PCT/JP2012/070883 2011-08-26 2012-08-17 Dispositif d'affichage à cristaux liquides et procédé de commande associé Ceased WO2013031552A1 (fr)

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WO2017170069A1 (fr) * 2016-03-30 2017-10-05 シャープ株式会社 Dispositif d'affichage à cristaux liquides
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JP2002182619A (ja) * 2000-10-05 2002-06-26 Sharp Corp 表示装置の駆動方法およびそれを用いた表示装置
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CN104464675A (zh) * 2014-10-24 2015-03-25 友达光电股份有限公司 电力管理方法与电力管理装置
WO2017170069A1 (fr) * 2016-03-30 2017-10-05 シャープ株式会社 Dispositif d'affichage à cristaux liquides
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