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WO2013018595A1 - Dispositif d'affichage et méthode d'alimentation correspondante - Google Patents

Dispositif d'affichage et méthode d'alimentation correspondante Download PDF

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Publication number
WO2013018595A1
WO2013018595A1 PCT/JP2012/068757 JP2012068757W WO2013018595A1 WO 2013018595 A1 WO2013018595 A1 WO 2013018595A1 JP 2012068757 W JP2012068757 W JP 2012068757W WO 2013018595 A1 WO2013018595 A1 WO 2013018595A1
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WIPO (PCT)
Prior art keywords
period
scanning
video signal
clock signal
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2012/068757
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English (en)
Japanese (ja)
Inventor
山本　薫
誠二 金子
小川　康行
耕平 田中
誠一 内田
泰 高丸
森　重恭
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Sharp Corp
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Sharp Corp
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Publication date
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Priority to JP2013526831A priority Critical patent/JP6076253B2/ja
Priority to CN201280048662.5A priority patent/CN103843056B/zh
Publication of WO2013018595A1 publication Critical patent/WO2013018595A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present invention relates to a display device and a driving method thereof, and more particularly, to a display device in which a display unit and a video signal line driving circuit are integrally formed and a driving method thereof.
  • a source driver for driving a source line (video signal line) of a liquid crystal display device is mounted as an IC (Integrated Circuit) chip on the periphery of a substrate constituting the liquid crystal panel.
  • IC Integrated Circuit
  • a liquid crystal display device provided with this monolithic source driver (hereinafter referred to as a “source driver monolithic liquid crystal display device”) is disclosed in, for example, Patent Document 1.
  • a-Si TFT a thin film transistor (hereinafter referred to as “a-Si TFT”) using amorphous silicon (a-Si) as a semiconductor layer has been conventionally employed as a driving element.
  • Patent Document 2 discloses a driving method of a display device in which a rest period T2 in which all gate lines are in a non-scanning state is provided after a scanning period T1 in which gate lines are scanned.
  • this idle period T2 no clock signal or the like is given to the gate driver.
  • the driving frequency of the gate line as a whole becomes about 30 Hz. For this reason, power consumption can be reduced.
  • an object of the present invention is to provide a display device in which a display unit and a video signal line driving circuit are integrally formed and a driving method thereof, with reduced power consumption.
  • a first aspect of the present invention is a display device, A plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and a display unit for displaying an image;
  • a video signal line driving circuit formed integrally with the display unit for driving the plurality of video signal lines;
  • a display control circuit for providing the video signal line driving circuit with a clock signal that periodically repeats an on level and an off level, and one or more predetermined number of video signals corresponding to an image to be displayed on the display unit;
  • the video signal line driving circuit includes: A shift register that sequentially turns on a plurality of output signals based on the clock signal; A plurality of sampling blocks each provided with the plurality of output signals, Each sampling block applies the predetermined number of video signals to the predetermined number of video signal lines based on the output signal received by the sampling block, The frequency of the clock signal in the idle period is lower than the frequency of the clock signal in the scanning period.
  • An amplitude of the clock signal in the pause period is smaller than an amplitude of the clock signal in the scanning period.
  • the pause period is longer than the scanning period.
  • each sampling block the output signal received by the sampling block is supplied to a control terminal, one of the predetermined number of video signals is supplied to a first conduction terminal, and one of the plurality of video signal lines It has one or more switching elements to which the second conduction terminal is connected.
  • Each sampling block has a plurality of the switching elements.
  • a sixth aspect of the present invention is the fifth aspect of the present invention,
  • the display unit displays a color image based on a plurality of primary colors;
  • the predetermined number of video signals respectively corresponding to the plurality of primary colors;
  • the number of the plurality of switching elements in each sampling block is the same number as the plurality of primary colors,
  • the display control circuit supplies the predetermined number of video signals different from each other to the first conduction terminals of the plurality of switching elements in each sampling block.
  • the display unit displays a color image based on a plurality of primary colors;
  • the number of the plurality of switching elements in each sampling block is an integer multiple of the plurality of primary colors;
  • the display control circuit has the predetermined number of images on the first conduction terminal of the switching element in which the second conduction terminal is connected to the video signal lines adjacent to each other among the plurality of switching elements in each sampling block. Video signals corresponding to different primary colors of the signals are respectively provided.
  • the video signal line driving circuit includes: A first video signal line driving circuit located on one side with respect to the display unit; And a second video signal line driving circuit positioned on the other side of the display unit.
  • the video signal line driver circuit is realized using a thin film transistor in which a semiconductor layer is formed of an oxide semiconductor.
  • the video signal line driving circuit is realized by using a thin film transistor in which a semiconductor layer is formed of amorphous silicon.
  • An eleventh aspect of the present invention includes a plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, a display unit for displaying an image, and an on level and an off level. And a display control circuit that outputs a predetermined number of video signals corresponding to an image to be displayed on the display unit, and a display control circuit that is formed integrally with the display unit, and that is based on the clock signal.
  • Video signal line driving circuit including a shift register for sequentially turning on the output signals of the plurality of output signals, and a plurality of sampling blocks to which the plurality of output signals are respectively applied, and scanning signal lines for driving the plurality of scanning signal lines
  • a driving method of a display device comprising a driving circuit, A scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are in a non-selected state alternate with a frame period that includes the scanning period and the pause period as a cycle.
  • a twelfth aspect of the present invention is the eleventh aspect of the present invention, An amplitude of the clock signal in the pause period is smaller than an amplitude of the clock signal in the scanning period.
  • a thirteenth aspect of the present invention is the eleventh aspect of the present invention,
  • the pause period is longer than the scanning period.
  • one frame period includes the scanning period and the pause period.
  • the frequency of the clock signal during this idle period is lower than the frequency of the clock signal during the scanning period. For this reason, the drive frequency of the selection circuit in the entire one frame period is reduced. Thereby, power consumption is reduced.
  • the display portion and the video signal line driving circuit are integrally formed, the frame area is reduced and the cost of the video signal line driving circuit is reduced.
  • the amplitude of the clock signal in the pause period is smaller than the amplitude of the clock signal in the scanning period. For this reason, further reduction in power consumption can be achieved.
  • the pause period becomes longer than the scanning period. For this reason, further reduction in power consumption can be achieved.
  • a sampling block can be realized by one or more switching elements.
  • a video signal is given to the switching element in the sampling block to which the output signal is given at the timing when the output signal of the shift register becomes high level based on the clock signal. For this reason, the influence of the noise etc. which a video signal line receives in an idle period is reduced. Thereby, the fall of display quality can be suppressed.
  • the frequency of the clock signal in the idle period is lower than that in the scanning period, the load applied to the switching element is reduced. Therefore, the threshold fluctuation in the switching element is reduced, so that a decrease in reliability of the switching element can be suppressed.
  • sequential driving can be performed in which video signals are simultaneously applied to a plurality of source lines.
  • the same effect as in the fifth aspect can be achieved.
  • a display device that displays an image based on a plurality of primary colors
  • video signals for an integral multiple of pixels composed of a plurality of primary colors are written at a time.
  • a sufficient pause period can be secured, or a video signal writing time can be secured sufficiently.
  • the number of sampling blocks can be reduced, the number of shift register stages can be reduced.
  • the number of stages of the video signal line driving circuit is halved. This doubles the layout pitch in the direction in which the scanning signal lines extend. Thereby, for example, high definition of the display unit can be achieved.
  • a video signal line driving circuit is realized using a thin film transistor in which a semiconductor layer is formed of an oxide semiconductor. Since the leakage current of the thin film transistor is sufficiently small, the frequency of the clock signal during the idle period can be further reduced. For this reason, further reduction in power consumption can be achieved. In addition, since the on-state current of the thin film transistor in which the semiconductor layer is formed using an oxide semiconductor is sufficiently large, the size of the thin film transistor can be sufficiently reduced. Thereby, further narrowing of the frame can be achieved.
  • a video signal line driving circuit is realized using a thin film transistor in which a semiconductor layer is formed of amorphous silicon. For this reason, further cost reduction can be achieved.
  • FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention. It is a block diagram for demonstrating the structure of the source driver in the said 1st Embodiment. It is a block diagram which shows the structure of the shift register in the said 1st Embodiment. It is a signal waveform diagram for demonstrating operation
  • the gate terminal of the thin film transistor corresponds to the control terminal
  • the drain terminal corresponds to the first conduction terminal
  • the source terminal corresponds to the second conduction terminal.
  • FIG. 1 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to a first embodiment of the present invention.
  • the liquid crystal display device includes a power source 100, a DC / DC converter 110, a display control circuit 200, a source driver (video signal line driving circuit) 300, a gate driver (scanning signal line driving circuit) 400, a common electrode driving circuit 500, and a display unit. 600.
  • the source driver 300 is formed on the liquid crystal display panel 700 including the display portion 600 using amorphous silicon, polycrystalline silicon, microcrystalline silicon, an oxide semiconductor (for example, IGZO), or the like. That is, in the liquid crystal display device according to this embodiment, the source driver 300 and the display unit 600 are formed on the same substrate (an array substrate that is one of the two substrates constituting the liquid crystal display panel). This is a source driver monolithic liquid crystal display device.
  • the gate driver 400 may also be formed over the liquid crystal display panel 700 using amorphous silicon, polycrystalline silicon, microcrystalline silicon, an oxide semiconductor, or the like. Specific implementation examples using these amorphous silicon and IGZO will be described later.
  • the display unit 600 includes n source lines (video signal lines) SL1 to SLn, m gate lines (scanning signal lines) GL1 to GLm, source lines SL1 to SLn, and gate lines GL1 to GLm.
  • M ⁇ n pixel forming portions provided corresponding to the respective intersections are formed.
  • the m ⁇ n pixel forming portions are arranged in a matrix to constitute a pixel array.
  • Each pixel forming portion includes a pixel thin film transistor 80 which is a switching element having a gate terminal connected to a gate line passing through a corresponding intersection and a source terminal connected to a source line passing through the intersection, and the pixel thin film transistor 80
  • a pixel electrode connected to the drain terminal, a common electrode Ec which is a counter electrode provided in common to the plurality of pixel formation portions, and a pixel electrode provided in common to the plurality of pixel formation portions.
  • the liquid crystal layer is sandwiched between the electrode Ec.
  • a pixel capacitor Cp is constituted by a liquid crystal capacitor formed by the pixel electrode and the common electrode Ec.
  • an auxiliary capacitor is provided in parallel with the liquid crystal capacitor in order to reliably hold the voltage in the pixel capacitor Cp.
  • the auxiliary capacitor is not directly related to the present invention, its description and illustration are omitted.
  • the pixel forming portion is configured as a set of three pixel forming portions corresponding to R, G, and B, respectively.
  • One pixel is formed by this one set.
  • the pixel formation portions corresponding to R, G, and B are referred to as “R pixel formation portion”, “G pixel formation portion”, and “B pixel formation portion”, respectively.
  • the power supply 100 supplies a predetermined power supply voltage to the DC / DC converter 110, the display control circuit 200, and the common electrode drive circuit 500.
  • the DC / DC converter 110 generates a predetermined DC voltage for operating the source driver 300 and the gate driver 400 from the power supply voltage and supplies it to the source driver 300 and the gate driver 400.
  • the common electrode drive circuit 500 gives a predetermined potential Vcom to the common electrode Ec.
  • the display control circuit 200 receives an image signal DAT and a timing signal group TG such as a horizontal synchronization signal and a vertical synchronization signal sent from the outside, and receives a video signal Vid and a source start pulse signal for controlling image display on the display unit 600.
  • the SSP, the source clock signal SCK, the gate start pulse signal GSP, and the gate clock signal GCK are output.
  • the high level potential of the source clock signal SCK is Vdd potential
  • the low level potential is Vss potential.
  • the source clock signal SCK is composed of two-phase source clock signals SCK1 and SCK2.
  • the source clock signal SCK1 is referred to as a “first source clock signal”
  • the source clock signal SCK2 is referred to as a “second source clock signal”.
  • the period from the time when each of the first source clock signal SCK1 and the second source clock signal SCK2 changes from the low level potential to the high level potential until the time when the high level potential changes to the low level potential is referred to as the “sampling period”.
  • the first source clock signal SCK1 and the second source clock signal SCK2 are out of phase with each other by one sampling period, and both are at a high level potential (Vdd potential) only for one sampling period among the two sampling periods (however, , Except for a rest period T2 described later).
  • the source driver 300 receives the video signal Vid, the source start pulse signal SSP, and the source clock signal SCK output from the display control circuit 200.
  • the source driver 300 supplies the received video signal Vid to the source lines SL1 to SLn at a predetermined timing.
  • This video signal Vid includes three video signals Vidr, Vidg, and Vidb.
  • the video signal Vidr is referred to as “R video signal”
  • the video signal Vidg is referred to as “G video signal”
  • the video signal Vidb is referred to as “B video signal”.
  • the R video signal Vidr, the G video signal Vidg, and the B video signal Vidb correspond to the R pixel forming unit, the G pixel forming unit, and the B pixel forming unit, respectively.
  • the source driver 300 in this embodiment performs so-called dot sequential driving. A detailed description of this source driver will be described later.
  • the gate driver 400 Based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200, the gate driver 400 supplies the high-level potential scanning signals GS (1) to GS (m) to the gate lines GL1 to GLm, respectively. Is repeated with one frame period as a cycle.
  • a period (one horizontal scanning period) in which a high level potential is applied to each gate line and the gate line is in a selected state is referred to as a “scanning selection period”.
  • a period during which the gate line GLi is in a selected state one horizontal scanning period
  • one frame period includes a scanning period T1 and a pause period T2 provided after the scanning period T1.
  • the gate driver 400 sequentially sets the scanning signals GS (1) to GS (m) to the high level potential based on the gate clock signal GCK.
  • the gate driver 400 sets the m gate lines GL1 to GLm (scanning signals GS (1) to GS (m)) to a low level potential.
  • the video signals are applied to the source lines SL1 to SLn, and the scanning signals GS (1) to GS (m) are applied to the gate lines GL1 to GLm, respectively.
  • An image based on DAT is displayed on the display unit 600.
  • FIG. 2 is a block diagram showing the configuration of the source driver 300 in this embodiment. As shown in FIG. 2, the source driver 300 includes a shift register 310 and a sampling circuit 320.
  • the shift register 310 receives the source start pulse signal SSP and the source clock signal SCK output from the display control circuit 200.
  • the shift register 310 sequentially transfers pulses included in the source start pulse signal SSP from the input end to the output end based on the source start pulse signal SSP and the source clock signal SCK.
  • the selection signals SEL (1) to SEL (k) which are output signals of the shift register 310, sequentially become a high level potential. These selection signals SEL (1) to SEL (k) are applied to the sampling circuit 320.
  • the sampling circuit 320 receives the selection signals SEL (1) to (k) output from the shift register 310 and the video signal Vid output from the display control circuit 200.
  • the sampling circuit 320 supplies the video signal Vid to the source lines SL1 to SLn at the timing when these selection signals SEL (1) to (k) become the high level potential.
  • FIG. 3 is a block diagram showing a configuration of the shift register 310 in the present embodiment.
  • the shift register 310 includes k bistable circuits 30 (1) to 30 (k) and one dummy bistable circuit 30 (k + 1).
  • the k + 1th stage may be referred to as a “dummy stage”.
  • Each bistable circuit is in one of two states (first state and second state) at each time point, and a signal indicating the state (hereinafter referred to as a “state signal”). Output.
  • a bistable circuit if the bistable circuit is in the first state, a high-level (on-level) potential state signal is output from the bistable circuit, and the bistable circuit is in the second state. Then, a state signal having a low level (off level) potential is output from the bistable circuit.
  • This state signal corresponds to the selection signal described above. That is, the state signals of the bistable circuits 30 (1) to 30 (k) correspond to the selection signals SEL (1) to SEL (k), respectively.
  • Each bistable circuit has an input terminal for receiving a clock signal CK1 (hereinafter referred to as “first clock signal”), an input terminal for receiving a clock signal CK2 (hereinafter referred to as “second clock signal”), An input terminal (not shown) for receiving a DC power supply potential Vss (the magnitude of this potential is also referred to as the “Vss potential”), an input terminal for receiving a set signal S, and an input for receiving a reset signal R A terminal and an output terminal for outputting a status signal Z are provided.
  • the shift register 310 is supplied with the two-phase first source clock signal SCK1 and second source clock signal SCK2 as the source clock signal SCK as described above.
  • this invention is not limited to this, It is good also as an aspect using the source clock signal of 3 phases or more.
  • the signals given to the input terminals of each stage (each bistable circuit) of the shift register 310 are as follows. That is, the first source clock signal SCK1 is provided as the first clock signal CK1, and the second source clock signal SCK2 is provided as the second clock signal CK2. In the even-numbered stage, the first source clock signal SCK1 is supplied as the second clock signal CK2, and the second source clock signal SCK2 is supplied as the first clock signal CK1. Further, a low level DC power supply potential Vss is commonly applied to each stage by means not shown.
  • the status signal Z output from the previous stage is given as the set signal S, and the status signal Z outputted from the next stage is given as the reset signal R.
  • the source start pulse signal SSP is given as the set signal S to the first stage (frontmost stage) 30 (1).
  • the source start pulse signal SSP is a signal that becomes a high level potential in the first sampling period in each scanning selection period.
  • a state signal output from the dummy stage 30 (k + 1) is given as a reset signal R to the k-th stage (last stage) 30 (k).
  • the dummy stage 30 (k + 1) is given the state signal Z output from the k-th stage 30 (k) as the set signal S, and its own state signal Z is given as the reset signal R.
  • the period in which the state signal Z of the dummy stage 30 (k + 1) is at the high level potential is shorter than the period in which the state signal Z of the other stage is at the high level potential.
  • the source end pulse signal SEP may be given as the reset signal R to the k-th stage 30 (k).
  • the source end pulse signal SEP is a signal that becomes a high level potential in one sampling period after the end of the k-th scanning selection period.
  • the source start pulse signal SSP as the set signal S is supplied to the first stage 30 (1) of the shift register 310, based on the first source clock signal SCK1 and the second source clock signal SCK2.
  • the pulses included in the source start pulse signal SSP (this pulse is included in the status signal Z output from each stage) are sequentially transferred from the first stage 30 (1) to the kth stage 30 (k).
  • the state signals Z output from the first stage 30 (1) to the kth stage 30 (k) are sequentially set to the high level potential.
  • the state signals Z output from the first stages 30 (1) to 30 (k) are supplied to the sampling circuit 320 as selection signals SEL (1) to SEL (k). As described above, as shown in FIG.
  • a selection signal that sequentially becomes a high level potential is supplied to the sampling circuit 320 for each sampling period.
  • a period during which each selection signal is at a high level potential is referred to as a “sampling selection period”.
  • a period during which the selection signal SEL (j) is at a high level is referred to as a “jth sampling selection period”.
  • FIG. 5 is a circuit diagram showing a configuration of each bistable circuit in the present embodiment.
  • the bistable circuit includes four thin film transistors (switching elements) M1 to M4, a capacitor C1, four input terminals 31 to 34, an input terminal for a low-level DC power supply potential Vss, and An output terminal 39 is used.
  • the input terminal that receives the first clock signal CK1 is denoted by reference numeral 31
  • the input terminal that receives the second clock signal CK2 is denoted by reference numeral 32
  • the input terminal that receives the set signal S is denoted by reference numeral 33.
  • the input terminal that receives the reset signal R is denoted by reference numeral 34.
  • reference numeral 39 is attached to an output terminal for outputting the status signal Z.
  • the bistable circuit of the shift register 310 is not limited to the configuration of the bistable circuit in the present embodiment, and bistable circuits having various configurations can be employed.
  • the gate terminal of the thin film transistor M1, the source terminal of the thin film transistor M3, the drain terminal of the thin film transistor M4, and one end of the capacitor C1 are connected to each other.
  • a connection point (wiring) where these are connected to each other is referred to as a “first node” for convenience.
  • the first node is denoted by reference numeral N1.
  • the gate terminal is connected to the first node N1, the drain terminal is connected to the input terminal 31, and the source terminal is connected to the output terminal 39.
  • the gate terminal is connected to the input terminal 32, the drain terminal is connected to the output terminal 39, and the source terminal is connected to the input terminal for the DC power supply potential Vss.
  • the gate terminal and the drain terminal are connected to the input terminal 33 (that is, diode connection), and the source terminal is connected to the first node N1.
  • the thin film transistor M4 has a gate terminal connected to the input terminal 34, a drain terminal connected to the first node N1, and a source terminal connected to the input terminal for the DC power supply potential Vss.
  • the capacitor C1 has one end connected to the first node N1 and the other end connected to the output terminal 39.
  • the thin film transistor M1 applies the potential of the first clock signal CK to the output terminal 39 when the potential of the first node N1 is at a high level.
  • the thin film transistor M2 changes the potential of the output terminal 39 toward the Vss potential when the potential of the second clock signal CK2 is at a high level.
  • the thin film transistor M3 changes the potential of the first node N1 toward the high level when the potential of the set signal S is at the high level.
  • the thin film transistor M4 changes the potential of the first node N1 toward the Vss potential when the potential of the reset signal R is at a high level.
  • the capacitor C1 functions as an auxiliary capacitor when the first node N1 is bootstrapped.
  • FIG. 6 is a signal waveform diagram for explaining the operation in the scanning period T1 among the operations of the bistable circuit in the present embodiment. Since the operation of other bistable circuits is the same, the description thereof is omitted.
  • this bistable circuit will be described as an odd-numbered stage. In the odd-numbered stages, the first source clock signal SCK1 and the second source clock signal SCK2 correspond to the first clock signal CK1 and the second clock signal CK2, respectively.
  • a period from time t1 to time t2 in FIG. 6 corresponds to a sampling selection period.
  • one sampling period immediately before the sampling selection period is referred to as a “set period”, and one sampling period immediately after the sampling selection period is referred to as a “reset period”.
  • a period other than the selection period, the set period, and the reset period in the scanning period is referred to as a “normal operation period”.
  • the potential of the set signal S changes from low level to high level. Since the thin film transistor M3 is diode-connected as shown in FIG. 5, when the potential of the set signal S goes high, the thin film transistor M3 is turned on and the capacitor C1 is charged (here, precharged). As a result, the potential of the first node N1 changes from the low level to the high level, and the thin film transistor M1 is turned on. However, in the set period, since the potential of the first source clock signal SCK1 (first clock signal CK1) is at a low level, the potential of the state signal Z is maintained at a low level.
  • the set signal S changes from high level to low level.
  • the thin film transistor M3 is turned off.
  • the first node N1 is in a floating state.
  • the potential of the first source clock signal SCK1 changes from the low level to the high level. Since the thin film transistor M1 is in an on state and has a gate capacitance, the potential of the first node N1 increases as the potential of the input terminal 31 increases (the first node N1 is bootstrapped).
  • the capacitor C1 works to promote the potential rise of the first node N1.
  • the gate potential of the thin film transistor M1 becomes sufficiently high, so that the potential of the state signal Z rises to the high level (Vdd potential) of the first source clock signal SCK1.
  • the potential of the first source clock signal SCK1 changes from high level to low level. Since the thin film transistor M1 is in the on state at time t2, the potential of the state signal Z decreases as the potential of the input terminal 31 decreases. As the potential of the state signal Z decreases in this way, the potential of the first node N1 also decreases via the capacitor C1. In the reset period, the reset signal R changes from a low level to a high level. For this reason, the thin film transistor M4 is turned on. As a result, during the reset period, the potential of the first node N1 is reliably lowered to a low level.
  • the second source clock signal SCK2 (second clock signal CK2) changes from the low level to the high level. For this reason, since the thin film transistor M2 is turned on, the potential of the state signal Z is reliably lowered to a low level.
  • the potential of the second source clock signal SCK2 repeats a high level and a low level every horizontal scanning period, so that the thin film transistor M2 is turned on every horizontal scanning period. For this reason, the potential of the state signal Z can be maintained at a low level.
  • each cycle of the first source clock signal SCK1 and the second source clock signal SCK2 in the scanning period T1 (hereinafter referred to as “scanning period cycle”) is represented by a reference tck1.
  • the respective frequencies of the first gate clock signal GCK1 and the second gate clock signal GCK2 in the scanning period T1 (hereinafter referred to as “scanning period frequency”) are denoted by reference numeral fck1.
  • the respective amplitudes of the first source clock signal SCK1 and the second source clock signal SCK2 in the scanning period T1 (hereinafter referred to as “scanning period amplitude”) are represented by reference sign Vck1.
  • FIG. 7 is a circuit diagram for explaining the configuration of the sampling circuit 320 in the present embodiment.
  • the sampling circuit 320 includes k sampling blocks 40 (1) to 40 (k).
  • the display unit 600 is formed with a pixel matrix of m rows ⁇ n columns, and the sampling blocks are provided so as to correspond to the columns of these pixel matrices in a three-to-one correspondence.
  • the source lines SL1 to SLn are grouped into source line groups SG1 to SGk in units of three.
  • the source line set SGj includes three source lines SL3j-2 to SL3j. These source line sets SG1 to SGk correspond to the sampling blocks 40 (1) to 40 (k), respectively.
  • a source line corresponding to R hereinafter referred to as “R source line” in the source line set SGj is represented by reference sign SLrj
  • G source line a source line corresponding to G
  • a source line corresponding to B (hereinafter referred to as a “B source line”) is represented by a symbol SLbj.
  • the G pixel formation portion provided corresponding to is represented by reference symbol gij
  • the B pixel formation portion provided corresponding to the intersection of the B source line SLbj and the gate line GLi is represented by reference symbol bij.
  • each sampling block is composed of three thin film transistors.
  • the three thin film transistors in the sampling block 40 (j) are referred to as “R thin film transistor 41r (j)”, “G thin film transistor 41g (j)”, and “B thin film transistor 41b (j)”, respectively.
  • a selection signal corresponding to the sampling block including the R thin film transistor is given to the gate terminal, an R video signal Vidr is given to the source terminal, and the R thin film transistor is given to the drain terminal.
  • R source lines in a source line set corresponding to the sampling block to be included are connected.
  • a gate terminal receives a selection signal corresponding to the sampling block including the G thin film transistor, a source terminal receives a G video signal Vidg, and a drain terminal receives the G thin film transistor.
  • G source lines in the source line set corresponding to the sampling block to be included are connected.
  • the gate terminal is supplied with a selection signal corresponding to the sampling block including the B thin film transistor, the source terminal is supplied with the B video signal Vidb, and the drain terminal is supplied with the B thin film transistor.
  • a source line for B in the source line set corresponding to the included sampling block is connected.
  • the source driver 300 including such a sampling circuit 320 realizes dot-sequential driving in which the video signal Vid is sequentially supplied to the source line in units of picture elements composed of R / G / B pixels in one horizontal scanning period. This operation will be described in detail later.
  • one frame period is composed of the scanning period T1 and the pause period T2 provided after the scanning period T1.
  • the operation of the liquid crystal display device according to the present embodiment will be described separately for the operation in the scanning period T1 and the operation in the pause period T2.
  • FIG. 8 is a signal waveform diagram for explaining the operation in the scanning period T1 of the liquid crystal display device according to this embodiment.
  • the scanning signals GS (1) to GS (m) are sequentially selected based on the gate clock signal GCK.
  • video signals are sequentially applied to the source line in block units (source group units).
  • FIG. 8 shows various signal waveforms related to driving of the source driver 300 in the first scan selection period. The operation in the scan selection period other than the first scan selection period is the same, and the description thereof is omitted.
  • the source start pulse signal SSP becomes a high level potential in the first sampling period.
  • the selection signals SEL (1) to SEL (k) sequentially become a high level potential.
  • the scanning period cycle tck1 is two sampling periods.
  • the G video signal Vidg has a potential corresponding to the G pixel forming portion gij in the jth sampling period in the i-th scanning selection period.
  • the B video signal Vidb has a potential corresponding to the B pixel formation portion bij in the jth sampling period in the i-th scanning selection period.
  • the polarity of each video signal is inverted every sampling period, the polarities of the video signals applied to the output signal lines adjacent to each other are inverted, and every frame period.
  • the polarity inversion drive is performed by inverting the polarity of each video signal, the present invention is not limited to this.
  • the selection signal SEL (1) is at a high level potential in the first sampling period, the R thin film transistor 41r (1), the G thin film transistor 41g (1), and the B use in the sampling block 40 (1) shown in FIG.
  • the thin film transistor 41b (1) is turned on. For this reason, the R video signal Vidr having a potential corresponding to the R pixel formation portion r11 is given to the R source line SLr1, and the G video signal Vidg having a potential corresponding to the G pixel formation portion g11 is obtained.
  • the B video signal Vidb which is given to the G source line SLg1 and has a potential corresponding to the B pixel formation portion b11, is given to the B source line SLb1.
  • the potentials of the R source line SLr1, the G source line SLg1, and the B source line SLb1 are positive, negative, and negative, respectively, from the potential (Vcom potential) in the preceding pause period T2. Change to positive polarity.
  • the potentials of the R source line SLr1, the G source line SLg1, and the B source line SLb1 are written to the R pixel forming portion r11, the G pixel forming portion g11, and the B pixel forming portion b11, respectively. Since the operation in the second to m sampling periods is the same, the description thereof is omitted.
  • the operation of one scanning selection period is realized by repeating the one sampling period as described above, and the operation of the scanning period T1 is realized by repeating this one scanning selection period.
  • FIG. 9 is a signal waveform diagram for explaining the operation in the pause period T2 of the liquid crystal display device according to the present embodiment.
  • the pause period T2 is longer than the scanning period T1.
  • the present invention is not limited to this, and the pause period T2 may be shorter than the scanning period T1.
  • X horizontal scanning period a period corresponding to the length of the first X scanning selection period (one horizontal scanning period) in the pause period T ⁇ b> 2.
  • the signal waveform is shown.
  • X is, for example, an integer of 2 or more, but the present invention is not limited to this.
  • the operation in the other X horizontal scanning periods is the same, and the description thereof is omitted.
  • the first source clock signal SCK1 and the second source clock signal SCK2 are at a high level potential in one sampling period with a period longer than the scanning period period tck1.
  • pause period cycle each cycle of the first source clock signal SCK1 and the second source clock signal SCK2 in the pause period T2 (hereinafter referred to as “pause period cycle”) is denoted by reference symbol tck2.
  • pause period frequencies the respective frequencies (hereinafter referred to as “pause period frequencies”) of the first source clock signal SCK1 and the second source clock signal SCK2 in the idle period T2 are denoted by a symbol fck2.
  • pause period amplitude the respective amplitudes (hereinafter referred to as “pause period amplitude”) of the first source clock signal SCK1 and the second source clock signal SCK2 in the pause period T2 are represented by reference sign Vck2.
  • the idle period cycle tck2 is longer than the scanning period cycle tck1. That is, the idle period frequency fck2 is lower than the scanning period frequency fck1.
  • the scanning period frequency fck1 is an integral multiple of the idle period frequency fck2.
  • the display control circuit 200 and the like can have a simple configuration.
  • the scanning period frequency fck1 is at least twice the idle period frequency fck2.
  • the idle period frequency fck2 is 1 ⁇ 2 times or less of the scanning period frequency fck1.
  • the power consumption required for driving the source driver 300 can be sufficiently reduced.
  • Such control of the frequency (cycle) of the source clock signal SCK is performed in the display control circuit 200, for example.
  • the idle period amplitude Vck2 and the scanning period amplitude Vck1 are the same.
  • the R video signal Vidr, the G video signal Vidg, and the B video signal Vidb are at the Vcom potential.
  • the potential is not limited to the Vcom potential, and may be another fixed potential.
  • the scanning signals GS (1) to GS (m) do not become a high level potential during the pause period T2, the video signal is written to the R pixel forming portion rij, the G pixel forming portion gij, and the B pixel forming portion bij. Absent.
  • the source start pulse signal SSP becomes a high level potential in the first sampling period in the X horizontal scanning period. Therefore, the selection signals SEL (1) to SEL (k) are sequentially set to the high level potential on the basis of the first source clock signal SCK1 and the second source clock signal SCK2 having the idle period frequency fck2 lower than the scanning period frequency fck1. Become.
  • FIG. 10 is a signal waveform diagram for explaining the operation of the bistable circuit in the present embodiment, in particular, the operation in the idle period T2. Since the operation of other bistable circuits is the same, the description thereof is omitted.
  • one horizontal scanning period in which the set signal S is at a high level potential is referred to as a “set period”, and a period from the end of the set period to the start of the sampling selection period is “selected”.
  • the period from the end of the sampling selection period to the time when the reset signal R changes to the high level potential is called the “waiting period”, and the period during which the reset signal R is at the high level potential Period.
  • a period other than the sampling selection period, the set period, the selection waiting period, the reset waiting period, and the reset period in the suspension period T2 is referred to as a “normal operation period”.
  • the operation in the set period (time points s0 to s1) is the same as the operation in the set period in the scanning period T1, and thus description thereof is omitted.
  • the potential of the set signal S changes from high level to low level, so that the thin film transistor M3 is turned off (see FIG. 5). For this reason, the first node N1 is in a floating state. Further, the first source clock signal SCK1 remains at a low level potential. For this reason, in the selection waiting period, the potential of the first node N1 in the set period is maintained. Note that since the potential of the second source clock signal SCK2 changes to a low level, the thin film transistor M2 is turned off.
  • the potential of the first source clock signal SCK1 changes from the high level to the low level, so that the potential of the first node N1 is influenced by the parasitic capacitance between the gate and the drain of the thin film transistor M1. Descends. This amount of decrease in potential corresponds to the amount of increase in potential due to the above-described boost strap. For this reason, the thin film transistor M1 is not turned off. Therefore, as described above, when the potential of the first source clock signal SCK1 changes from the high level to the low level, the potential of the state signal Z changes to the low level. Further, after that, the potential of the first source clock signal SCK1 is maintained at the low level, so that the potential of the state signal Z is maintained at the low level.
  • the selection signals SEL (1) to SEL (k) are sequentially set to the high level potential in a period longer than the period in the scanning period T1. Therefore, the R thin film transistor, the G thin film transistor, and the B thin film transistor in each of the sampling blocks 40 (1) to 40 (k) are sequentially turned on.
  • the R thin film transistor is turned on, the R video signal Vidr having the Vcom potential is applied to the R source line.
  • the G thin film transistor is turned on, the G video signal Vidg at the Vcom potential is applied to the G source line.
  • the B thin film transistor is turned on, the B video signal Vidb at the Vcom potential is applied to the B source line.
  • the scanning signals GS (1) to GS (m) do not become high level potentials in the idle period T2, and therefore the potentials of these R source line, G source line, and B source line are R respectively. It is not written in the pixel formation portion, the G pixel formation portion, and the B pixel formation portion.
  • the source line is in a floating state. For this reason, the source line is likely to be affected by noise or the like in the pause period T2. Since there is a parasitic capacitance between the source line and the pixel electrode, and the pixel electrode is also in a floating state, noise in the source line also affects the pixel potential due to capacitive coupling. As a result, the display quality may be degraded.
  • the selection signals SEL (1) to SEL (k) are generated by the shift register 310 operating on the first source clock signal SCK1 and the second source clock signal SCK2 in the pause period T2. Sequentially becomes a high level potential.
  • the Vcom potential is applied to the source line in the source line group corresponding to each selection signal at the high level.
  • the influence of noise and the like received by the source lines SL1 to SLm is reduced by the source lines SL1 to SLm being in the floating state in the pause period T2.
  • each thin film transistor in the sampling circuit 320 is kept on during the rest period T2 and each video signal is set to the Vcom potential, it is necessary to continuously apply a high level potential to the gate terminal of the thin film transistor. Since the gate bias stress is applied to the thin film transistor for a long time, the threshold fluctuation in the thin film transistor is increased. As a result, the thin film transistor is lowered.
  • the shift register 310 operates based on the first source clock signal SCK1 and the second source clock signal SCK2 in the pause period T2, so that the selection signal SEL ( 1) to SEL (k) sequentially become high level potentials.
  • the high level potential is applied to the gate terminal of the thin film transistor in the sampling circuit 320 only in one sampling period in each X horizontal scanning period.
  • a-Si or an oxide semiconductor can be used for the semiconductor layer of each thin film transistor in the sampling circuit 320 in the present embodiment.
  • the oxide semiconductor typically, InGaZnO x (hereinafter referred to as “IGZO”), which is an oxide semiconductor mainly containing indium, gallium, zinc, and oxygen, is used. It is not limited. For example, any oxide semiconductor containing at least one of indium, gallium, zinc, copper, silicon, tin, aluminum, calcium, germanium, and lead may be used.
  • FIG. 11 is a graph showing drain current-gate voltage characteristics of a TFT using a-Si TFT and IGZO as a semiconductor layer (hereinafter referred to as “IGZOTFT”).
  • the horizontal axis represents the gate voltage Vg
  • the vertical axis represents the drain current Ids.
  • the leakage current of the IGZOTFT is 1/1000 or less of the leakage current of the a-Si TFT
  • the on-current of the IGZOTFT is about 20 times the on-current of the a-Si TFT.
  • the IGZOTFT has a small leakage current as described above, when the IGZOTFT is used as each thin film transistor in the sampling circuit 320 in the present embodiment, the source driver 300 (sampling circuit 320 is used even when the a-Si TFT is used as this thin film transistor. ) Driving power can be reduced (1/100 or less).
  • the IGZOTFT has a large on-state current as described above, when the IGZOTFT is used, the size of the TFT can be reduced to about 1/20 compared to the case where the a-Si TFT is used.
  • this embodiment can be realized at a lower cost than when an IGZO TFT is used.
  • the pause period T2 is provided after the scanning period T1 within one frame period. Since the idle period frequency fck2 is lower than the scanning period frequency fck1, the driving frequency of the entire source frame of the source driver 300 is reduced. For this reason, the power consumption required for driving the source driver 300 is reduced. Further, since the source driver 300 is monolithically formed, the frame area of the liquid crystal display panel 700 is reduced and the cost of the source driver 300 is reduced.
  • the Vcom potential is applied to the source line in the corresponding source line group at the timing when each selection signal becomes high level in the pause period T2. For this reason, since the source lines SL1 to SLm are in the floating state in the suspension period T2, the influence of noise and the like received by these source lines SL1 to SLm is reduced. Thereby, the fall of display quality can be suppressed.
  • the high level potential is applied to the gate terminal of each thin film transistor in the sampling circuit 320 only in one sampling period in each X horizontal scanning period in the pause period T2, the gate bias stress applied to the thin film transistor is reduced. . As a result, a decrease in driving capability (reliability) of each thin film transistor in the sampling circuit 320 can be suppressed.
  • the pause period T2 is provided longer than the scanning period T1, further power consumption can be achieved.
  • the leakage current of the IGZOTFT is sufficiently small, so that the idle period frequency fck2 can be further reduced. For this reason, power consumption can be reduced.
  • the TFT size can be sufficiently reduced. Thereby, further narrowing of the frame can be achieved. Note that by using the IGZOTFT as each thin film transistor in the bistable circuit, further reduction in power consumption and narrowing of the frame can be achieved.
  • the cost can be further reduced.
  • FIG. 12 is a signal waveform diagram for explaining the operation in the pause period T2 of the liquid crystal display device according to the second embodiment of the present invention. Since the present embodiment is the same as the first embodiment except for the operation during the suspension period, the description of the same portion is omitted.
  • the pause period amplitude Vck2 is smaller than the scanning period amplitude Vck1. Note that, in order to ensure that each thin film transistor in the sampling circuit 320 is turned on in the pause period T2, it is necessary to be higher than the threshold voltage of this thin film transistor. That is, the pause period amplitude Vck in this embodiment is smaller than the scanning period amplitude Vck2 and larger than the threshold voltage of each thin film transistor in the sampling circuit 320.
  • the pause period amplitude Vck2 which is the amplitude of each of the first source clock signal SCK1 and the second source clock signal SCK2 in the pause period T2, is the first source clock signal SCK1 and the second source in the scan period T1. It is smaller than the scanning period amplitude Vck1 that is the amplitude of each of the clock signals SCK2. For this reason, further reduction in power consumption can be achieved.
  • the gate bias stress applied to the R thin film transistor, the G thin film transistor, and the B thin film transistor is further reduced during the suspension period T2, the R thin film transistor, the G thin film transistor, and the B thin film transistor are further improved in reliability. Can be achieved.
  • FIG. 13 is a circuit diagram for explaining the configuration of the sampling circuit 320 according to the third embodiment of the present invention. Since this embodiment is the same as the first embodiment except for the configuration of the sampling circuit 320 and the detailed operation of the liquid crystal display device, the description of the same parts is omitted. In this embodiment, the relationship between the sampling blocks 40 (1) to 40 (k) and the source lines SL1 to SLn is different from that in the first embodiment, and sampling is performed so as to correspond to each column of the pixel matrix on a one-to-one basis. Blocks are provided.
  • the video signal Vid includes 24 video signals Vidr1 to Vidr8, Vidg1 to Vidg8, and Vidb1 to Vidb8.
  • the video signal Vidrx is referred to as “xR video signal”
  • the video signal Vidigx is referred to as “xG video signal”
  • the first to eighth R video signals Vidr1 to Vidr8 correspond to the R pixel forming unit
  • the first to 8G video signals Vidg1 to Vidg8 correspond to the G pixel forming unit
  • the first to 8B video signals Vidb1 to Vidb8 are This corresponds to the B pixel forming portion.
  • the source lines SL1 to SLn are grouped into source line groups SG1 to SGk in units of 24.
  • the source line set SGj is composed of 24 source lines SL24j-23 to SL24j.
  • These source line sets SG1 to SGk correspond to the sampling blocks 40 (1) to 40 (k), respectively.
  • eight source lines corresponding to the same color are provided in each source line group.
  • xG source lines eight G source lines in the source line set SGj
  • xB source lines eight B source lines in the source line set SGj
  • SLbj_x eight B source lines in the source line set SGj
  • an R pixel forming portion provided corresponding to the intersection of the xR source line SLrj_x and the gate line GLi is denoted by rij_x (i to m), and the intersection of the xG source line SLgj_x and the gate line GLi.
  • a G pixel forming portion provided for the xb is represented by reference symbol gij_x
  • a G pixel forming portion provided corresponding to the intersection of the xb source line SLbj_x and the gate line GLi is represented by bij_x.
  • Each sampling block is composed of 24 thin film transistors as shown in FIG.
  • the gate terminal For each xR thin film transistor, the gate terminal is supplied with a selection signal corresponding to the sampling block including the xR thin film transistor, the source terminal is supplied with the xR video signal Vidrx, and the drain terminal is supplied with the second signal.
  • the xR source line in the source line set corresponding to the sampling block including the xR thin film transistor is connected.
  • the gate terminal For each xG thin film transistor, the gate terminal is supplied with a selection signal corresponding to the sampling block including the xG thin film transistor, the source terminal is supplied with the xG video signal Vidgx, and the drain terminal is supplied with the corresponding second signal.
  • the xG source line in the source line set corresponding to the sampling block including the xG thin film transistor is connected.
  • a selection signal corresponding to the sampling block including the xB thin film transistor is given to the gate terminal, the xB video signal Vidbx is given to the source terminal, and the corresponding xth video signal Vidbx is given to the drain terminal.
  • the xB source line in the source line set corresponding to the sampling block including the xB thin film transistor is connected.
  • the source driver 300 including such a sampling circuit 320 realizes block sequential driving in which a video signal Vid is sequentially applied to a source line in block units (source group units) and a plurality of picture elements are simultaneously written in one horizontal scanning period. The This operation will be described in detail later.
  • FIG. 14 is a signal waveform diagram for explaining the operation in the scanning period T1 of the liquid crystal display device according to this embodiment.
  • the description of the common parts with the first embodiment is omitted as appropriate.
  • FIG. 14 shows various signal waveforms related to driving of the source driver 300 in the first scan selection period. The operation in the scan selection period other than the first scan selection period is the same, and the description thereof is omitted.
  • the xG video signal Vidgx has a potential corresponding to the xG pixel forming unit gij_x in the jth sampling period in the i-th scanning selection period.
  • the xB video signal Vidbx has a potential corresponding to the xB pixel formation portion bij_x in the jth sampling period in the i-th scanning selection period.
  • the selection signal SEL (1) becomes a high level potential in the first sampling period
  • the xB thin film transistor 41bx (1) is turned on.
  • the xR video signal Vidrx having a potential corresponding to the R pixel forming portion r11_x is supplied to the xR source line SLr1_x, and the xG video having a potential corresponding to the G pixel forming portion g11_x.
  • the signal Vidx is supplied to the xG source line SLg1_x, and the xB video signal Vidbx having a potential corresponding to the B pixel formation portion b11_x is supplied to the xB source line SLb1_x.
  • the potentials of the xR source line SLr1_x, the xG source line SLg1_x, and the xB source line SLb1_x change from the potential (Vcom potential) in the preceding pause period T2 to a positive polarity or a negative polarity. Change.
  • the potentials of the xR source line SLr1_x, the xG source line SLg1_x, and the xB source line SLb1_x are written to the R pixel formation portion r11_x, the G pixel formation portion g11_x, and the B pixel formation portion b11_x, respectively. Since the operation in the second to m sampling periods is the same, the description thereof is omitted.
  • the operation of one scanning selection period is realized by repeating the one sampling period as described above, and the operation of the scanning period T1 is realized by repeating this one scanning selection period.
  • FIG. 15 is a signal waveform diagram for explaining the operation in the pause period T2 of the liquid crystal display device according to the present embodiment.
  • the xR Vidrx, the xG Viggx, and the xB Vidbx are at the Vcom potential in the suspension period T2. Note that the potential is not limited to the Vcom potential, and may be another fixed potential.
  • the xR thin film transistor is turned on, the xR video signal Vidrx having the Vcom potential is applied to the xR source line.
  • the xG thin film transistor is turned on, the xG video signal Vidgx at the Vcom potential is applied to the xG source line.
  • the xB video signal Vidbx having the Vcom potential is applied to the xB source line.
  • the scanning signals GS (1) to GS (m) do not become a high level potential in the pause period T2, and therefore, the potentials of the xR source line, the xG source line, and the xB source line. Are not written in the R pixel forming portion, the G pixel forming portion, and the B pixel forming portion, respectively.
  • the number of pixel forming portions in which a video signal can be written at a time is increased as compared with the first embodiment. For this reason, it is possible to secure a sufficient rest period T2 by shortening the scanning period T1 compared to the first embodiment, or to provide the scanning period T1 having the same length as that of the first embodiment. As a result, it is possible to secure a sufficient video signal writing time for each pixel formation portion. Further, the number of stages of the shift register 310 can be reduced by reducing the number of sampling blocks.
  • FIG. 16 is a circuit diagram for explaining a configuration of a source driver 300 according to the fourth embodiment of the present invention. Since this embodiment is the same as the first embodiment except for the configuration of the source driver 300, the description of the same portion is omitted.
  • the source driver 300 in the present embodiment is divided into both sides (upper and lower sides in FIG. 16) of the display unit 600.
  • a portion of the source driver 300 that is disposed on the upper side of the display unit 600 is referred to as a “first source driver” and is denoted by reference numeral 300a.
  • a portion of the source driver 300 that is disposed below the display unit 600 is referred to as a “second source driver” and is denoted by reference numeral 300 b.
  • the shift register 310 in the present embodiment is configured separately on both sides of the display unit 600.
  • a portion of the shift register 310 that is disposed on the upper side of the display unit 600 is referred to as a “first shift register” and is denoted by reference numeral 310a.
  • a portion of the shift register 310 disposed below the display unit 600 is referred to as a “second shift register” and is denoted by reference numeral 310 b.
  • the first shift register 310a corresponds to a portion composed of an odd-stage bistable circuit in the shift register 310 in the first embodiment.
  • the second shift register 310b corresponds to a portion made up of an even number of bistable circuits in the shift register in the first embodiment.
  • the sampling circuit 320 in the present embodiment is configured separately on both sides of the display unit 600.
  • a portion of the sampling circuit 320 that is disposed on the upper side of the display unit 600 is referred to as a “first sampling circuit” and is denoted by reference numeral 320a.
  • a portion of the sampling circuit 320 disposed below the display unit 600 is referred to as a “second sampling circuit” and is denoted by reference numeral 320b.
  • the first sampling circuit 320a corresponds to a portion of the sampling circuit 320 in the first embodiment, which is composed of odd-numbered sampling blocks counted from the side where the gate driver 400 is disposed.
  • the second sampling circuit 320b corresponds to a part of the sampling circuit 320 in the first embodiment, which is composed of even-numbered sampling blocks counted from the side where the gate driver 400 is arranged.
  • the first source driver 300a includes a first shift register 310a and a first sampling circuit 320a.
  • the second source driver 300b includes a second shift register 310b and a second sampling circuit 320b.
  • the number of stages of the first source driver 300a and the second source driver 300b respectively disposed on the upper and lower sides of the display unit is approximately the number of stages of the source driver 300 in the first embodiment. Halved. For this reason, the layout pitch in the extending direction of the gate line is doubled. Thereby, for example, it becomes possible to deal with a higher-definition liquid crystal display panel.
  • the present invention is not limited to the configuration of the present embodiment, and for example, as shown in FIG. 17, the first sampling circuit 320a and the second sampling circuit 320b may share the sampling blocks 40 (1) to 40 (k). That is, in this case, the odd-numbered sampling blocks counted from the side on which the gate driver 400 is arranged are arranged on the lower side of the display unit 600 and the R thin film transistor and the B thin film transistor. And a thin film transistor for G. Further, the even-numbered sampling blocks counted from the side where the gate driver 400 is disposed include the G thin film transistor disposed on the upper side of the display unit 600, the R thin film transistor disposed on the lower side of the display unit 600, and B Thin film transistor.
  • the first source driver 300a includes the shift register 310 and the first sampling circuit 320a
  • the second source driver 300a includes the shift register 310 and the second sampling circuit 320b.
  • the number of stages of the shift register 310 arranged on each of the upper side and the lower side of the display unit is the same as the number of stages of the shift register 310 in the first embodiment, but the upper side and the lower side of the display unit.
  • the number of stages of each of the first sampling circuit 320a and the second sampling circuit 320b arranged on the side is about half of the number of stages of the sampling circuit 320 in the first embodiment. For this reason, as in the fourth embodiment, the layout pitch in the direction in which the gate lines extend can be doubled.
  • color image display using the three primary colors RGB is described, but the present invention is not limited to this.
  • color image display may be performed using four primary colors such as RGBY, or five or more primary colors.
  • Monochrome image display may be performed.
  • each set of source lines is composed of 24 source lines, but the present invention is not limited to this.
  • each source line group may be configured by source lines that are multiples of the number of primary colors.
  • the thin film transistors are all assumed to be n-channel type, but the present invention is not limited to this. The present invention can be applied even if the thin film transistor is a p-channel type.
  • the liquid crystal display device has been described as an example, but the present invention is not limited to this.
  • the present invention can also be applied to other display devices such as organic EL (Electro Luminescence) display devices.
  • organic EL Electro Luminescence
  • the above-described embodiments can be variously modified and implemented without departing from the spirit of the present invention.
  • a display device in which a display unit and a video signal line driving circuit are integrally formed with reduced power consumption and a method for controlling the video signal line driving circuit in the display device are provided.
  • the present invention can be applied to a display device in which a display unit and a video signal line driving circuit are integrally formed.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)

Abstract

La présente invention concerne un dispositif d'affichage qui diminue la consommation électrique. Il se compose d'une unité d'affichage et d'un circuit de commande de signaux d'image formés en une seule pièce. Un pilote source (300) est configuré à partir d'un registre à décalage (310) et d'un circuit d'échantillonnage (320). Le circuit d'échantillonnage (320) est configuré à partir de blocs d'échantillonnage (40(1)-40(k)). Chacun de ces blocs est configuré à partir de trois transistors à couche mince. Le registre à décalage émet des signaux de sortie (SEL(1)-SEL(k)) sur la base d'un signal d'horloge source (SCK2). Les signaux de sélection (SEL(1)-SEL(k)) sont affectés aux blocs d'échantillonnage (40(1)-40(k)). Une période de balayage (T1) est suivie d'une période d'inactivité (T2). Au cours de la période d'inactivité (T2), le registre à décalage (310) fonctionne sur la base du signal d'horloge source (SCK), en utilisant la fréquence de la période d'inactivité (fck2). La fréquence de la période d'inactivité (fck2) est inférieure à la fréquence de la période de balayage (fck1).
PCT/JP2012/068757 2011-08-02 2012-07-25 Dispositif d'affichage et méthode d'alimentation correspondante Ceased WO2013018595A1 (fr)

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WO2017033844A1 (fr) * 2015-08-27 2017-03-02 シャープ株式会社 Dispositif d'affichage et procédé de commande de source d'alimentation associé
US20200020271A1 (en) * 2018-07-13 2020-01-16 Innolux Corporation Display device
WO2022183440A1 (fr) * 2021-03-04 2022-09-09 Boe Technology Group Co., Ltd. Substrat électroluminescent, appareil d'affichage et procédé d'excitation de substrat électroluminescent
WO2022183441A1 (fr) * 2021-03-04 2022-09-09 Boe Technology Group Co., Ltd. Substrat électroluminescent, appareil d'affichage et procédé d'excitation de substrat électroluminescent
KR20240134617A (ko) * 2023-03-02 2024-09-10 삼성전자주식회사 디스플레이 장치

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