WO2013008528A1 - Pixel circuit and display device - Google Patents

Abstract

Provided are a pixel circuit and a display device that stably display images. The pixel circuit (2) comprises: a display element section (21) including a unit display element (LC); an internal node (N1) that configures part of the display element section (21) and holds the pixel data voltage applied to the display element section (21); and a switch circuit (22) having a series circuit for a first and a second transistor element (T1, T2) and which sends the source voltage applied to one end thereof to the internal node (N1) connected to the other end thereof, via the series circuit. The pixel circuit (2) has an electrical capacitance element (Cd) between the internal node (N1) and an intermediate node (N2) connecting the first and second transistor elements (T1, T2).

Description

Pixel circuit and display device

The present invention relates to a pixel circuit and a display device including the pixel circuit, and more particularly to an active matrix liquid crystal display device.

In recent years, active matrix liquid crystal display devices have become widespread. An active matrix liquid crystal display device includes a plurality of pixel circuits arranged in a row direction and a column direction (arranged in a matrix).

A pixel circuit provided in an active matrix liquid crystal display device will be described with reference to the drawings. FIG. 8 is a circuit diagram showing the structure of a conventional pixel circuit. As shown in FIG. 8, the pixel circuit 100 includes a unit liquid crystal display element lc having a liquid crystal whose orientation state is controlled according to an applied voltage, a control terminal connected to the gate line gl, and a first terminal connected to the gate line gl. A transistor (for example, TFT: Thin Film Transistor) t having a second terminal connected to the unit liquid crystal display element lc connected to the source line sl, and one end connected to a connection node n1 of the transistor t2 and the unit liquid crystal display element lc. And a capacitive element c1 whose other end is grounded.

In the pixel circuit 100 shown in FIG. 8, conduction / non-conduction between the first terminal and the second terminal of the transistor t is controlled by the voltage applied to the gate line gl. When the first terminal and the second terminal of the transistor t are made conductive, the voltage applied to the source line sl is applied to the unit liquid crystal display element lc, and the alignment state of the liquid crystal included in the unit liquid crystal display element lc is controlled. . Thereby, the polarization direction of the light transmitted through the unit liquid crystal display element lc is controlled. Then, the light that passes through the unit liquid crystal display element lc selectively passes through a polarizing plate that is separately provided according to the polarization direction, thereby displaying an image.

Also, the gate lines gl connected to the pixel circuits 100 arranged in the same row are common, and the source lines sl connected to the pixel circuits 100 arranged in the same column are also common. Therefore, for example, when the voltage applied to the source line sl is applied to the unit liquid crystal display element lc of each pixel circuit 100 arranged in a certain row, each pixel circuit arranged in the certain row. A voltage that makes the first terminal and the second terminal of the transistor t conductive is applied to the gate line gl connected in common to 100. On the other hand, a voltage that makes the first terminal and the second terminal of the transistor t non-conductive is applied to the gate line gl connected in common to the pixel circuits 100 arranged in other rows. Then, each voltage to be applied to the unit liquid crystal display element lc of the pixel circuit 100 arranged in the certain row is applied to each source line sl. These operations are repeated while switching the row of the pixel circuit 100 to which a voltage is to be applied to the unit liquid crystal display element lc.

In order for the liquid crystal display device to stably display an image by suppressing the occurrence of flicker or the like, a unit liquid crystal display element is used during a period in which the first terminal and the second terminal of the transistor t are non-conductive. It is necessary to suppress fluctuations in the voltage applied to lc (the voltage held by the connection node n1). However, the transistor t generates a leakage current when the potential difference between the first terminal and the second terminal becomes large even if the first terminal and the second terminal are non-conductive, and the voltage held by the connection node n1 This can be a problem because it can fluctuate. In particular, when the voltage applied to the source line sl sequentially changes as described above, the potential difference between the source line sl to which the first terminal of the transistor t is connected and the connection node n1 to which the second terminal of the transistor t is connected. Can be large.

Therefore, Patent Document 1 proposes a pixel circuit having a structure corresponding to the above problem. This pixel circuit will be described with reference to FIG. FIG. 9 is a circuit diagram showing the structure of a conventional pixel circuit. As shown in FIG. 9, the pixel circuit 200 includes a transistor t1 having a first terminal connected to the source line sl and a control terminal connected to the gate line gl, and a first terminal connected to the second terminal of the transistor t1. A transistor t2 whose control terminal is connected to the gate line gl, a unit liquid crystal display element lc whose one end is connected to the second terminal of the transistor t2 and whose other end is grounded, and one end of which is the transistor t2 and the unit liquid crystal. A capacitive element c1 connected to the connection node n1 of the display element lc and having the other end grounded; a capacitive element c2 having one end connected to the connection node n2 of the transistors t1 and t2 and the other end grounded; Is provided.

In the pixel circuit 200 shown in FIG. 9, by providing two transistors t1 and t2 connected in series, a change in the voltage applied to the source line sl changes the voltage applied to the unit liquid crystal display element lc (at the connection node n1). The direct influence on the held voltage is suppressed. In addition, the pixel circuit 200 includes the capacitive element c2, thereby suppressing a change in voltage held at the connection node n2.

JP-A-4-251818

In recent liquid crystal display devices, low power consumption is required. For example, in a liquid crystal display device mounted on a battery-driven device such as a mobile phone or an electronic book reader, low power consumption is particularly required in order to enable long-time use with a single charge. . Therefore, specific consideration will be given to reducing the power consumption of the liquid crystal display device including the pixel circuit 200 shown in FIG.

For example, a reduction in power consumption of a liquid crystal display device can be achieved by reducing the frame frequency (for example, lowering the frame frequency when displaying an image with little motion such as a still image), or the absolute voltage applied to the source line sl. The value is reduced (for example, after a voltage having a relatively small absolute value is applied to the unit liquid crystal display element lc via the source line sl, a predetermined voltage is applied to the other end side of the capacitive element c1, thereby the voltage held by n1 is pushed up or down, and the absolute value of the voltage held by the connection node n1 is increased).

When the former method is adopted, the fluctuation of the voltage applied to the unit liquid crystal display element lc significantly affects the displayed image. Therefore, it is necessary to accurately suppress fluctuations in the voltage held by the connection node n1 (leakage current between the first terminal and the second terminal of the transistor t2). When the latter method is employed, the voltage held by the connection node n1 can vary independently of the voltage held by the connection node n2. Then, the potential difference between the connection node n1 and the connection node n2 increases, and a leakage current between the first terminal and the second terminal of the transistor t2 is generated. As a result, the voltage applied to the unit liquid crystal display element lc (the voltage held by the connection node n1) fluctuates, which causes a problem because an image displayed on the liquid crystal display device becomes unstable.

The present invention has been made in view of the above problems, and an object thereof is to provide a pixel circuit and a display device that stably display an image.

In order to achieve the above object, the present invention provides a display element unit including a unit display element,
An internal node that forms part of the display element unit and holds a pixel data voltage applied to the display element unit;
A switch circuit having a series circuit of first and second transistor elements, and transferring a source voltage applied to one end to the internal node connected to the other end via the series circuit;
A capacitance element having one end connected to an intermediate node connecting the first and second transistor elements and the other end connected to the internal node or a node that induces a voltage variation in the internal node;
A pixel circuit is provided.

Furthermore, the pixel circuit having the above characteristics is characterized in that the other end of the capacitance element is connected to the internal node.

With this configuration, the intermediate node voltage can be effectively tracked and varied with any variation in the pixel data voltage held by the internal node.

Further, in the pixel circuit having the above characteristics, the capacitance of the electric capacitance element is equal to or more than a capacitance combining a parasitic capacitance formed between the control terminal of each of the first and second transistor elements and the intermediate node. It is preferable.

With this configuration, it is possible to make the fluctuation of the voltage held by the intermediate node 50% or less as compared with the case where no capacitance element is provided.

Furthermore, the pixel circuit having the above characteristics includes an auxiliary capacitance element having one end connected to the internal node and the other end applied with an auxiliary capacitance voltage.
Further provision is preferable.

With this configuration, the pixel data voltage can change via the auxiliary capacitance element. Therefore, the absolute value of the difference between the voltage held by the intermediate node and the pixel data voltage held by the internal node can be larger, but by providing a capacitance element, the voltage held by the intermediate node can be reduced by the internal node. It is possible to change the pixel data voltage to follow the held pixel data voltage.

Furthermore, the pixel circuit having the above characteristics further includes an auxiliary capacitance element having one end connected to the internal node and the other end applied with an auxiliary capacitance voltage.
The other end of the electric capacitive element is connected to the other end of the auxiliary capacitive element.

Furthermore, in the pixel circuit having the above characteristics, the switch circuit includes a series circuit of the first and second transistor elements,
The source voltage is applied to a first terminal of the first transistor element;
A second terminal of the first transistor element and a first terminal of the second transistor element are connected to the intermediate node, and a second terminal of the second transistor element is connected to the internal node;
Preferably, the capacitance element is connected to the internal node and the intermediate node in parallel with the second transistor element.

Furthermore, in the pixel circuit having the above characteristics, when the electric capacitance element includes at least one of a cross capacitance of the semiconductor layer and the metal wiring layer, a cross capacitance of the plurality of metal wires, and a MOS capacitance, preferable.

Furthermore, in order to achieve the above object, the present invention forms a pixel circuit array by arranging a plurality of pixel circuits having the above characteristics in the row direction and the column direction, respectively.
A source voltage application circuit for applying the source voltage to one end of the switch circuit;
A gate voltage application circuit that applies a gate voltage to the switch circuit to control the presence or absence of conduction of the switch circuit;
A display device is provided.

According to the pixel circuit and the display device having the above characteristics, by providing the capacitance element, fluctuation of the voltage held by the intermediate node is suppressed. Therefore, the absolute value of the difference between the voltage held by the intermediate node and the pixel data voltage held by the internal node can be kept small. Therefore, it becomes possible to display an image stably.

Note that when applied to a display device that performs color display, the pixel circuit of the present invention configures each sub-pixel corresponding to each color (for example, three primary colors of RGB) included in each pixel, and performs a monochrome display. When applied to the above, each pixel is constituted.

1 is a block diagram showing an example of a schematic configuration of a liquid crystal display device according to an embodiment of the present invention. 1 is a partial cross-sectional schematic structure diagram of a liquid crystal display device according to an embodiment of the invention. 1 is a circuit diagram showing a basic circuit configuration of a pixel circuit included in a liquid crystal display device according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a circuit configuration example of a pixel circuit included in the liquid crystal display device according to the embodiment of the invention. FIG. 6 is a timing chart showing an operation example of the liquid crystal display device and the pixel circuit according to the embodiment of the present invention. The timing diagram which shows the operation result of a comparative example. The timing diagram which shows the operation result of an Example. Circuit diagram showing the structure of a conventional pixel circuit Circuit diagram showing the structure of a conventional pixel circuit

<Schematic configuration of liquid crystal display device>
A schematic configuration of a liquid crystal display device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of a schematic configuration of a liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display device 1 includes an active matrix substrate 10, a common electrode 30, a display control circuit 11, a common electrode drive circuit 12, a source driver 13, a gate driver 14, and various wirings to be described later. On the active matrix substrate 10, a plurality of pixel circuits 2 are arranged in the row direction (horizontal direction in the figure) and in the column direction (vertical direction in the figure) to form a pixel circuit array. In the active matrix substrate 10 shown in FIG. 1, a total of n × m pixel circuits of n in the column direction and m in the row direction are arranged. Note that n and m are natural numbers. In FIG. 1, the uppermost row is the first row, the lowermost row is the nth row, the leftmost column is the first column, and the rightmost column is the mth column. To do. In the following, when referring to the pixel circuit 2 in a specific row and column, it is referred to as 2 (row, column). For example, the pixel circuit 2 arranged in the n-th row and the m-th column at the lower right in the drawing is referred to as 2 (n, m).

In FIG. 1, the pixel circuit 2 is displayed in a block form in order to avoid complicated drawing. In FIG. 1, the active matrix substrate 10 is illustrated on the upper side of the common electrode 30 for the sake of convenience in order to clearly display that various wirings are formed on the active matrix substrate 10.

For convenience, the minimum display unit corresponding to one pixel circuit 2 is referred to as a “pixel”. At this time, the “pixel data voltage” held in each pixel circuit 2 is a voltage that controls the gradation of each color (for example, the three primary colors of RGB) when performing color display, and the luminance when performing monochrome display. The voltage to be controlled.

FIG. 2 is a partial sectional schematic structural diagram of the liquid crystal display device according to the embodiment of the present invention. FIG. 2 is a schematic cross-sectional structure diagram showing the relationship between the active matrix substrate 10 and the common electrode 30, and shows the structure of the display element unit 21 (see FIG. 3) that is a component of the pixel circuit 2. The active matrix substrate 10 is a light transmissive transparent substrate, and is made of, for example, glass or plastic. As shown in FIG. 1, the pixel circuit 2 connected to each wiring is formed on the active matrix substrate 10. In FIG. 2, the pixel electrode 20 is illustrated as a representative of the components of the pixel circuit 2. The pixel electrode 20 is made of a light transmissive transparent conductive material, for example, ITO (indium tin oxide).

Further, a light-transmitting counter substrate 31 is disposed so as to face the active matrix substrate 10, and a liquid crystal layer 33 is held in a gap between the two substrates. Polarizing plates (not shown) are attached to the outer surfaces of both substrates.

The liquid crystal layer 33 is sealed with a sealing material 32 in the peripheral portions of both substrates. A common electrode 30 made of a light-transmissive transparent conductive material such as ITO is formed on the counter substrate 31 so as to face the pixel electrode 20. The common electrode 30 is formed as a single film so as to spread over the counter substrate 31 substantially on one surface. Here, a unit liquid crystal display element LC (corresponding to a unit display element) is formed by one pixel electrode 20, a common electrode 30, and a liquid crystal layer 33 sandwiched therebetween.

In the case where the liquid crystal display device 1 is a transmissive liquid crystal display device, for example, a backlight device (not shown) is disposed on the back side of the active matrix substrate 10, and light is emitted from the active matrix substrate 10 toward the counter substrate 31. Is irradiated.

As shown in FIG. 1, a plurality of wirings are formed on the active matrix substrate 10 in the vertical and horizontal directions. Specifically, n gate lines (GL (1), GL (2),..., GL (n)) extending in the horizontal direction (row direction) and the horizontal direction (row). N auxiliary capacitance lines (CSL (1), CSL (2),..., CSL (n)) in order from the top in the figure, and m lines extending in the vertical direction (column direction). Source lines (SL (1), SL (2),..., SL (m)) are formed in order from the left in the figure. Hereinafter, for convenience, each gate line (GL (1), GL (2),..., GL (n)) is generalized and referred to as a gate line GL, and each auxiliary capacitance line (CSL (1)). , CSL (2),..., CSL (n)) are generically referred to as auxiliary capacitance lines CSL, and each source line (SL (1), SL (2),..., SL (m)) Generally referred to as source line SL.

In the liquid crystal display device 1, the same number of gate lines GL and auxiliary capacitance lines CSL as the number of rows n of the pixel circuit 2 are formed on the active matrix substrate 10. Then, the m pixel circuits 2 (i, 1) to 2 (i, m) arranged in a certain row are connected to the same gate line GL (i) and the same auxiliary capacitance line CSL (i) (i Is a natural number between 1 and n). In the liquid crystal display device 1, the same number of source lines SL as the number m of columns of the pixel circuits 2 are formed on the active matrix substrate 10. Then, n pixel circuits 2 (1, j) to 2 (n, j) arranged in a certain column are connected to the same source line SL (j) (j is a natural number of 1 to m).

The source driver 13, the gate driver 14, and the CS driver 15 sequentially apply a voltage corresponding to an image to be displayed to the source line SL, the gate line GL, and the auxiliary capacitance line CSL. A voltage is applied to the pixel electrode 20 formed in (1). At this time, the source driver 13 can individually apply the source line voltage V _SL (corresponding to the source voltage) to each of the source lines SL (1) to SL (m). Similarly, the gate driver 14 can individually apply the gate line voltage V _GL (corresponding to the gate voltage) to each of the gate lines GL (1) to GL (n). Similarly, the CS driver 15 can individually apply the auxiliary capacitance line voltage V _CSL (corresponding to the auxiliary capacitance voltage) to each of the auxiliary capacitance lines CSL (1) to CSL (n). On the other hand, the common electrode drive circuit 12 applies a common voltage V _COM to the common electrode 30.

The display control circuit 11 receives a data signal Dv and a timing signal Ct representing an image to be displayed from an external signal source. Then, the display control circuit 11 uses the digital image signal DA and the data side timing control signal Stc to be supplied to the source driver 13 as signals for displaying an image on the display element unit 21 of the pixel circuit array based on the signals Dv and Ct. And a scanning side timing control signal Gtc to be given to the gate driver 14, a common voltage control signal Sec to be given to the common electrode driving circuit 12, and an auxiliary capacitance line voltage control signal CStc to be given to the CS driver 15, respectively. Note that a part or all of the display control circuit 11 may be formed in the source driver 13 or the gate driver 14.

The liquid crystal display device 1 makes the common voltage V _COM constant, and inverts the magnitude relationship of the source line voltage V _{SL with} respect to the common voltage V _COM at a predetermined timing, thereby changing the polarity of the voltage applied to the liquid crystal at a predetermined timing. The “common voltage DC drive” that suppresses the burn-in of the display screen by reversing can be performed. Note that the polarity of the voltage applied to the liquid crystal in the liquid crystal display device 1 when the common electrode drive circuit 12 switches the common voltage _VCOM between a high level and a low level at a predetermined timing by the control from the display control circuit 11. It is also possible to perform “common voltage AC drive” that suppresses burn-in of the display screen by inverting the display at a predetermined timing. Any of the driving methods can be realized by appropriately selecting various voltages to be applied to the pixel circuit 2, but in the following, for the sake of concrete description, the liquid crystal display device 1 performs “common voltage DC driving”. Illustrate.

Furthermore, the liquid crystal display device 1 is arranged in the polarity of the voltage applied to the unit liquid crystal display element LC by the pixel circuits 2 (i, 1) to 2 (i, m) arranged in the same row and in the adjacent row. The pixel circuits 2 (i ± 1, 1) to 2 (i ± 1, m) are periodically (for example, one vertical period) so that the polarity of the voltage applied to the unit liquid crystal display element LC is reversed. Each time, each pixel circuit 2 can perform “row line inversion driving” in which the polarity of the voltage applied to the unit liquid crystal display element LC is inverted. In the liquid crystal display device 1, the pixel circuits 2 (1, j) to 2 (n, j) arranged in the same column are arranged in adjacent columns and the polarity of the voltage applied to the unit liquid crystal display element LC. The pixel circuits 2 (1, j ± 1) to 2 (n, j ± 1) are periodically (for example, one vertical period) so that the polarity of the voltage applied to the unit liquid crystal display element LC is reversed. It is also possible to perform “column line inversion driving” in which each pixel circuit 2 inverts the polarity of the voltage applied to the unit liquid crystal display element LC. Further, the liquid crystal display device 1 has a polarity of a voltage applied to a unit liquid crystal display element LC by a pixel circuit 2 (i, j) and a pixel circuit 2 (i ± 1, j ± 1) adjacent in the row direction or the column direction. ) Is applied to the unit liquid crystal display element LC periodically (for example, every vertical period) so that the polarity of the voltage applied to the unit liquid crystal display element LC is reversed. It is also possible to perform “dot inversion driving” that inverts the polarity of. Any of the driving methods can be realized by appropriately selecting wirings connected to the pixel circuit 2 and various voltages to be applied, but in the following, the liquid crystal display device 1 will be referred to as “row line inversion driving” for the sake of concrete description. An example of performing the above will be described.

Based on the digital image signal DA and the data-side timing control signal Stc, the source driver 13 has a difference between the common voltage V _COM and the source line voltage V _{SL corresponding} to one row (m) of pixels represented by the digital signal DA. Each source line voltage _VSL is generated and applied to each source line SL for each horizontal period so as to correspond to the value. However, the source driver 13 determines the source line voltage V V so that the polarity of the difference between the common voltage V _COM and the source line voltage V _SL in each pixel circuit 2 is periodically inverted (for example, every vertical period). Control _SL .

Based on the scanning side timing control signal Gtc, the gate driver 14 can apply the source line voltage V _SL to the connected pixel circuit 2 with respect to the gate line GL connected to the pixel circuit 2 arranged in a predetermined row. A gate line voltage _VGL having a voltage value to be applied is applied. As a result, the source line voltage _VSL is applied to the pixel circuits 2 arranged in the predetermined row. Furthermore, the gate driver 14 switches the gate line GL to which the source line voltage V _GL that enables the source line voltage V _SL to be applied to the pixel circuit 2 is switched every horizontal period, so that the source line voltage V _SL. Are sequentially applied to the pixel circuit 2.

The CS driver 15 applies the connected pixel circuit 2 to the unit liquid crystal display element LC with respect to the auxiliary capacitance line CSL connected to the pixel circuit 2 arranged in a predetermined row based on the auxiliary capacitance line voltage control signal CStc. A storage capacitor line voltage V _CSL that increases the absolute value of the voltage to be applied (the difference between the voltage level of the common voltage V _COM and the source line voltage V _SL ) is applied. The CS driver 15 continues to apply the same auxiliary capacitance line voltage V _CSL to the auxiliary capacitance line CSL until a new source line voltage V _SL is applied to the pixel circuit 2.

The details of the operations of the source driver 13, the gate driver 14, and the CS driver 15 and the operations of the pixel circuit 2 associated with these operations will be described later.

The liquid crystal display device 1 may be any of a transmissive type, a reflective type, and a transflective type. In FIG. 1, the gate driver 14 and the CS driver 15 are disposed so as to face each other with the active matrix substrate 10 interposed therebetween, but may be disposed on the same side. Further, the gate driver 14 and the CS driver 15 may be integrated. Further, the gate driver 14 and the CS driver 15 may be formed on the active matrix substrate 10 similarly to the pixel circuit 2.

<Configuration of pixel circuit>
A configuration of the pixel circuit 2 provided in the liquid crystal display device 1 according to the embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a circuit diagram showing a basic circuit configuration of a pixel circuit included in the liquid crystal display device according to the embodiment of the present invention. FIG. 4 is a circuit diagram of the pixel circuit included in the liquid crystal display device according to the embodiment of the present invention. It is a circuit diagram which shows a structural example.

As shown in FIG. 3, the pixel circuit 2 includes a display element unit 21 including a unit liquid crystal display element LC, a switch circuit 22, an auxiliary capacitance element Cs, and an electric capacitance element Cd. As described with reference to FIG. 2, the unit liquid crystal display element LC includes the pixel electrode 20 and the common electrode 30. Note that the basic circuit configuration shown in FIG. 3 is a high-level circuit configuration including the specific circuit configuration example shown in FIG.

The switch circuit 22 includes a transistor T1 (corresponding to a first transistor element) and a transistor T2 (corresponding to a second transistor element) connected in series. Each of the transistors T1 and T2 includes a first terminal and a second terminal (source electrode and drain electrode), and a control terminal (gate electrode).

A source line SL is connected to one end of the switch circuit 22, and one end of the auxiliary capacitive element Cs is connected to the other end to form an internal node N1. The pixel data voltage V _N1 held by the internal node N1 is applied to the pixel electrode 20 and is an image corresponding to the pixel data voltage V _N1 (more precisely, the difference between the pixel data voltage V _N1 and the common voltage V _COM ). The image according to the liquid crystal voltage V _LC ) is displayed on the liquid crystal display device 1. The other end of the auxiliary capacitance element Cs is connected to the auxiliary capacitance line CSL.

The control terminals of the transistors T1 and T2 of the switch circuit 22 are both connected to the gate line GL. That is, the conduction state of both the transistors T1 and T2 is controlled by the gate line voltage _VGL . The second terminal of the transistor T1 and the first terminal of the transistor T2 are connected to form an intermediate node N2. Accordingly, when at least the transistors T1 and T2 are turned off, the source line SL and the internal node N1 are turned off, and the source line voltage _VSL is not applied to the internal node N1. In the circuit configuration example shown in FIG. 3, the switch circuit 22 may include elements other than the transistor T1 and the transistor T2. On the other hand, in the circuit configuration example shown in FIG. 4, the switch circuit 22 is configured only by a series circuit of a transistor T1 and a transistor T2, the first terminal of the transistor T1 is connected to the source line SL, and the second of the transistor T2 is connected. A terminal is connected to internal node N1.

The electric capacitance element Cd has one end connected to the intermediate node N2 and the other end connected to the internal node N1. For example, the electric capacitance element Cd may be constituted by a predetermined capacitance element, may be constituted by a cross capacitance of a semiconductor layer and a metal wiring layer, a cross capacitance of a plurality of metal wires, or a MOS capacitance. It may be configured by combining at least two of these.

The transistors T1 and T2 are both thin film transistors such as polycrystalline silicon TFTs or amorphous silicon TFTs formed on the active matrix substrate 10. For example, the transistors T1 and T2 may be configured with a single transistor or may be configured with a common control terminal. In the following, for the sake of concrete explanation, a case where the transistors T1 and T2 are N-channel TFTs is illustrated.

3 and 4, among the parasitic capacitances of the transistors T1 and T2, the parasitic capacitance Cp1 between the control electrode and the second terminal of the transistor T1, and the parasitic capacitance Cp2 between the control electrode and the first terminal of the transistor T2. Is illustrated.

<Operation Example of Liquid Crystal Display Device and Pixel Circuit>
An operation example of the liquid crystal display device 1 and the pixel circuit 2 according to the embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a timing diagram showing an operation example of the liquid crystal display device and the pixel circuit according to the embodiment of the present invention. In the following, for the sake of concrete description, a case where the pixel circuit 2 included in the liquid crystal display device 1 has the configuration of the pixel circuit 2 illustrated in FIG. 4 is illustrated.

As shown in FIG. 5, when the liquid crystal display device 1 operates, the gate line voltage V _GL having a voltage value H (for example, 10 V) that makes the transistors T1 and T2 conductive is set to the gate lines GL (1), GL ( 2),..., GL (n), and applied while being switched every horizontal period (1H). Thereby, when the transistors T1 and T2 of each pixel circuit 2 arranged in a certain row are in a conductive state, each pixel circuit 2 has the source line voltage V _SL applied to the source line SL at that time. Applied to the pixel electrode 20 of the unit liquid crystal display element LC, the pixel data voltage V _N1 is held in the internal node N1. Note that when the gate line voltage V _GL having a voltage value that makes the transistors T1 and T2 conductive is not applied, the gate line GL has a voltage value L (for example, −5V) that makes the transistors T1 and T2 nonconductive. gate line voltage _{V GL} of) is applied.

As described above, the liquid crystal display device 1 of this example performs “common voltage DC driving” and “row line inversion driving”. Therefore, the common voltage V _COM is constant (for example, 2.0 V). Further, the source line SL, 1 every horizontal period, the common voltage _{V COM} is greater than positive (+) and source line voltage _{V SL} of the voltage value of the polarity, the common voltage _{V COM} less negative (-) polarity of the voltage The source line voltage _VSL that is a value is applied alternately. Further, the polarity of the source line voltage V _SL applied to the source line SL of a certain column during a certain vertical period (1V) and the source line voltage V applied to the source line _SL of the certain column during the next vertical period. _This is the opposite of the polarity of _SL .

In a certain horizontal period, the pixel circuit 2 to which the transistors T1 and T2 are turned on and the source line voltage _VSL is applied is connected to the auxiliary capacitance line voltage applied to the connected auxiliary capacitance line CSL in the next horizontal period. V _CSL changes (in this example, increasing from L to H or decreasing from H to L). As a result, the pixel data voltage V _N1 held by the internal node N1 is pushed up or pushed down via the auxiliary capacitance element Cs, thereby increasing the absolute value of the voltage applied to the unit liquid crystal display element LC. Therefore, the absolute value of the source line voltage _VSL can be reduced, and power consumption can be reduced.

Specifically, for example, in a certain pixel circuit 2, when the source line voltage _VSL having a positive voltage value is applied, the auxiliary capacitance line voltage V _CSL increases from L to H, and the pixel held by the internal node N1 The data voltage V _N1 is pushed up. On the other hand, when a source line voltage _VSL having a negative voltage value is applied in a certain pixel circuit 2, the auxiliary capacitance line voltage V _CSL decreases from H to L, and the pixel data voltage V held by the internal node N1 _N1 is pushed down.

Then, after the storage capacitor line voltage V _CSL applied to a certain pixel circuit 2 changes in a certain vertical period, the horizontal period in which the source line voltage V _SL is applied to the certain pixel circuit 2 in the next vertical period ends. (The storage capacitor line voltage V _CSL changes in the horizontal period next to the horizontal period). In this way, the pixel circuit 2 applies a desired voltage to the unit liquid crystal display element LC.

In the pixel circuit 2 described above, when the transistors T1 and T2 are turned off, if the voltage value L of the gate line voltage _VGL is sufficiently small, the source line voltage _VSL changes every horizontal period. This is preferable because current leakage through the transistors T1 and T2 can be suppressed.

However, reducing the voltage value L of the gate line voltage V _GL, when falling of the gate line voltage V _GL to (when changing to L from H), after the gate line voltage transistors T1, T2 becomes non-conductive state As V _GL further decreases, the feedthrough increases, and the intermediate node voltage V _N2 held by the intermediate node _N2 decreases. Therefore, there is a concern that the pixel data voltage V _N1 held by the internal node N1 fluctuates due to a leak current through the transistor T2. In particular, in order to reduce power consumption, the smaller the frame frequency, the longer the time during which leakage current can occur, and the fluctuation in the pixel data voltage V _N1 increases, making it difficult to display images stably. There is concern about becoming.

In the pixel circuit 2 of this example, by including the capacitance element Cd, it is possible to suppress the leakage current of the transistor T2 and the fluctuation of the pixel data voltage V _N1 and display an image stably. This will be described below by comparing the operation result of the “comparative example” with the operation result of the “example”. The “comparative example” is obtained by removing the capacitance element Cd from the pixel circuit 2 shown in FIG. On the other hand, the “example” refers to the pixel circuit 2 shown in FIG. 4 including the capacitance element Cd (that is, the above-described embodiment).

In the following, an arbitrary pixel circuit 2 (i, j) will be described. Note that the pixel circuit 2 (i, j) has a gate line _{GL (i) to} which the gate line voltage _{VGL (i)} is applied and a source line _{SL (to} which the source line voltage _{VSL (j)} is applied. j) and the auxiliary capacitance line _{CSL (i)} to which the auxiliary capacitance line voltage V _{CSL (i)} is applied are respectively connected, and the internal node N1 (i, j) is connected to the pixel data voltage V _{N1 (i, j).} , And the intermediate node N2 (i, j) holds the intermediate node voltage _{VN2 (i, j)} . Furthermore, in the following, for simplification of description, a case where the source line voltage _{VSL (j)} can take a positive voltage and a negative voltage one by one is illustrated.

<Operation result of comparative example>
FIG. 6 is a timing chart showing the operation result of the comparative example. As shown on the left side of FIG. 6, when the source line voltage _{VSL (j)} is a positive voltage and the gate line voltage _{VGL (i)} is changed from L to H, the internal node N1 (i, j) becomes The pixel data voltage V _{N1 (i, j)} (broken line in the figure ₎ that is the source line voltage V _{SL (j)} is held. Similarly, the intermediate node N2 (i, j) holds the intermediate node voltage V _{N2 (i, j)} (solid line in the figure ₎ that is the source line voltage V _{SL (j)} . At this time, the pixel data voltage V _{N1 (i, j)} and the intermediate node voltage V _{N2 (i, j)} are both equal to or greater than the common voltage V _COM (one-dot chain line in the figure).

When the gate line voltage V _{GL (i)} is changed from H to L, the gate line voltage V _{GL (i)} is greatly reduced from the voltage value required to turn off the transistors T1 and T2. The intermediate node voltage V _{N2 (i, j)} is greatly reduced by the feedthrough. Specifically, the fluctuation range ΔV _N2 of the intermediate node voltage V _{N2 (i, j)} is obtained by deactivating the capacitance Cp obtained by combining the parasitic capacitances Cp1 and Cp2 described above, the other parasitic capacitance Cmisc related to the intermediate node N2, and the transistors T1 and T2. Using the difference value ΔV _{G obtained} by subtracting the voltage value L from the gate line voltage V _{GL (i)} necessary for making the conductive state, it is expressed as the following formula (1).

(Equation 1)
ΔV _N2 ≈Cp / (Cp + Cmisc) × ΔV _G = α × ΔV _G (1)

Α in the above formula (1) is larger than at least 50% because the parasitic capacitance Cmisc is sufficiently smaller than the parasitic capacitance Cp. On the other hand, the pixel data voltage V _{N1 (i, j)} decreases small because elements having large capacitances such as the unit liquid crystal display element LC and the auxiliary capacitance element Cs are connected to the internal node N1. Therefore, the absolute value Dc1 of the difference between the intermediate node voltage V _{N2 (i, j)} and the pixel data voltage V _{N1 (i, j)} becomes large.

Thereafter, the auxiliary capacitance line voltage V _{CSL (i)} changes from L to H in order to push up the pixel data voltage V _{N1 (i, j)} . Then, the pixel data voltage V _{N1 (i, j)} is further increased by being pushed up through the auxiliary capacitance element Cs, but the intermediate node voltage V _{N2 (i, j)} does not particularly change. Therefore, the absolute value Dc2 of the difference between the intermediate node voltage V _{N2 (i, j)} and the pixel data voltage V _{N1 (i, j)} is further larger than the absolute value Dc1 of the difference.

On the other hand, as shown on the right side of FIG. 6 (after the passage of one vertical period on the left side of FIG. 6), the source line voltage _{VSL (j)} is a negative voltage, and the gate line voltage _{VGL (i)} is changed from L. When it becomes H, the internal node N1 (i, j) holds the pixel data voltage V _{N1 (i, j)} which is the source line voltage V _{SL (j)} . Similarly, the intermediate node N2 (i, j) holds the intermediate node voltage _{VN2 (i, j)} that is the source line voltage _{VSL (j)} . At this time, the pixel data voltage V _{N1 (i, j)} and the intermediate node voltage V _{N2 (i, j)} are both equal to or smaller than the common voltage V _COM (one-dot chain line in the figure).

When the gate line voltage V _{GL (i)} is changed from H to L, the intermediate node voltage V _{N2 (i, j)} is greatly reduced and the pixel data voltage V _{N1 (i, j)} is reduced as in the case described above. Decrease small. Therefore, the absolute value Dc3 of the difference between the intermediate node voltage V _{N2 (i, j)} and the pixel data voltage V _{N1 (i, j)} becomes large. However, in this case, the gate line voltage _{VGL (i)} necessary for bringing the transistors T1 and T2 into a non-conductive state is smaller than that on the left side of FIG. ΔV _G is reduced. Therefore, Dc3 is smaller than Dc1 described above.

Thereafter, the auxiliary capacitance line voltage V _{CSL (i)} changes from H to L in order to push down the pixel data voltage V _{N1 (i, j)} . Then, the pixel data voltage V _{N1 (i, j)} is reduced by being pushed down through the auxiliary capacitance element Cs, but the intermediate node voltage V _{N2 (i, j)} does not particularly vary. Therefore, the absolute value Dc4 of the difference between the intermediate node voltage V _{N2 (i, j)} and the pixel data voltage V _{N1 (i, j)} is smaller than the above-described Dc3. However, the difference Dc4 is still large because the above-described Dc3 is sufficiently larger than the fluctuation due to the pixel data voltage V _{N1 (i, j)} being pushed down.

In the comparative example, corresponds to a period (one vertical period to the pixel circuits 2 (i, j) the source line voltage V _{SL (j)} is then the source line voltage V _SL after being applied _(j) is applied The difference between the pixel data voltage V _{N1 (i, j)} held by the internal node N1 (i, j) and the intermediate node voltage V _{N2 (i, j)} held by the intermediate node _{N2 (i, j)} However, it will grow and be maintained. Therefore, during the period, a leak current is generated between the internal node N1 (i, j) and the intermediate node N2 (i, j), and the pixel data voltage V _{N1 (i , J)} varies, the pixels displayed by the pixel circuit 2 (i, j) vary (luminance varies).

Further, when a new source line voltage V _{SL (j)} is applied to the pixel circuit 2 (i, j), the pixel data voltage V _N1 after the change that the internal node N1 (i, j) has held so far. _Since an unscheduled difference due to the change occurs between _{(i, j)} and the pixel data voltage V _{N1 (i, j)} before the change that is newly held thereafter, the pixel circuit 2 (i, j ) Display pixels become unstable. Specifically, for example, when the pixel circuit 2 (i, j) continuously displays the same pixel, even if the data of the pixel to be displayed is the same, before and after switching the pixel to be displayed The pixels are different (there is a luminance difference, that is, flickering occurs).

Thus, in the comparative example, it is difficult to display an image stably.

<Operational results of the example>
FIG. 7 is a timing chart showing an operation result of the embodiment. As shown on the left side of FIG. 7, when the source line voltage _{VSL (j)} is a positive voltage and the gate line voltage _{VGL (i)} is changed from L to H, the internal node N1 (i, j) becomes The pixel data voltage V _{N1 (i, j)} (broken line in the figure ₎ that is the source line voltage V _{SL (j)} is held. Similarly, the intermediate node N2 (i, j) holds the intermediate node voltage V _{N2 (i, j)} (solid line in the figure ₎ that is the source line voltage V _{SL (j)} . At this time, the pixel data voltage V _{N1 (i, j)} and the intermediate node voltage V _{N2 (i, j)} are both equal to or greater than the common voltage V _COM (one-dot chain line in the figure).

When the gate line voltage V _{GL (i)} is changed from H to L, the gate line voltage V _{GL (i)} is greatly reduced from the voltage value necessary for making the transistors T1 and T2 non-conductive. The intermediate node voltage V _{N2 (i, j)} decreases due to the slew. Specifically, the fluctuation range ΔV _N2 of the intermediate node voltage V _{N2 (i, j)} includes the capacitance Cp obtained by combining the parasitic capacitances Cp1 and Cp2, the capacitance C1 of the electric capacitance element Cd, and other parasitic capacitances related to the intermediate node N2. Cmisc, a difference value ΔV _{G obtained} by subtracting the voltage value L from the gate line voltage V _{GL (i)} necessary for bringing the transistors T1 and T2 into a non-conductive state, is expressed as the following equation (2). The

(Equation 2)
ΔV _N2 ≈Cp / (Cp + C1 + Cmisc) × ΔV _G = β × ΔV _G (2)

Β in the above equation (2) is smaller than α in the above equation (1) because the capacitance C1 of the capacitance element Cd is included in the denominator. Therefore, the fluctuation of the intermediate node voltage V _{N2 (i, j)} can be made smaller than that of the comparative example. Specifically, for example, by making the capacitance C1 of the electric capacitance element Cd equal to or higher than the capacitance Cp obtained by combining the parasitic capacitances Cp1 and Cp2, the fluctuation of the intermediate node voltage V _{N2 (i, j)} is compared. It becomes possible to make it 50% or less of the example. Therefore, the absolute value De1 of the difference between the intermediate node voltage V _{N2 (i, j)} and the pixel data voltage V _{N1 (i, j)} can be made smaller than Dc1 in the comparative example.

Thereafter, the auxiliary capacitance line voltage V _{CSL (i)} changes from L to H in order to push up the pixel data voltage V _{N1 (i, j)} . Then, the pixel data voltage V _{N1 (i, j)} is further increased by being pushed up through the auxiliary capacitance element Cs. At this time, the intermediate node voltage V _{N2 (i, j)} is pushed up via the capacitance element Cd as the pixel data voltage V _{N1 (i, j)} increases, so that the pixel data voltage V _{N1 (i, j) ) And} become even larger. Therefore, the absolute value De2 of the difference between the intermediate node voltage V _{N2 (i, j)} and the pixel data voltage V _{N1 (i, j)} can be maintained as small as the above-described De1.

On the other hand, as shown on the right side of FIG. 7 (after the passage of one vertical period on the left side of FIG. 7), the source line voltage V _{SL (j)} is a negative voltage and the gate line voltage V _{GL (i)} is changed from L. When it becomes H, the internal node N1 (i, j) holds the pixel data voltage V _{N1 (i, j)} which is the source line voltage V _{SL (j)} . Similarly, the intermediate node N2 (i, j) holds the intermediate node voltage _{VN2 (i, j)} that is the source line voltage _{VSL (j)} . At this time, the pixel data voltage V _{N1 (i, j)} and the intermediate node voltage V _{N2 (i, j)} are both equal to or smaller than the common voltage V _COM (one-dot chain line in the figure).

When the gate line voltage V _{GL (i)} is changed from H to L, the intermediate node voltage V _{N2 (i, j)} is reduced to a small value as in the case described above. Therefore, the absolute value De3 of the difference between the intermediate node voltage V _{N2 (i, j)} and the pixel data voltage V _{N1 (i, j)} can be made smaller than the absolute value Dc3 of the difference in the comparative example. In this case, the gate line voltage _{VGL (i)} necessary for bringing the transistors T1 and T2 into a non-conductive state is smaller than that on the left side of FIG. ΔV _G is reduced. Therefore, De3 is further smaller than De1 described above.

Thereafter, the auxiliary capacitance line voltage V _{CSL (i)} changes from H to L in order to push down the pixel data voltage V _{N1 (i, j)} . Then, the pixel data voltage V _{N1 (i, j)} is reduced by being pushed down through the auxiliary capacitance element Cs. In this case, the intermediate node voltage _{V N2 (i, j)} is due to the decrease of the pixel data voltage _{V N1 (i, j),} since the lowered thrust through the capacitance element Cd, pixel data voltage _{V N1 (i, It} becomes smaller following _j) . Therefore, the absolute value De4 of the difference between the intermediate node voltage V _{N2 (i, j)} and the pixel data voltage V _{N1 (i, j)} can be maintained as small as De3 described above.

In the embodiment, corresponds to a period (one vertical period to the pixel circuits 2 (i, j) the source line voltage V _{SL (j)} is then the source line voltage V _SL after being applied _(j) is applied The difference between the pixel data voltage V _{N1 (i, j)} held by the internal node N1 (i, j) and the intermediate node voltage V _{N2 (i, j)} held by the intermediate node _{N2 (i, j)} The absolute value of can be kept small. Therefore, the leakage current between the internal node N1 (i, j) and the intermediate node N2 (i, j) is suppressed during the period, so that the pixel data voltage held by the internal node N1 (i, j) Variations in V _{N1 (i, j)} are suppressed.

Even when a new source line voltage _{VSL (j)} is applied to the pixel circuit 2 (i, j), the pixel data voltage _{VN1 (i} ) held by the internal node N1 (i, j) until then. _{, J)} is maintained at the expected size. Therefore, the pixels displayed by the pixel circuit 2 (i, j) are stable.

As described above, the liquid crystal display device 1 and the pixel circuit 2 according to the embodiment of the present invention can display an image stably.

<Modification>
<1> From the viewpoint of stably displaying an image on the liquid crystal display device 1 (suppressing fluctuations in the pixel data voltage V _N1 held by the internal node N1), it is preferable that the capacitance C1 of the capacitance element Cd is larger. However, by increasing the capacitance C1 of the capacitance element Cd, the capacitance element Cd blocks light transmitted through the pixel circuit 2 (the aperture ratio is deteriorated). Therefore, it is preferable that the capacitance C1 of the electric capacitance element Cd be kept at a necessary minimum value.

<2> The internal node voltage V _N1 set to a desired value (for example, the internal node voltage V _N1 after being pushed up or pushed down through the auxiliary capacitance element Cs as described above) and the source line voltage V _SL (In other words, the internal node voltage V _{N1 (i, j) of} the pixel circuit 2 _{(i, j)} and the source line voltage V _{SL (j)} can be made close to each other _). In the case), it is preferable to set the capacitance C1 of the electric capacitance element Cd so as to satisfy the following formula (3), because fluctuations in the internal node voltage _VN1 can be more effectively suppressed.

(Equation 3)
C1 = Cp + Cmisc (3)

When the capacitance C1 of the capacitance element Cd is set to be about 50% of the total parasitic capacitance (Cp + C1 + Cmisc) related to the intermediate node N2 as in the above equation (3), the transistors T1 and T2 are in a non-conductive state. Even if a leak current sometimes occurs, fluctuations in the internal node voltage V _N1 can be more effectively suppressed. This will be described below.

When the transistors T1 and T2 are non-conductive, the charge flowing out from the internal node N1 to the intermediate node N2 via the transistor T2 is Q2, and the charge flowing out from the source line SL to the intermediate node N2 via the transistor T1 Is Q1, and the total parasitic capacitance related to the internal node N1 is Cpix. At this time, it is generated by the change ΔV _{N1 in} the potential of the internal node N1 caused by the charge Q2 flowing out from the internal node N1 to the intermediate node N2, and the charges Q1 and Q2 flowing into the intermediate node N2 via the transistors T1 and T2. the change [Delta] V _N2 of the potential of the intermediate node N2, as shown in the following equation (4).

(Equation 4)
ΔV _N1 = −Q2 / Cpix
ΔV _N2 = (Q1 + Q2) / (C1 + Cp + Cmisc) (4)

The potential change ΔV _N1 ′ of the internal node N1 pushed up or pushed down via the electric capacitance element Cd by the potential change ΔV _N2 of the intermediate node N2 is expressed by the following equation (5).

(Equation 5)
ΔV _N1 ′ = C1 / Cpix × ΔV _N2
= C1 / (C1 + Cp + Cmisc) × (Q1 + Q2) / Cpix (5)

Here, if the characteristics of the transistors T1 and T2 are equal, the charges Q1 and Q2 are approximately the same from the above assumption ( _VSL and _VN1 are approximately the same). Here, considering Q1 = Q2, ΔV _N1 in the above equation (3), the above equation (4), and the above equation (5), the total potential change ΔV _N1 + ΔV _N1 ′ of the internal node N1 is expressed by the following equation: It becomes 0 as shown in (6). Therefore, fluctuations in internal node voltage V _N1 can be more effectively suppressed. Here, for simplicity of explanation, Q1 = Q2, but even if Q1 ≠ Q2, if Q1≈Q2, an effect of more effectively suppressing the fluctuation of the internal node voltage V _N1 can be obtained. Can do.

(Equation 6)
ΔV _N1 + ΔV _N1 ′ = −Q2 / Cpix + 0.5 × 2 × Q2 / Cpix
= 0 (6)

Further, in consideration of the effect of suppressing the fluctuation of the intermediate node voltage V _N2 described in <1>, the optimum value of the capacitance C1 of the capacitance element Cd is equal to or higher than the total of other parasitic capacitances (Cp + Cmisc) related to the intermediate node N2. It is preferable that the decrease in the aperture ratio is determined within an allowable range. Moreover, since the effect obtained according to the capacity | capacitance C1 of the electrical capacitance element Cd may change with the specifications of the display apparatus 1, it is more preferable to determine an optimal value based on the specifications of the display apparatus 1.

<3> The configuration in which the pixel circuit 2 includes the auxiliary capacitance element Cs and pushes up or pushes down the pixel data voltage V _N1 held by the internal node N1 via the auxiliary capacitance element Cs has been illustrated. The element Cs may not be provided. However, in the pixel circuit 2 including the auxiliary capacitance element Cs, the absolute value of the difference between the intermediate node voltage V _N2 and the pixel data voltage V _N1 becomes larger as described above, so that the effect obtained by applying the present invention can be obtained. growing.

<4> As long as one end of the capacitance element Cd is connected to the intermediate node N2 and the other end is connected to a node that induces a voltage fluctuation of the internal node N1, the electric capacitance element Cd has an intermediate node voltage V _N2 and a pixel data voltage V _N1 . The absolute value of the difference can be reduced. That is, the circuit configuration illustrated as the embodiment (see FIGS. 3 and 4) is not limited, and other circuit configurations may be used.

Specifically, for example, one end of the electric capacitance element Cd is connected to the intermediate node N2, and the other end is not the internal node N1, but the auxiliary capacitance line CSL (the pixel data voltage V _N1 held by the internal node N1 via the auxiliary capacitance element Cs) May be connected to a node that induces fluctuations. Even in such a circuit configuration, a change in the intermediate node voltage V _N2 due to the feedthrough is suppressed, or a change in the pixel data voltage V _N1 due to the change in the auxiliary capacitance line voltage V _CSL is followed by the intermediate node voltage V _N2. Can be changed.

However, in this circuit configuration, the capacity coupling efficiency with respect to the intermediate node voltage V _N2 according to the change in the auxiliary capacitance line voltage V _CSL is larger than the circuit configuration exemplified as the embodiment. Therefore, the optimum value of the capacitance C1 of the electric capacitance element Cd may be different from the optimum value in the circuit configuration exemplified as the embodiment. Further, as in the circuit configuration exemplified in the embodiment, when the circuit configuration is such that one end of the capacitance element Cd is connected to the intermediate node N2 and the other end is connected to the internal node N1, the pixel data voltage held by the internal node N1 Any variation in V _N1 (for example, variation due to variation in common voltage V _COM , etc.) is preferable because the intermediate node voltage V _N2 can be effectively followed and varied.

<5> The case where the transistors T1 and T2 included in the pixel circuit 2 are N-channel TFTs has been illustrated, but may be a P-channel TFT. When the pixel circuit 2 includes a P-channel TFT, it is possible to execute the same operation by taking measures such as reversing the positive / negative of the voltage value in the operation example of the liquid crystal display device 1 and the pixel circuit 2 described above. The same effect can be obtained.

<6> Although the case where the present invention is applied to the liquid crystal display device 1 is illustrated, the present invention is applicable to other than the liquid crystal display device 1. The present invention can be applied to a display device other than a liquid crystal display device as long as the display device can hold a pixel data voltage and display an image based on the pixel data voltage.

The pixel circuit according to the present invention and the display device including the pixel circuit can be used for a liquid crystal display device, for example.

1: Liquid Crystal Display Device 2: Pixel Circuit 10: Active Matrix Substrate 11: Display Control Circuit 12: Electrode Driver Circuit 13: Source Driver 14: Gate Driver 20: Pixel Electrode 21: Display Element Unit 22: Switch Circuit 30: Common Electrode 31 : Counter substrate 32: Sealing material 33: Liquid crystal layer GL: Auxiliary gate line SL: Source line CSL: Auxiliary capacitance line LC: Unit liquid crystal display element N1: Internal node N2: Intermediate node T1, T2: Transistor Cs: Auxiliary capacitance element Cd : Electric capacitance element Cp1, Cp2: Parasitic capacitance

Claims (8)

A display element unit including a unit display element;
An internal node that forms part of the display element unit and holds a pixel data voltage applied to the display element unit;
A switch circuit having a series circuit of first and second transistor elements, and transferring a source voltage applied to one end to the internal node connected to the other end via the series circuit;
A capacitance element having one end connected to an intermediate node connecting the first and second transistor elements and the other end connected to the internal node or a node that induces a voltage variation in the internal node;
A pixel circuit comprising: 2. The pixel circuit according to claim 1, wherein the other end of the capacitance element is connected to the internal node. 3. The capacitance of the electric capacitance element is equal to or more than a combination of parasitic capacitances formed between respective control terminals of the first and second transistor elements and the intermediate node. The pixel circuit described. An auxiliary capacitance element having one end connected to the internal node and the other end applied with an auxiliary capacitance voltage;
The pixel circuit according to claim 2, further comprising: An auxiliary capacitance element having one end connected to the internal node and the other end applied with an auxiliary capacitance voltage;
The pixel circuit according to claim 1, wherein the other end of the electric capacitance element is connected to the other end of the auxiliary capacitance element. The switch circuit includes a series circuit of the first and second transistor elements;
The source voltage is applied to a first terminal of the first transistor element;
A second terminal of the first transistor element and a first terminal of the second transistor element are connected to the intermediate node, and a second terminal of the second transistor element is connected to the internal node;
6. The pixel circuit according to claim 1, wherein the capacitance element is connected to the internal node and the intermediate node in parallel with the second transistor element. 7. The electric capacitance element according to claim 1, wherein the electric capacitance element includes at least one of a cross capacitance of a semiconductor layer and a metal wiring layer, a cross capacitance of a plurality of metal wires, and a MOS capacitance. The pixel circuit according to any one of the above items. A pixel circuit array is configured by arranging a plurality of pixel circuits according to any one of claims 1 to 7 respectively in a row direction and a column direction,
A source voltage application circuit for applying the source voltage to one end of the switch circuit;
A gate voltage application circuit that applies a gate voltage to the switch circuit to control the presence or absence of conduction of the switch circuit;
A display device comprising:

Images